Display device and method of driving display panel using the same

Abstract

The present application relates to a display apparatus and a method of driving a display panel using the display apparatus. The display apparatus includes a display panel, a gate driver, a data driver, a driving controller, and a power voltage generator. The display panel displays an image based on input image data. The gate driver outputs a gate signal to a gate line. The data driver outputs a data voltage to a data line. The driving controller drives a plurality of display areas of the display panel at different driving frequencies. The power voltage generator outputs a data power voltage to the data driver. The driving controller outputs an output data enable signal for each display area including a write period having an active signal and a hold period having an inactive signal. The power voltage generator generates the data power voltage having a high power voltage level during the write period and having a low power voltage level in at least a portion of the hold period.

Description

TECHNICAL FIELD

[0001] Example embodiments of the present inventive concept relate to a display apparatus and a method of driving a display panel using the display apparatus. More particularly, example embodiments of the present inventive concept relate to a display apparatus that reduces power consumption and a method of driving a display panel using the display apparatus. BACKGROUND

[0002] Methods of minimizing power consumption of IT products such as tablet PCs and notebook computers have been researched.

[0003] In order to minimize power consumption of an IT product including a display panel, power consumption of the display panel should be minimized. When the display panel displays a still image, the display panel can be driven at a relatively low frequency, so that power consumption of the display panel can be reduced.

[0004] When a portion of the display panel displays a moving image and another portion of the display panel displays a still image, the display panel can be driven at a relatively high frequency, so that power consumption of the display panel cannot be effectively reduced.

[0005] In addition, when a moving image is displayed only on a portion of the display panel and an analog power voltage remains at a high level, the effect of reducing power consumption can not be significant. SUMMARY

[0006] Example embodiments of the present inventive concept provide a display apparatus that can reduce power consumption and improve display quality.

[0007] Example embodiments of the present inventive concept also provide a method of driving a display panel using the display apparatus.

[0008] In example embodiments of a display apparatus according to the present inventive concept, the display apparatus includes a display panel, a gate driver, a data driver, a driving controller, and a power voltage generator. The display panel includes gate lines, data lines, and pixels, and is configured to display an image based on input image data. The gate driver is configured to output gate signals to the gate lines. The data driver is configured to output data voltages to the data lines. The driving controller is configured to drive a plurality of display areas of the display panel at different driving frequencies. The power voltage generator is configured to output a data power voltage to the data driver. The driving controller is configured to output output data enable signals including a write period having valid signals and a hold period having invalid signals for the plurality of display areas, respectively. The power voltage generator is configured to generate the data power voltage having a high power voltage level during the write period and a low power voltage level in at least a portion of the hold period.

[0009] In an example embodiment, the drive controller can include a still image determiner configured to determine whether each of the plurality of display areas represents a still image or a moving image.

[0010] In an example embodiment, the drive controller can further include a drive frequency determiner configured to determine a drive frequency of the plurality of display areas based on a flicker value according to a gray scale value of input image data corresponding to the plurality of display areas.

[0011] In an example embodiment, the drive controller can be configured to determine whether each of the plurality of display areas is in a write period or in a hold period in a frame based on the drive frequency of the plurality of display areas. The drive controller can be configured to generate a multi-frequency signal having an active level during the write period and having an inactive level during the hold period.

[0012] In an example embodiment, the drive controller can be configured to generate a power control signal having a first level during the write period and having a second level in at least a part of the hold period.

[0013] In an example embodiment, when a first group of the plurality of display areas has the write period and a second group of the plurality of display areas has the hold period in the frame, the multi-frequency signal has the active level when the power control signal has the first level, and the multi-frequency signal has the inactive level when the power control signal has the second level.

[0014] In an example embodiment, when the display area is in the hold period, a period in which the power control signal has the second level can be shorter than a period in which the multi-frequency signal has the inactive level.

[0015] In an example embodiment, when the display area is in the hold period, a time point at which the power control signal changes from the first level to the second level can be later than a time point at which the multi-frequency signal changes from the active level to the inactive level. When the display area is in the hold period, a time point at which the power control signal changes from the second level to the first level in the hold period can be the same as a time point at which the multi-frequency signal changes from the inactive level to the active level.

[0016] In an example embodiment, when the display area is in the hold period, a time point at which the power control signal changes from the first level to the second level in the hold period can be later than a time point at which the multi-frequency signal changes from the active level to the inactive level. When the display area is in the hold period, a time point at which the power control signal changes from the second level to the first level in the hold period can be earlier than a time point at which the multi-frequency signal changes from the inactive level to the active level.

[0017] In an example embodiment, the drive controller can further include a fixed frequency determiner configured to determine whether the input frequency of the input image data has a normal type by counting a number of pulses of the vertical synchronization signal within one second.

[0018] In an example embodiment, the drive controller can further include a compensation frame inserter configured to insert a compensation frame between a frame of the first frequency and a frame of the second frequency when the drive frequency of the display area is changed from the first frequency to the second frequency by the drive frequency determiner.

[0019] In an example embodiment, the number of the plurality of display areas can be equal to or greater than three. The plurality of display areas can be driven at different frequencies from each other.

[0020] In an example embodiment, the sizes of the plurality of display areas can be different from each other.

[0021] In an example embodiment, the drive controller can be configured to determine the sizes of the plurality of display areas based on a flicker value for a gray scale value of the input image data and a boundary between a still image display area representing a still image and a moving image display area representing a moving image.

[0022] In an example embodiment, when the size of the display area is equal to or greater than a threshold value and the display area has a hold period, the data supply voltage can have a low supply voltage level in at least a portion of the hold period. When the size of the display area is less than the threshold value and the display area has a hold period, the data supply voltage can have a high supply voltage level during the hold period.

[0023] In an example embodiment, when the size of the display area is equal to or greater than a threshold value and the display area has a hold period, the data supply voltage can have a first low supply voltage level in at least a portion of the hold period. When the size of the display area is less than the threshold value and the display area has a hold period, the data supply voltage can have a second low supply voltage level greater than the first low supply voltage level and less than a high supply voltage level during the hold period.

[0024] In an example embodiment, the data power voltage can have a low power voltage level in at least a portion of the hold period of the current display area when the size of the current display area is equal to or greater than a threshold value and the current display area has a hold period. The data power voltage can have a low power voltage level in at least a portion of the hold period of the current display area when the size of the current display area is less than a threshold value, the current display area has a hold period, and the data power voltage has a low power voltage level for a previous display area. The data power voltage can have a high power voltage level during the hold period of the current display area when the size of the current display area is less than a threshold value, the current display area has a hold period, and the data power voltage does not have a low power voltage level for a previous display area.

[0025] In an example embodiment of a method of driving a display panel, the method includes independently determining driving frequencies of a plurality of display areas, generating output data enable signals including a write period having an active signal and a hold period having an inactive signal for the plurality of display areas, respectively, generating a data power voltage having a high power voltage level during the write period and having a low power voltage level in at least a portion of the hold period, outputting gate signals to gate lines of the display panel, and outputting data voltages to data lines of the display panel using input image data, the output data enable signals, and the data power voltage.

[0026] In an example embodiment, the method can further include determining whether each of the plurality of display areas represents a still image or a moving image.

[0027] In an example embodiment, the driving frequencies of the plurality of display areas can be determined based on a flicker value according to a gray value of input image data corresponding to the plurality of display areas.

[0028] According to the method of driving a display panel and the display apparatus for driving a display panel, the driving frequencies are determined according to images displayed on the display panel, so that power consumption of the display apparatus can be reduced. In addition, when the input image data includes a still image display area and a moving image display area, the still image display area and the moving image display area can be driven at different frequencies, so that power consumption of the display apparatus can be further reduced.

[0029] In addition, when a display area is in a hold period corresponding to a low frequency driving mode, a level of a data power voltage output to a data driver can be reduced, so that power consumption of the display apparatus can be reduced. BRIEF DESCRIPTION OF DRAWINGS

[0030] The above and other features and advantages of the present inventive concepts will become more apparent by describing in detail example embodiments thereof with reference to the attached drawings in which:

[0031] The above and other features and advantages of the present inventive concepts will become more apparent by describing in detail example embodiments thereof with reference to the attached drawings in which:Figure 1 is a block diagram showing a display device according to an example embodiment of the present inventive concept;

[0032] Figure 2 is a block diagram showing a drive controller of Figure 1 ;

[0033] Figure 3 is a timing chart showing an operation of a fixed frequency determiner of Figure 2 ;

[0034] Figure 4 is a conceptual diagram showing a display panel of Figure 1 including a first display area driven at a frequency of 120 Hz and a second display area driven at a frequency of 1 Hz;

[0035] Figure 5 is a timing chart showing a gate signal output from a gate driver during a first frame in the case of Figure 4 ;

[0036] Figure 6 is a timing chart showing a gate signal output from a gate driver during a second frame in the case of Figure 4 ;

[0037] Figure 7 is a timing chart showing input signals, generated signals, and output signals of a drive controller of Figure 1 and output signals of a power supply voltage generator of Figure 1 ;

[0038] Figure 8 is a timing chart showing input signals, generated signals, and output signals of a drive controller of Figure 1 and output signals of a power supply voltage generator of Figure 1 ;

[0039] Figure 9 is a table showing an example of a flicker value storage of Figure 2 ;

[0040] Figure 10 is a timing chart showing input signals, generated signals, and output signals of a drive controller of a display device and output signals of a power supply voltage generator of the display device according to an example embodiment of the present inventive concept;

[0041] Figure 11 is a timing chart showing input signals, generated signals, and output signals of a drive controller of a display device and output signals of a power supply voltage generator of the display device according to an example embodiment of the present inventive concept;

[0042] Figure 12is a block diagram of a driving controller of a display apparatus showing an example embodiment according to the present inventive concept;

[0043] Figure 13 is a conceptual diagram of a display panel of the display apparatus of Figure 1

[0044] Figure 14 is a timing chart showing a signal generated by the driving controller of Figure 13 Figure 12 Figure 1 is a timing chart showing an output voltage of a power supply voltage generator of the display apparatus of

[0045] Figure 15 is a timing chart showing a signal generated by the driving controller of the display apparatus according to the example embodiment of the present inventive concept corresponding to the display area and an output voltage of a power supply voltage generator of the display apparatus corresponding to the display area when the display panel includes eight display areas;

[0046] Figure 16 is a timing chart showing a signal generated by the driving controller of the display apparatus according to the example embodiment of the present inventive concept corresponding to the display area and an output voltage of a power supply voltage generator of the display apparatus corresponding to the display area when the display panel includes eight display areas; and

[0047] Figure 17 is a timing chart showing a signal generated by the driving controller of the display apparatus according to the example embodiment of the present inventive concept corresponding to the display area and an output voltage of a power supply voltage generator of the display apparatus corresponding to the display area when the display panel includes eight display areas. DETAILED DESCRIPTION

[0048] Hereinafter, the present inventive concept will be explained in detail with reference to the accompanying drawings.

[0049] Figure 1 is a block diagram of a display apparatus according to the example embodiment of the present inventive concept.

[0050] Referring to Figure 1 , the display apparatus includes a display panel 100 and a display panel driver. The display panel driver includes a driving controller 200, a gate driver 300, a gamma reference voltage generator 400, and a data driver 500. The display panel driver can further include a power supply voltage generator 600.

[0051] ​​​The driving controller 200 and the data driver 500 can be integrally formed in one integrated circuit chip. The driving controller 200, the gamma reference voltage generator 400, and the data driver 500 can be integrally formed in one integrated circuit chip. The driving controller 200, the gamma reference voltage generator 400, the data driver 500, and the power voltage generator 600 can be integrally formed in one integrated circuit chip. A driving module including at least the driving controller 200 and the data driver 500 integrally formed in one integrated circuit chip can be referred to as a timing controller embedded data driver (TED).

[0052] The display panel 100 includes a plurality of gate lines GL, a plurality of data lines DL, and a plurality of pixels connected to the gate lines GL and the data lines DL, respectively. The gate lines GL extend in a first direction D1, and the data lines DL extend in a second direction D2 crossing the first direction D1.

[0053] For example, the display panel 100 can be an organic light emitting display panel including an organic light emitting element.

[0054] The display panel 100 can be driven in a normal driving mode in which the display panel 100 is driven at a normal driving frequency and a low frequency driving mode in which the display panel 100 is driven at a frequency lower than the normal driving frequency.

[0055] For example, when the input image data represents a moving image, the display panel 100 can be driven in the normal driving mode. For example, when the input image data represents a still image, the display panel 100 can be driven in the low frequency driving mode. For example, when the display apparatus operates in an always-on mode, the display panel 100 can be driven in the low frequency driving mode.

[0056] Further, in the present example embodiment, a portion of the input image data representing a moving image can be driven in the normal driving mode, and another portion of the input image data representing a still image can be driven in the low frequency driving mode.

[0057] The display panel 100 can be driven in units of frames. The display panel 100 can be refreshed in each frame in the normal driving mode. Accordingly, the normal driving mode includes only a write period in which data is written in the pixels.

[0058] The display panel 100 can be refreshed in the low frequency driving mode at a frequency lower than a refresh frequency of the normal driving mode. Accordingly, one frame in the low frequency driving mode can include a write period in which data is written in the pixels and a hold period in which the written data is maintained without writing data in the pixels.

[0059] In the present exemplary embodiment, the display panel 100 can include a first portion having a write period and a second portion having a hold period in a single frame.

[0060] The driving controller 200 receives input image data IMG and input control signals CONT from an external device, such as a graphic controller of an IT product. The input image data IMG can include red image data, green image data, and blue image data. The input image data IMG can further include white image data. The input image data IMG can include magenta image data, yellow image data, and cyan image data. The input control signals CONT can include a main clock signal and a data enable signal (input data enable signal). The input control signals CONT can further include a vertical synchronization signal and a horizontal synchronization signal.

[0061] The driving controller 200 generates a first control signal CONT1, a second control signal CONT2, a third control signal CONT3, and a data signal DATA based on the input image data IMG and the input control signals CONT.

[0062] The driving controller 200 generates the first control signal CONT1 for controlling the operation of the gate driver 300 based on the input control signals CONT, and outputs the first control signal CONT1 to the gate driver 300. The first control signal CONT1 can include a vertical start signal and a gate clock signal.

[0063] The driving controller 200 generates the second control signal CONT2 for controlling the operation of the data driver 500 based on the input control signals CONT, and outputs the second control signal CONT2 to the data driver 500. The second control signal CONT2 can include a horizontal start signal and a load signal.

[0064] The driving controller 200 generates the data signal DATA based on the input image data IMG. The driving controller 200 outputs the data signal DATA to the data driver 500.

[0065] For example, the driving controller 200 can adjust a driving frequency of the display panel 100 based on the input image data IMG.

[0066] The driving controller 200 generates the third control signal CONT3 for controlling the operation of the gamma reference voltage generator 400 based on the input control signals CONT, and outputs the third control signal CONT3 to the gamma reference voltage generator 400.

[0067] Reference will now be made in detail to the structure and operation of the driving controller 200. Figures 2 to 9 Reference will now be made in detail to the structure and operation of the driving controller 200.

[0068] The gate driver 300 generates a gate signal that drives the gate line GL in response to a first control signal CONT1 received from the driving controller 200. The gate driver 300 outputs the gate signal to the gate line GL. For example, the gate driver 300 can sequentially output the gate signal to the gate line GL. The gate driver 300 can be mounted on the display panel 100. The gate driver 300 can be integrated on the display panel 100.

[0069] The gamma reference voltage generator 400 generates a gamma reference voltage VGREF in response to a third control signal CONT3 received from the driving controller 200. The gamma reference voltage generator 400 provides the gamma reference voltage VGREF to the data driver 500. The gamma reference voltage VGREF has a value corresponding to a level of the data signal DATA.

[0070] In an example embodiment, the gamma reference voltage generator 400 can be embedded in the driving controller 200, or embedded in the data driver 500.

[0071] The data driver 500 receives the second control signal CONT2 and the data signal DATA from the driving controller 200, and receives the gamma reference voltage VGREF from the gamma reference voltage generator 400. The data driver 500 converts the data signal DATA into a data voltage having an analog type using the gamma reference voltage VGREF. The data driver 500 outputs the data voltage to the data line DL.

[0072] The power voltage generator 600 can generate a data power voltage AVDD for driving the data driver 500, and output the data power voltage AVDD to the data driver 500. The power voltage generator 600 can also output the data power voltage AVDD to the gamma reference voltage generator 400.

[0073] Figure 2 is a block diagram illustrating Figure 1 the driving controller 200. Figure 3 is a timing chart illustrating Figure 2 the operation of the fixed frequency determiner 210.

[0074] Referring to Figures 1 to 3 , the driving controller 200 can include a still image determiner 220, a driving frequency determiner 230, and a flicker value storage 240. The driving controller 200 can also include the fixed frequency determiner 210. The driving controller 200 can also include a compensation frame inserter 250.

[0075] The fixed frequency determiner 210 can determine whether the input image data IMG has a normal input frequency. For example, the fixed frequency determiner 210 can determine whether the input frequency of the input image data IMG has a normal input frequency by counting the number of pulses of the horizontal synchronization signal HSYNC between the first and second pulses of the vertical synchronization signal VSYNC or by counting the number of pulses of the input data enable signal IDE between the first and second pulses of the vertical synchronization signal VSYNC.

[0076] The duration between the first and second pulses of the vertical synchronization signal VSYNC can be defined as one frame. When the input frequency of the input image data IMG is 120Hz, the number of pulses of the vertical synchronization signal VSYNC during one second can be 120.

[0077] When the number of pulses of the vertical synchronization signal VSYNC within one second is equal to the input frequency, the fixed frequency determiner 210 can determine that the input frequency of the input image data IMG has a normal type. Conversely, when the number of pulses of the vertical synchronization signal VSYNC within one second is not equal to the input frequency, the fixed frequency determiner 210 can determine that the input frequency of the input image data IMG does not have a normal type.

[0078] The fixed frequency determiner 210 can generate a frequency flag FF indicating whether the input frequency of the input image data IMG has a normal type. The fixed frequency determiner 210 can output the frequency flag FF to the driving frequency determiner 230. The driving frequency determiner 230 can determine a driving frequency of the display panel 100 in response to the frequency flag FF. For example, when the input frequency of the input image data IMG does not have a normal type, for example, when the input frequency of the input image data IMG has a low driving frequency, the driving frequency determiner 230 can not drive the switching elements in the pixels at the low driving frequency but at a normal driving frequency (e.g., 120Hz). When the input frequency of the input image data IMG has a low driving frequency and the display panel 100 is driven at the low driving frequency, an image displayed on the display panel 100 can have a display defect, for example, flicker. In addition, when the input frequency of the input image data IMG does not have a normal type, the still image determiner 220 can not operate because the driving frequency is fixed to a normal driving frequency when the input frequency of the input image data IMG does not have a normal type.

[0079] Figure 4 is a conceptual diagram illustrating the display panel 100 including a first display area Z1 driven at a frequency of 120Hz and a second display area Z2 driven at a frequency of 1Hz. Figure 1 is a conceptual diagram illustrating the display panel 100 including a first display area Z1 driven at a frequency of 120Hz and a second display area Z2 driven at a frequency of 1Hz. Figure 5 is a conceptual diagram illustrating the display panel 100 including a first display area Z1 driven at a frequency of 120Hz and a second display area Z2 driven at a frequency of 1Hz. Figure 4a timing chart of the gate signal output from the gate driver 300 during the first frame in the case where the input image data IMG corresponding to the first display region Z1 represents a still image. Figure 6 is a timing chart of the gate signal output from the gate driver 300 during the second frame in the case where the input image data IMG corresponding to the second display region Z2 represents a still image. Figure 4 is a timing chart of the gate signal output from the gate driver 300 during the second frame in the case where the input image data IMG corresponding to the second display region Z2 represents a still image. Figure 7 is a timing chart of the gate signal output from the gate driver 300 during the second frame in the case where the input image data IMG corresponding to the second display region Z2 represents a still image. Figure 1 is a timing chart of the gate signal output from the gate driver 300 during the second frame in the case where the input image data IMG corresponding to the second display region Z2 represents a still image. Figure 1 is a timing chart of the gate signal output from the gate driver 300 during the second frame in the case where the input image data IMG corresponding to the second display region Z2 represents a still image.

[0080] Referring to Figures 1 to 7 , the display panel 100 can include a plurality of display regions. In the present example embodiment, the display panel 100 can include a first display region Z1 and a second display region Z2.

[0081] The drive controller 200 can drive the display regions Z1 and Z2 of the display panel 100 at different drive frequencies RDATA1 and RDATA2. The drive controller 200 can independently determine the drive frequencies RDATA1 and RDATA2 of the display regions Z1 and Z2 of the display panel 100.

[0082] When the input image data IMG corresponding to the first display region Z1 represents a still image, the drive controller 200 can determine a first drive frequency of the first display region Z1 based on a flicker value according to a gray value of the input image data IMG, and generate a data signal of the first drive frequency corresponding to the first display region Z1.

[0083] When the input image data IMG corresponding to the second display region Z2 represents a still image, the drive controller 200 can determine a second drive frequency of the second display region Z2 based on a flicker value according to a gray value of the input image data IMG, and generate a data signal of the second drive frequency corresponding to the second display region Z2.

[0084] The still image determiner 220 can determine whether the display areas Z1 and Z2 represent still images or moving images, respectively. The still image determiner 220 can output a flag signal SF representing whether the display areas Z1 and Z2 represent still images or moving images. The still image determiner 220 can output the flag signal SF to the driving frequency determiner 230. For example, when the display areas Z1 and Z2 represent still images, the still image determiner 220 can output a flag signal SF of 1 to the driving frequency determiner 230. When the display areas Z1 and Z2 represent moving images, the still image determiner 220 can output a flag signal SF of 0 to the driving frequency determiner 230. When the display panel 100 is operated in a normal mode in which a user is allowed to customize a display screen to display time, date, battery status, notifications, a screen saver, etc., the still image determiner 220 can output a flag signal SF of 1 to the driving frequency determiner 230.

[0085] For example, the driving frequency determiner 230 can drive the switching elements of the pixels of the display area having the flag signal SF of 1 at a low driving frequency. The driving frequency determiner 230 can drive the switching elements of the pixels of the display area having the flag signal SF of 0 at a normal driving frequency.

[0086] The driving frequency determiner 230 can determine the driving frequencies of the display areas Z1 and Z2 based on the flicker values according to the gray values of the input image data IMG corresponding to the display areas Z1 and Z2.

[0087] The driving frequency determiner 230 can refer to the flicker value storage 240 to determine the frequency to be used for the low driving frequency. The flicker value storage 240 can include flicker values representing the degree of flicker according to the gray values of the input image data IMG.

[0088] The flicker value storage 240 can store the gray values of the input image data IMG and the flicker values corresponding to the gray values. The flicker value corresponding to the gray value means the degree of flicker perceived by a user when an image has the gray value. When the flicker value is high, the flicker can not be perceived by a user only when the display panel 100 is driven at a relatively high driving frequency.

[0089] Accordingly, when the flicker value corresponding to the gray value is high, the driving frequency determiner 230 can determine the driving frequency of the display panel 100 to be high. In contrast, when the flicker value corresponding to the gray value is low, the driving frequency determiner 230 can determine the driving frequency of the display panel 100 to be low.

[0090] When the driving frequency of a display area (e.g., Z1 and Z2) is changed from a first frequency to a second frequency higher than the first frequency by the driving frequency determiner 230, the compensation frame inserter 250 can insert at least one compensation frame between adjacent frames of the first frequency.

[0091] For example, the compensation frame inserter 250 can independently operate with respect to the display areas Z1 and Z2. When the driving frequency of the first display area Z1 changes from a first frequency to a second frequency higher than the first frequency, the compensation frame inserter 250 can insert a compensation frame between adjacent frames of the first frequency, thereby making the image have the second frequency higher than the first frequency. When the driving frequency of the first display area Z1 changes from a third frequency to a fourth frequency higher than the third frequency, the compensation frame inserter 250 can insert a compensation frame between adjacent frames of the third frequency, thereby making the image have the fourth frequency higher than the third frequency.

[0092] The compensation frame inserter 250 can determine a frequency of the compensation frame and a number of the compensation frame. For example, when the driving frequency of the first display area Z1 changes from a first frequency to a second frequency lower than the first frequency, the frequency of the compensation frame can be determined to have a value between the first frequency and the second frequency. For example, when the driving frequency changes from 60 Hz to 10 Hz, the frequency of the compensation frame can be determined to be one of 30 Hz, 20 Hz, and 15 Hz. For example, when the driving frequency changes from 60 Hz to 1 Hz, the frequency of the compensation frame can be determined to be one of 30 Hz, 20 Hz, 15 Hz, 10 Hz, 5 Hz, and 2 Hz. The compensation frame inserter 250 can determine a plurality of frequencies of the compensation frame.

[0093] The compensation frame inserter 250 can determine the number of the compensation frame based on a difference between the first frequency and the second frequency. For example, when the difference between the first frequency and the second frequency is small, the number of the compensation frame can be small. In contrast, when the difference between the first frequency and the second frequency is large, the number of the compensation frame can be large.

[0094] In Figures 4 to 7 For example, the driving frequency determiner 230 can determine that the driving frequency of the first display area Z1 is 120 Hz and the driving frequency of the second display area Z2 is 1 Hz.

[0095] The gate driver 300 can output a first gate signal group G11 to G1N corresponding to the first display area Z1 and a second gate signal group G21 to G2N corresponding to the second display area Z2.

[0096] The gate driver 300 can stop output of at least one of the first gate signal group G11 to G1N and the second gate signal group G21 to G2N based on the driving frequency of the first display area Z1 and the driving frequency of the second display area Z2.

[0097] For example, when the driving frequency of the first display area Z1 is 120 Hz and the driving frequency of the second display area Z2 is 1 Hz, the first display area Z1 can have one hundred and twenty write periods within one second, and the second display area Z2 can have one write period and one hundred and nineteen hold periods within one second.

[0098] When the first display area Z1 has a write period, the first gate signal group G11 to G1N corresponding to the first display area Z1 can be enabled. When the first display area Z1 has a hold period, the first gate signal group G11 to G1N corresponding to the first display area Z1 can be disabled. For example, the first gate signal group G11 to G1N can be disabled by a masking method.

[0099] When the second display area Z2 has a write period, the second gate signal group G21 to G2N corresponding to the second display area Z2 can be enabled. When the second display area Z2 has a hold period, the second gate signal group G21 to G2N corresponding to the second display area Z2 can be disabled. For example, the second gate signal group G21 to G2N can be disabled by a masking method.

[0100] For example, Figure 5 represents a first frame and the first display area Z1 has a write period in the first frame and the second display area Z2 has a write period in the first frame. Accordingly, the first gate signal group G11 to G1N and the second gate signal group G21 to G2N can be enabled in the first frame.

[0101] For example, Figure 6 represents a second frame and the first display area Z1 has a write period in the second frame but the second display area Z2 has a hold period in the second frame. Accordingly, the first gate signal group G11 to G1N can be enabled in the second frame but the second gate signal group G21 to G2N can be disabled in the second frame.

[0102] As shown in FIG. 2A, Figure 7 The driving controller 200 can receive an input vertical start signal IVS and an input data enable signal IDE, as shown in FIG. 2B. The input vertical start signal IVS can have a period of a frame (e.g., 1F to 121F in FIG. 2B). The input data enable signal IDE can have a period of a horizontal line period. Figure 7

[0103] The driving frequency determiner 230 can determine driving frequencies of the display areas Z1 and Z2, and determine whether each of the display areas Z1 and Z2 is in a write period W or in a hold period H based on the driving frequencies of the display areas Z1 and Z2.

[0104] ​The driving frequency determiner 230 can generate a multi-frequency signal MFD representing whether each of the display areas Z1 and Z2 is in a write period W or in a hold period H based on driving frequencies of the display areas Z1 and Z2.

[0105] The multi-frequency signal MFD can have an active level during the write period W. The multi-frequency signal MFD can have an inactive level during the hold period H.

[0106] The driving controller 200 can generate an output data enable signal ODE representing an active state of the data signal DATA based on the multi-frequency signal MFD.

[0107] The output data enable signal ODE has the active level when the multi-frequency signal MFD has the active level. The output data enable signal ODE has the inactive level when the multi-frequency signal MFD has the inactive level.

[0108] For example, the output data enable signal ODE can have the same pulse as a pulse of the input data enable signal IDE when the multi-frequency signal MFD has the active level. In contrast, the output data enable signal ODE can be generated by masking the input data enable signal IDE when the multi-frequency signal MFD has the inactive level.

[0109] The first display area Z1 is driven at a frequency of 120Hz such that the multi-frequency signal MFD can have the write period W corresponding to the first display area Z1 in the first frame to the first one hundred and twenty frame. The second display area Z2 is driven at a frequency of 1Hz such that the multi-frequency signal MFD can have the write period W in the first frame and have the hold period H in the second frame to the first one hundred and twenty frame.

[0110] When the driving frequencies of the display areas Z1 and Z2 are constant, Figure 7 waveforms of signals in the first frame to the first one hundred and twenty frame of Equation 1 can be repeated in the first one hundred and twenty one frame to the second two hundred and forty frame.

[0111] When the second display area Z2 has the hold period H, a pulse of a gate signal corresponding to the second display area Z2 can not be outputted as described with reference to FIG. 2B, and a pulse of an output data enable signal ODE corresponding to the second display area Z2 can not be outputted as described with reference to FIG. 2C. Figure 6 Figure 7 When the second display area Z2 has the hold period H, a pulse of a gate signal corresponding to the second display area Z2 can not be outputted as described with reference to FIG. 2B, and a pulse of an output data enable signal ODE corresponding to the second display area Z2 can not be outputted as described with reference to FIG. 2C.

[0112] In the present exemplary embodiment, when the second display area Z2 has the hold period H, a data supply voltage AVDD applied to the data driver 500 can be turned off such that power consumption of the data driver 500 can be reduced.

[0113] When the data supply voltage AVDD is turned off, power consumption of the gamma reference voltage generator 400 can also be reduced.​

[0114] In the present example embodiment, the data supply voltage AVDD can have a high supply voltage level during the write period W and a low supply voltage level during the hold period H.

[0115] The drive frequency determiner 230 can generate a supply control signal WFC that controls the data supply voltage AVDD to be a high supply voltage level or a low supply voltage level based on the drive frequencies of the display regions Z1 and Z2. The supply control signal WFC can have a first level for setting the data supply voltage AVDD to be a high supply voltage level and a second level for setting the data supply voltage AVDD to be a low supply voltage level.

[0116] In the present example embodiment, when some display regions have the write period W and other display regions have the hold period H in a frame, the supply control signal WFC can have a first level corresponding to the period in which the multi-frequency signal MFD has an active level, and the supply control signal WFC can have a second level corresponding to the period in which the multi-frequency signal MFD has an inactive level. For example, when some display regions have the write period W and other display regions have the hold period H in a frame, the period in which the supply control signal WFC has the first level can be equal to the period in which the multi-frequency signal MFD has the active level, and the period in which the supply control signal WFC has the second level can be equal to the period in which the multi-frequency signal MFD has the inactive level.

[0117] Figure 8 is a timing diagram showing the input signals, the generated signals, and the output signals of the drive controller 200 of Figure 1 and the output signals of the supply voltage generator 600 of Figure 1 .

[0118] Referring to Figures 1 to 8 , for example, in Figure 8 , the drive frequency determiner 230 can determine the drive frequency of the first display region Z1 to be 120 Hz and determine the drive frequency of the second display region Z2 to be 60 Hz.

[0119] The first display region Z1 is driven at a frequency of 120 Hz so that the multi-frequency signal MFD can have the write period W corresponding to the first display region Z1 in the first frame to the first one hundred and twenty frame. The second display region Z2 is driven at a frequency of 60 Hz so that the multi-frequency signal MFD can have the write period W corresponding to the second display region Z2 in odd frames, e.g., the first frame, the third frame, …, and the first one hundred and nineteen frame, and have the hold period H corresponding to the second display region Z2 in even frames, e.g., the second frame, the fourth frame, …, and the first one hundred and twenty frame.

[0120] When the driving frequencies of display areas Z1 and Z2 remain unchanged, Figure 8 The waveforms of the signals in the first to the 120th frames can be repeated in the 121st to the 240th frames.

[0121] The drive frequency determiner 230 can generate a power control signal WFC based on the drive frequencies of display areas Z1 and Z2, which controls the data power supply voltage AVDD to a high or low power supply voltage level. For example... Figure 8 As shown, the waveform of the power control signal WFC can be basically the same as the waveform of the multi-frequency signal MFD.

[0122] Figure 9 It is shown Figure 2 A table of examples of the flash value memory 240.

[0123] Reference Figures 1 to 9 The flicker value memory 240 can store the grayscale values ​​of the input image data IMG and the flicker values ​​corresponding to the grayscale values ​​used to determine the driving frequency of the display panel 100. For example, the flicker value memory 240 can be a lookup table.

[0124] exist Figure 9 In the input image data IMG, the input grayscale value can be 8 bits, the minimum grayscale value of the input image data IMG can be 0, and the maximum grayscale value of the input image data IMG can be 255. The number of flicker setting levels in the flicker value memory 240 can be 64. When the number of flicker setting levels increases, flicker can be effectively eliminated, but the logic size of the drive controller 200 also increases. Therefore, the number of flicker setting levels is limited.

[0125] Although the input grayscale value is Figure 9 It has an 8-bit value, but the concept of the present invention is not limited thereto.

[0126] exist Figure 9In this case, the number of gray scale values of the input image data IMG is 256 and the number of flicker setting levels is 64, so that a single flicker value in the flicker value storage 240 can correspond to four gray scale values. For example, the first flicker setting level stores a flicker value 0 for gray scale values 0 to 3. Here, the flicker value 0 can indicate a driving frequency of 1 Hz. For example, the second flicker setting level stores a flicker value 0 for gray scale values 4 to 7. Here, the flicker value 0 can indicate a driving frequency of 1 Hz. For example, the third flicker setting level stores a flicker value 40 for gray scale values 8 to 11. Here, the flicker value 40 can indicate a driving frequency of 2 Hz. For example, the fourth flicker setting level stores a flicker value 80 for gray scale values 12 to 15. Here, the flicker value 80 can indicate a driving frequency of 5 Hz. For example, the fifth flicker setting level stores a flicker value 120 for gray scale values 16 to 19. Here, the flicker value 120 can indicate a driving frequency of 10 Hz. For example, the sixth flicker setting level stores a flicker value 160 for gray scale values 20 to 23. Here, the flicker value 160 can indicate a driving frequency of 30 Hz. For example, the seventh flicker setting level stores a flicker value 200 for gray scale values 24 to 27. Here, the flicker value 200 can indicate a driving frequency of 60 Hz. For example, the sixty-second flicker setting level stores a flicker value 0 for gray scale values 244 to 247. Here, the flicker value 0 can indicate a driving frequency of 1 Hz. For example, the sixty-third flicker setting level stores a flicker value 0 for gray scale values 248 to 251. Here, the flicker value 0 can indicate a driving frequency of 1 Hz. For example, the sixty-fourth flicker setting level stores a flicker value 0 for gray scale values 252 to 255. Here, the flicker value 0 can indicate a driving frequency of 1 Hz.

[0127] According to the present example embodiment, the driving frequency is determined according to the image displayed on the display panel 100, so that the power consumption of the display apparatus can be reduced. Further, when the input image data IMG includes a still image display region and a moving image display region, the still image display region and the moving image display region can be driven at different frequencies, so that the power consumption of the display apparatus can be further reduced.

[0128] Further, when the display region has a hold period H corresponding to the low frequency driving mode, the level of the data supply voltage AVDD output to the data driver 500 during the hold period H can be reduced, so that the power consumption of the display apparatus can be reduced.

[0129] Figure 10 FIG. 7 is a timing chart showing input signals, generated signals, and output signals of the driving controller 200 of the display apparatus according to the example embodiment of the present inventive concept, and output signals of the power supply voltage generator 600 of the display apparatus.

[0130] The display device and the method of driving a display panel according to the present example embodiment are substantially the same as those of the previously described example embodiment except for the waveforms of the power supply control signal and the waveforms of the data power supply voltage. Figures 1 to 9 The display device and the method of driving a display panel of the previously described example embodiment are substantially the same. Therefore, the same reference numerals will be used to refer to the same or similar parts as those described in the previously described example embodiment, and any repeated explanation regarding the above parts will be omitted. Figures 1 to 9 The display device and the method of driving a display panel of the previously described example embodiment are substantially the same. Therefore, the same reference numerals will be used to refer to the same or similar parts as those described in the previously described example embodiment, and any repeated explanation regarding the above parts will be omitted.

[0131] Referring to Figures 1 to 6 , Figure 9 and Figure 10 , the display device includes a display panel 100 and a display panel driver. The display panel driver includes a driving controller 200, a gate driver 300, a gamma reference voltage generator 400, and a data driver 500. The display panel driver can further include a power supply voltage generator 600.

[0132] The driving controller 200 can include a still image determiner 220, a driving frequency determiner 230, and a flicker value storage 240. The driving controller 200 can further include a fixed frequency determiner 210. The driving controller 200 can further include a compensation frame inserter 250.

[0133] The display panel 100 can include a plurality of display areas. In the present example embodiment, the display panel 100 can include a first display area Z1 and a second display area Z2.

[0134] The driving controller 200 can drive the display areas Z1 and Z2 of the display panel 100 at different driving frequencies. The driving controller 200 can independently determine the driving frequencies of the display areas Z1 and Z2 of the display panel 100.

[0135] The driving frequency determiner 230 can generate a multi-frequency signal MFD representing whether the display areas Z1 and Z2 have a write period W or a hold period H in a frame based on the driving frequencies of the display areas Z1 and Z2.

[0136] In the present example embodiment, when the second display area Z2 has the hold period H, the data power supply voltage AVDD applied to the data driver 500 can be turned off, so that the power consumption of the data driver 500 can be reduced.

[0137] In the present example embodiment, the data power supply voltage AVDD can have a high power supply voltage level during the write period W and a low power supply voltage level during the hold period H.

[0138] The drive frequency determiner 230 can generate a power control signal WFC that controls the data power supply voltage AVDD to be a high power supply voltage level or a low power supply voltage level, based on the drive frequencies of the display regions Z1 and Z2. The power control signal WFC can have a first level for setting the data power supply voltage AVDD to be the high power supply voltage level and a second level for setting the data power supply voltage AVDD to be the low power supply voltage level.

[0139] In the present example embodiment, in the hold period H, the period WD2 in which the power control signal WFC has the second level can be shorter than the period WD1 in which the multi-frequency signal MFD has the inactive level.

[0140] For example, in the hold period H, the point in time at which the power control signal WFC changes from the first level (high level) to the second level (low level) can be later than the point in time at which the multi-frequency signal MFD changes from the active level to the inactive level. For example, in the hold period H, the point in time at which the power control signal WFC changes from the second level to the first level can be the same as the point in time at which the multi-frequency signal MFD changes from the inactive level to the active level.

[0141] The point in time at which the power control signal WFC turns off the data power supply voltage AVDD can be set to be later than the point in time at which the multi-frequency signal MFD changes from the active level to the inactive level, so that it is possible to prevent unexpected degradation of the display panel 100 due to turning off of the data power supply voltage AVDD.

[0142] According to the present example embodiment, the drive frequency is determined in accordance with the image displayed on the display panel 100, so that it is possible to reduce the power consumption of the display device. Furthermore, when the input image data IMG includes a still image display region and a moving image display region, the still image display region and the moving image display region can be driven at different frequencies, so that it is possible to further reduce the power consumption of the display device. For example, the still image display region can be driven at a frequency lower than the frequency of the moving image display region.

[0143] Furthermore, when the display region has a hold period H corresponding to a low frequency drive mode, it is possible to reduce the level of the data power supply voltage AVDD output to the data driver 500 during the hold period H, so that it is possible to reduce the power consumption of the display device.

[0144] Figure 11 is a timing chart showing input signals, generated signals, and output signals of the drive controller 200 of the display device according to the example embodiment of the present inventive concept, and output signals of the power supply voltage generator 600 of the display device.

[0145] In addition to the waveforms of the power control signal and the data power supply voltage, the display device and the method of driving a display panel according to the present example embodiment are the same as those described with reference to Figures 1 to 9The display apparatus and the method of driving a display panel of the previous example embodiment of the description are substantially the same. Therefore, the same reference numerals will be used to refer to the parts which are the same as or similar to those described in the previous example embodiment, and any repeated explanation about the above parts will be omitted. Figures 1 to 9 The display apparatus and the method of driving a display panel of the previous example embodiment of the description are substantially the same. Therefore, the same reference numerals will be used to refer to the parts which are the same as or similar to those described in the previous example embodiment, and any repeated explanation about the above parts will be omitted.

[0146] Referring to Figures 1 to 6 , Figure 9 and Figure 11 , the display apparatus includes a display panel 100 and a display panel driver. The display panel driver includes a driving controller 200, a gate driver 300, a gamma reference voltage generator 400, and a data driver 500. The display panel driver can further include a supply voltage generator 600.

[0147] The driving controller 200 can include a still image determiner 220, a driving frequency determiner 230, and a flicker value storage 240. The driving controller 200 can further include a fixed frequency determiner 210. The driving controller 200 can further include a compensation frame inserter 250.

[0148] The display panel 100 can include a plurality of display areas. In the present example embodiment, the display panel 100 can include a first display area Z1 and a second display area Z2.

[0149] The driving controller 200 can drive the display areas Z1 and Z2 of the display panel 100 at different driving frequencies. The driving controller 200 can independently determine the driving frequencies of the display areas Z1 and Z2 of the display panel 100.

[0150] The driving frequency determiner 230 can generate a multi-frequency signal MFD representing whether the display areas Z1 and Z2 have a write period W or a hold period H in a frame based on the driving frequencies of the display areas Z1 and Z2.

[0151] In the present example embodiment, when the second display area Z2 has the hold period H, a data supply voltage AVDD applied to the data driver 500 can be turned off, so that power consumption of the data driver 500 can be reduced.

[0152] In the present example embodiment, the data supply voltage AVDD can have a high supply voltage level during the write period W and a low supply voltage level during the hold period H.

[0153] The drive frequency determiner 230 can generate a power control signal WFC that controls the data power supply voltage AVDD to be a high power supply voltage level or a low power supply voltage level, based on the drive frequencies of the display regions Z1 and Z2. The power control signal WFC can have a first level for setting the data power supply voltage AVDD to be the high power supply voltage level and a second level for setting the data power supply voltage AVDD to be the low power supply voltage level.

[0154] In the present example embodiment, the period WD3 in which the power control signal WFC has the second level can be shorter than the period WD1 in which the multi-frequency signal MFD has the inactive level, in the hold period H.

[0155] For example, in the hold period H, the point in time at which the power control signal WFC changes from the first level (high level) to the second level (low level) can be later than the point in time at which the multi-frequency signal MFD changes from the active level to the inactive level. For example, in the hold period H, the point in time at which the power control signal WFC changes from the second level to the first level can be earlier than the point in time at which the multi-frequency signal MFD changes from the inactive level to the active level.

[0156] The point in time at which the power control signal WFC turns off the data power supply voltage AVDD can be set to be later than the point in time at which the multi-frequency signal MFD changes from the active level to the inactive level, and the point in time at which the power control signal WFC turns on the data power supply voltage AVDD again can be set to be earlier than the point in time at which the multi-frequency signal MFD changes from the inactive level to the active level again, so that it is possible to prevent unexpected degradation of the display panel 100 due to turning off of the data power supply voltage AVDD or due to rapid turning off of the data power supply voltage AVDD.

[0157] According to the present example embodiment, the drive frequency is determined in accordance with the image displayed on the display panel 100, so that it is possible to reduce the power consumption of the display device. Furthermore, when the input image data IMG includes a still image display region and a moving image display region, the still image display region and the moving image display region can be driven at different frequencies, so that it is possible to further reduce the power consumption of the display device.

[0158] Furthermore, when the display region has a hold period H corresponding to a low frequency drive mode, it is possible to reduce the level of the data power supply voltage AVDD output to the data driver 500 during the hold period H, so that it is possible to reduce the power consumption of the display device.

[0159] Figure 12 is a block diagram illustrating a drive controller 200 of a display device according to an example embodiment of the present inventive concept. Figure 13 is a conceptual diagram of a display panel 100 of a display device according to an example embodiment of the present inventive concept. Figure 1 is a conceptual diagram of a display panel 100 of a display device according to an example embodiment of the present inventive concept. Figure 14 is a conceptual diagram of a display panel 100 of a display device according to an example embodiment of the present inventive concept.Figure 13 corresponding to the display regions Z1 to Z8 of the display device 1 Figure 12 the generated signals of the drive controller 200 and Figure 1 a timing chart of the output voltage of the power supply voltage generator 600 of the display device.

[0160] The display device and the method of driving a display panel according to the present example embodiment are substantially the same as the display device and the method of driving a display panel of the previous example embodiment described with reference to Figures 1 to 9 the same reference numerals will be used to refer to the same or similar parts as those described in the previous example embodiment, and any repeated explanation regarding the above parts will be omitted. Figures 1 to 9 the same reference numerals will be used to refer to the same or similar parts as those described in the previous example embodiment, and any repeated explanation regarding the above parts will be omitted.

[0161] With reference to Figure 1 and Figures 12 to 14 , the display device includes a display panel 100 and a display panel driver. The display panel driver includes a drive controller 200, a gate driver 300, a gamma reference voltage generator 400, and a data driver 500. The display panel driver can further include a power supply voltage generator 600.

[0162] The drive controller 200 can include a still image determiner 220A, a drive frequency determiner 230A, and a flicker value storage 240. The drive controller 200 can further include a fixed frequency determiner 210. The drive controller 200 can further include a compensation frame inserter 250.

[0163] The display panel 100 can include a plurality of display regions. In the present example embodiment, the display panel 100 can include a first display region Z1 to an eighth display region Z8.

[0164] In the present example embodiment, the sizes of some of the first display region Z1 to the eighth display region Z8 can be different from each other.

[0165] For example, the drive controller 200 can determine the sizes of the display regions based on the boundaries between the still image display regions representing still images and the moving image display regions representing moving images and the flicker values for the gray scale values of the input image data IMG.

[0166] The drive controller 200 can drive the display regions Z1 to Z8 of the display panel 100 at different drive frequencies RDATA1 to RDATAM. The drive controller 200 can independently determine the drive frequencies RDATA1 to RDATAM of the display regions Z1 to Z8 of the display panel 100.

[0167] The drive frequency determiner 230A can determine whether the display regions Z1 to Z8 have the write period W or the hold period H based on the drive frequencies of the display regions Z1 to Z8.

[0168] In the present example embodiment, when the display region has the hold period H, the data supply voltage AVDD applied to the data driver 500 during the hold period H can be turned off, so that the power consumption of the data driver 500 can be reduced.

[0169] The drive frequency determiner 230A can generate a power control signal WFC that controls the data supply voltage AVDD to be a high supply voltage level or a low supply voltage level based on the drive frequencies of the display regions Z1 to Z8. The power control signal WFC can have a first level LH for setting the data supply voltage AVDD to the high supply voltage level VON and a second level LL for setting the data supply voltage AVDD to the low supply voltage level VOFF.

[0170] In the present example embodiment, when the display region has the hold period H, the data supply voltage AVDD applied to the data driver 500 during the hold period H can be turned off, so that the power consumption of the data driver 500 can be reduced. Figure 14

[0171] According to the present example embodiment, the drive frequencies are determined in accordance with the image displayed on the display panel 100, so that the power consumption of the display apparatus can be reduced. Further, when the input image data IMG includes a still image display region and a moving image display region, the still image display region and the moving image display region can be driven at different frequencies, so that the power consumption of the display apparatus can be further reduced.

[0172] Further, when the display region has the hold period H corresponding to the low frequency drive mode, the level of the data supply voltage AVDD output to the data driver 500 during the hold period H can be reduced, so that the power consumption of the display apparatus can be reduced.

[0173] Figure 15 is a timing chart showing the generated signals of the drive controller of the display apparatus according to the example embodiment of the present inventive concept corresponding to the display regions and the output voltages of the power supply voltage generator of the display apparatus when the display panel includes eight display regions.

[0174] The display apparatus and the method of driving the display panel according to the present example embodiment are substantially the same as the display apparatus and the method of driving the display panel described with reference to the previous example embodiments except for the waveforms of the power control signal and the waveform of the data supply voltage. Figures 12 to 14 Therefore, the same reference numerals will be used to refer to the parts that are the same as or similar to those described in the previous example embodiments, and any repeated explanation regarding the above parts will be omitted. Figures 12 to 14

[0175] Referring to​​Figure 1 、 Figure 12 、 Figure 13 and Figure 15 The display apparatus includes a display panel 100 and a display panel driver. The display panel driver includes a driving controller 200, a gate driver 300, a gamma reference voltage generator 400, and a data driver 500. The display panel driver can further include a supply voltage generator 600.

[0176] The driving controller 200 can include a still image determiner 220A, a driving frequency determiner 230A, and a flicker value storage 240. The driving controller 200 can further include a fixed frequency determiner 210. The driving controller 200 can further include a compensation frame inserter 250.

[0177] The display panel 100 can include a plurality of display areas. In the present example embodiment, the display panel 100 can include a first display area Z1 to an eighth display area Z8.

[0178] In the present example embodiment, the sizes of the first display area Z1 to the eighth display area Z8 can be different from each other.

[0179] The driving controller 200 can drive the display areas Z1 to Z8 of the display panel 100 at different driving frequencies RDATA1 to RDATAM. The driving controller 200 can independently determine the driving frequencies RDATA1 to RDATAM of the display areas Z1 to Z8 of the display panel 100.

[0180] The driving frequency determiner 230A can determine whether the display areas Z1 to Z8 have a write period W or a hold period H based on the driving frequencies of the display areas Z1 to Z8.

[0181] In the present example embodiment, when the display areas have the hold period H, a data supply voltage AVDD applied to the data driver 500 during the hold period H can be turned off, so that power consumption of the data driver 500 can be reduced.

[0182] In the present example embodiment, the turning off of the data supply voltage AVDD can be determined according to the sizes of the display areas Z1 to Z8.

[0183] For example, when the sizes of the display areas Z1 to Z8 are equal to or greater than a threshold value and the display areas Z1 to Z8 have the hold period H, the data supply voltage AVDD can have a low supply voltage level VOFF in at least a portion of the hold period H.

[0184] In contrast, when the sizes of the display areas Z1 to Z8 are less than the threshold value and the display areas Z1 to Z8 have the hold period H, the data supply voltage AVDD can have a high supply voltage level VON during the hold period H.

[0185] For example, in Figure 15 , the sizes of the display regions Z1, Z2, and Z5 can be equal to or greater than a threshold value, and the sizes of the display regions Z3, Z4, Z6, Z7, and Z8 can be less than the threshold value.

[0186] According to the present example embodiment, the driving frequency is determined according to the image displayed on the display panel 100, so that the power consumption of the display apparatus can be reduced. In addition, when the input image data IMG includes a still image display region and a moving image display region, the still image display region and the moving image display region can be driven at different frequencies, so that the power consumption of the display apparatus can be further reduced.

[0187] In addition, when the display region has a hold period H corresponding to the low frequency driving mode, the level of the data supply voltage AVDD output to the data driver 500 during the hold period H can be reduced, so that the power consumption of the display apparatus can be reduced.

[0188] Figure 16 is a timing chart showing the generated signals of the driving controller of the display apparatus according to the example embodiment of the present inventive concept corresponding to the display regions and the output voltages of the power supply voltage generator of the display apparatus when the display panel includes eight display regions.

[0189] The display apparatus and the method of driving a display panel according to the present example embodiment are substantially the same as the display apparatus and the method of driving a display panel described with reference to the previous example embodiments except for the waveforms of the power supply control signals and the waveforms of the data supply voltages. Figures 12 to 14 Therefore, the same reference numerals will be used to refer to the same or similar parts as those described in the previous example embodiments, and any repeated explanation about the above parts will be omitted. Figures 12 to 14 Therefore, the same reference numerals will be used to refer to the same or similar parts as those described in the previous example embodiments, and any repeated explanation about the above parts will be omitted.

[0190] Referring to Figure 1 , Figure 12 , Figure 13 and Figure 16 , the display apparatus includes a display panel 100 and a display panel driver. The display panel driver includes a driving controller 200, a gate driver 300, a gamma reference voltage generator 400, and a data driver 500. The display panel driver can further include a power supply voltage generator 600.

[0191] The driving controller 200 can include a still image determiner 220A, a driving frequency determiner 230A, and a flicker value storage 240. The driving controller 200 can further include a fixed frequency determiner 210. The driving controller 200 can further include a compensation frame inserter 250.

[0192] The display panel 100 can include a plurality of display areas. In the present example embodiment, the display panel 100 can include a first display area Z1 to an eighth display area Z8.

[0193] In the present example embodiment, the sizes of the first display area Z1 to the eighth display area Z8 can be different from each other.

[0194] The drive controller 200 can drive the display areas Z1 to Z8 of the display panel 100 at different drive frequencies RDATA1 to RDATAM. The drive controller 200 can independently determine the drive frequencies RDATA1 to RDATAM of the display areas Z1 to Z8 of the display panel 100.

[0195] The drive frequency determiner 230A can determine whether the display areas Z1 to Z8 have a write period W or a hold period H based on the drive frequencies of the display areas Z1 to Z8.

[0196] In the present example embodiment, when the display areas have the hold period H, the data supply voltage AVDD applied to the data driver 500 during the hold period H can be turned off or reduced, so that the power consumption of the data driver 500 can be reduced.

[0197] In the present example embodiment, the turning off of the data supply voltage AVDD can be determined according to the sizes of the display areas Z1 to Z8.

[0198] For example, when the sizes of the display areas Z1 to Z8 are equal to or greater than a threshold value and the display areas Z1 to Z8 have the hold period H, the data supply voltage AVDD can have a first low power voltage level VOFF1 in at least a portion of the hold period H.

[0199] In contrast, when the sizes of the display areas Z1 to Z8 are less than the threshold value and the display areas Z1 to Z8 have the hold period H, the data supply voltage AVDD can have a second low power voltage level VOFF2 greater than the first low power voltage level VOFF1 and less than a high power voltage level VON during the hold period H.

[0200] For example, in Figure 16 In the present example embodiment, the sizes of the display areas Z1, Z2, and Z5 can be equal to or greater than a threshold value, and the sizes of the display areas Z3, Z4, Z6, Z7, and Z8 can be less than the threshold value.

[0201] According to the present example embodiment, the drive frequencies are determined according to the images displayed on the display panel 100, so that the power consumption of the display apparatus can be reduced. Furthermore, when the input image data IMG includes still image display areas and moving image display areas, the still image display areas and the moving image display areas can be driven at different frequencies, so that the power consumption of the display apparatus can be further reduced.

[0202] Further, when the display area has a hold period H corresponding to the low-frequency driving mode, the level of the data supply voltage AVDD output to the data driver 500 during the hold period H can be lowered, so that the power consumption of the display device can be reduced.

[0203] Figure 17 is a timing chart showing the generated signals of the driving controller of the display device according to the example embodiment of the present inventive concept and the output voltages of the power supply voltage generator of the display device corresponding to the display areas when the display panel includes eight display areas.

[0204] The display device and the method of driving a display panel according to the present example embodiment are substantially the same as the display device and the method of driving a display panel described with reference to the previous example embodiments except for the waveforms of the power supply control signals and the waveforms of the data supply voltages. Figures 12 to 14 The display device and the method of driving a display panel according to the present example embodiment are substantially the same as the display device and the method of driving a display panel described with reference to the previous example embodiments except for the waveforms of the power supply control signals and the waveforms of the data supply voltages. Figures 12 to 14 The same or similar parts as those described in the previous example embodiments will be referred to using the same reference numerals, and any repeated explanation regarding the above parts will be omitted.

[0205] Referring to Figure 1 , Figure 12 , Figure 13 and Figure 17 , the display device includes a display panel 100 and a display panel driver. The display panel driver includes a driving controller 200, a gate driver 300, a gamma reference voltage generator 400, and a data driver 500. The display panel driver can further include a power supply voltage generator 600.

[0206] The driving controller 200 can include a still image determiner 220A, a driving frequency determiner 230A, and a flicker value storage 240. The driving controller 200 can further include a fixed frequency determiner 210. The driving controller 200 can further include a compensation frame inserter 250.

[0207] The display panel 100 can include a plurality of display areas. In the present example embodiment, the display panel 100 can include a first display area Z1 to an eighth display area Z8.

[0208] In the present example embodiment, the sizes of the first display area Z1 to the eighth display area Z8 can be different from each other.

[0209] The driving controller 200 can drive the display areas Z1 to Z8 of the display panel 100 at different driving frequencies RDATA1 to RDATAM. The driving controller 200 can independently determine the driving frequencies RDATA1 to RDATAM of the display areas Z1 to Z8 of the display panel 100.

[0210] The driving frequency determiner 230A can determine whether the display regions Z1 to Z8 have a write period W or a hold period H based on the driving frequencies of the display regions Z1 to Z8.

[0211] In the present example embodiment, when a display region has a hold period H, the data supply voltage AVDD applied to the data driver 500 during the hold period H can be turned off, so that the power consumption of the data driver 500 can be reduced.

[0212] In the present example embodiment, the turning off of the data supply voltage AVDD can be determined according to the size of the display region Z1 to Z8 and the level of the data supply voltage AVDD applied to the previous display region.

[0213] For example, when the size of a display region is equal to or greater than a threshold value and the display region has a hold period H, the data supply voltage AVDD can have a low power voltage level VOFF in at least a portion of the hold period H of the current display region (e.g., Z2).

[0214] Further, when the size of a display region is less than a threshold value, the display region has a hold period H, and the data supply voltage AVDD has a low power voltage level VOFF for the previous display region, the data supply voltage AVDD can have a low power voltage level VOFF in at least a portion of the hold period H of the current display region (e.g., Z3).

[0215] In contrast, when the size of a display region is less than a threshold value, the display region has a hold period H, and the data supply voltage AVDD has a high power voltage level VON for the previous display region, the data supply voltage AVDD can have a high power voltage level VON during the hold period H of the current display region (e.g., Z6 and Z7).

[0216] For example, in the case where the size of the display region Z1 is equal to or greater than a threshold value and the display region Z1 has a hold period H, the data supply voltage AVDD can have a low power voltage level VOFF in at least a portion of the hold period H of the display region Z1. Figure 17 In the present example embodiment, the size of the display regions Z1, Z2, and Z5 can be equal to or greater than a threshold value, and the size of the display regions Z3, Z4, Z6, Z7, and Z8 can be less than a threshold value.

[0217] According to the present example embodiment, the driving frequency is determined according to the image displayed on the display panel 100, so that the power consumption of the display apparatus can be reduced. Further, when the input image data IMG includes a still image display region and a moving image display region, the still image display region and the moving image display region can be driven at different frequencies, so that the power consumption of the display apparatus can be further reduced.

[0218] Further, when the display region has a hold period H corresponding to the low-frequency driving mode, the level of the data supply voltage AVDD output to the data driver 500 during the hold period H can be lowered, so that the power consumption of the display device can be reduced.

[0219] According to the inventive concept as described above, the power consumption of the display device can be reduced.

[0220] The foregoing is a summary of the inventive concept and should not be construed as limiting the inventive concept. Although several example embodiments of the inventive concept have been described, those skilled in the art will readily appreciate that many modifications are possible in the example embodiments without materially departing from the novel teachings and advantages of the inventive concept. Accordingly, all such modifications are intended to be included within the scope of the inventive concept as defined in the claims. In the claims, the means-plus-function clause is intended to cover the structures described herein as performing the recited functions and not only structural equivalents but also equivalent structures. Therefore, it is to be understood that the foregoing is a description of the inventive concept and is not to be construed as limiting the inventive concept to the specifically disclosed embodiments, modifications to the specifically disclosed embodiments, and other example embodiments are intended to be included within the scope of the claims. The inventive concept is defined by the claims appended hereto and including full equivalents thereof.

Claims

1. A display device, comprising: The display panel includes gate lines, data lines, and pixels, and is configured to display images based on input images; A gate driver is configured to output a gate signal to the gate line; A data driver is configured to output a data voltage to the data line; The drive controller is configured to drive multiple display areas of the display panel at different drive frequencies; as well as A power supply voltage generator is configured to output a data power supply voltage to the data driver. The drive controller is configured to output output data enable signals for the plurality of display areas, including a write period with a valid signal and a hold period with an invalid signal. The drive controller is configured to generate a multi-frequency signal, based on the drive frequency of the plurality of display areas, indicating whether each of the plurality of display areas is in the write period or the hold period. The drive controller is configured to generate a power control signal having a first level during the write period and a second level during at least a portion of the hold period based on the drive frequency of the plurality of display areas, and output the power control signal to the power voltage generator. The power supply voltage generator is configured to generate a data power supply voltage that has a high power supply voltage level during the write period and a low power supply voltage level during at least a portion of the hold period, based on the power control signal. Specifically, when the first group of display areas in the plurality of display areas in the frame is in the write period and the second group of display areas in the plurality of display areas is in the hold period, when the power control signal has the first level, the multi-frequency signal has an active level, and when the power control signal has the second level, the multi-frequency signal has an inactive level.

2. The display device according to claim 1, wherein, The drive controller includes a still image determiner configured to determine whether each of the plurality of display areas represents a still image or a moving image.

3. The display device according to claim 2, wherein, The drive controller further includes a drive frequency determiner configured to determine the drive frequency of the plurality of display areas based on the flicker value of the grayscale value of the input image data corresponding to the plurality of display areas.

4. The display device according to claim 3, wherein, The drive controller is configured to determine, based on the drive frequency of the plurality of display areas, whether each of the plurality of display areas is in the write period or the hold period in the frame, and The drive controller is configured to generate the multi-frequency signal having the active level during the write period and the inactive level during the hold period.

5. The display device according to claim 4, wherein, When the display area is in the hold period, the period during which the power control signal has the second level is shorter than the period during which the multi-frequency signal has the invalid level.

6. The display device according to claim 5, wherein, When the display area is in the hold period, the time point at which the power control signal changes from the first level to the second level is later than the time point at which the multi-frequency signal changes from the active level to the inactive level, and Specifically, when the display area is in the holding period, the time point at which the power control signal changes from the second level to the first level during the holding period is the same as the time point at which the multi-frequency signal changes from the invalid level to the valid level.

7. The display device according to claim 5, wherein, When the display area is in the hold period, the time point at which the power control signal changes from the first level to the second level during the hold period is later than the time point at which the multi-frequency signal changes from the active level to the inactive level, and Specifically, when the display area is in the holding period, the time point at which the power control signal changes from the second level to the first level during the holding period is earlier than the time point at which the multi-frequency signal changes from the invalid level to the valid level.

8. The display device according to claim 3, wherein, The drive controller also includes a fixed frequency determiner configured to determine whether the input frequency of the input image data has a normal type by counting the number of pulses of the vertical synchronization signal within one second.

9. The display device according to claim 3, wherein, The drive controller further includes a compensation frame inserter configured to insert a compensation frame between a frame at the first frequency and a frame at the second frequency when the drive frequency in the display area changes from a first frequency to a second frequency by the drive frequency determiner.

10. The display device according to claim 1, wherein, The number of the plurality of display areas is equal to or greater than three, and The plurality of display areas are driven at different frequencies.

11. The display device according to claim 1, wherein, The multiple display areas have different sizes.

12. The display device according to claim 11, wherein, The drive controller is configured to determine the size of the plurality of display areas based on the boundary between a still image display area representing a still image and a moving image display area representing a moving image, as well as the flicker value for the grayscale value of the input image data.

13. The display device according to claim 11, wherein, When the size of the display area is equal to or greater than the threshold and the display area has the hold period, the data power supply voltage has the low power supply voltage level during at least a portion of the hold period, and Specifically, when the size of the display area is smaller than the threshold and the display area has the hold period, the data power supply voltage has the high power supply voltage level during the hold period.

14. The display device according to claim 11, wherein, When the size of the current display area is equal to or greater than the threshold and the current display area has the hold period, the data power supply voltage has the low power supply voltage level during at least a portion of the hold period of the current display area. Wherein, when the size of the current display area is smaller than the threshold, the current display area has the hold period, and the data power supply voltage has the low power supply voltage level relative to the previous display area, the data power supply voltage has the low power supply voltage level during at least a portion of the hold period of the current display area, and Specifically, when the size of the current display area is smaller than the threshold, the current display area has the holding period, and the data power supply voltage does not have the low power supply voltage level relative to the previous display area, the data power supply voltage has the high power supply voltage level during the holding period of the current display area.

15. A display device, comprising: The display panel includes gate lines, data lines, and pixels, and is configured to display images based on input images; A gate driver is configured to output a gate signal to the gate line; A data driver is configured to output a data voltage to the data line; The drive controller is configured to drive multiple display areas of the display panel at different drive frequencies; as well as A power supply voltage generator is configured to output a data power supply voltage to the data driver. The drive controller is configured to output output data enable signals for the plurality of display areas, including a write period with a valid signal and a hold period with an invalid signal. The drive controller is configured to generate a multi-frequency signal, based on the drive frequency of the plurality of display areas, indicating whether each of the plurality of display areas is in the write period or the hold period. The drive controller is configured to generate a power control signal having a first level during the write period and a second level during at least a portion of the hold period based on the drive frequency of the plurality of display areas, and output the power control signal to the power voltage generator. The power supply voltage generator is configured to generate a data power supply voltage that has a high power supply voltage level during the write period and a low power supply voltage level during at least a portion of the hold period, based on the power control signal. The multiple display areas have different sizes. Wherein, when the size of the first display area is equal to or greater than a threshold and the first display area has the hold period, the data power supply voltage has a first low power supply voltage level during at least a portion of the hold period, and Wherein, when the size of the first display area is smaller than the threshold and the first display area has the hold period, the data power supply voltage has a second low power supply voltage level that is greater than the first low power supply voltage level and less than the high power supply voltage level during the hold period.

16. A method for driving a display panel, the method comprising: The driving frequency of multiple display areas can be determined independently; Generate output data enable signals for the plurality of display areas, including a write period with a valid signal and a hold period with an invalid signal; Based on the driving frequency of the plurality of display areas, a multi-frequency signal is generated to indicate whether each of the plurality of display areas is in the write period or the hold period; A power control signal having a first level during the write period and a second level during at least a portion of the hold period is generated based on the driving frequency of the plurality of display areas; A data power voltage is generated based on the power control signal, which has a high power supply voltage level during the write period and a low power supply voltage level during at least a portion of the hold period; Output gate signals to the gate lines of the display panel; as well as The data voltage is output to the data lines of the display panel using the input image data, the output data enable signal, and the data power supply voltage. Specifically, when the first group of display areas in the plurality of display areas in the frame is in the write period and the second group of display areas in the plurality of display areas is in the hold period, when the power control signal has the first level, the multi-frequency signal has an active level, and when the power control signal has the second level, the multi-frequency signal has an inactive level.

17. The method of claim 16, further comprising: Determine whether each of the plurality of display areas represents a still image or a moving image.

18. The method according to claim 17, wherein, The driving frequency of the plurality of display areas is determined based on the flicker value of the grayscale value of the input image data corresponding to the plurality of display areas.

Images