Semiconductor package

Abstract

A semiconductor package may include: a semiconductor chip located on a substrate; and an underfill layer located between the semiconductor chip and the substrate. The semiconductor chip may include: a semiconductor substrate including a first region and a second region; and an interlayer dielectric layer that may cover the semiconductor substrate and may include connection lines therein. A first conductive pad may be located on the first region and may be electrically connected to some of the connection lines. A second conductive pad may be located on the second region and may be electrically isolated from all the connection lines. The semiconductor chip may further include a passivation layer that may cover the interlayer dielectric layer and may include first holes that may respectively expose the first conductive pad and the second conductive pad. On the second region, the underfill layer may include a portion that may be located in one of the first holes and may contact one of the second conductive pads.

Description

[0001] Cross - reference to related applications

[0002] This application claims the priority of Korean Patent Application No. 10 - 2020 - 0037642, filed on March 27, 2020, and Korean Patent Application No. 10 - 2020 - 0081030, filed on July 1, 2020, with the Korean Intellectual Property Office, the disclosures of which are incorporated herein by reference in their entireties. Technical field

[0003] The inventive concept relates to semiconductor packages. Background art

[0004] Semiconductor packages are provided to implement integrated circuit chips suitable for use in electronic products. Semiconductor packages are generally configured such that semiconductor chips are mounted on a printed circuit board (PCB), and bonding wires or bumps are used to electrically connect the semiconductor chips to the printed circuit board. With the development of the electronics industry, many studies have been conducted to improve the reliability and durability of semiconductor packages. Summary of the invention

[0005] Some example embodiments of the inventive concept provide semiconductor packages having improved reliability and improved and / or optimized performance.

[0006] The object of the inventive concept is not limited to the above, and other objects not mentioned above will be clearly understood by those skilled in the art from the following description.

[0007] According to some example embodiments of the inventive concept, a semiconductor package may include: a semiconductor chip located on a package substrate; and an underfill layer located between the semiconductor chip and the package substrate. The semiconductor chip may include: a semiconductor substrate; an interlayer dielectric layer located on the semiconductor substrate and including a plurality of connection lines therein; a plurality of conductive pads located on the interlayer dielectric layer, where a first some conductive pads (or a first portion of conductive pads or a first plurality of conductive pads) of the plurality of conductive pads are electrically connected to a first some connection lines (or a first portion of connection lines or a first plurality of connection lines) of the plurality of connection lines, and a second some conductive pads (or a second portion of conductive pads or a second plurality of conductive pads) of the plurality of conductive pads are electrically isolated from the plurality of connection lines; a passivation layer located on the interlayer dielectric layer and including a plurality of first holes respectively located on the first some conductive pads and the second some conductive pads of the plurality of conductive pads; and a plurality of first conductive bumps respectively bonded to the first some conductive pads of the plurality of conductive pads. The underfill layer may include a first portion, and the first portion may be located in a first-first hole of the plurality of first holes and may contact a first conductive pad of the second some conductive pads of the plurality of conductive pads.

[0008] According to some example embodiments of the inventive concept, a semiconductor package may include: a semiconductor chip located on a package substrate. The semiconductor chip may include: a semiconductor substrate; an interlayer dielectric layer located on the semiconductor substrate and including a plurality of connection lines therein; a plurality of conductive pads located on the interlayer dielectric layer, where a first some conductive pads of the plurality of conductive pads are electrically connected to a first some connection lines of the plurality of connection lines, and a second some conductive pads of the plurality of conductive pads are electrically isolated from the plurality of connection lines; and a passivation layer located on the interlayer dielectric layer. The passivation layer may include a plurality of first holes and second holes. Some first holes (or a portion of first holes) of the plurality of first holes may be respectively located on the first some conductive pads and the second some conductive pads of the plurality of conductive pads. The second holes may not vertically overlap with the first some conductive pads of the plurality of conductive pads and may not vertically overlap with the second some conductive pads of the plurality of conductive pads.

[0009] According to some example embodiments of the inventive concept, a semiconductor package may include: a first semiconductor chip, a second semiconductor chip, and a third semiconductor chip stacked in sequence; a plurality of first conductive bumps and a plurality of first dummy conductive bumps located between the first semiconductor chip and the second semiconductor chip; and a plurality of second conductive bumps and a plurality of second dummy conductive bumps located between the second semiconductor chip and the third semiconductor chip. The plurality of first conductive bumps and the plurality of second conductive bumps may transmit electrical signals between the first semiconductor chip, the second semiconductor chip, and the third semiconductor chip. The plurality of first dummy conductive bumps and the plurality of second dummy conductive bumps may be electrically floating. The number of the first conductive bumps may be equal to the number of the second conductive bumps. The number of the first dummy conductive bumps may be different from the number of the second dummy conductive bumps. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 The top view shown illustrates a semiconductor package according to some example embodiments of the inventive concept.

[0011] Figure 2 The cross-sectional view taken along line A-A' Figure 1 illustrates a semiconductor package according to some example embodiments of the inventive concept.

[0012] Figure 3 The cross-sectional view taken along line B-B' Figure 1 illustrates a semiconductor package according to some example embodiments of the inventive concept.

[0013] Figure 4 The cross-sectional view taken along line C-C' Figure 1 illustrates a semiconductor package according to some example embodiments of the inventive concept.

[0014] Figure 5 The cross-sectional view taken along line D-D' Figure 1 illustrates a semiconductor package according to some example embodiments of the inventive concept.

[0015] Figure 6 The cross-sectional view taken along line E-E' Figure 1 illustrates a semiconductor package according to some example embodiments of the inventive concept.

[0016] Figure 7 The cross-sectional view taken along line F-F' Figure 1 illustrates a semiconductor package according to some example embodiments of the inventive concept.

[0017] Figure 8 The cross-sectional view taken along line G-G' Figure 1 illustrates a semiconductor package according to some example embodiments of the inventive concept.

[0018] Figure 9 The enlarged view shown shows part P1 of Figure 8 in accordance with some example embodiments of the inventive concept.

[0019] Figure 10 shows a cross-sectional view taken along line H-H' of Figure 1 in accordance with some example embodiments of the inventive concept.

[0020] Figure 11 The cross-sectional view shown shows a method of manufacturing a semiconductor package in accordance with some example embodiments of the inventive concept.

[0021] Figure 12 The cross-sectional view shown shows a semiconductor package in accordance with some example embodiments of the inventive concept.

[0022] Figure 13 The cross-sectional view shown shows a semiconductor package in accordance with some example embodiments of the inventive concept. DETAILED DESCRIPTION

[0023] Some example embodiments of the inventive concept will now be described in detail with reference to the accompanying drawings to help clearly explain the inventive concept.

[0024] Figure 1 The top view shown shows a semiconductor package in accordance with some example embodiments of the inventive concept. Figure 2 shows a cross-sectional view taken along line A-A' of Figure 1 in accordance with some example embodiments of the inventive concept.

[0025] Referring to Figure 1 and Figure 2 , a semiconductor package 100 according to some example embodiments may include a semiconductor chip 50 mounted on a package substrate 10. A single semiconductor chip 50 is shown by way of example, but a plurality of semiconductor chips 50 may be stacked on top of each other or may be arranged side by side. The package substrate 10 may be, for example, a single-layer or multi-layer printed circuit board. In some embodiments, the package substrate 10 may be an embedded substrate formed of silicon. In some embodiments, the package substrate 10 may be a separate semiconductor chip. The package substrate 10 may have a first substrate surface 10a and a second substrate surface 10b that face each other. The semiconductor chip 50 may be mounted on the first substrate surface 10a. The semiconductor chip 50 and the package substrate 10 may be covered by a molding layer 70. The molding layer 70 may include, for example, a dielectric resin such as an epoxy molding compound (EMC). The molding layer 70 may also include a filler that may be dispersed in the dielectric resin. The filler may include, for example, silicon dioxide (SiO2).

[0026] On the first substrate surface 10a, a first substrate pad 12 may be provided. On the second substrate surface 10b, a second substrate pad 14 may be provided. In the packaging substrate 10, an internal substrate line 18 may be provided, and the internal substrate line 18 connects some of the first substrate pads in the first substrate pad 12 to some of the second substrate pads in the second substrate pad 14 respectively. The internal substrate line 18 may include vias. The first substrate pad 12, the second substrate pad 14, and the internal substrate line 18 may include a metal such as copper or aluminum. Solder balls 22 may be bonded to the second substrate pad 14. The solder balls 22 may include, for example, tin, lead, and / or silver. As used herein, the term "and / or" includes any and all combinations of one or more of the related listed items.

[0027] The semiconductor chip 50 may be one selected from a system LSI (Large Scale Integration) chip, a logic circuit chip, an image sensor chip such as a CMOS image sensor (CIS), a flash memory chip, a DRAM chip, an SRAM chip, an EEPROM chip, a PRAM chip, an MRAM chip, and a ReRAM chip.

[0028] The semiconductor chip 50 may have a first chip surface 50s1 and a second chip surface 50s2 facing each other. The first chip surface 50s1 may be adjacent to and / or may face the first substrate surface 10a. The semiconductor chip 50 may include a first region R1 and a second region R2. The first region R1 may be a central portion. The second region R2 may be an edge portion surrounding the first region R1. The first region R1 may be a region on which terminals for transmitting electrical signals are provided. The second region R2 may be a region on which dummy terminals unrelated to the transmission of electrical signals are provided. The dummy terminals may not transmit electrical signals during the operation of the semiconductor chip 50. The first region R1 and the second region R2 may be differently arranged. For example, the second region R2 may be provided in the center, and the first region R1 may surround (e.g., partially surround or completely surround) the second region R2. In some embodiments, one or both of the first region R1 and the second region R2 may be provided as multiple. Conductive bumps RBP1, RBP2, DBP1, and DBP2 may be bonded to the first chip surface 50s1. The conductive bumps RBP1, RBP2, DBP1, and DBP2 may include a single-layer or multi-layer structure containing copper and / or nickel.

[0029] The conductive bumps RBP1, RBP2, DBP1, and DBP2 may include a first conductive bump RBP1, a second conductive bump RBP2, a first dummy conductive bump DBP1, and a second dummy conductive bump DBP2. The first conductive bump RBP1 and the second conductive bump RBP2 may actually be used for the input and output of electrical signals (e.g., data signals, power signals, and ground signals). The first dummy conductive bump DBP1 and the second dummy conductive bump DBP2 may be electrically floating, and / or may not be supplied with electrical signals. In some embodiments, the first dummy conductive bump DBP1 and the second dummy conductive bump DBP2 may not be electrically connected to any conductive elements (e.g., Figure 3 the plurality of stacked chip internal lines 53 and the plurality of top wirings 55 in), such that current may not flow through the first dummy conductive bump DBP1 and the second dummy conductive bump DBP2. The first conductive bump RBP1 may be disposed on the first region R1. The second conductive bump RBP2 and the first dummy conductive bump DBP1 and the second dummy conductive bump DBP2 may be disposed on the second region R2.

[0030] Figure 3 A cross-sectional view taken along line B-B' of some example embodiments according to the inventive concept is shown. Figure 1 of.

[0031] Referring to Figure 3 , the semiconductor chip 50 may include a semiconductor substrate 51. The semiconductor substrate 51 may be, for example, a single crystal silicon substrate. A plurality of transistors TR may be disposed on the semiconductor substrate 51. The transistors TR may be covered by an interlayer dielectric layer 52. The interlayer dielectric layer 52 may have a single-layer or multi-layer structure including a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, and / or a porous dielectric layer. The interlayer dielectric layer 52 may have a plurality of stacked chip internal lines 53, a plurality of top wirings 55, and a plurality of internal vias 57 therein. The chip internal lines 53 may be electrically connected to the transistors TR. The transistors TR and the chip internal lines 53 may constitute an internal integrated circuit. The top wiring 55 may be one of the chip internal lines 53 and may correspond to one of the chip internal lines 53 existing at the uppermost position. The chip internal lines 53 may include, for example, copper and / or tungsten. The top wiring 55 may include, for example, aluminum. The thickness of the chip internal lines 53 may be less than the thickness of the top wiring 55.

[0032] Conductive pads RPA1, RPA2, and DPA may be disposed on the interlayer dielectric layer 52. The conductive pads RPA1, RPA2, and DPA may include, for example, aluminum. The conductive pads RPA1, RPA2, and DPA may include a first conductive pad RPA1, a second conductive pad RPA2, and a dummy conductive pad DPA. The first conductive pad RPA1 may be disposed on the first region R1. The second conductive pad RPA2 and the dummy conductive pad DPA may be disposed on the second region R2.

[0033] The first conductive pad RPA1 and the second conductive pad RPA2 can be connected (e.g., electrically connected) to the top wiring 55 through an internal via 57. The dummy conductive pad DPA can be electrically insulated (or floating) without being connected to the top wiring 55. The interlayer dielectric layer 52 can be covered by a passivation layer 59. In some embodiments, the dummy conductive pad DPA may not be electrically connected to any conductive elements (e.g., Figure 3 the multiple stacked chip internal lines 53 and the multiple top wirings 55 in), such that current may not flow through the dummy conductive pad DPA. The passivation layer 59 can have, for example, a bilayer structure including a silicon oxide layer and a silicon nitride layer. In some embodiments, the passivation layer 59 may further include photosensitive polyimide (PSPI) located on the silicon nitride layer. The passivation layer 59 can include a first via H1 exposing the conductive pads RPA1, RPA2, and DPA. The passivation layer 59 can have a top surface corresponding to the first chip surface 50s1 of the semiconductor chip 50. The semiconductor substrate 51 can have a bottom surface corresponding to the second chip surface 50s2 of the semiconductor chip 50.

[0034] The first conductive bump RBP1 can be correspondingly bonded to the first conductive pad RPA1. In some exemplary embodiments, the second conductive bump RBP2 can be bonded to the second conductive pad RPA2. Figure 3 A single second conductive bump RBP2 is depicted, but as Figure 1 shown, the semiconductor package 100 can include multiple second conductive bumps RBP2 and multiple second conductive pads RPA2 corresponding to the multiple second conductive bumps RBP2. The second conductive bumps RBP2 can be correspondingly bonded to the second conductive pads RPA2. The first conductive bump RBP1 and the second conductive bumps RBP2 can be correspondingly bonded to the first substrate pads 12 through a solder layer 20. The solder layer 20 can include tin, lead, and / or silver. In some embodiments, as Figure 3 shown, each of the first conductive bump RBP1 and the second conductive bumps RBP2 can respectively contact the corresponding solder layer in the solder layer 20 that contacts the first substrate pad 12, such that the first conductive bump RBP1 and the second conductive bumps RBP2 can be electrically connected to the corresponding first substrate pads in the first substrate pads 12 through the intermediate solder layer 20.

[0035] Although Figure 3 not shown in, but the metal matrix layer (e.g., Figure 9The metal matrix layer 71) can be interposed between the first conductive pad RPA1 and the first conductive bump RBP1, and between the second conductive pad RPA2 and the second conductive bump RBP2. The metal matrix layer can include, for example, a diffusion barrier layer and / or a seed layer. The diffusion barrier layer can include, for example, a titanium layer and / or a titanium nitride layer. The seed layer can include, for example, a copper layer.

[0036] Although Figure 3 not shown in, the diffusion barrier layer and / or the adhesive layer (e.g., Figure 9 the diffusion barrier layer 62 and the adhesive layer 64 in) can be interposed between the solder layer 20 and each of the first conductive bump RBP1 and the second conductive bump RBP2. The diffusion barrier layer 62 can include, for example, nickel and can be used to prevent the diffusion of copper. The adhesive layer can include, for example, copper and / or gold and can be used to increase the adhesion between the diffusion barrier layer and the solder layer 20.

[0037] The first substrate surface 10a and the second substrate surface 10b of the package substrate 10 can be covered by a substrate passivation layer 16. The substrate passivation layer 16 can be, for example, a photosensitive solder resist (PSR) layer. The underfill layer 60 can fill the gap between the package substrate 10 and the semiconductor chip 50. The underfill layer 60 can include, for example, a thermosetting resin and / or a photocurable resin. The underfill layer 60 can be formed of, for example, a non-conductive film (NCF). It will be understood that "element A covers element B" (or similar language) can mean that element A is on element B, but does not necessarily mean that element A completely covers element B.

[0038] As Figure 3 shown, Figure 1 neither the first dummy conductive bump DBP1 nor the second dummy conductive bump DBP2 of can be provided on the dummy conductive pad DPA. The top surface of the dummy conductive pad DPA can be exposed to the first hole H1. The underfill layer 60 can contact the top surface of the dummy conductive pad DPA through the first hole H1. The underfill layer 60 can fill the first hole H1 on the dummy conductive pad DPA.

[0039] Figure 4 Shows a cross-sectional view taken along the Figure 1 line C-C' of some exemplary embodiments according to the inventive concept.

[0040] Referring to Figure 4, the first dummy conductive bump DBP1 can be bonded to some first dummy conductive pads (or the first part of the dummy conductive pads or the first plurality of dummy conductive pads) in the dummy conductive pad DPA. The first dummy conductive bump DBP1 may not be bonded to some second dummy conductive pads (or the second part of the dummy conductive pads or the second plurality of dummy conductive pads) in the dummy conductive pad DPA, and the underfill layer 60 may be in contact with some second dummy conductive pads in the dummy conductive pad DPA. The first dummy conductive bump DBP1 may not be used for signal transmission, but may support the semiconductor chip 50, may reduce and / or control the warpage of the semiconductor package 100, or may adjust the heat dissipation property of the semiconductor package 100. Therefore, the number and position of the first dummy conductive bump DBP1 can be adjusted to improve or optimize the reliability and performance of the semiconductor package 100. For example, when the first dummy conductive bump DBP1 is provided in a very large number or is very close to the first conductive bump RBP1 and the second conductive bump RBP2, a short circuit is likely to occur between the conductive bumps RBP1, RBP2, DBP1, and DBP2.

[0041] In addition, the conductive bumps RBP1, RBP2, DBP1, and DBP2 may have different thermal and physical properties with respect to the semiconductor chip 50 and the package substrate 10. Therefore, when the number of the dummy conductive bumps DBP1 and DBP2 is too large or too small, the semiconductor package 100 may have poor warpage or heat dissipation characteristics. Therefore, if necessary, the number of the first dummy conductive bump DBP1 can be adjusted and / or optimized.

[0042] Although Figure 4 not shown in Figure 9 , a metal matrix layer (e.g., the metal matrix layer 71 in Figure 9 ) may be interposed between the dummy conductive pad DPA and the first dummy conductive bump DBP1. Additionally, a diffusion stop layer and / or an adhesion layer (e.g., the diffusion stop layer 62 and the adhesion layer 64 in Figure 3 ) may be interposed between the solder layer 20 and the first dummy conductive bump DBP1. Other configurations may be the same as or similar to the configurations discussed with reference to Figure 3 .

[0043] Figure 5 FIG. shows a cross-sectional view taken along line D-D' of some example embodiments according to the inventive concept. Figure 1 of

[0044] Referring to Figure 5, the second conductive bump RBP2 may not be disposed on the second conductive pad RPA2. On the second region R2, the top surfaces of the dummy conductive pads DPA and the second conductive pad RPA2 may be exposed to the first hole H1 and contact the underfill layer 60. According to some example embodiments, the second conductive pad RPA2 may be connected to a test circuit TC, which may include at least one intra-chip line 53 and at least one transistor TR. The test circuit TC may be substantially independent of the operation of the semiconductor chip 50 and may be present to determine whether the transistor TR and the intra-chip line 53 are properly formed. In some example embodiments, the second conductive pad RPA2 may be used to check the test circuit TC after manufacturing the semiconductor chip 50. In some embodiments, the test circuit TC may not be used during the operation of the semiconductor chip 50. Since the second conductive pad RPA2 is not related to the actual operation of the semiconductor package 100, it may not be necessary for the second conductive pad RPA2 to be connected to the second conductive bump RBP2. Other configurations may be the same as or similar to those discussed above with reference to Figure 3 and Figure 4 those configurations.

[0045] Figure 6 FIG. shows a cross-sectional view taken along line Figure 1 E-E' according to some example embodiments of the inventive concept.

[0046] Referring to Figure 6 , the second conductive bump RBP2 may not be disposed on the second conductive pad RPA2. The first dummy conductive bump DBP1 may be bonded to all of the dummy conductive pads DPA. In some example embodiments, the second conductive pad RPA2 may be connected to the test circuit TC. The underfill layer 60 may contact the second conductive pad RPA2 through the first hole H1. Other configurations may be the same as or similar to those discussed with reference to Figures 3 to 5 those configurations.

[0047] Figure 7 FIG. shows a cross-sectional view taken along line Figure 1 F-F' according to some example embodiments of the inventive concept.

[0048] Referring to Figure 7 , the second conductive bump RBP2 may not be disposed on the second conductive pad RPA2. The first dummy conductive bump DBP1 may be bonded to some first dummy conductive pads among the dummy conductive pads DPA, and some second dummy conductive pads among the dummy conductive pads DPA may be exposed without being bonded to the first dummy conductive bump DBP1 thereon. Other configurations may be the same as or similar to those discussed with reference to Figures 3 to 5 those configurations.

[0049] Figure 8A cross-sectional view taken along line G-G' according to some example embodiments of the inventive concept is shown. Figure 1 The enlarged view shown shows a portion P1 according to some example embodiments of the inventive concept. Figure 9 The enlarged view shown shows a portion P1 according to some example embodiments of the inventive concept. Figure 8 The enlarged view shown shows a portion P1 according to some example embodiments of the inventive concept.

[0050] Referring to Figure 8 and Figure 9 , on the second region R2, the second conductive bump RBP2 can be bonded to the second conductive pad RPA2, and the first dummy conductive bump DBP1 can be bonded to all the dummy conductive pads DPA. Additionally, the second dummy conductive bump DBP2 can be bonded to the passivation layer 59. On the second region R2, the passivation layer 59 can include one or more second holes H2 spaced apart from the first hole H1. The second holes H2 may not perpendicularly overlap any of the conductive pads RPA1, RPA2, and DPA. It will be understood that as used herein, "element A does not perpendicularly overlap element B" (or similar language) means that there is no vertical line that intersects both element A and element B. The second holes H2 may not expose the interlayer dielectric layer 52. In some embodiments, the second holes H2 may not extend through the passivation layer 59 and may partially extend into the passivation layer 59 in the thickness direction of the passivation layer 59, as Figure 8 shown. Thus, a portion of the passivation layer 59 can be located between the second dummy conductive bump DBP2 and the interlayer dielectric layer 52. The second holes H2 can be referred to as recesses or trenches. In some embodiments, the second dummy conductive bump DBP2 can be directly bonded to the upper portion of the passivation layer 59 without the second holes H2.

[0051] None of the conductive pads RPA1, RPA2, and DPA may be present below the second holes H2. The first hole H1 may have a first depth D1 from the first chip surface 50s1 which is the top surface of the passivation layer 59. The second holes H2 may have a second depth D2 from the first chip surface 50s1. The second depth D2 may be greater than the first depth D1. The metal matrix layer 71 can be interposed between the second dummy conductive bump DBP2 and the passivation layer 59. The diffusion stop layer 62 and the adhesion layer 64 can be interposed between the second dummy conductive bump DBP2 and the solder layer 20. The second dummy conductive bump DBP2 can be provided in a plurality. Similar to the first dummy conductive bump DBP1, the number of the second dummy conductive bumps DBP2 can be adjusted to improve or optimize the reliability and performance of the semiconductor package 100.

[0052] In some example embodiments, the passivation layer 59 may include a first sub-passivation layer 59a, a second sub-passivation layer 59b, and a third sub-passivation layer 59c that are sequentially stacked and have dielectric materials different from each other. The first sub-passivation layer 59a may be formed of, for example, a silicon oxide layer. The second sub-passivation layer 59b may be formed of, for example, a silicon nitride layer. The third sub-passivation layer 59c may be formed of, for example, photosensitive polyimide (PSPI). The third sub-passivation layer 59c may be spaced apart from the conductive bumps RBP1, RBP2, DBP1, and DBP2. The third sub-passivation layer 59c may have sidewalls that are not aligned with the sidewalls of each of the first sub-passivation layer 59a and the second sub-passivation layer 59b but are spaced apart therefrom. The bottom surface of the second via H2 may be located in the first sub-passivation layer 59a. Other configurations may be the same as or similar to those discussed with reference to Figures 1 to 5 Those configurations discussed

[0053] In some example embodiments of the inventive concept, the third sub-passivation layer 59c may be omitted. The diffusion stop layer 62 and the adhesion layer 64 may be omitted to allow the conductive bumps RBP1, RBP2, DBP1, and DBP2 to directly contact the solder layer 20. In this case, the conductive bumps RBP1, RBP2, DBP1, and DBP2 may include nickel.

[0054] Figure 10 A cross-sectional view taken along line H-H' according to some example embodiments of the inventive concept is shown. Figure 1 of the

[0055] Referring to Figure 10 , the passivation layer 59 may include a second via H2 as discussed in Figure 8 , but the second dummy conductive bump DBP2 may be excluded or omitted. The underfill layer 60 may fill the second via H2. Since Figure 8 the second conductive bump RBP2 is excluded or omitted, the first via H1 may expose the second conductive pad RPA2. The second conductive pad RPA2 may be connected to the test circuit TC. In some example embodiments, one of the first dummy conductive bumps DBP1 may not exist to allow the first via H1 to expose the dummy conductive pad DPA. The underfill layer 60 may fill the first via H1. Other configurations may be the same as or similar to those discussed with reference to Figure 8 Those configurations discussed

[0056] According to some example embodiments of the inventive concept, the semiconductor chip 50 may be configured such that the passivation layer 59 includes a first hole H1 exposing all of the conductive pads RPA1, RPA2, and DPA. Accordingly, compared to a case where only the conductive pads RPA1 and RPA2 are exposed, the first hole H1 may have a uniform density per unit area, and thus process defects caused by differences in load effects may be reduced or avoided. In addition, a second hole H2 may be formed even at a position where any of the conductive pads RPA1, RPA2, and DPA do not exist, and thus, the density of all of the holes H1 and H2 may become more uniform. In summary, the semiconductor package 100 may have improved reliability.

[0057] In addition, according to some example embodiments of the inventive concept, the semiconductor chip 50 may be configured such that dummy conductive bumps DBP1 and DBP2 are selectively positioned at predetermined positions or desired positions, and thus, the semiconductor package 100 may have improved reliability.

[0058] According to some example embodiments of the inventive concept, the semiconductor package 100 may include all of the components discussed with reference to Figures 3 to 10 or may selectively include one or more of these components.

[0059] Figure 11 The cross-sectional view shown illustrates a method of manufacturing a semiconductor package depicted in one of some example embodiments of the inventive concept. Figures 3 to 7 One of the semiconductor packages depicted in one of some example embodiments of the inventive concept.

[0060] With reference to Figure 11 , a semiconductor substrate 51 (e.g., a wafer) including a first region R1 and a second region R2 may be subjected to various processes to form transistors TR, intra-chip lines 53, an interlayer dielectric layer 52, top wirings 55, internal vias 57, and conductive pads RPA1, RPA2, and DPA. A passivation layer 59 may be formed to cover the interlayer dielectric layer 52 and the conductive pads RPA1, RPA2, and DPA. A pad opening process may be performed in which the passivation layer 59 is patterned to form a first hole H1 exposing the conductive pads RPA1, RPA2, and DPA. In this step, when the passivation layer 59 has properties such as Figure 9When forming a structure such as the structure of, an exposure and development process may be performed to pattern a third sub-passivation layer 59c formed of photosensitive polyimide (PSPI). An anisotropic etching process may be performed to etch the first sub-passivation layer 59a and the second sub-passivation layer 59b. When the third sub-passivation layer 59c is omitted, the exposure and development process for patterning the third sub-passivation layer 59c may be omitted. For example, the pad opening process may selectively include an exposure and development process to pattern the third sub-passivation layer 59c, and may substantially include an anisotropic etching process to etch the first sub-passivation layer 59a and the second sub-passivation layer 59b. In the pad opening process, it may be necessary to form the first holes H1 to be evenly distributed to prevent process defects caused by the loading effect. In some embodiments, the first holes H1 may be spaced apart from each other by a uniform distance, as Figure 11 shown.

[0061] In the anisotropic etching process, when only the conductive pads RPA1 and RPA2 are open to the first holes H1, and when the dummy conductive pad DPA is covered by the passivation layer 59, the first holes H1 may have different densities between the first region R1 and the second region R2, which may cause process defects caused by the loading effect. In this case, a difference in etchant density may occur in the anisotropic etching process, and a relatively large amount of etchant may appear on the second conductive pad RPA2 rather than the first conductive pad RPA1, resulting in an oxide layer (e.g., an alumina layer) being overly formed on the top surface of the second conductive pad RPA2. Therefore, when subsequently bonding the conductive bumps RBP1 and RBP2 to the conductive pads RPA1 and RPA2, bonding failure or contact failure may occur on the second conductive pad RPA2. In contrast, according to the inventive concept, the first holes H1 may expose all of the conductive pads RPA1, RPA2, and DPA, and may be evenly distributed. Therefore, process defects may be reduced or prevented.

[0062] In addition, as Figure 9 shown, in the pad opening process, at least one second hole H2 may be formed even at a position where none of the conductive pads RPA1, RPA2, and DPA exist, so that all of the holes H1 and H2 may be evenly distributed. In some embodiments, the holes including both the first holes H1 and the second holes H2 may be spaced apart from each other by a uniform distance, as Figure 8 shown. The second holes H2 may be formed simultaneously or concurrently with the first holes H1. However, since none of the conductive pads RPA1, RPA2, and DPA exist at the position where the second holes H2 are formed, the passivation layer 59 may be over-etched, resulting in a depth difference between the first holes H1 and the second holes H1, as Figure 9As shown. In some embodiments, holes including a first hole H1 and a second hole H2 may be formed in the same manufacturing step at approximately the same (but not necessarily exactly the same) time.

[0063] After performing a pad opening process as Figure 11 shown, a test process may be performed on the test circuit TC using the second conductive pad RPA2. A metal matrix layer 71 may be conformally formed over the entire surface of the passivation layer 59, and a photoresist pattern (not shown) may be formed to limit the locations where the conductive bumps RBP1, RBP2, DBP1, and DBP2 will be formed. For example, a plating process may be performed to form the conductive bumps RBP1, RBP2, DBP1, and DBP2. In this step, the number and positions of the dummy conductive bumps DBP1 and DBP2 may be adjusted to optimize the characteristics of the semiconductor package 100. A solder layer 20 may be formed on each of the conductive bumps RBP1, RBP2, DBP1, and DBP2. A singulation process may be performed to cut the wafer 51 into a plurality of chips, and thus, semiconductor chips 50 may be formed. Returning to Figure 2 , the semiconductor chip 50 may be mounted on the package substrate 10 using a non-conductive film (NCF), and then the non-conductive film may be heated to form an underfill layer 60. A molding layer 70 may be formed to cover the semiconductor chip 50 and the package substrate 10.

[0064] Figure 12 The cross-sectional view shown illustrates a semiconductor package according to some example embodiments of the inventive concept.

[0065] Referring to Figure 12 , the semiconductor package 101 may include first to fifth semiconductor chips 50a to 50e stacked in sequence. Each of the first to fifth semiconductor chips 50a to 50e may have a first chip surface 50s1 and a second chip surface 50s2 facing each other. In some embodiments, the width of the first semiconductor chip 50a may be greater than the widths of the second to fifth semiconductor chips 50b to 50e, as Figure 12As shown. In some embodiments, the width of the first semiconductor chip 50a may be greater than the widths of the second semiconductor chip 50b to the fourth semiconductor chip 50d. In some embodiments, the width of the fifth semiconductor chip 50e may be greater than the widths of the first semiconductor chip 50a to the fourth semiconductor chip 50d. In some embodiments, the width of the fifth semiconductor chip 50e may be greater than the widths of the second semiconductor chip 50b to the fourth semiconductor chip 50d. The type of the first semiconductor chip 50a may be different from the types of the second semiconductor chip 50b to the fifth semiconductor chip 50e. The second semiconductor chip 50b to the fifth semiconductor chip 50e may be of the same type. For example, the first semiconductor chip 50a may be a logic chip, and the second semiconductor chip 50b to the fifth semiconductor chip 50e may be the same memory chips, for example, DRAM chips.

[0066] In some exemplary embodiments, five semiconductor chips are stacked, but the number and / or positions of the stacked semiconductor chips may be changed differently. The thickness of the fifth semiconductor chip 50e may be greater than the thicknesses of the second semiconductor chip 50b to the fourth semiconductor chip 50d.

[0067] The underfill layer 60 may be interposed between the first semiconductor chip 50a to the fifth semiconductor chip 50e. The molding layer 70 may cover the side surfaces of the second semiconductor chip 50b to the fifth semiconductor chip 50e and the top surface of the first semiconductor chip 50a. The fifth semiconductor chip 50e may have a top surface that is exposed and not covered by the molding layer 70. The top surface of the fifth semiconductor chip 50e may be coplanar with the top surface of the molding layer 70. The semiconductor package 101 may be a high bandwidth memory (HBM) chip.

[0068] Each of the first semiconductor chip 50a to the fifth semiconductor chip 50e may have one of the structures discussed with reference to Figures 3 to 10 discussed. For example, as discussed with reference to Figures 3 to 10 discussed, each of the first semiconductor chip 50a to the fifth semiconductor chip 50e may include conductive pads RPA1, RPA2, and DPA disposed adjacent to the first chip surface 50s1. Additionally, each of the first semiconductor chip 50a to the fourth semiconductor chip 50d may further include upper conductive pads 58 disposed on the second chip surface 50s2. Each of the first semiconductor chip 50a to the fifth semiconductor chip 50e may include a semiconductor substrate 51, transistors TR, an interlayer dielectric layer 52, intra-chip lines 53, and top wirings 55 discussed with reference to Figure 3 discussed. For the sake of simplicity of illustration, not shown in the first semiconductor chip 50a to the fifth semiconductor chip 50e are Figure 3a semiconductor core substrate 51, transistors TR, an interlayer dielectric layer 52, and top wirings 55. Each of the first semiconductor chip 50a to the fourth semiconductor chip 50d may further include a through-via TSV that penetrates part of it. The through-via TSV may penetrate Figure 3 at least a part of the semiconductor substrate 51 and the interlayer dielectric layer 52, so as to have an electrical connection with the internal chip line 53. The through-via TSV may be connected to a corresponding upper conductive pad 58.

[0069] Each of the first semiconductor chip 50a to the fifth semiconductor chip 50e may include a passivation layer 59, and the passivation layer 59 includes a first hole H1 and a second hole H2, as referred to Figures 3 to 10 discussed. The passivation layer 59 included in the first semiconductor chip 50a may have, for example, a structure of the passivation layer 59 as Figure 9 shown (for example, including a first sub-passivation layer 59a, a second sub-passivation layer 59b, and a third sub-passivation layer 59c). The passivation layer 59 included in each of the second semiconductor chip 50b to the fifth semiconductor chip 50e may have a structure in which the third sub-passivation layer 59c is omitted from the passivation layer 59 as Figure 9 shown.

[0070] The conductive bumps RBP1, RBP2, and DBP1 may be bonded to the conductive pads RPA1, RPA2, and DPA in each of the first semiconductor chip 50a to the fifth semiconductor chip 50e. Additionally, a second dummy conductive bump DBP2 may be bonded to the passivation layer 59. The solder layer 20 may be bonded to each of the conductive bumps RBP1, RBP2, DBP1, and DBP2.

[0071] The number and position of the dummy conductive bumps DBP1 and DBP2 may be adjusted to improve or optimize the reliability and performance of the semiconductor package 101. For example, the second semiconductor chip 50b to the fifth semiconductor chip 50e may have the same number of conductive bumps RBP1 and RBP2 bonded to the first chip surface 50s1, but may have different numbers of dummy conductive bumps DBP1 and DBP2. In some exemplary embodiments, the number of dummy conductive bumps DBP1 and DBP2 may increase as approaching the first semiconductor chip 50a. For example, when observed in a cross-section of Figure 12 the semiconductor package 101, in the second semiconductor chip 50b, the third semiconductor chip 50c, the fourth semiconductor chip 50d, and the fifth semiconductor chip 50e, the number of dummy conductive bumps DBP1 and DBP2 bonded to the first chip surface 50s1 may be eight, six, four, and zero, respectively. Therefore, the load applied to the first semiconductor chip 50a can be reduced, and the warpage phenomenon of the semiconductor package 101 can be improved.

[0072] The number and positions of dummy conductive bumps DBP1 and DBP2 in the semiconductor package 101 can be variably changed to improve and optimize the performance of the semiconductor package 101. For example, the number of dummy conductive bumps DBP1 and DBP2 can be reduced as approaching the first semiconductor chip 50a. In some embodiments, the number of dummy conductive bumps DBP1 and DBP2 provided on even-numbered semiconductor chips can be different from the number of dummy conductive bumps DBP1 and DBP2 provided on odd-numbered semiconductor chips.

[0073] In Figure 12 , the package substrate can replace the first semiconductor chip 50a located at the bottommost position. In this specification, the term “semiconductor chip” may refer to “semiconductor die”.

[0074] Figure 13 The cross-sectional view shown illustrates a semiconductor package according to some example embodiments of the inventive concept.

[0075] Referring to Figure 13 , the semiconductor package 102 can be configured to be similar to Figure 12 the semiconductor package 101 depicted in Figure 12 . For example, the second semiconductor chip 50b to the fifth semiconductor chip 50e can have the same number of conductive bumps RBP1 and RBP2 bonded to the first chip surface 50s1, and can also have the same number of dummy conductive bumps DBP1 and DBP2. Other configurations can be the same as or similar to those discussed above with reference to Figure 12 .

[0076] The semiconductor chips included in the semiconductor package according to the inventive concept can be configured such that the passivation layer includes first holes exposing all the conductive pads, so that process defects caused by the loading effect can be reduced or prevented in the pad opening process.

[0077] In addition, the semiconductor package according to the inventive concept can include one or more second holes formed at positions where no conductive pads exist, so that process defects caused by the loading effect can be reduced or prevented in the pad opening process.

[0078] Furthermore, in the semiconductor package according to the inventive concept, the number and positions of the dummy conductive bumps can be adjusted to improve or optimize the performance of the semiconductor package and to improve or enhance the reliability of the semiconductor package.

[0079] Although the inventive concept has been described in connection with some example embodiments shown in the accompanying drawings, those skilled in the art will understand that various changes and modifications can be made without departing from the technical spirit and basic features of the inventive concept. It will be apparent to those skilled in the art that various substitutions, modifications, and changes can be made herein without departing from the scope of the inventive concept. For example, Figures 1 to 13 the components of can be combined with each other. The subject matter disclosed above should be considered illustrative rather than restrictive, and the appended claims are intended to cover all such modifications, enhancements, and other embodiments that fall within the scope of the inventive concept.

Claims

1. A semiconductor package, the semiconductor package comprising: A semiconductor chip, the semiconductor chip being located on a package substrate; And An underfill layer, the underfill layer being located between the semiconductor chip and the package substrate, Wherein, the semiconductor chip includes: A semiconductor substrate; An interlayer dielectric layer, the interlayer dielectric layer being located on the semiconductor substrate and including a plurality of connection lines therein; A plurality of conductive pads, the plurality of conductive pads being located on the interlayer dielectric layer, a plurality of first conductive pads among the plurality of conductive pads being electrically connected to a plurality of first connection lines among the plurality of connection lines respectively, and a plurality of second conductive pads among the plurality of conductive pads being electrically isolated from the plurality of connection lines; A passivation layer, the passivation layer being located on the interlayer dielectric layer and including a plurality of first holes, the plurality of first holes being located on the plurality of first conductive pads and the plurality of second conductive pads among the plurality of conductive pads respectively; and A plurality of first conductive bumps, the plurality of first conductive bumps being bonded to the plurality of first conductive pads among the plurality of conductive pads respectively, Wherein, the underfill layer includes a first portion, and the first portion is located in one of the plurality of first holes and is in contact with one of the plurality of second conductive pads among the plurality of conductive pads.

2. The semiconductor package according to claim 1, the semiconductor package further comprising a second conductive bump, the second conductive bump being bonded to another second conductive pad among the plurality of second conductive pads among the plurality of conductive pads.

3. The semiconductor package according to claim 1, wherein, The plurality of conductive pads further includes a third conductive pad, the third conductive pad being electrically connected to a second connection line among the plurality of connection lines, and Wherein, the underfill layer includes a second portion, and the second portion is located in another one of the plurality of first holes and is in contact with the third conductive pad.

4. The semiconductor package according to claim 3, wherein, The semiconductor chip further includes a test circuit, the test circuit being connected to the third conductive pad and being located in the interlayer dielectric layer.

5. The semiconductor package according to claim 1, wherein, The plurality of conductive pads further includes a third conductive pad, the third conductive pad being electrically connected to a second connection line among the plurality of connection lines, and Wherein, the semiconductor package further includes a third conductive bump, the third conductive bump extending through the passivation layer and being bonded to the third conductive pad.

6. The semiconductor package according to claim 1, wherein, The passivation layer further includes second holes spaced apart from the plurality of first holes, Wherein, the second holes partially extend into the passivation layer in the thickness direction of the passivation layer.

7. The semiconductor package according to claim 6, wherein, The depth of the second holes is greater than each of the depths of the plurality of first holes.

8. A semiconductor package, the semiconductor package comprising: A semiconductor chip, the semiconductor chip being located on a package substrate, Wherein, the semiconductor chip includes: A semiconductor substrate; An interlayer dielectric layer, the interlayer dielectric layer being located on the semiconductor substrate and including a plurality of connection lines therein; A plurality of conductive pads, the plurality of conductive pads being located on the interlayer dielectric layer, a plurality of first conductive pads among the plurality of conductive pads being electrically connected to a plurality of first connection lines among the plurality of connection lines, and a plurality of second conductive pads among the plurality of conductive pads being electrically isolated from the plurality of connection lines; and A passivation layer, the passivation layer being located on the interlayer dielectric layer, wherein the passivation layer includes a plurality of first holes and second holes, wherein some of the plurality of first holes are respectively located on the plurality of first conductive pads among the plurality of conductive pads and the plurality of second conductive pads among the plurality of conductive pads, and wherein the second holes do not vertically overlap with any of the plurality of first conductive pads among the plurality of conductive pads and do not vertically overlap with any of the plurality of second conductive pads among the plurality of conductive pads.

9. The semiconductor package according to claim 8, wherein, The second holes do not extend through the passivation layer.

10. The semiconductor package according to claim 8, wherein, Each of the plurality of first holes has a first depth, the second holes have a second depth, and the second depth is greater than the first depth.

11. The semiconductor package according to claim 8, wherein, The semiconductor chip further includes a second conductive bump, the second conductive bump being bonded to one of the plurality of second conductive pads among the plurality of conductive pads.

12. The semiconductor package according to claim 8, wherein, The plurality of conductive pads further includes a third conductive pad, the third conductive pad being electrically connected to a second connection line among the plurality of connection lines, and wherein the semiconductor package further includes a third conductive bump, the third conductive bump extending through the passivation layer and being bonded to the third conductive pad.

13. The semiconductor package according to claim 8, the semiconductor package further includes an underfill layer, the underfill layer being located between the package substrate and the semiconductor chip, Among them, The plurality of conductive pads further includes a third conductive pad, the third conductive pad being electrically connected to a second connection line among the plurality of connection lines, wherein one of the plurality of first holes of the passivation layer is located on the third conductive pad, wherein the underfill layer includes a portion located in the one of the plurality of first holes and in contact with the third conductive pad.

14. The semiconductor package according to claim 13, wherein, The semiconductor chip further includes a test circuit, and the test circuit is connected to the third conductive pad and is disposed in the interlayer dielectric layer.

15. A semiconductor package, the semiconductor package comprising: A first semiconductor chip, a second semiconductor chip, and a third semiconductor chip stacked in sequence; A plurality of first conductive bumps and a plurality of first dummy conductive bumps, located between the first semiconductor chip and the second semiconductor chip; and A plurality of second conductive bumps and a plurality of second dummy conductive bumps, located between the second semiconductor chip and the third semiconductor chip, wherein the plurality of first conductive bumps and the plurality of second conductive bumps are configured to transmit electrical signals between the first semiconductor chip, the second semiconductor chip, and the third semiconductor chip, wherein the plurality of first dummy conductive bumps and the plurality of second dummy conductive bumps are electrically floating, Among them, the multiple first conductive bumps and the multiple second conductive bumps include an equal number of conductive bumps, and Among them, the multiple first dummy conductive bumps and the multiple second dummy conductive bumps include different numbers of dummy conductive bumps.

16. The semiconductor package according to claim 15, wherein, The width of the first semiconductor chip is greater than the width of each of the second semiconductor chip and the third semiconductor chip.

17. The semiconductor package according to claim 15, wherein the first semiconductor chip is a logic chip, and the second semiconductor chip and the third semiconductor chip are memory chips.

18. The semiconductor package according to claim 15, the semiconductor package further includes an underfill layer located between the first semiconductor chip and the second semiconductor chip, Among them, The second semiconductor chip includes: a semiconductor substrate; an interlayer dielectric layer, the interlayer dielectric layer is located on the semiconductor substrate and includes a plurality of connection lines; a plurality of conductive pads, the plurality of conductive pads are located on the interlayer dielectric layer, a plurality of first conductive pads among the plurality of conductive pads are respectively electrically connected to some of the plurality of connection lines, and a plurality of second conductive pads among the plurality of conductive pads are electrically isolated from the plurality of connection lines; a passivation layer, the passivation layer is located on the interlayer dielectric layer and includes a plurality of first holes respectively located on the plurality of first conductive pads among the plurality of conductive pads and the plurality of second conductive pads among the plurality of conductive pads; and a plurality of first conductive bumps, the plurality of first conductive bumps are respectively bonded to the plurality of first conductive pads among the plurality of conductive pads, wherein, the underfill layer includes a portion, the portion is located in one of the plurality of first holes and contacts one of the plurality of second conductive pads among the plurality of conductive pads.

19. The semiconductor package according to claim 18, wherein, Some of the first dummy conductive bumps are respectively bonded to the corresponding second conductive pads among the plurality of second conductive pads among the plurality of conductive pads.

20. The semiconductor package according to claim 18, wherein, At least one of the plurality of first dummy conductive bumps is bonded to the passivation layer.

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