Display device

Abstract

A display device is provided. The display device includes: a substrate including a display area and a non-display area; pixels arranged in the display area, each pixel including a pixel circuit and a light-emitting diode; a driving voltage supply line arranged in the non-display area, the driving voltage supply line supplying a driving voltage to the pixels; a common voltage supply line arranged in the non-display area and electrically connected to a counter electrode of the light-emitting diode to supply a common voltage; and a sealing portion surrounding the display area. The common voltage supply line, the driving voltage supply line, and the sealing portion are arranged in the order of the common voltage supply line, the driving voltage supply line, and the sealing portion in a direction away from the display area.

Description

[0001] This application claims the benefit of Korean Patent Application No. 10-2020-0037057, filed on Mar. 26, 2020, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] The present disclosure relates to a display device. Background Art

[0003] Generally, a display device may be used in a mobile device (such as a smart phone, a laptop computer, a digital camera, a camcorder, a portable information terminal, a notebook computer, or a tablet personal computer) or may be used in an electronic device (such as a desktop computer, a television, an outdoor advertising board, a display device for an exhibition, a dashboard for a vehicle, or a head-up display (HUD)).

[0004] The display device includes various circuits to provide an image, and the circuits may be disposed in a non-display area outside a display area where the image is displayed. In the non-display area, various wirings, a gate driver, a data driver, and a controller that transmit an electrical signal to the display area may be provided.

[0005] It is to be understood that this Background Art section is intended to provide useful background for understanding the technology in part. However, this Background Art section may also include ideas, concepts, or knowledge that are known or understood by those skilled in the art in the relevant field before the effective filing date of the corresponding subject matter not disclosed herein. Summary of the Invention

[0006] Generally, display devices are not only becoming more versatile but also thinner and lighter. As display devices can be used in various ways, it may be advantageous to increase a display area that provides an image and to decrease a non-display area that does not provide an image.

[0007] One or more embodiments include a display device that includes a reduced non-display area while maintaining the performance of the display device.

[0008] According to one or more embodiments, a display device may include: a substrate including a display area for displaying an image and a non-display area adjacent to the display area; a plurality of pixels arranged in the display area, each pixel of the plurality of pixels including a pixel circuit and a light-emitting diode, the light-emitting diode including a pixel electrode electrically connected to the pixel circuit, an emission layer, and a counter electrode; a driving voltage supply line arranged in the non-display area to supply a driving voltage to the plurality of pixels; a common voltage supply line arranged in the non-display area and electrically connected to the counter electrode to supply a common voltage; and a sealing portion surrounding the display area. The common voltage supply line, the driving voltage supply line, and the sealing portion may be arranged in the order of the common voltage supply line, the driving voltage supply line, and the sealing portion in a direction away from the display area.

[0009] In an embodiment, the common voltage supply line may be electrically connected to the counter electrode through a connection electrode. The connection electrode and the pixel electrode may be arranged on the same layer.

[0010] In an embodiment, the display device may further include: an auxiliary common voltage supply line arranged between the common voltage supply line and the display area; and a switching circuit including at least one thin film transistor arranged between the common voltage supply line and the auxiliary common voltage supply line. The at least one thin film transistor may supply a data signal to the plurality of pixels.

[0011] In an embodiment, the common voltage supply line and the auxiliary common voltage supply line may include the same stacked structure and may be electrically connected to each other through a connection electrode.

[0012] In an embodiment, an area where the common voltage supply line, the auxiliary common voltage supply line, the connection electrode, and the counter electrode are electrically connected to each other may be arranged around an upper portion of the switching circuit.

[0013] In an embodiment, the connection electrode electrically connected to the counter electrode may be arranged on the common voltage supply line.

[0014] In an embodiment, a planarization layer including at least one layer may cover the common voltage supply line, the connection electrode may be arranged on the planarization layer and may be electrically connected to the common voltage supply line through a contact hole of the planarization layer, and the counter electrode may be electrically connected to the connection electrode through an opening of a pixel defining layer covering at least a portion of the pixel electrode.

[0015] In an embodiment, the connection electrode may include a plurality of holes, the pixel defining layer may cover an edge of the connection electrode where the plurality of holes are arranged, and an opening of the pixel defining layer may expose a portion of the connection electrode electrically connected to the counter electrode.

[0016] In an embodiment, the driving voltage supply line may be arranged adjacent to the sealing portion.

[0017] In an embodiment, at least a portion of the sealing part may overlap with the driving voltage supply line. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The above and other aspects, features, and advantages of the disclosed embodiments will become more apparent from the following description taken in conjunction with the accompanying drawings, in which:

[0019] Figure 1 is a schematic perspective view showing a display device according to an embodiment;

[0020] Figure 2A and Figure 2B is a schematic cross-sectional view showing a display device according to an embodiment;

[0021] Figure 3 is a schematic plan view showing a display device according to an embodiment;

[0022] Figure 4A and Figure 4B is an equivalent circuit diagram of a pixel according to an embodiment;

[0023] Figure 5 is along Figure 3 schematic cross-sectional views of the display device taken along lines I-I' and II-II';

[0024] Figure 6 is from Figure 5 schematic cross-sectional views of the display device modified from the embodiment shown therein; and

[0025] Figure 7 is a schematic cross-sectional view showing a display device according to another embodiment. DETAILED DESCRIPTION

[0026] Reference will now be made in detail to the embodiments, examples of which are illustrated in the accompanying drawings, wherein like reference numerals always refer to like elements. In this regard, the embodiments may have different forms and should not be construed as limited to the description set forth herein. Accordingly, the embodiments are described below only by referring to the drawings to explain aspects of the present disclosure.

[0027] As used herein, the term "and / or" may include any combination and all combinations of one or more of the associated listed items. Throughout the disclosure, the expression "at least one of a, b, and c" indicates only a, only b, only c, both a and b, both a and c, both b and c, all of a, b, and c, or variations thereof.

[0028] Since the disclosure permits various changes and many embodiments, specific embodiments will be shown in the drawings and described in detail in the written description. The effects and features of the disclosure and the method of achieving them can be more easily understood by referring to the following detailed description of the preferred embodiments and the drawings. However, the disclosure can be implemented in many different forms and should not be construed as limited to the embodiments set forth herein.

[0029] When a layer, film, region, substrate, or zone is referred to as being "on" another layer, film, region, substrate, or zone, the layer, film, region, substrate, or zone can be directly on the other layer, film, region, substrate, or zone, or an intermediate layer, intermediate film, intermediate region, intermediate substrate, or intermediate zone can be present therebetween. In contrast, when a layer, film, region, substrate, or zone is referred to as being "directly on" another layer, film, region, substrate, or zone, no intermediate layer, intermediate film, intermediate region, intermediate substrate, or intermediate zone will be present therebetween. Additionally, when a layer, film, region, substrate, or zone is referred to as being "under" another layer, film, region, substrate, or zone, the layer, film, region, substrate, or zone can be directly under the other layer, film, region, substrate, or zone, or an intermediate layer, intermediate film, intermediate region, intermediate substrate, or intermediate zone can be present therebetween. In contrast, when a layer, film, region, substrate, or zone is referred to as being "directly under" another layer, film, region, substrate, or zone, no intermediate layer, intermediate film, intermediate region, intermediate substrate, or intermediate zone will be present therebetween. Further, "above" or "on" can include being positioned on or under an object and does not necessarily imply a direction based on gravity.

[0030] For ease of description, spatial relative terms such as "under", "below", "lower", "above", "upper", etc. may be used herein to describe the relationship between one element or component and another element or component as shown in the drawings. It will be understood that the spatial relative terms are intended to cover different orientations of the device in use or operation in addition to the orientation depicted in the drawings. For example, in the case where the device shown in the drawings is flipped, a device positioned "under" or "below" another device can be located "above" the other device. Thus, the illustrative term "under" can include both the position below and the position above. The device can also be oriented in other directions, and thus the spatial relative terms can be interpreted differently depending on the orientation.

[0031] Throughout the specification, the x-axis, y-axis, and z-axis are not limited to the three axes on a rectangular coordinate system and can be interpreted in a broader sense. For example, the x-axis, y-axis, and z-axis can be orthogonal to each other, or can represent different directions that are not orthogonal to each other.

[0032] In addition, in the specification, the phrase "in a plan view" means when the object part is observed from above, and the phrase "in a cross-sectional view" means when the cross-section obtained by vertically cutting the object part is observed from the side. In addition, the term "superposed" or its variants means that the first object can be above or below the second object, and vice versa.

[0033] It will be understood that although terms such as "first" and "second" may be used herein to describe various components, these components should not be limited by these terms, and these terms are only used to distinguish one component from another.

[0034] In addition, as used herein, the singular forms "a" and "the" are also intended to include the plural forms, unless the context clearly indicates otherwise.

[0035] In addition, it will be understood that the terms "comprising", "including" and "having" as used herein specify the presence of the stated features or components, but do not preclude the presence or addition of one or more other features or components.

[0036] When describing embodiments with reference to the accompanying drawings, the same reference numerals are assigned to the same or corresponding components, and redundant descriptions thereof may be omitted.

[0037] In the following embodiments, when layers, regions or components are connected to each other, the layers, regions or components may be directly connected to each other, or another layer, region or component may be interposed between the layers, regions or components, so that the layers, regions or components may be indirectly connected to each other. For example, in the following embodiments, when layers, regions or components are electrically connected to each other, the layers, regions or components may be directly electrically connected to each other, or another layer, region or component may be interposed between the layers, regions or components, so that the layers, regions or components may be indirectly electrically connected.

[0038] Figure 1 is a schematic perspective view showing a display device 100 according to an embodiment.

[0039] Referring to Figure 1 , the display device 100 includes a display area DA and a non-display area NDA adjacent to the display area DA. The display device 100 can display an image through the display area DA. The display device 100 may include a liquid crystal display, an electrophoretic display, an organic light emitting display, an inorganic light emitting display, a quantum dot light emitting display, a field emission display, a surface conduction electron emitter display, a plasma display or a cathode ray display.

[0040] Hereinafter, an exemplary organic light emitting display device will be described as the display device 100 according to an embodiment. However, the display device 100 is not limited thereto, and various types of display devices may be used as the display device 100.

[0041] Figure 2A and Figure 2B is a schematic cross-sectional view showing a display device 200 according to an embodiment.

[0042] Referring to Figure 2A , the display device 200 includes a display element layer 220 located on a substrate 210 and a packaging member 230 covering the display element layer 220.

[0043] The substrate 210 may include a polymer resin such as polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, or cellulose acetate propionate. The substrate 210 may have a single-layer structure material or a multi-layer structure material, and in the case of a multi-layer structure, the substrate 210 may further include an inorganic layer (not shown). The substrate 210 may have flexible, rollable, or bendable characteristics.

[0044] The display element layer 220 may include pixels, and each pixel may include an organic light-emitting diode and a pixel circuit electrically connected to the organic light-emitting diode. The pixel circuit may include a thin-film transistor, a storage capacitor, and conductive wires electrically connected to the thin-film transistor and the storage capacitor, and may include an insulating layer.

[0045] The packaging member 230 may protect the display element layer 220 from external foreign substances (such as moisture). The packaging member 230 may be a thin-film encapsulation layer including at least one inorganic encapsulation layer (e.g., a first inorganic encapsulation layer 240 and a second inorganic encapsulation layer 260) and at least one organic encapsulation layer 250. Each of the first inorganic encapsulation layer 240 and the second inorganic encapsulation layer 260 may include a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, a titanium oxide layer, an aluminum oxide layer, etc. However, the disclosure is not limited thereto. The organic encapsulation layer 250 may include an acrylic organic material. However, the disclosure is not limited thereto.

[0046] Although Figure 2A the packaging member 230 of Figure 2A may include a first inorganic encapsulation layer 240, a second inorganic encapsulation layer 260, and an organic encapsulation layer 250 located therebetween, the disclosure is not limited thereto. The stacking order of the first inorganic encapsulation layer 240, the second inorganic encapsulation layer 260, and the organic encapsulation layer 250 may be changed. Although Figure 2A shows that the packaging member 230 is a thin-film encapsulation layer, the disclosure is not limited thereto.

[0047] Referring to Figure 2B , the display device 200' may include a packaging member 230', and the packaging member 230' includes a sealing portion 240' and a packaging substrate 250'. Figure 2BThe base 210 may include the above-mentioned polymer resin or include glass or the like.

[0048] The encapsulation base 250' may be arranged to face the base 210, and the sealing portion 240' may be arranged between the base 210 and the encapsulation base 250'. The sealing portion 240' may surround the display area DA. The internal space defined by the base 210, the encapsulation base 250', and the sealing portion 240' may be spatially separated from the outside and may prevent the penetration of moisture or impurities. The encapsulation base 250' may include the above-mentioned polymer resin or glass, and the sealing portion 240' may use a material such as frit or epoxy resin.

[0049] Figure 3 is a schematic plan view showing a display device 300 according to an embodiment, Figure 4A and Figure 4B is an equivalent circuit diagram of a pixel P according to an embodiment.

[0050] Referring to Figure 3 , the display device 300 includes pixels P arranged in the display area DA. Each of the pixels P may emit red, green, blue, or white light and may include, for example, an organic light-emitting diode. In addition, each of the pixels P may include elements such as a thin-film transistor or a capacitor.

[0051] Referring to Figure 4A , each pixel P may include a pixel circuit PC electrically connected to a scan line SL and a data line DL and an organic light-emitting diode OLED electrically connected to the pixel circuit PC. The pixel circuit PC may include a driving thin-film transistor T1, a switching thin-film transistor T2, and a storage capacitor Cst.

[0052] The switching thin-film transistor T2 may transmit a data signal Dm input through the data line DL to the driving thin-film transistor T1 according to a scan signal Sn input through the scan line SL.

[0053] The storage capacitor Cst is electrically connected to the switching thin-film transistor T2 and the driving voltage line PL and may store a voltage corresponding to the difference between the voltage received from the switching thin-film transistor T2 and the first power voltage (or driving voltage) ELVDD supplied to the driving voltage line PL.

[0054] The driving thin-film transistor T1 is electrically connected to the driving voltage line PL and the storage capacitor Cst and may control the driving current flowing through the organic light-emitting diode OLED from the driving voltage line PL in response to the voltage value stored in the storage capacitor Cst. The driving current may cause the organic light-emitting diode OLED to emit light with a predetermined brightness.

[0055] Figure 4Aillustrates a case where the pixel circuit PC includes two thin film transistors and a storage capacitor. However, the disclosure is not limited thereto.

[0056] Referring Figure 4B , the pixel circuit PC may include a driving thin film transistor T1, a switching thin film transistor T2, a compensating thin film transistor T3, a first initialization thin film transistor T4, a first emission control thin film transistor T5, a second emission control thin film transistor T6, and a second initialization thin film transistor T7.

[0057] Although Figure 4B illustrates a case where signal lines SLn, SLn-1, EL, and DL, an initialization voltage line VL, and a driving voltage line PL are provided for the pixel P, the disclosure is not limited thereto. In another embodiment, at least one of the signal lines SLn, SLn-1, EL, and DL and / or the initialization voltage line VL may be shared by adjacent pixels P.

[0058] The drain electrode of the driving thin film transistor T1 may be electrically connected to the organic light emitting diode OLED via the second emission control thin film transistor T6. The driving thin film transistor T1 may receive a data signal Dm according to the switching operation of the switching thin film transistor T2 and supply a driving current to the organic light emitting diode OLED.

[0059] The gate electrode of the switching thin film transistor T2 may be electrically connected to the first scan line SLn, and the source electrode of the switching thin film transistor T2 may be electrically connected to the data line DL. The drain electrode of the switching thin film transistor T2 may be electrically connected to the source electrode of the driving thin film transistor T1 and may be electrically connected to the driving voltage line PL via the first emission control thin film transistor T5.

[0060] The switching thin film transistor T2 may be turned on according to the first scan signal Sn received through the first scan line SLn and perform a switching operation for transmitting the data signal Dm transmitted to the data line DL to the source electrode of the driving thin film transistor T1.

[0061] The gate electrode of the compensating thin film transistor T3 may be electrically connected to the first scan line SLn. The source electrode of the compensating thin film transistor T3 may be electrically connected to the drain electrode of the driving thin film transistor T1 and may be electrically connected to the pixel electrode of the organic light emitting diode OLED via the second emission control thin film transistor T6. The drain electrode of the compensating thin film transistor T3 may be electrically connected to one electrode of the storage capacitor Cst, the source electrode of the first initialization thin film transistor T4, and the gate electrode of the driving thin film transistor T1. The compensating thin film transistor T3 may be turned on according to the first scan signal Sn received through the first scan line SLn to electrically connect the gate electrode and the drain electrode of the driving thin film transistor T1 to each other. Therefore, the driving thin film transistor T1 may be diode-connected.

[0062] The gate electrode of the first initialization thin film transistor T4 can be electrically connected to the second scan line SLn-1 which serves as the previous scan line. The drain electrode of the first initialization thin film transistor T4 can be electrically connected to the initialization voltage line VL. The source electrode of the first initialization thin film transistor T4 can be electrically connected to one electrode of the storage capacitor Cst, the drain electrode of the compensation thin film transistor T3, and the gate electrode of the driving thin film transistor T1. The first initialization thin film transistor T4 can be turned on according to the second scan signal Sn-1 received through the second scan line SLn-1 and transmit the initialization voltage VINT to the gate electrode of the driving thin film transistor T1 to perform an initialization operation for initializing the voltage of the gate electrode of the driving thin film transistor T1.

[0063] The gate electrode of the first emission control thin film transistor T5 can be electrically connected to the emission control line EL. The source electrode of the first emission control thin film transistor T5 can be electrically connected to the driving voltage line PL. The drain electrode of the first emission control thin film transistor T5 can be electrically connected to the source electrode of the driving thin film transistor T1 and the drain electrode of the switching thin film transistor T2.

[0064] The gate electrode of the second emission control thin film transistor T6 can be electrically connected to the emission control line EL. The source electrode of the second emission control thin film transistor T6 can be electrically connected to the drain electrode of the driving thin film transistor T1 and the source electrode of the compensation thin film transistor T3. The drain electrode of the second emission control thin film transistor T6 can be electrically connected to the pixel electrode of the organic light emitting diode OLED. The first emission control thin film transistor T5 and the second emission control thin film transistor T6 can be turned on simultaneously according to the emission control signal En transmitted through the emission control line EL. Therefore, the first power voltage ELVDD can be transmitted to the organic light emitting diode OLED and a driving current can flow through the organic light emitting diode OLED.

[0065] The gate electrode of the second initialization thin film transistor T7 can be electrically connected to the second scan line SLn-1. The source electrode of the second initialization thin film transistor T7 can be electrically connected to the pixel electrode of the organic light emitting diode OLED. The drain electrode of the second initialization thin film transistor T7 can be electrically connected to the initialization voltage line VL. The second initialization thin film transistor T7 can be turned on according to the second scan signal Sn-1 received through the second scan line SLn-1 to initialize the pixel electrode of the organic light emitting diode OLED.

[0066] At Figure 4BAmong them, the first initialization thin film transistor T4 and the second initialization thin film transistor T7 are electrically connected to the second scan line SLn-1. However, the disclosure is not limited thereto. In another embodiment, the first initialization thin film transistor T4 may be electrically connected to the second scan line SLn-1 as the previous scan line and driven according to the second scan signal Sn-1. The second initialization thin film transistor T7 may be electrically connected to a separate signal line (e.g., the subsequent scan line) and may be driven according to the signal transmitted to the separate signal line.

[0067] One electrode of the storage capacitor Cst may be electrically connected to the gate electrode of the driving thin film transistor T1, the drain electrode of the compensation thin film transistor T3, and the source electrode of the first initialization thin film transistor T4. The other electrode of the storage capacitor Cst may be electrically connected to the driving voltage line PL.

[0068] The counter electrode (e.g., the cathode) of the organic light emitting diode OLED is supplied with the second power voltage (or the common power voltage) ELVSS. The organic light emitting diode OLED may emit light by receiving a driving current from the driving thin film transistor T1.

[0069] The pixel circuit PC is not limited to the circuit design described with reference to Figure 4A and Figure 4B the number of thin film transistors and storage capacitors, and the number of thin film transistors and storage capacitors as well as the circuit design may vary.

[0070] Returning to Figure 3 , the non-display area NDA of the display device 300 may surround the display area DA. The non-display area NDA may be an area where no image is provided.

[0071] The scan driving circuit 310 as the first external circuit, the control driving circuit 320 as the second external circuit, the terminal portion 330, the driving voltage supply line 340 and the common voltage supply line 350, and the sealing portion 400 may be arranged in the non-display area NDA.

[0072] The scan driving circuit 310 may be arranged in the non-display area NDA of the substrate 501. The scan driving circuit 310 may be electrically connected to the scan line SL and may supply a scan signal to the scan line SL.

[0073] The control driving circuit 320 may be arranged in the non-display area NDA of the substrate 501. The scan driving circuit 310 and the control driving circuit 320 may be arranged parallel to each other, and the display area DA is arranged therebetween. The scan driving circuit 310 may be arranged near the first side edge of the display area DA, and the control driving circuit 320 may be arranged near the second side edge opposite to the first side edge of the display area DA.

[0074] The terminal portion 330 may be disposed at one end of the substrate 501. The terminal portion 330 may be exposed without being covered by an insulating layer and is electrically connected to the printed circuit board PCB. The terminal portion 330 may be disposed in the non-display area NDA where the scan driving circuit 310 and the control driving circuit 320 are not located. For example, the terminal portion 330 may be disposed parallel to the third side edge of the display area DA.

[0075] The terminal PCB-P of the printed circuit board PCB may be electrically connected to the terminal portion 330 of the display device 300. The printed circuit board PCB may supply power or signals from a controller (not shown) to the display device 300. The control signals generated by the controller may be transmitted to each of the scan driving circuit 310 and the control driving circuit 320 through the printed circuit board PCB.

[0076] The controller may provide a first power voltage ELVDD and a second power voltage ELVSS through the first connection line 340a and the second connection line 350a, respectively. The first power voltage ELVDD may be supplied to each pixel P through the driving voltage line PL electrically connected to the driving voltage supply line 340, and the second power voltage ELVSS may be supplied to the counter electrode of the pixel P electrically connected to the common voltage supply line 350.

[0077] The data driving circuit 360 may be electrically connected to the data line DL. The data signals of the data driving circuit 360 may be provided to each pixel P through the wiring 361 electrically connected to the terminal portion 330 and the data line DL electrically connected to the wiring 361. Figure 3 It is shown that the data driving circuit 360 is disposed on the printed circuit board PCB. However, the disclosure is not limited thereto. In another embodiment, the data driving circuit 360 may be disposed on the substrate 501. For example, the data driving circuit 360 may be disposed Figure 3 between the terminal portion 330 and the driving voltage supply line 340 as shown.

[0078] The driving voltage supply line 340 may be disposed in the non-display area NDA. The driving voltage supply line 340 may be disposed adjacent to the third side edge of the substrate 501. For example, the driving voltage supply line 340 may be disposed in the lower portion of the substrate 501 in the y direction. The first connection line 340a may extend from the driving voltage supply line 340 toward the first terminal 331 disposed in the lower portion of the substrate 501 in the y direction. The first connection line 340a may be electrically connected to the first terminal 331 of the terminal portion 330.

[0079] The common voltage supply line 350 may be disposed in the non-display area NDA. The common voltage supply line 350 may partially surround the display area DA along the edge of the display area DA. For example, the common voltage supply line 350 may have an annular shape, and a portion corresponding to the lower part of the substrate 501 is open in the y direction. The second connection line 350a may extend parallel to the first connection line 340a in the y direction and may be electrically connected to the second terminal 332 of the terminal portion 330.

[0080] The controller may transmit different voltages to the driving voltage supply line 340 and the common voltage supply line 350 through the first terminal 331 and the second terminal 332, respectively. The common voltage supply line 350 may have a voltage lower than that of the driving voltage supply line 340. The controller may convert an image signal transmitted from an external component into an image data signal and transmit the image data signal to the display area DA through the third terminal 333 of the terminal portion 330.

[0081] The auxiliary common voltage supply line 370 may be further disposed in the non-display area NDA. The auxiliary common voltage supply line 370 may be disposed adjacent to the third side edge of the substrate 501. The auxiliary common voltage supply line 370 may be disposed in the lower part of the substrate 501 in the y direction. The auxiliary common voltage supply line 370 may be disposed between the display area DA and the common voltage supply line 350.

[0082] The display device 300 may further include a switch circuit 380 as a third external circuit. The switch circuit 380 may be electrically connected to the data driving circuit 360 and the data line DL of the pixel P. The switch circuit 380 may include a demultiplexer that demultiplexes a data signal output from the data driving circuit 360 and supplies the output signal to the data line DL. The switch circuit 380 may be disposed between the common voltage supply line 350 and the auxiliary common voltage supply line 370.

[0083] The common voltage supply line 350 and the auxiliary common voltage supply line 370 may be spaced apart from each other in the lower part of the substrate 501 in the y direction, and the switch circuit 380 is disposed between the common voltage supply line 350 and the auxiliary common voltage supply line 370. The common voltage supply line 350 and the auxiliary common voltage supply line 370 may be electrically connected to each other through a connection electrode 390.

[0084] The sealing portion 400 may surround the display area DA. The sealing portion 400 may seal the display area DA from external air.

[0085] Figure 5 is a schematic cross-sectional view of the display device 300 taken along Figure 3 lines I-I' and II-II'.

[0086] Reference Figure 5 , in region I-I' which is part of the cross-section of display area DA, buffer layer 502 can be disposed on substrate 501. Buffer layer 502 can block foreign objects or moisture penetrating substrate 501. For example, buffer layer 502 can include inorganic materials such as silicon oxide, silicon nitride, and / or silicon oxynitride, and can include a single layer or multiple layers.

[0087] Thin film transistor TFT, storage capacitor Cst, and organic light-emitting diode OLED electrically connected to thin film transistor TFT and storage capacitor Cst can be disposed on substrate 501. Thin film transistor TFT includes semiconductor layer ACT and gate electrode GE. Semiconductor layer ACT can include polycrystalline silicon, amorphous silicon, oxide semiconductor, organic semiconductor material, etc. In an embodiment, semiconductor layer ACT can include channel region CR, source region SR, and drain region DR. Channel region CR is stacked with gate electrode GE. Source region SR and drain region DR are disposed on both sides of channel region CR and include impurities with a higher concentration than that in channel region CR. In this case, the impurities can include N-type impurities or P-type impurities. Source region SR and drain region DR can be electrically connected to source electrode 515 and drain electrode 516 respectively.

[0088] Gate insulating layer 503 can be disposed between semiconductor layer ACT and gate electrode GE. Gate insulating layer 503 can be an inorganic material layer including silicon oxynitride, silicon oxide, and / or silicon nitride, and the inorganic material layer can include a single layer or multiple layers.

[0089] Storage capacitor Cst includes first storage capacitor plate CE1 and second storage capacitor plate CE2 stacked with each other. First interlayer insulating layer 504 can be disposed between first storage capacitor plate CE1 and second storage capacitor plate CE2. First interlayer insulating layer 504 can be a layer with a predetermined dielectric constant. First interlayer insulating layer 504 can be an inorganic material layer including silicon oxynitride, silicon oxide, and / or silicon nitride, and can include a single layer or multiple layers.

[0090] Although Figure 5 it shows the case where storage capacitor Cst is stacked with thin film transistor TFT and first storage capacitor plate CE1 is the gate electrode of thin film transistor TFT, the disclosure is not limited thereto. In another embodiment, storage capacitor Cst can be not stacked with thin film transistor TFT, and first storage capacitor plate CE1 can be an independent component separated from gate electrode GE of thin film transistor TFT.

[0091] Storage capacitor Cst can be covered by second interlayer insulating layer 505. Second interlayer insulating layer 505 can be an inorganic material layer including silicon oxynitride, silicon oxide, and / or silicon nitride, and can include a single layer or multiple layers.

[0092] The driving voltage line PL may include a first driving voltage line PL1 and a second driving voltage line PL2. The first driving voltage line PL1 may include aluminum (Al), copper (Cu), titanium (Ti), etc., and may include multiple layers or a single layer. In an embodiment, the first driving voltage line PL1 may have a multi-layer structure of Ti / Al / Ti. The first driving voltage line PL1 may be covered by a first planarization layer 507. An inorganic protection layer 506 for protecting the conductive wire may be further disposed under the first planarization layer 507. The conductive wire and the first driving voltage line PL1 may be disposed on the same layer.

[0093] The second driving voltage line PL2 may be disposed on the first driving voltage line PL1 with the first planarization layer 507 therebetween, and the second driving voltage line PL2 may be electrically connected to the first driving voltage line PL1 through a contact hole formed in the first planarization layer 507. The second driving voltage line PL2 may include Al, Cu, Ti, etc., and may include multiple layers or a single layer. In an embodiment, the second driving voltage line PL2 may have a multi-layer structure of Ti / Al / Ti. The first planarization layer 507 may include an organic insulating material; and the organic insulating material may include an imide polymer, a general polymer such as polymethyl methacrylate or polystyrene, a polymer derivative having a phenolic group, an acrylic polymer, an aryl ether polymer, an amide polymer, a fluoropolymer, a parylene polymer, a polyvinyl alcohol polymer, or a blend thereof. In an embodiment, the first planarization layer 507 may include polyimide.

[0094] The driving voltage line PL may be covered by a second planarization layer 508, and the second planarization layer 508 may include an organic insulating material. For example, the second planarization layer 508 may include an imide polymer, a general polymer such as polymethyl methacrylate or polystyrene, a polymer derivative having a phenolic group, an acrylic polymer, an aryl ether polymer, an amide polymer, a fluoropolymer, a parylene polymer, a polyvinyl alcohol polymer, or a blend thereof. In an embodiment, the second planarization layer 508 may include polyimide.

[0095] The pixel electrode 509 may be disposed on the second planarization layer 508. The pixel defining layer 510 may be disposed on the pixel electrode 509. The pixel defining layer 510 may have an opening corresponding to each pixel P, for example, an opening 511 that exposes a part of the pixel electrode 509 and defines the pixel P. In addition, the pixel defining layer 510 may increase the distance between the edge of the pixel electrode 509 and the counter electrode 512, and may prevent the formation of an arc or the like therebetween. The pixel defining layer 510 may include an organic material such as polyimide or hexamethyldisiloxane.

[0096] The intermediate layer 513 may include a low molecular weight material or a polymer material.

[0097] When the intermediate layer 513 includes a low molecular weight material, the intermediate layer 513 may have a structure in which a hole injection layer, a hole transport layer, an emission layer, an electron transport layer, an electron injection layer, etc. are stacked in a single structure or a composite structure. The intermediate layer 513 may include various organic materials such as copper phthalocyanine, N,N'-bis(naphthalen-1-yl)-N,N'-diphenyl-benzidine, and tris(8-hydroxyquinoline)aluminum (Alq3). These layers may be formed by a vapor deposition method.

[0098] When the intermediate layer 513 includes a polymer material, the intermediate layer 513 may have a structure including a hole transport layer and an emission layer. The hole transport layer may include poly(3,4-ethylenedioxythiophene) (PEDOT); and the emission layer may include polymer materials such as polyphenylene vinylene (PPV)-type polymers or polyfluorene-type polymers. The structure of the intermediate layer 513 is not limited to the above structure, and the intermediate layer 513 may have various structures. For example, at least one of the layers constituting the intermediate layer 513 may be integrally formed on the pixel electrode 509. Alternatively, the intermediate layer 513 may include layers patterned to correspond to each of the pixel electrodes 509.

[0099] The counter electrode 512 may be disposed above the display area DA to cover the display area DA. Specifically, the counter electrode 512 may be formed as a monomer to cover the pixel P.

[0100] In region II-II' of Figure 5 which is a part of the cross-section of the display area DA, the inorganic insulating layer 514 may be disposed on the substrate 501. The inorganic insulating layer 514 may include at least one of a buffer layer 502, a gate insulating layer 503, a first interlayer insulating layer 504, and a second interlayer insulating layer 505.

[0101] The driving voltage supply line 340, the common voltage supply line 350, the auxiliary common voltage supply line 370, the switching circuit 380, and the sealing portion 400 may be disposed in the non-display area NDA.

[0102] The driving voltage supply line 340 may include a first layer 341 and a second layer 342, and the second layer 342 is electrically connected to the first layer 341. The first layer 341 may be disposed on the second interlayer insulating layer 505. The first layer 341, the source electrode 515, and the drain electrode 516 may be disposed on the same layer and may include the same material.

[0103] The first layer 341 may be covered by the first planarization layer 507. The first planarization layer 507 may include a first opening OP1, and at least a portion of the first layer 341 is exposed through the first opening OP1. The separated portions 507a of the first planarization layer 507 may be disposed in the opening OP1 and spaced apart from each other.

[0104] The second layer 342 may be disposed on the first planarization layer 507. A portion of the second layer 342 may contact the first layer 341 through the opening OP1. The second layer 342 may cover the separated portions 507a of the first planarization layer 507 disposed in the opening OP1 to increase the contact area. The second layer 342 and a conductive wire such as the second driving voltage line PL2 may be disposed on the same layer and may include the same material. The second layer 342 may be covered by the second planarization layer 508.

[0105] The first layer 341 for the driving voltage supply line and the second layer 342 for the driving voltage supply line, which are electrically connected to each other, may form (or constitute) the driving voltage supply line 340, and the driving voltage supply line 340 supplies the first power voltage ELVDD to each pixel P through the driving voltage line PL. In an embodiment, the driving voltage supply line 340 has a structure in which the first layer 341 and the second layer 342 are stacked, but is not limited thereto. For example, the driving voltage supply line 340 may include only one of the first layer 341 and the second layer 342. The driving voltage supply line 340 may have any structure capable of supplying the first power voltage ELVDD to each pixel P.

[0106] The common voltage supply line 350 may be disposed closer to the display area DA than the driving voltage supply line 340. For example, the common voltage supply line 350 may be disposed between the display area DA and the driving voltage supply line 340 in the lower portion of the substrate 501 in Figure 3 the y direction.

[0107] The common voltage supply line 350 includes a first layer 351 for the common voltage supply line and a second layer 352 for the common voltage supply line, and the second layer 352 is electrically connected to the first layer 351. The first layer 351 may be disposed on the interlayer insulating layer 505. The first layer 351, the source electrode 515, and the drain electrode 516 may be disposed on the same layer and may include the same material.

[0108] The first layer 351 may be covered by the first planarization layer 507. The first planarization layer 507 may include a second opening OP2, and at least a portion of the first layer 351 is exposed through the second opening OP2. The second layer 352 may be disposed on the first planarization layer 507. A portion of the second layer 352 may contact the first layer 351 through the second opening OP2. The second layer 352 and a conductive line such as the second driving voltage line PL2 may be disposed on the same layer and may include the same material. The second layer 352 may be covered by the second planarization layer 508.

[0109] The first layer 351 and the second layer 352 that are electrically connected to each other for the common voltage supply line may form (or constitute) the common voltage supply line 350, and the common voltage supply line 350 supplies the second power voltage ELVSS to each pixel P through the connection electrode 390 and the counter electrode 512. In an embodiment, the common voltage supply line 350 has a structure in which the first layer 351 and the second layer 352 are stacked, but is not limited thereto. For example, the common voltage supply line 350 may include only one of the first layer 351 or the second layer 352. The common voltage supply line 350 may have any structure capable of supplying the second power voltage ELVSS to each pixel P.

[0110] The fan-out line 517 may be disposed under the driving voltage supply line 340 and the common voltage supply line 350. The fan-out line 517 includes a first fan-out line 518 disposed on the gate insulating layer 503 and a second fan-out line 519 disposed on the first interlayer insulating layer 504. Since the first fan-out line 518 and the second fan-out line 519 are disposed on different layers and the first interlayer insulating layer 504 is therebetween, more fan-out lines 517 may be disposed in the same area, and a short circuit between the fan-out lines 517 can be prevented.

[0111] The auxiliary common voltage supply line 370 may be disposed closer to the display area DA than the common voltage supply line 350. Specifically, the auxiliary common voltage supply line 370 may be disposed between the display area DA and the common voltage supply line 350 in the lower portion of the substrate 501 in the Figure 3 y direction. The auxiliary common voltage supply line 370 may be installed to prevent a voltage drop of the common voltage supply line 350.

[0112] The auxiliary common voltage supply line 370 and the common voltage supply line 350 may have substantially the same stacked structure. The auxiliary common voltage supply line 370 includes a first layer 371 for the auxiliary common voltage supply line and a second layer 372 for the auxiliary common voltage supply line, and the second layer 372 is electrically connected to the first layer 371. Similar to the common voltage supply line 350, the second layer 372 may contact the first layer 371 through a third opening OP3 of the first planarization layer 507, and at least a part of the first layer 371 is exposed through the third opening OP3. In another embodiment, the auxiliary common voltage supply line 370 may have a stacked structure different from that of the common voltage supply line 350.

[0113] The common voltage supply line 350 and the auxiliary common voltage supply line 370 may be electrically connected to each other through a connection electrode 390. The connection electrode 390 may be disposed on the common voltage supply line 350 and the auxiliary common voltage supply line 370. For example, the connection electrode 390 may be disposed on the second planarization layer 508. The connection electrode 390 may cover an edge of the common voltage supply line 350 and an edge of the auxiliary common voltage supply line 370 that face each other.

[0114] The connection electrode 390 and the pixel electrode 509 may be disposed on the same layer and may include the same material. The connection electrode 390 may include a hole 390H. The pixel defining layer 510 may include a fourth opening OP4 that exposes at least a part of the connection electrode 390. The pixel defining layer 510 may expose a part of the connection electrode 390 and cover the edge of the connection electrode 390 in a part where each of the holes 390H is disposed.

[0115] The counter electrode 512 may be electrically connected to the connection electrode 390 through the fourth opening OP4. A first part 391 of the connection electrode 390 may be electrically connected to the common voltage supply line 350 through a contact hole formed in the second planarization layer 508, and a second part 392 of the connection electrode 390 may be electrically connected to the auxiliary common voltage supply line 370 through a contact hole formed in the second planarization layer 508.

[0116] In this way, the common voltage supply line 350 may be electrically connected to the auxiliary common voltage supply line 370 through the first part 391 of the connection electrode 390, the counter electrode 512, and the second part 392 of the connection electrode 390.

[0117] The switch circuit 380 may be disposed between the common voltage supply line 350 and the auxiliary common voltage supply line 370. For example, on the substrate 501 at Figure 3In the lower part in the y direction thereof, the common voltage supply line 350 and the auxiliary common voltage supply line 370 may be spaced apart from each other, and the switching circuit 380 is disposed therebetween. The switching circuit 380 may receive a data signal from a controller and may distribute or provide the data signal to the pixel P. The switching circuit 380 may include at least one thin film transistor TFT. The thin film transistor TFT includes a semiconductor layer ACT, a gate electrode G, a source electrode S, and a drain electrode D.

[0118] An area where the common voltage supply line 350 and the counter electrode 512 are electrically connected to each other may be disposed on the switching circuit 380. For example, an area where the common voltage supply line 350, a first part 391 of the connection electrode 390, the counter electrode 512, a second part 392 of the connection electrode 390, and the auxiliary common voltage supply line 370 are electrically connected to each other may be disposed around the upper part of the switching circuit 380.

[0119] The sealing part 400 may be disposed between the substrate 501 and the encapsulation substrate 520. The sealing part 400 may surround the display area DA. The sealing part 400 may include epoxy resin, a sealant, glass, or a glass frit. The encapsulation substrate 520 may include glass, plastic, or metal. A heat source (such as resistive heat or a laser) may be used to cure the sealing part 400 to bond the substrate 501 and the encapsulation substrate 520 together. The sealing part 400 may be bonded to the substrate 501 and the encapsulation substrate 520 to prevent external moisture, air, etc. from penetrating into the display area DA.

[0120] In an embodiment, the display area DA may be sealed with a thin film encapsulation layer including at least one inorganic encapsulation layer and at least one organic encapsulation layer. The thin film encapsulation layer may cover the display area DA and may extend outside the display area DA.

[0121] In the non-display area NDA, the auxiliary common voltage supply line 370, the switching circuit 380, the common voltage supply line 350, the driving voltage supply line 340, and the sealing part 400 may be arranged in such an order (i.e., the auxiliary common voltage supply line 370, the switching circuit 380, the common voltage supply line 350, the driving voltage supply line 340, and the sealing part 400) in a direction away from the display area DA.

[0122] An area where the common voltage supply line 350 and the counter electrode 512 are electrically connected to each other may be disposed between the display area DA and the driving voltage supply line 340, rather than between the driving voltage supply line 340 and the sealing part 400. Accordingly, a connection part between the common voltage supply line 350 for applying the second power voltage ELVSS and the counter electrode 512 may not be affected by a margin between the sealing part 400 and an end of the counter electrode 512. For example, in the non-display area NDA, on the substrate 501 Figure 3When the area in the lower part in the y-direction decreases, since the connection part between the common voltage supply line 350 and the counter electrode 512 is arranged closer to the display area DA than the area where the driving voltage supply line 340 is arranged, the space where the common voltage supply line 350 and the counter electrode 512 are electrically connected to each other will not be insufficient.

[0123] In addition, the driving voltage supply line 340 can be arranged away from the display area DA and in a direction farther from the display area DA than the common voltage supply line 350. The driving voltage supply line 340 can be arranged adjacent to the sealing part 400. The driving voltage supply line 340 can be electrically connected to the pixel P. For example, the driving voltage supply line 340 can be electrically connected to the pixel P through a conductive wire such as a driving voltage line PL that passes through the area where the common voltage supply line 350, the switch circuit 380, and the auxiliary common voltage supply line 370 are arranged.

[0124] As Figure 6 shown, in an embodiment of the display device 600, the driving voltage supply line 340 and the sealing part 610 can overlap each other. Specifically, the first planarization layer 507, the second planarization layer 508, and the pixel defining layer 510 can be arranged on the driving voltage supply line 340. At least a part of the sealing part 610 can cover the top surface and the side surface of the pixel defining layer 510 arranged on the driving voltage supply line 340. Therefore, in the non-display area NDA in the lower part in the Figure 3 y-direction of the substrate 501 can be further reduced.

[0125] Figure 7 FIG. is a schematic cross-sectional view showing a display device 700 according to an embodiment.

[0126] Except for the absence of Figure 5 the auxiliary common voltage supply line 370 and the switch circuit 380, Figure 7 the display device 700 and Figure 5 the display device 500 have basically the same structure. Therefore, the differences between the display device 700 and the display device 500 will be mainly described below.

[0127] Referring to Figure 7 , the driving voltage supply line 740 includes a first layer 741 for the driving voltage supply line and a second layer 742 for the driving voltage supply line, and the second layer 742 is electrically connected to the first layer 741. The driving voltage supply line 740 can be arranged adjacent to the sealing part 400.

[0128] The common voltage supply line 750 may be arranged closer to the display area DA than the driving voltage supply line 740. For example, the common voltage supply line 750 may be arranged between the display area DA and the driving voltage supply line 740. The common voltage supply line 750 includes a first layer 751 for the common voltage supply line and a second layer 752 for the common voltage supply line, and the second layer 752 is electrically connected to the first layer 751.

[0129] The common voltage supply line 750 may be electrically connected to the counter electrode 512 through the connection electrode 790. The connection electrode 790 may be arranged on the common voltage supply line 750. The connection electrode 790 and the pixel electrode 509 may be arranged on the same layer. The counter electrode 512 may be in electrical contact with the connection electrode 790 through a fifth opening OP5 formed in the pixel defining layer 510. The connection electrode 790 may be electrically connected to the common voltage supply line 750 through a contact hole defined in the second planarization layer 508.

[0130] In the non-display area NDA, the common voltage supply line 750, the driving voltage supply line 740, and the sealing part 400 may be arranged in this order (i.e., the common voltage supply line 750, the driving voltage supply line 740, and the sealing part 400) in a direction away from the display area DA. Since the area where the common voltage supply line 750 and the counter electrode 512 are electrically connected to each other is arranged closer to the display area DA than the driving voltage supply line 740, the non-display area NDA in the lower part of the substrate 501 may be reduced and the common voltage supply line 750 and the counter electrode 512 may be easily connected.

[0131] The display device according to one or more embodiments may reduce the voltage drop phenomenon and may include a non-display area having a reduced area.

[0132] In addition to the above effects, the effects of the inventive concept may be derived from the description given above with reference to the drawings.

[0133] It should be understood that the embodiments described herein should be understood only in a descriptive sense and not for the purpose of limitation. The description of features or aspects within each embodiment should generally be considered applicable to other similar features or aspects in other embodiments. Although the embodiments have been described with reference to the drawings, those of ordinary skill in the art will understand that various changes in form and detail may be made herein without departing from the spirit and scope defined by the claims.

Claims

1. A display device, the display device comprising: a substrate including a display area for displaying an image and a non-display area adjacent to the display area; a plurality of pixels arranged in the display area, each pixel of the plurality of pixels including: a pixel circuit; and a light-emitting diode, the light-emitting diode including a pixel electrode electrically connected to the pixel circuit, an emission layer, and a counter electrode; a driving voltage supply line arranged in the non-display area, the driving voltage supply line supplying a driving voltage to the plurality of pixels; a common voltage supply line arranged in the non-display area and electrically connected to the counter electrode to supply a common voltage; and a sealing portion surrounding the display area, wherein, in a cross-sectional view of a region adjacent to a terminal portion, the common voltage supply line, the driving voltage supply line, and the sealing portion are arranged in the order of the common voltage supply line, the driving voltage supply line, and the sealing portion in a direction away from the display area, such that in a direction perpendicular to a side of the display area facing the terminal portion, a distance between the side of the display area and the common voltage supply line is less than a distance between the side of the display area and the driving voltage supply line.

2. The display device according to claim 1, wherein The common voltage supply line is electrically connected to the counter electrode through a connection electrode, and the connection electrode and the pixel electrode are arranged on the same layer.

3. The display device according to claim 2, the display device further comprising: an auxiliary common voltage supply line arranged between the common voltage supply line and the display area; and a switching circuit including at least one thin-film transistor arranged between the common voltage supply line and the auxiliary common voltage supply line, the at least one thin-film transistor supplying a data signal to the plurality of pixels.

4. The display device according to claim 3, wherein, The common voltage supply line and the auxiliary common voltage supply line have the same stacked structure and are electrically connected to each other through the connection electrode.

5. The display device according to claim 4, wherein, A region where the common voltage supply line, the auxiliary common voltage supply line, the connection electrode, and the counter electrode are electrically connected to each other is arranged around an upper portion of the switching circuit.

6. The display device according to claim 2, wherein, The connection electrode electrically connected to the counter electrode is arranged on the common voltage supply line.

7. The display device according to claim 2, wherein: a planarization layer including at least one layer covers the common voltage supply line, the connection electrode is arranged on the planarization layer and is electrically connected to the common voltage supply line through a contact hole in the planarization layer, and the counter electrode is electrically connected to the connection electrode through an opening in a pixel defining layer covering at least a part of the pixel electrode.

8. The display device according to claim 7, wherein: the connection electrode includes a plurality of holes, the pixel defining layer covers an edge of the connection electrode where the plurality of holes are arranged, and the opening in the pixel defining layer exposes a portion of the connection electrode electrically connected to the counter electrode.

9. The display device according to claim 1, wherein, The driving voltage supply line is arranged adjacent to the sealing portion.

10. The display device according to claim 1, wherein, At least a part of the sealing portion overlaps with the driving voltage supply line.

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