Quantum circuit layout

Abstract

A quantum circuit arrangement (100) having at least one quantum circuit (110) for performing a computation on a quantum computer, the quantum circuit arrangement (100) comprising at least a lookup structure (50) configured to determine a value of a predefined function based on a variable represented by a set of qubits (12, 14, 16, 18), and a binning structure (60) configured to identify predetermined bins (64, 66) based on the variable, wherein the lookup structure (50) is adapted to determine the value of the predefined function based on the bins (64, 66). Furthermore, a method for compiling the quantum circuit arrangement (100) having at least one quantum circuit (110) for performing a computation on a quantum computer is provided, which can be implemented on a classical computer.

Description

Technical Field

[0001] The present invention relates generally to data processing systems, and in particular to a quantum circuit arrangement having at least one quantum circuit for performing a calculation on a quantum computer, and a method implementable on a classical computer for compiling a quantum circuit arrangement having at least one quantum circuit for performing a calculation on a quantum computer. Background Art

[0002] Quantum computers perform calculations based on quantum mechanics. They can significantly accelerate the performance of specialized problems. Quantum algorithms are known in the art for estimating the characteristics of solutions to a set of linear equations. These algorithms can exponentially speed up classical algorithms for the same task.

[0003] Linear equations, important in many fields of science and engineering, are often defined by very large matrices in real-world problems, requiring the storage and processing of large amounts of data. Discrete partial differential equations are an example of an application of linear equations. Here, classical computing can reach its limitations in terms of time and memory capacity. Therefore, solving linear equations is a task typically reserved for quantum computers, which possess extraordinary computational speeds.

[0004] The so-called HHL algorithm, described by Harrow, Aram W; Hassidim, Avinatan; Lloyd, Seth (2009), 'Quantum algorithm for solving linear systems of equations', Physical Review Letters, 103(15), 150502, is capable of solving linear systems of equations with exponential speedup on a quantum computer. The HHL algorithm consists of several computational steps performed on data stored in a quantum register.

[0005] For a specific step of the HHL algorithm, the so-called controlled rotation, no efficient implementation is known to date, since in the original description of the HHL algorithm the authors assumed that a solution was given for this step.

[0006] Due to the quantum nature of the stored data, classical computing cannot be applied, as the readout of the quantum state by a classical computer would be computationally expensive. Summary of the Invention

[0007] A quantum circuit arrangement having at least one quantum circuit for performing a computation on a quantum computer is provided, the quantum circuit arrangement comprising at least: a lookup structure configured to determine a value of a predefined function based on a variable represented by a set of qubits; and a binning structure configured to identify a predetermined bin based on the variable. The lookup structure is adapted to determine the value of the predefined function based on the bin.

[0008] Advantageously, quantum circuits can be implemented on quantum registers comprising a few qubits to efficiently execute the HHL algorithm for solving linear equations, which solves problems almost exponentially faster than classical algorithms for the same task.

[0009] According to advantageous embodiments of the present invention, an efficient controlled rotation step in the HHL algorithm may be advantageously facilitated for applications where small errors can be tolerated.

[0010] In particular, this embodiment allows controllable parameters to set an application-dependent level of accuracy and reduce the introduced error to arbitrarily small values ​​without the cost of a large number of quantum gates, which translates into algorithmic running time and the number of qubits used.

[0011] Typically, the overall HHL algorithm based on the proposed embodiment can be simulated to achieve a fidelity better than 99.999% and an output probability of 20-30% on average for a certain set of parameters.

[0012] Embodiments of the present invention are based on looking up pre-computed values ​​of a structure for a specific function and binning multiple values ​​in a binned structure.

[0013] Precomputed values ​​can be computed with high precision on a classical computer. Any arbitrary classically computable function can be used, but the proposed search structure can be advantageously used for monotonically decreasing functions. Thus, in the case of the HHL algorithm, the method can be simplified to the functions 1 / x and arcsin(1 / x). Precomputation is performed during compilation of the quantum circuit and does not increase the runtime of the quantum algorithm.

[0014] Binning multiple values ​​allows reducing the number of rotations required within a quantum circuit. The exponential number of rotations in the exact case is reduced to a linear number in the binned case. The binning method introduces a small error that is limited to a maximum value. The number of controlled rotations depends linearly on the overall eigenvalue accuracy, but scales exponentially with the choice of rotation accuracy.

[0015] Possible applications for using the proposed quantum circuit arrangement may advantageously be, for example, solving differential equations, least squares fitting, classical perceptrons, electromagnetic scattering or cubic spline interpolation.

[0016] According to an advantageous embodiment of the quantum circuit arrangement of the invention, the predefined function may have a negative derivative whose absolute value decreases monotonically, which means that a monotonically decreasing function is used. Thus, an advantageous lookup structure with an efficient and unique binning structure may be implemented in an embodiment.

[0017] According to an advantageous embodiment of the quantum circuit arrangement of the invention, the size of the bins can be increased for increasing values ​​of the variables. In this way, the number of necessary rotations can be reduced for higher eigenvalues ​​to be used as input variables of the predefined function.

[0018] According to an advantageous embodiment of the present quantum circuit arrangement, the size of a bin can be based on the position of the first qubit within a variable. The bin size is derived from the number of qubits and can be defined by the number of qubits following the first qubit within the variable. Thus, by using the first qubit as the most significant qubit of an eigenvalue, an efficient binning structure can be implemented using the proposed quantum circuit arrangement.

[0019] According to an advantageous embodiment of the quantum circuit arrangement of the present invention, the size of the bin can be based on the position of the last qubit within the variable. The bin size is derived from the number of qubits, and the bin size can be defined by the number of qubits after the first qubit within the variable. Alternatively, depending on the method of binning, in a similar embodiment, the last qubit can be used, which is the qubit farthest to the right. This can be used to cover different qubit orientations (endianness) here. For different endianness, the first qubit will still be the first qubit, but from the other direction, from the right instead of from the left.

[0020] According to an advantageous embodiment of the inventive quantum circuit arrangement, the lookup structure may comprise at least one quantum gate arrangement for performing a controlled rotation of the further set of qubits. Thus, an efficient implementation of the HHL algorithm may be achieved for calculations on a quantum computer.

[0021] According to an advantageous embodiment, the quantum circuit arrangement of the present invention can be configured to perform the HHL algorithm, further comprising a quantum phase estimation structure configured to perform quantum phase estimation, an inverse quantum phase estimation structure configured to perform inverse quantum phase estimation, and a lookup structure for performing a controlled rotation of another set of qubits. In this way, the complete HHL algorithm can be efficiently implemented on a quantum computer, executing all three main steps of the algorithm. Compared to classical algorithms for the same task, the HHL algorithm solves the problem almost exponentially faster.

[0022] According to an advantageous embodiment of the inventive quantum circuit arrangement, the function may comprise an arcsin(1 / λ) function. The proposed function advantageously meets the requirement of a monotonically decreasing function.

[0023] According to an advantageous embodiment of the quantum circuit arrangement of the present invention, the quantum circuit can be configured to perform, on a variable, iterative access to at least one sub-qubit pattern of a pattern equal to the maximum size of a bin minus one. By introducing the sub-qubit pattern, the efficiency of the binning structure can be advantageously further improved.

[0024] According to an advantageous embodiment, the quantum circuit arrangement of the present invention can also be configured to be compiled on a classical computer. Thus, the values ​​of predefined functions can be pre-calculated to effectively improve the control process of the quantum circuit arrangement. Consequently, a significantly more efficient rotation step can be achieved in the HHL algorithm.

[0025] According to an advantageous embodiment of the quantum circuit arrangement of the present invention, the quantum circuit can be configured with negation of control over the first qubit and control over the second qubit, further comprising entanglement of an auxiliary qubit in its ground state with the control and uncompute of the auxiliary qubit. In this way, the quantum circuit arrangement can be implemented with a reduced number of necessary quantum gates.

[0026] Decomputation is a technique used in reversible quantum circuits to eliminate temporary side effects on auxiliary bits so they can be reused. Decomputation is crucial for quantum computing. Whether or not intermediate effects have been decomputed affects how states interfere with each other when the resulting measurement is made.

[0027] According to an advantageous embodiment of the quantum circuit arrangement of the present invention, the quantum circuit can be configured to use a second auxiliary qubit, entangled with multiple controlled NOT operations depending on a sub-qubit pattern comprising two auxiliary qubits, and to perform a controlled rotation conditional on the auxiliary qubit and the remaining combinations. The number of remaining combinations is equal to 2 (n-z) , where n is the number of qubits defining the corresponding bin and z is the length of the sub-qubit pattern. In this embodiment, the efficiency of the quantum circuit arrangement can be further improved.

[0028] Furthermore, a method for compiling a quantum circuit arrangement having at least one quantum circuit for performing a computation on a quantum computer, which can be implemented on a classical computer, is provided. The method comprises pre-calculating a set of values ​​of a predefined function for selected values ​​of a variable represented by a set of qubits, and generating at least one quantum circuit configured to perform a controlled rotation of each value in the pre-calculated set of values.

[0029] The method of the present invention is based on pre-computed values ​​of a lookup structure for a specific function and binning multiple values ​​in a binned structure.

[0030] The precomputed values ​​can be computed with high precision on a classical computer. Any arbitrary classically computable function can be used, but the presented lookup method can be advantageously used for monotonically decreasing functions. Thus, in the case of the HHL algorithm, the method can be simplified to the functions 1 / x and arcsin(1 / x). The precomputation is performed during the compilation of the quantum circuit and does not increase the runtime of the quantum algorithm.

[0031] According to an advantageous embodiment, the method of the present invention may include predefining a set of bins, each value in the precomputed set corresponding to a bin in the predefined set of bins. Binning multiple values ​​allows reducing the number of required rotations performed within the quantum circuit. The number of rotations, which would have been exponential in the exact case, is reduced to a linear number in the binned case. The binning method introduces a small error that is limited to a maximum value. The number of controlled rotations depends linearly on the overall eigenvalue accuracy, but scales exponentially with the choice of rotation accuracy.

[0032] According to an advantageous embodiment, the method of the present invention may further include executing the HHL algorithm, including a quantum phase estimation structure configured to perform quantum phase estimation and an inverse quantum phase estimation structure configured to perform inverse quantum phase estimation, and further including a lookup structure for performing a controlled rotation of another set of qubits. In this manner, the complete HHL algorithm can be efficiently implemented on a quantum computer, executing all three main steps of the algorithm. Compared to classical algorithms for the same task, the HHL algorithm solves the problem exponentially faster.

[0033] According to an advantageous embodiment of the method according to the invention, the function may comprise an arcsin(1 / λ) function. The proposed function satisfies the requirement of a monotonically decreasing function in an advantageous manner.

[0034] According to an advantageous embodiment of the method of the present invention, the quantum circuit can be configured to perform, on the variable, at least one sub-qubit pattern of a pattern that iteratively accesses the maximum bin size minus one. By introducing the sub-qubit pattern, the efficiency and fault tolerance of the binning architecture can be advantageously further improved.

[0035] According to an advantageous embodiment of the method, the values ​​of the variables can be selected according to a predefined set of bins. Binning multiple values ​​allows reducing the number of required rotations performed within the quantum circuit. The amount of exponential rotation in the exact case is reduced to a linear rotation in the binned case.

[0036] According to an advantageous embodiment of the inventive method, the size of a bin can be based on the position of the first qubit within a variable. Derived from the number of qubits, the bin size can be defined by the number of qubits following the first qubit within the variable. Thus, by using the first qubit as the most significant qubit of an eigenvalue, an efficient binning structure can be implemented using the proposed quantum circuit arrangement.

[0037] According to an advantageous embodiment of the method of the present invention, the size of the bin can be based on the position of the last qubit in the variable. The bin size is derived from the number of qubits, and the bin size can be defined by the number of qubits after the first qubit in the variable. Alternatively, depending on the binning method, in a similar embodiment, the last qubit can be used, which is the qubit farthest to the right. This can be used to cover different qubit orientations (endianness) here. For different endianness, the first qubit will still be the first qubit, but from the other direction, from the right instead of from the left.

[0038] According to an advantageous embodiment, the method of the present invention may further comprise a quantum circuit configured with negation of control over the first qubit and control over the second qubit, entanglement of an auxiliary qubit in its ground state with the control, and decomputation of the auxiliary qubit. In this way, a quantum circuit arrangement may be implemented with a significantly reduced number of necessary quantum gates.

[0039] According to an advantageous embodiment, the method of the present invention may further comprise using a second auxiliary qubit, entangled with multiple controlled NOT operations depending on a sub-qubit pattern comprising two auxiliary qubits, and performing a controlled rotation conditioned on the auxiliary qubit and the remaining combinations. The number of remaining combinations is equal to 2 (n-z) , where n is the number of qubits defining the corresponding bin, and z is the length of the sub-qubit pattern. In this embodiment, the efficiency of the quantum circuit arrangement can be further improved.

[0040] Furthermore, an advantageous computer program product is proposed for compiling a quantum circuit arrangement having at least one quantum circuit for performing a calculation on a quantum computer.

[0041] The computer program product includes a computer-readable storage medium having program instructions embodied therein, the program instructions being executable by a computer system to cause the computer system to perform a method comprising: pre-calculating a set of values ​​of a predefined function for selected values ​​of the variable based on the variable represented by a set of qubits; and generating at least one quantum circuit configured to perform a controlled rotation of each value in the pre-calculated set of values.

[0042] Furthermore, a data processing system for executing a data processing program is proposed, comprising computer-readable program instructions for executing the above method. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] The present invention, together with the foregoing and other objects and advantages, will be best understood from the following detailed description of the embodiments thereof, which are not intended to be limiting.

[0044] Figure 1 Depicted is a quantum circuit arrangement for performing calculations on a quantum computer, configured to perform the HHL quantum algorithm according to an embodiment of the present invention.

[0045] Figure 2 A quantum circuit according to an embodiment of the invention is depicted.

[0046] Figure 3 Depicted is a quantum circuit for controlled rotation of an eigenvalue register according to an embodiment of the present invention.

[0047] Figure 4 Depicted is a quantum circuit for controlled rotation of an eigenvalue register using sub-qubit patterns according to another embodiment of the invention.

[0048] Figure 5 Depicted is a flow chart for executing the HHL algorithm on a quantum circuit arrangement according to an embodiment of the present invention.

[0049] Figure 6 Depicted is a flow chart for preparing a lookup structure on a quantum circuit according to an embodiment of the present invention.

[0050] Figure 7 Depicted is a flow chart for determining a bin position within a bin structure, in accordance with an embodiment of the present invention.

[0051] Figure 8 Depicted is a flow chart for determining a bin position within a binning structure having a sub-qubit pattern, according to another embodiment of the present invention.

[0052] Figure 9 Depicted is a binning example according to an embodiment of the present invention.

[0053] Figure 10 Another binning example according to another embodiment of the present invention is depicted.

[0054] Figure 11 An exemplary embodiment of a data processing system for performing the method according to the invention is depicted. DETAILED DESCRIPTION

[0055] In the accompanying drawings, the same elements are represented by the same reference numerals. The accompanying drawings are merely schematic representations and are not intended to depict specific parameters of the present invention. In addition, the accompanying drawings are intended only to illustrate typical embodiments of the present invention and are therefore not to be considered as limiting the scope of the present invention.

[0056] The illustrative embodiments described herein provide a quantum circuit arrangement having at least one quantum circuit for performing computations on a quantum computer.

[0057] The illustrative embodiments may be used in a quantum circuit arrangement comprising at least a lookup structure configured to determine a value of a predefined function based on a variable represented by a set of qubits; and a binning structure configured to identify a predetermined bin based on the variable, wherein the lookup structure is adapted to determine the value of the predefined function based on the bin.

[0058] Illustrative embodiments are sometimes described herein using specific techniques only as examples for clarity of description.

[0059] According to the proposed quantum circuit arrangement for executing the HHL algorithm, the eigenvalue λ can be taken and a controlled rotation of arcsin(C / λ) is applied to the auxiliary qubit. Assuming that arcsin can be calculated with arbitrary precision and that the rotation about the y-axis does not add additional error to the reciprocal, the eigenvalue λ can be given with k qubits of precision. C is the value that must satisfy C≤λ. min A constant, where λ min is the smallest eigenvalue, and C can be set to 2 -k .

[0060] msq can be defined as the bit-position of the most significant qubit (MSQ), which is the leftmost in the qubit representation used, i.e., corresponds to the largest exponent of 2 in the binary representation of λ set to 1. In this approach, for a given λ, for example, λ = '11100' = 2 in binary form -1 +2 -2 +2 -3 = 0.825. In this example, msq is 1 (i.e., the highest qubit is set at 2 -1 The total length k is 5. The n qubits after MSQ define a bin, which stores 2 k-(msq+n) Different binary patterns. For 2 qubits consisting of msq and then n qubits n For each of the binary patterns, the pre-computed inverse λ min / λ is assigned to all binary patterns that fall into the corresponding bin. Therefore, within a bin, if the bin midpoint is taken as the estimate, the error for λ is ε λ ≤2 -(msq+n) / 2 (equal only in the limit of non-truncated qubit representations, i.e., infinite precision). In the following, the limit in which the previous expressions are equal is used as an upper bound on the error caused by binning.

[0061] Under the initial assumptions, the error added by the rotation is given by:

[0062]

[0063] in, is defined as the bin midpoint, since arcsin values ​​can be computed and decomputed via rotations to arbitrary precision. Due to symmetry around 0, only the region λ ≥ 0 is observed. Since the derivative of 1 / x is negative and its absolute value decreases monotonically within the defined range, the maximum error for each bin is introduced at the left boundary of each bin (hence, is used). The expression for the error reformulated and inserted into λ is:

[0064]

[0065] MSQ can be obtained from the following relationship:

[0066]

[0067] Plugging this expression in, we get:

[0068] ε rot ≤2 -(n+1)

[0069]

[0070] This means that the number of qubits that need to be considered to achieve a certain accuracy is independent of the register length k. Due to binning, the number of controlled rotations is linear in the register size k and is now (k-n+1). 2n , instead of 2 k .

[0071] The process of quantum circuit design can be summarized as examining a qubit pattern of length n and performing a controlled rotation corresponding to an angle θ = arcsin(C / λ), where C is a qubit that must satisfy C ≤ λ. min The constant, λ min is the minimum eigenvalue, and C can be set to 2 -k .

[0072] It iterates over all MSQs (k-n+1 in total), and for each iteration, the control shift of the readout n-qubit pattern is shifted by one qubit. To prevent "erroneous" rotations due to potentially ignored qubits (because these qubits are more than n qubits behind the MSQ), the current MSQ is kept track of, and this is included as an additional control. This means that for each MSQ, a controlled NOT operation is performed on a msq-redundant qubit (garbage qubit) that has a control node that negates all qubits above the current MSQ and a control node for the current MSQ. After each MSQ, a register is decalculated. This register is hereinafter referred to as |msq>, where |msq> represents the corresponding qubit.

[0073] For example, in a circuit where |msq> is set to m=2, before decomputation, 2 can be performed under the condition of |msq>. n times rotation.

[0074] For another example, the numbers '101011' and '11010' should be considered as eigenvalues ​​λ. If k = 6 and n = 5, then in both cases, the substring '101' will be checked for being in the middle of the qubit pattern. Instead, it is possible to iterate over all possible substrings of the n-qubit pattern, where the substring is z qubits long. In this example, '101' is checked in qubits 3 to 5. This result can be expressed using Λ z (σ x ) function is stored in the redundant bits, Λ z (σ x ) function is defined as a z-qubit controlled Toffoli gate according to the embodiment shown in the paper ABarenco et al. (1995), 'Elementary gates for quantum computing', Physical Review A, 52, 3457. The symbol represents σ x The z-qubit is controlled to execute. Then, all the remaining 2 n-z Iterate it over the combinations and use Λ to take into account the results in the redundant qubits n-z (σ z ) gate to rotate the auxiliary qubit. Then, use Λ z (σ x ) de-computing the redundant qubit and starting over with the next z-qubit pattern. Doing so effectively reuses the information that the two numbers share the same sub-qubit pattern and reduces the gate count. n Λ z (σ x ) gates are replaced with 2z (2Λ z (σ x )+2 n-z Λ n-z+1 (σ x )) gates. Since rotations have corresponding operators in SU(2), we can use the following method to perform controlled rotations.

[0075] To implement this, no additional qubits are used to perform the multiplicity of controlled operations. It is iterated k-n+1 times to access 2 n combinations, and controlled rotations are performed. Using z substrings, this can be done using (k-n+1)2 z (2Λ z (σ x )+2 n-z 2[Λ n-z (σ x )+Λ2(R y )] to execute.

[0076] Λ i (U) Door requires (2 n-1 -1)Λ1(V or ) and (2 n-1 -2)Λ1(σ x ) gates. See reference ABarencoet al.(1995),'Elementary gates for quantum computing',Physical Review A,52,3457,V or is defined as All Λ1 of the SU(2) operator can be implemented with 4 to 5 gates, where for the Ry rotation only 4 basic gates are used.

[0077] Added gates to set MSQ registers. The idea is to have multiple controlled NOT gates that check whether the next higher qubit is 0 for each iteration of the MSQ. Here, for large k, different methods can be used to test whether all qubits are 0. Using a favorable implementation, at most kn different bins are checked, which can result in a gate count that is exponential in k.

[0078] However, using a small number of additional qubits (which, for some embodiments, do not even have to be zero) can make the gate technology linear or quadratic in k.

[0079] Now, the gate count is exponential in n, however, since the accuracy of the rotation angle is independent of k, the size of n does not have to scale with large register sizes.

[0080] For negative eigenvalues, you can think of converting the negative eigenvalue to its absolute value and performing another y-axis rotation of π based on the set sign bit. To get the absolute value, you can invert each bit and then increment the number (2's complement). This can be done conditionally on the sign bit.

[0081] Advantageously, z qubit patterns can be combined via several MSQs. Z If we change the position of the qubit string z within the register, we can reuse Λ more often. Z Door.

[0082] In the following Figures 1 to 10 Implementations of the described quantum circuits and processes are described in .

[0083] Figure 1 A quantum circuit arrangement 100 for performing computations on a quantum computer is depicted, configured to perform the HHL quantum algorithm according to an embodiment of the present invention. The quantum circuit arrangement 100, having at least one quantum circuit 110, comprises: a lookup structure 50 configured to determine the value of a predefined function based on a variable represented by a set of qubits 12, 14, 16, 18; and a binning structure 60 configured to identify predetermined bins 64, 66 (see FIG. 1 ) based on the variable. Figure 9 The lookup structure 50 is adapted to be based on the bins 64, 66 (see Figure 9 ) determines the value of a predefined function.

[0084] The quantum circuit arrangement 100 further comprises a quantum phase estimation structure 40 configured to perform quantum phase estimation and an inverse quantum phase estimation structure 42 configured to perform inverse quantum phase estimation. A lookup structure 50 is configured to perform a controlled rotation of the further set of qubits 12, 14, 16, 18, the lookup structure 50 comprising at least one quantum gate arrangement 30 for performing a controlled rotation of the further set of qubits 12, 14, 16, 18.

[0085] exist Figure 1 In FIG, the input of the quantum phase estimation structure 40 is depicted as an eigenvalue register 10, including qubits 12, 14, 16, 18 and quantum register 24. Eigenvalue register 10 is in the ground state and quantum state register 24 is in the state '|b>'. The controlled rotation is performed by the quantum gate arrangement 30 with the aid of the auxiliary qubit 22, which is also in the ground state. The output state of the auxiliary qubit 22 is measured by the measurement operation 44, in Figure 1 The output state of auxiliary qubit 22 is '|1>', which means that the controlled rotation has a successful result. Eigenvalue register 10 is in the ground state again after the reverse quantum phase estimation 42. Quantum register 24 is in the state '|x>'.

[0086] The quantum circuit arrangement 100 is configured to be compiled on a classical computer.

[0087] The quantum circuit arrangement 100 can be compiled on a classical computer to calculate a set of values ​​of a pre-computed predefined function for selected values ​​of the variable based on the variable represented by a set of qubits 12, 14, 16, 18. At least one quantum circuit 110 can be generated, configured to perform a controlled rotation of each value in the pre-computed set of values.

[0088] Figure 2 A quantum circuit 110 according to an embodiment of the present invention is depicted. Qubits 12, 14, and 16 of eigenvalue register 10 are used as inputs to a controlled rotation process along with an auxiliary qubit 22. To reduce the number of gates, the number of gate controls is reduced. Thus, quantum circuit 110 is configured to have a negated control (marked by an open circle) on first qubit 12 and a control (marked by a solid circle) on second qubit 14. Furthermore, auxiliary qubit 22, which is in the ground state '0', is entangled with the control. Subsequently, auxiliary qubit 22 is decomputable and can be reused.

[0089] Figure 3 A quantum circuit 110 for controlled rotation of an eigenvalue register 10 is depicted in accordance with an embodiment of the present invention. The input to the rotation process is an eigenvalue register 10 having qubits 12, 14, 16, 18, a first qubit 20 (|msq>) as the position of the most significant qubit, and an auxiliary qubit 22 (target). Based on the position of the first qubit 20 within the variable, the first qubit 20 is determined in block 46 and is used to determine the size of bins 64, 66 (see Figure 9 ).

[0090] Alternatively, the size of bins 64, 66 can be based on the position of the last qubit within a variable. The bin size 64, 66 is derived from the number of qubits, which can be defined by the number of qubits after the first qubit within the variable. This can be used to cover different qubit orientations (endianness) here. For different endiannesses, the first qubit will still be the first qubit, but from the other direction, from the right instead of the left.

[0091] exist Figure 3In FIG, an example of a rotation process of an eigenvalue λ is shown, which is equal to '0100', corresponding to the binary fraction of 0.25, and is stored in qubits 12, 14, 16, 18 of eigenvalue register 10. The controlled rotation is performed for an angle θ, which can be determined from a lookup structure 50 as θ=arcsin(1 / λ). The rotation is performed by quantum gate arrangement 30 in two steps 32 and 34 by angles θ / 2 and -θ / 2, respectively. Before decomputing the first qubit 20 in block 48, a further rotation of the eigenvalue '01**' is performed, where '**' represents a combination of '0' and '1'.

[0092] Thus, the method includes quantum circuit 110 configured with negated control on first qubit 12 and control on second qubit 14, entangled an auxiliary qubit 22 in its ground state with the control, and causing auxiliary qubit 22 to compute.

[0093] Figure 4 A quantum circuit 110 for controlled rotation of an eigenvalue register 10 using a sub-qubit pattern according to another embodiment of the present invention is depicted. This embodiment can be further improved. Quantum circuit 110 can be configured to use a second auxiliary qubit 26, entangled with a multiple controlled NOT gate that relies on a sub-qubit pattern including two auxiliary qubits 22 and 26, and perform a controlled rotation conditional on the auxiliary qubits 22, 26 and the remaining combination.

[0094] Here, quantum circuit 110 is configured to perform iterations on a variable that access at least one sub-qubit pattern in a pattern of the maximum size minus one of bins 64, 66. The inputs to quantum gate arrangement 30 for controlled rotation are eigenvalue register 10 with qubits, auxiliary qubit 22 (auxiliary qubit), first qubit 20 (msq), and qubit 26 of the sub-qubit pattern (z-bipat), qubit 26 being a second auxiliary qubit. Figure 3 In the illustrated embodiment, a controlled rotation is performed at an angle θ determined from the look-up structure 50 .

[0095] for Figure 4 In the embodiment shown in , the circuit creation routine includes, for each first qubit 20: first qubit 20 is entangled. Then, for each sub-qubit pattern, a first loop includes: sub-qubit pattern qubit 26 is entangled, followed by the steps of: for each (nz) pattern, where n is the bin size and z is the sub-qubit pattern size, a second loop includes: performing a conditional rotation on sub-qubit pattern qubit 26, first qubit 20, and the nz qubits in eigenvalue register 10. Sub-qubit pattern qubit 26 is then decomputed and the first loop ends. Finally, first qubit 20 is decomputed.

[0096] Figure 5 Described is a method for implementing a quantum circuit arrangement ( Figure 1 The execution of the HHL algorithm begins with the transmission of input parameters to the quantum circuit arrangement in step S100, followed by the Hamiltonian function simulation in step S102. Figure 1 In step S104, quantum phase estimation is performed by the quantum phase estimation structure. The lookup structure can then be used to deliver the appropriate rotation angle in order to perform a controlled rotation in step S106. After the controlled rotation is completed, in step S108, an inverse quantum phase estimation is performed by the inverse quantum phase estimation structure. Then, in step S110, the measurement unit can measure the auxiliary qubit. In step S112, it is checked whether the result is successful, meaning that the auxiliary qubit delivers a '1'. If so, the output of the HHL algorithm is delivered in step S114. If not, the loop returns to step S102 for performing a new Hamiltonian function simulation.

[0097] exist Figure 6 , a flowchart for preparing a lookup structure on a quantum circuit according to an embodiment of the present invention is depicted. This process can be performed on a classical computer to precompute a set of values ​​for a predefined function (e.g., the arcsin(1 / λ) function). The preparation process begins by selecting the precision for eigenvalue determination in step S200, where this precision is determined by the number of qubits |k> in the eigenvalue register. Next, in step S202, the bin positions are calculated using the established binning structure. Then, in step S204, a rotation angle is determined using a predefined function. In step S206, a controlled rotation of the eigenvalue is performed using this rotation angle, after which the quantum circuit is compiled on a classical computer in step S208. The results of the preparation process are output in step S210.

[0098] Figure 7 A flow chart for determining a bin position within a binning structure according to an embodiment of the present invention is depicted. The input to this process is the size k of the eigenvalue register and the length n of the qubit pattern given in step S300. Then, within sub-process S301, at step S302, an outer loop is performed on the position of the first qubit FO, which is the most significant qubit within the first kn qubits of the eigenvalue register. At step S304, an inner loop is performed on all qubit patterns, repeated 2 n In step S306, the exact point or bin midpoint is calculated for the rotation angle within the loop, and then in step S308, the point or midpoint and the qubit pattern are stored. In sub-process S301, the binning process is performed in a loop ranging from 1 to kn.

[0099] Next, if the loop for the first qubit is completed in sub-process S309, the loop is performed again for all qubit patterns in step S310, and repeated 2 times. n Within the loop, in step S312, the precise point is calculated for the rotation angle, and then in step S314, the point and the qubit pattern are stored. In sub-process S309, the first qubit is not determined and the binning process is not performed.

[0100] Then, an output is given in step S316.

[0101] Figure 8 A flow chart for determining a bin position within a binning structure having a sub-qubit pattern according to another embodiment of the present invention is depicted. The inputs to this process are the size k of the eigenvalue register given in step S400, the length n of the qubit pattern, and the length m of the sub-qubit pattern. Thus, the length of the main qubit pattern is given by nm.

[0102] In sub-process S401, at step S402, an outer loop is performed on the position of the first qubit which is the most significant qubit among the first k-n+1 qubits of the eigenvalue register. At step S404, an inner loop is performed on all sub-qubit patterns, and repeated 2 m Step S406, execute the next inner loop on all master qubit patterns, repeat 2 n-m times. In step S408, the qubit patterns are concatenated within the loop. Next, in step S410, an exact point or bin midpoint is calculated for the rotation angle, after which, in step S412, this point or midpoint is stored along with the main qubit pattern and the sub-qubit pattern. In subprocess S401, the binning process is performed in loops ranging from 1 to kn.

[0103] Next, if the outer loop on the first qubit is completed in sub-process S413, then in step S414, the inner loop is executed on all sub-qubit patterns, and repeated 2 m Step S416, the next inner loop is executed on all master qubit patterns, and repeated 2 n-m times. In step S418, the qubit patterns are concatenated within the loop. Next, in step S420, a precise point is calculated for the rotation angle, after which, in step S422, this point is stored along with the main qubit pattern and the sub-qubit pattern. In sub-process S413, the first qubit is not determined, and the binning process is not performed.

[0104] Then, an output is given in step S424.

[0105] Figure 9An example of binning according to an embodiment of the present invention is depicted. The 1 / λ-value 52 is shown as a function of the eigenvalue λ 54. The size of the eigenvalue register is k=4, so the eigenvalue λ 54 ranges from '0000' to '1111', or as a binary fraction 56 from 0.0000 to 0.9375. Therefore, for each eigenvalue λ 54, a corresponding 1 / λ-value 52 can be selected from the curve to determine the angle θ of the controlled rotation by calculating arcsin(1 / λ).

[0106] according to Figure 7 , for a qubit pattern with a first qubit of 1 and a length of 1 (i.e., n=1), the qubit pattern '1' can be found four times in a value qubit such as '11**', which means that the derived bin size 68 is 4. This is depicted in field 66 Bin Size 4. The bin size is indicated by a bar symbol 68.

[0107] For the case where the first qubit is 2, the qubit pattern '1' can be found twice in the value qubit, for example '011*', which means that the derived bin size 68 is 2. This is described in field 64 Bin Size 2. The bin size is indicated by the bar symbol 68.

[0108] Thus, the size of the bins 64, 66 increases with increasing values ​​of the eigenvalue λ 54. The method comprises predefining a set of bins 64, 66, each value in the set of precomputed values ​​corresponding to a bin 64, 66 in the set of predefined bins 64, 66. The value of the variable is selected based on the predefined set of bins 64, 66.

[0109] For the remaining eigenvalues ​​λ54, we can get Figure 9 The curve in selects an exact rotation value of 62, so for the example of an eigenvalue register size k=4 and a pattern length n=1, a total of 8 controlled rotations can be performed.

[0110] from Figure 9 The process of selecting the angle θ for controlled rotation by the binning structure 60 is shown in FIG. Figure 1 ) is executed in

[0111] Figure 10 Another binning example according to another embodiment of the present invention is depicted for comparison. In this case, an example of a size k=4 of the feature value register and a pattern length n=2 is selected.

[0112] according to Figure 7In the flowchart in FIG, for the case where the first qubit is 1 and the length of the qubit pattern is 2 (i.e., n=2), the qubit pattern '11' can be found twice in the value qubit '111*', which means that the bin size 68 can be selected to be 2. This is described in field 64 Bin size 2. The bin size is represented by the bar symbol 68, and the same applies to the qubit pattern '10', which can be found twice in '110*'.

[0113] For the remaining eigenvalues ​​λ54, we can get Figure 10 The curve in is chosen to have exact values, so for the example with an eigenvalue register size of k=4 and a pattern length of n=2, a total of 12 controlled rotations can be performed.

[0114] Now refer to Figure 11 , a schematic diagram of an example of a data processing system 210 is shown. Data processing system 210 is merely an example of a suitable data processing system and is not intended to suggest any limitation on the scope of use or functionality of the embodiments of the present invention described herein. Regardless, data processing system 210 is capable of implementing and / or performing any of the functions described herein.

[0115] In data processing system 210, there is a computer system / server 212, which is operable with numerous other general-purpose or special-purpose computing system environments or configurations. Examples of well-known computing systems, environments, and / or configurations suitable for use with computer system / server 212 include, but are not limited to, personal computer systems, server computer systems, thin clients, fat clients, handheld or laptop devices, multiprocessor systems, microprocessor-based systems, set-top boxes, programmable consumer electronics, network PCs, minicomputer systems, mainframe computer systems, and distributed cloud computing environments including any of the above systems or devices, etc.

[0116] Computer system / server 212 can be described in the general context of computer system-executable instructions, such as program modules, executed by the computer system. Generally, program modules can include routines, programs, objects, components, logic, data structures, etc. that perform specific tasks or implement specific abstract data types. Computer system / server 212 can be practiced in a distributed cloud computing environment, where tasks are performed by remote processing devices linked through a communication network. In a distributed cloud computing environment, program modules can be located in both local and remote computer system storage media, including memory storage devices.

[0117] like Figure 11As shown, computer system / server 212 in data processing system 210 is shown in the form of a general-purpose computing device. Components of computer system / server 212 may include, but are not limited to, one or more processors or processing units 216, system memory 228, and bus 218 that couples various system components including system memory 228 to processor 216.

[0118] Bus 218 represents one or more of any of several types of bus structures, including a memory bus or memory controller, a peripheral bus, an accelerated graphics port, and a processor or local bus using any of a variety of bus architectures. By way of example and not limitation, these architectures include an Industry Standard Architecture (ISA) bus, a Micro Channel Architecture (MCA) bus, an Enhanced ISA (EISA) bus, a Video Electronics Standards Association (VESA) local bus, and a Peripheral Component Interconnect (PCI) bus.

[0119] Computer system / server 212 typically includes a variety of computer system readable media. Such media can be any available media that can be accessed by computer system / server 212, and it includes both volatile and nonvolatile media, removable and non-removable media.

[0120] System memory 228 may include computer system readable media in the form of volatile memory, transferred into random access memory (RAM) 230 and / or cache memory 232. Computer system / server 212 may also include other removable / non-removable, volatile / non-volatile computer system storage media. By way of example only, storage system 234 may be provided for reading from and writing to a non-removable, non-volatile magnetic medium (not shown and commonly referred to as a "hard drive"). Although not shown, a magnetic disk drive for reading from and writing to a removable, non-volatile magnetic disk (e.g., a "floppy disk") may be provided, as well as an optical disk drive for reading from or writing to a removable, non-volatile optical disk such as a CD-ROM, DVD-ROM, or other optical media. In such a case, each may be connected to bus 218 via one or more data media interfaces. As will be further depicted and described below, memory 228 may include at least one program product having a set (e.g., at least one) program module configured to perform the functions of an embodiment of the present invention.

[0121] A program / utility 240 having a set (at least one) of program modules 242, as well as an operating system, one or more application programs, other program modules, and program data, may be stored in memory 228, by way of example and not limitation. Each of the operating system, one or more application programs, other program modules, and program data, or some combination thereof, may include an implementation of a networking environment. The program modules 242 generally perform the functions and / or methods of embodiments of the present invention as described herein.

[0122] Computer system / server 212 may also communicate with one or more external devices 214, such as a keyboard, pointing device, display 224, or the like; one or more devices that enable a user to interact with computer system / server 212; and / or any device that enables computer system / server 212 to communicate with one or more other computing devices (e.g., a network card, modem, etc.). Such communication may occur via input / output (I / O) interface 222. Furthermore, computer system / server 212 may communicate with one or more networks, such as a local area network (LAN), a general-purpose wide area network (WAN), and / or a public network (e.g., the Internet), via network adapter 220. As depicted, network adapter 220 communicates with other components of computer system / server 212 via bus 218. It should be understood that, although not shown, other hardware and / or software components may be used in conjunction with computer system / server 212. Examples include, but are not limited to, microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data archival storage systems.

[0123] The present invention may be a system, method, and / or computer program product. The computer program product may include a computer-readable storage medium (or multiple media) having computer-readable program instructions thereon, the computer-readable program instructions being used to cause a processor to perform various aspects of the present invention.

[0124] Computer readable storage medium can be a tangible device that can retain and store the instructions used by the instruction execution device. Computer readable storage medium can be, for example, but not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. A non-exhaustive list of more specific examples of computer readable storage medium includes the following: a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a static random access memory (SRAM), a portable compact disc read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanical encoding device such as a punch card or a raised structure in a groove on which instructions are recorded, and any suitable combination of the foregoing. As used herein, computer readable storage medium should not be interpreted as a temporary signal itself, such as a radio wave or other freely propagating electromagnetic wave, an electromagnetic wave propagated by a waveguide or other transmission medium (for example, a light pulse by an optical fiber cable), or an electrical signal transmitted by a wire.

[0125] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to a corresponding computing / processing device, or downloaded to an external computer or external storage device via a network, such as the Internet, a local area network, a wide area network, and / or a wireless network. The network can include copper transmission cables, optical transmission fibers, wireless transmission, routers, firewalls, switches, gateway computers, and / or edge servers. The network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards the computer-readable program instructions to be stored in a computer-readable storage medium within the corresponding computing / processing device.

[0126] The computer-readable program instructions for performing the operation of the present invention can be assembly instructions, instruction set architecture (ISA) instructions, machine-related instructions, microcode, firmware instructions, state setting data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​(such as Smalltalk, C++, etc.) and conventional procedural programming languages ​​(such as, " C " programming language or similar programming languages). The computer-readable program instructions can be executed completely on the user's computer, partially on the user's computer, executed as an independent software package, partially on the user's computer and partially on a remote computer, or completely on a remote computer or server. In the latter case, the remote computer can be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or can be connected to an external computer (for example, using an internet service provider to connect to the internet). In certain embodiments, in order to perform various aspects of the present invention, the electronic circuit system including, for example, a programmable logic circuit system, a field programmable gate array (FPGA) or a programmable logic array (PLA) can perform the computer-readable program instructions to personalize the electronic circuit system by utilizing the state information of the computer-readable program instructions.

[0127] Various aspects of the present invention are described herein with reference to flowcharts and / or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the present invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowcharts and / or block diagrams, can be implemented by computer-readable program instructions.

[0128] These computer-readable program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device to produce a machine, such that the instructions executed by the processor of the computer or other programmable data processing device create a device for implementing the functions / actions specified in one or more blocks of the flowchart and / or block diagram. These computer-readable program instructions can also be stored in a computer-readable storage medium, which can direct the computer, programmable data processing device, and / or other equipment to operate in a specific manner, such that the computer-readable storage medium having the instructions stored therein includes an article of manufacture, which includes instructions for implementing various aspects of the functions / actions specified in one or more blocks of the flowchart and / or block diagram.

[0129] The computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable apparatus, or other device to produce a computer-implemented process, so that the instructions executed on the computer, other programmable apparatus, or other device implement the functions / actions specified in one or more boxes of the flowchart and / or block diagram.

[0130] The flow charts and block diagrams in the accompanying drawings illustrate the possible implementation architecture, functionality and operation of the system, method and computer program product according to various embodiments of the present invention. In this regard, each frame in the flow chart or block diagram can represent a module, segment or part of an instruction, which includes one or more executable instructions for implementing the specified logical function. In some alternative embodiments, the function mentioned in the frame may not occur in the order mentioned in the figure. For example, the two frames shown in succession can actually be performed substantially simultaneously, or these frames can sometimes be performed in reverse order, depending on the function involved. It will also be noted that the combination of the frames in each frame of the block diagram and / or the flow chart and the block diagram and / or the flow chart can be implemented by a dedicated hardware-based system that performs a specified function or action or performs a combination of special-purpose hardware and computer instructions.

[0131] The description of various embodiments of the present invention has been provided for the purpose of illustration, but is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, practical applications, or improvements over existing technologies in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.

[0132] Reference Symbols

[0133] 10 Quantum Circuits

[0134] 12 qubits

[0135] 14 qubits

[0136] 16 qubits

[0137] 18 qubits

[0138] 20 msq

[0139] 22 auxiliary qubits

[0140] 24 quantum registers

[0141] 26 second auxiliary qubit

[0142] 30 Quantum gate arrangement for controlled rotation

[0143] 32+ rotations

[0144] 34 - Rotation

[0145] 40 Quantum Phase Estimation Structure

[0146] 42 Inverse quantum phase estimation structure

[0147] 44 Measurement Operations

[0148] 46 Calculate the first

[0149] 48 Calculate the first

[0150] 50 Search Structure

[0151] 52 1 / λ value

[0152] 54 eigenvalues

[0153] 56 Binary fraction of eigenvalue

[0154] 60 Bin structure

[0155] 62 Precise Rotation

[0156] 64 Bin size 2

[0157] 66 Bin size 4

[0158] 68 Warehouse Size

[0159] 100 Quantum Circuit Layout

[0160] 110 Quantum Circuits

[0161] 210 Data Processing System

[0162] 212 Computing Systems / Servers

[0163] 214 External Devices

[0164] 216 CPU / data processing unit

[0165] 218 I / O bus

[0166] 220 Network Adapter

[0167] 222 I / O interface

[0168] 224 Display

[0169] 228 Memory

[0170] 230 RAM

[0171] 232 Cache

[0172] 234 Storage System

[0173] 240 Programs / Utilities

[0174] 240 program modules

[0175] θ rotation angle

[0176] S100 transmits input parameters to the quantum circuit

[0177] S102 Hamiltonian Simulation

[0178] S104 Quantum Phase Estimation

[0179] S106 Find Rotation Angle

[0180] S108 Inverse Quantum Phase Estimation

[0181] S110 Measurement Assistant Qubit

[0182] S112 Check whether the result is successful

[0183] S114 Delivering output results

[0184] S200 Select the precision for characteristic value determination

[0185] S202 Calculation of warehouse position

[0186] S204 Calculate rotation angle

[0187] S206 Generate Controlled Rotation

[0188] S208 Compiling quantum circuits on classical computers

[0189] S210 Output of the results of the preparation process

[0190] The input size k of the S300 eigenvalue register and the length n of the qubit pattern

[0191] S301 Sub-process binning program

[0192] S302 performs an outer loop for the position of the first qubit

[0193] S304 performs an inner loop over all qubit patterns, repeating 2 n Second-rate

[0194] S306 Calculates the exact point or bin center point for the rotation angle

[0195] S308 Storage Points or Points in Bins, and Qubit Patterns

[0196] S309 sub-process

[0197] S310 performs an inner loop over all qubit patterns, repeating 2 n Second-rate

[0198] S312 Calculates exact points for rotation angles

[0199] S314 Storage Points and Qubit Patterns

[0200] Output of S316 results

[0201] S400 Input size k of the eigenvalue register, length n of the qubit pattern, and length m of the sub-qubit pattern

[0202] S401 Sub-process binning program

[0203] S402 performs an outer loop for the position of the first qubit

[0204] S404 performs an inner loop over all qubit patterns, repeating 2 n Second-rate

[0205] S406 performs the next inner loop on all master qubit patterns, repeating 2 n-m Second-rate

[0206] S408 juxtaposed qubit mode

[0207] S410 calculates exact point or bin center point for rotation angle

[0208] S412 Storage point or mid-point, main qubit pattern and sub-qubit pattern

[0209] S413 sub-process

[0210] S414 performs an inner loop over all sub-qubit patterns, repeating 2 m Second-rate

[0211] S416 performs the next inner loop on all master qubit patterns, repeating 2 n-m Second-rate

[0212] S418 juxtaposed qubit mode

[0213] S420 calculates precise points for rotation angles

[0214] S422 Storage Points, Master Qubit Patterns, and Sub-Qubit Patterns

[0215] Output of S424 results

Claims

1. A quantum circuit arrangement (100) having at least one quantum circuit (110) for performing a calculation on a quantum computer, the quantum computer being configured to perform the HHL algorithm, the quantum circuit arrangement (100) comprising: a lookup structure (50) configured to determine a value of a predefined function of a first level of precision based on a variable represented by a set of qubits (12, 14, 16, 18), and the lookup structure further comprising at least one quantum gate arrangement for performing a controlled rotation of another set of qubits; a binning structure (60) configured to identify predetermined bins (64, 66) based on the variables, wherein the lookup structure (50) is configured to determine a value of a predefined function of the first level of accuracy based on the bins (64, 66), and the number of controlled rotations required to achieve the first level of accuracy is based on the bins; a quantum phase estimation structure (40) configured to perform quantum phase estimation; The inverse quantum phase estimation structure (42) is configured to perform inverse quantum phase estimation. 2 . The quantum circuit arrangement according to claim 1 , wherein the predefined function has a negative derivative whose absolute value decreases monotonically.

3. A quantum circuit arrangement according to claim 1 or 2, wherein The size of the bins (64, 66) increases for increasing values ​​of the variable.

4. A quantum circuit arrangement according to claim 1 or 2, wherein The size of the bin (64, 66) is based on the position of the first qubit (20) within the variable, wherein the size of the bin (64, 66) is defined by the number of ones after the first qubit (20) within the variable.

5. The quantum circuit arrangement according to claim 1 or 2, wherein: The size of the bin (64, 66) is based on the position of the last qubit within the variable, wherein the size of the bin (64, 66) is defined by the number of ones preceding the first qubit (20) within the variable.

6. The quantum circuit arrangement according to claim 1 or 2, wherein: The function includes an arcsin(1 / λ) function.

7. The quantum circuit arrangement of claim 1 or 2, the quantum circuit (110) being configured to perform on the variable at least one sub-qubit pattern of a pattern that iteratively accesses a maximum size of the bins (64, 66) minus one.

8. The quantum circuit arrangement according to claim 1 or 2, further configured to be compiled on a classical computer.

9. The quantum circuit arrangement of claim 1 or 2, the quantum circuit (110) being configured with negation of control of the first qubit (12) and control of the second qubit (14), further comprising: entangle the auxiliary qubit (22) in its ground state with the control, and Decomputation is performed on the auxiliary qubit (22).

10. The quantum circuit arrangement according to claim 9, the quantum circuit (10) being configured to: Using a second auxiliary qubit (26), Entanglement with multiple controlled NOT operations relying on sub-qubit patterns involving two auxiliary qubits (22, 26), A controlled rotation is performed conditioned on the auxiliary qubits (22, 26) and the remaining combination of sub-qubit patterns of the variable.

11. A method implementable on a classical computer for compiling a quantum circuit arrangement (100) having at least one quantum circuit (110) for performing a calculation on a quantum computer, the quantum computer being configured to perform the HHL algorithm, the method comprising: determining, by a lookup structure, a value of a predefined function at a first level of precision based on a variable represented by a set of qubits, and the lookup structure also performing a controlled rotation of another set of qubits; identifying, by the binning structure, a predetermined bin based on the variable; wherein the value of the predefined function of the first level of precision is determined based on the bins (64, 66), and the number of controlled rotations of the further set of qubits required to achieve the first level of precision is based on the bins; performing quantum phase estimation by a quantum phase estimation structure (40); and The inverse quantum phase estimation is performed by an inverse quantum phase estimation structure (42).

12. The method of claim 11, wherein: The predefined function has a negative derivative whose absolute value decreases monotonically.

13. The method according to claim 11 or 12, wherein: The function includes an arcsin(1 / λ) function.

14. The method according to claim 11 or 12, wherein: The quantum circuit (110) is configured to perform on the variable at least one sub-qubit pattern of a pattern that iteratively accesses a maximum size of the bins (64, 66) minus one.

15. The method according to claim 11 or 12, wherein: The value of the variable is selected according to the bin (64, 66).

16. The method according to claim 11 or 12, wherein: The size of the bin (64, 66) is based on the position of the first qubit (20) within the variable, wherein the size of the bin (64, 66) is defined by the number of ones after the first qubit (20) within the variable.

17. The method according to claim 11 or 12, wherein: The size of the bin (64, 66) is based on the position of the last qubit within the variable, wherein the size of the bin (64, 66) is defined by the number of ones preceding the first qubit (20) within the variable.

18. The method according to claim 11 or 12, further comprising: The quantum circuit (110) is configured with negation control of the first qubit (12) and control of the second qubit (14), entangle the auxiliary qubit (22) in its ground state with the control, Decomputation is performed on the auxiliary qubit (22).

19. The method according to claim 18, further comprising: Using a second auxiliary qubit (26), Entanglement with multiple controlled NOT operations relying on sub-qubit patterns involving two auxiliary qubits (22, 26), A controlled rotation is performed under the conditions of the auxiliary qubits (22, 26) and the remaining combination.

20. A computer program product for compiling a quantum circuit arrangement (100) having at least one quantum circuit (110) for performing a calculation on a quantum computer, the quantum computer being configured to perform the HHL algorithm, The computer program product includes a computer-readable storage medium having program instructions thereon, the program instructions being executable by a computer system (212) to cause the computer system (212) to perform a method comprising: determining, by a lookup structure, a value of a predefined function at a first level of precision based on a variable represented by a set of qubits, and also performing a controlled rotation of another set of qubits; identifying, by the binning structure, a predetermined bin based on the variable; wherein the value of the predefined function for a first level of accuracy is determined based on the bins (64, 66), and the number of controlled rotations required to achieve the first level of accuracy is based on the bins; Quantum phase estimation is performed by a quantum phase estimation structure (40) and inverse quantum phase estimation is performed by an inverse quantum phase estimation structure (42).

21. A data processing system (210) for executing a data processing program (240), comprising: a memory storing computer-readable program instructions; A processor for executing the computer-readable program instructions to cause the data processing system to perform the method according to any one of claims 11 to 19.

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