Manufacturing method of array substrate and array substrate

Abstract

The application provides a manufacturing method of an array substrate and the array substrate. The manufacturing method comprises the following steps: depositing a gate metal layer on a substrate, forming a gate and a scanning line by first photoetching; sequentially depositing a gate insulating layer, a semiconductor layer and a source-drain metal layer, forming an active island by second photoetching, and forming a source, a drain and a data line by the source-drain metal layer, and forming a channel region between the source and the drain; coating a color filter color resist layer by a suspension coating process, and performing an exposure and development process; depositing a protective layer, forming a conductive via on the protective layer and the color filter color resist layer above the drain by third photoetching; depositing a transparent conductive layer, forming a pixel electrode by fourth photoetching, and making the pixel electrode and the drain communicate through the conductive via. The manufacturing method of the array substrate and the array substrate can prevent the silicon oxide protective layer from oxidizing the metal copper.

Description

Technical Field

[0001] This invention relates to the field of liquid crystal display technology, and in particular to a method for manufacturing an array substrate and the array substrate itself. Background Technology

[0002] With the development of display technology, flat panel displays such as Liquid Crystal Displays (LCDs) have become mainstream in various consumer electronics products, including mobile phones, televisions, personal digital assistants, and laptops, due to their advantages such as high image quality, energy saving, thin body, and no radiation. An LCD panel generally consists of an array substrate, a color filter substrate, and a layer of liquid crystal molecules sandwiched between them. By applying a driving voltage between the array substrate and the color filter substrate, the rotation of the liquid crystal molecules can be controlled, causing the light from the backlight module to refract and produce an image.

[0003] In the manufacturing process of array substrates provided by existing technologies, metal oxide semiconductor layers are used as active layers. Metal oxide TFTs (thin film transistors) are sensitive to hydrogen (H), which can even cause them to lose their properties. Therefore, silicon oxide is generally used instead of silicon nitride as the protective layer for metal oxide TFTs.

[0004] However, array substrates often use copper as the source and drain metal layers. When depositing the protective layer of the silicon oxide TFT, the copper is exposed to oxygen plasma and is severely oxidized, or even peeled off. Summary of the Invention

[0005] This invention provides a method for manufacturing an array substrate and an array substrate, which can prevent the protective layer from oxidizing the copper metal of the source, drain and data lines.

[0006] This invention provides a method for fabricating an array substrate, comprising:

[0007] A gate metal layer is deposited on a substrate, and the gate metal layer forms the gate and scan line through a first photolithography process;

[0008] A gate insulating layer, a semiconductor layer, and a source / drain metal layer are deposited sequentially. A second photolithography process is used to form an active island in the semiconductor layer, while the source / drain metal layer forms the source, drain, and data lines. A channel region is formed between the source and the drain.

[0009] A color filter resist layer is coated using a suspension coating process, followed by exposure and development.

[0010] A protective layer is deposited, and conductive vias are formed on the protective layer above the drain and the color filter resist layer through a third photolithography process.

[0011] A transparent conductive layer is deposited, and a fourth photolithography process is used to form a pixel electrode on the transparent conductive layer, and the pixel electrode is connected to the drain through the conductive via.

[0012] In the array substrate fabrication method described above, the source / drain metal layer includes a copper barrier layer and a copper layer covering the copper barrier layer.

[0013] In the array substrate fabrication method described above, the source / drain metal layer further includes a copper protective layer covering the copper metal layer.

[0014] In the array substrate fabrication method described above, both the copper barrier layer and the copper protective layer comprise chromium, tungsten, tantalum, molybdenum, or titanium.

[0015] In the array substrate fabrication method described above, the thickness of the copper barrier layer is 1 / 20 to 1 / 10 of the thickness of the copper layer.

[0016] In the array substrate fabrication method described above, the second photolithography process includes a grayscale mask process or a halftone mask process.

[0017] The fabrication method of the array substrate described above, wherein the second photolithography process specifically includes:

[0018] By exposing and developing a photomask, a fully transparent area, a partially transparent area, and an opaque area are formed. The opaque area corresponds to the source, the drain, and the data line, and the partially transparent area corresponds to the channel area.

[0019] The first etching is performed to etch away the source / drain metal layer and the semiconductor layer corresponding to the fully transparent area;

[0020] A photolithography ashing process is performed to remove the photoresist in the partially transparent area; a second etching process is performed to etch away the source / drain metal layer in the partially transparent area to form the channel region.

[0021] The source and drain metal layers corresponding to the opaque areas are retained to form the source, the drain, and the data lines.

[0022] In the array substrate fabrication method described above, the gate metal layer includes an adhesion layer and a copper layer covering the adhesion layer.

[0023] In the array substrate fabrication method described above, the semiconductor layer includes a first metal oxide semiconductor layer and a second metal oxide semiconductor layer covering the first metal oxide semiconductor layer, wherein the conductivity of the first metal oxide semiconductor layer is lower than the conductivity of the second metal oxide semiconductor layer.

[0024] In another aspect, the present invention provides an array substrate, which is manufactured by the manufacturing method described above.

[0025] The array substrate fabrication method and array substrate provided in this invention employ a metal-oxide-slim thin-film transistor (MTBT) structure. After forming the source and drain electrodes in the second photolithography process, a step of coating a color filter resist layer is added. This allows the color filter resist layer at the TSBT to absorb light, thereby improving the photoluminescence stability of the TSBT. Simultaneously, the color filter resist layer above the data lines protects the copper layer in the data lines from oxidation during the formation of the protective layer. Furthermore, in this embodiment, the data lines, source, and drain electrodes all adopt a double-layer structure: a bottom barrier layer and an upper copper layer. The barrier layer prevents copper from diffusing into the semiconductor layer and increases the adhesion of the copper layer. In addition, the second photolithography process uses a halftone or grayscale mask to simultaneously form the metal-oxide-slim semiconductor layer pattern, source and drain metal electrodes, data scan lines, and the channel region between the source and drain electrodes, saving two photolithography processes and improving production efficiency. Attached Figure Description

[0026] To more clearly illustrate the technical solutions of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0027] Figure 1 This is a schematic diagram of the structure of the array substrate provided in an embodiment of the present invention;

[0028] Figure 2 A flowchart illustrating a method for fabricating an array substrate according to an embodiment of the present invention;

[0029] Figure 3 A cross-sectional view along the AB direction of the array substrate provided in an embodiment of the present invention after the first photolithography process is completed;

[0030] Figure 4 A cross-sectional view along the AB direction of the array substrate provided in the embodiment of the present invention after exposure and development in the second photolithography process;

[0031] Figure 5 A cross-sectional view along the AB direction of the array substrate after the first etching in the second photolithography process provided in the embodiment of the present invention;

[0032] Figure 6 A cross-sectional view along the AB direction of the array substrate after ashing in the second photolithography process provided in this embodiment of the invention;

[0033] Figure 7 A cross-sectional view along the AB direction of the array substrate after the second photolithography process is completed, provided in an embodiment of the present invention;

[0034] Figure 8 A cross-sectional view along the AB direction of the array substrate provided in the embodiment of the present invention after the color filter color resist layer has been coated;

[0035] Figure 9 A cross-sectional view at the data line of the array substrate provided in an embodiment of the present invention after the color filter resist layer has been coated;

[0036] Figure 10 A cross-sectional view along the AB direction of the array substrate after the third photolithography process is completed, provided in an embodiment of the present invention;

[0037] Figure 11 A cross-sectional view along the AB direction of the array substrate after the fourth photolithography process provided in an embodiment of the present invention;

[0038] Figure 12 A cross-sectional view of the data lines on the array substrate after the fourth photolithography process provided in this embodiment of the invention.

[0039] Figure label:

[0040] 10-Substrate; 11-Gate; 111-Adhesion layer; 12-Scan line; 13-Gate insulating layer; 14-Semiconductor layer; 15-Source / drain metal layer; 151-Copper barrier layer; 152-Copper layer; 17-Source; 18-Drain; 19-Data line; 20-Channel region; 21-Color filter color resist layer; 22-Protective layer; 23-Conductive via; 24-Pixel electrode; 25-Photoresist; 251-Fully transparent area; 252-Partially transparent area; 253-Opaque area. Detailed Implementation

[0041] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0042] It is important to understand that a traditional liquid crystal display panel is made by bonding a thin film transistor array substrate (TFT array substrate) and a color filter substrate (CF substrate). Pixel electrodes and common electrodes are formed on the array substrate and the color filter substrate, respectively, and liquid crystal is filled between the array substrate and the color filter substrate. Its working principle is to apply a driving voltage between the pixel electrode and the common electrode, and use the electric field formed between the pixel electrode and the common electrode to control the rotation of liquid crystal molecules in the liquid crystal layer, so as to refract the light from the backlight module to produce an image.

[0043] A photomask, also known as a mask, is a pattern template used in photolithography. It consists of an opaque thin film (chromium) formed on a transparent substrate, onto which the pattern is transferred using photolithography. The exposure process involves ultraviolet light passing through the photomask and irradiating the photoresist, transferring the pattern from the photomask onto the photoresist. In array engineering, the photoresist acts as a mask. During the etching process, the thin film layer on the substrate corresponding to the photoresist pattern is preserved, while other areas are etched away. Finally, the photoresist is removed, and the pattern on the photomask is transferred to the substrate. This process is called photolithography. Each photolithography process involves thin film deposition, photoresist coating, exposure, development, etching, and photoresist stripping.

[0044] Understandably, the number of lithography steps affects both panel production capacity and manufacturing cost, so fewer lithography steps are better.

[0045] In the manufacturing process of array substrates provided by existing technologies, metal oxide semiconductor layers are used as active layers. Metal oxide TFTs (thin-film transistors) are sensitive to hydrogen (H), which can even cause them to lose their properties. Therefore, silicon oxide is generally used instead of silicon nitride as the protective layer for metal oxide TFTs. However, array substrates often use copper as the source and drain metal layers. During the deposition of the protective layer for silicon oxide TFTs, the copper is exposed to oxygen plasma, resulting in severe oxidation and even peeling.

[0046] To address the aforementioned issues, in this embodiment, after the source, drain, and data lines are etched and formed, a color filter layer is added to separate the copper metal from the silicon oxide-containing protective layer, preventing the copper metal from being oxidized.

[0047] The method for manufacturing an array substrate and the array substrate provided in the embodiments of the present invention will be described below with reference to the accompanying drawings and specific embodiments.

[0048] Figure 1 This is a schematic diagram of the array substrate provided in an embodiment of the present invention, with reference to... Figure 1 As shown, the array substrate provided in this embodiment of the invention includes multiple pixel regions. Scan lines 12 and data lines 19 are arranged in a crisscross pattern and surround the pixel regions. The surface of the pixel regions is covered with pixel electrodes 24. Thin-film transistors are disposed at the edges of the pixel regions. The thin-film transistors include a gate connected to the scan lines 12, a source 17 connected to the data lines 19, and a drain 18 connected to the pixel electrodes 24 through conductive vias 23.

[0049] It should be noted that, Figure 1 This is a plan view of the array substrate. Due to the viewing angle, some structures of the array substrate are not shown. Figure 1 As shown in the diagram, it is not described here.

[0050] Figure 2 A flowchart illustrating the method for fabricating an array substrate according to an embodiment of the present invention is provided, with reference to... Figure 2 As shown, the method for fabricating an array substrate provided in this embodiment of the invention includes:

[0051] S101. A gate metal layer is deposited on the substrate 10, and the gate metal layer forms the gate 11 and the scan line 12 through the first photolithography process.

[0052] Specifically, a thickness of approximately [thickness missing] is deposited on the substrate 10 using sputtering or thermal evaporation methods. The gate metal layer can be made of metals or alloys such as Cr, W, Ti, Ta, Mo, Al, and Cu. A gate metal layer composed of multiple metals can also meet the requirements.

[0053] Figure 3 This is a cross-sectional view along the AB direction of the array substrate provided in an embodiment of the present invention after the first photolithography process, with reference to... Figure 3 As shown, after the first photolithography process, the gate metal layer finally forms the gate 11, and as shown... Figure 1 The scan line 12 is shown. In one possible embodiment, the gate metal layer includes an adhesion layer 111 and a copper layer covering the adhesion layer 111. The adhesion layer 111 can be selected from Cr, W, Ti, Ti alloy, Ta, Mo, Mo alloy, etc., and the thickness of the adhesion layer 111 is approximately [missing information]. The thickness of the copper layer is approximately The adhesion layer 111 is mainly used to increase the adhesion of the copper layer to the substrate 10, so as to improve the reliability of the gate 11 and the scan line 12.

[0054] S102, a gate insulating layer 13, a semiconductor layer 14 and a source / drain metal layer 15 are deposited sequentially. Through a second photolithography process, the semiconductor layer 14 forms an active island, while the source / drain metal layer 15 forms a source 17, a drain 18 and a data line 19. A channel region 20 is formed between the source 17 and the drain 18.

[0055] Figure 4 A cross-sectional view along the AB direction of the array substrate after exposure and development in the second photolithography process provided in this embodiment of the invention, with reference to... Figure 4 As shown, in S102, firstly, a thickness of [thickness value missing] is continuously deposited on the substrate 10 after S101 by plasma-enhanced chemical vapor deposition (PECVD). The gate insulating layer 13 can be made of oxide, nitride, or oxynitride compound, and the corresponding reaction gas can be SiH4, NH3, N2, or SiH2C. l2 , NH3, N2.

[0056] Then, a semiconductor layer 14 is deposited by sputtering. The semiconductor layer 14 can be an amorphous oxide semiconductor or a polycrystalline oxide semiconductor, such as amorphous indium gallium zinc oxide a-IGZO, HIZO, IZO, a-InZnO, ZnO:F, In2O3:Sn, In2O3:Mo, Cd2SnO4, ZnO:Al, TiO2:Nb, Cd-Sn-O or other metal oxides, and can be a single layer or multiple layers.

[0057] In one possible implementation, the semiconductor layer 14 includes a first metal oxide semiconductor layer and a second metal oxide semiconductor layer covering the first metal oxide semiconductor layer, wherein the conductivity of the first metal oxide semiconductor layer is lower than that of the second metal oxide semiconductor layer.

[0058] The thickness of the first metal oxide semiconductor layer is The thickness of the second metal oxide semiconductor layer is When depositing a metal oxide semiconductor layer, the conductivity of the metal oxide semiconductor can be effectively controlled by controlling the oxygen content in the metal oxide semiconductor film. The higher the oxygen content in the deposited metal oxide semiconductor film, the better the conductivity of the metal oxide semiconductor film, which is close to that of a conductor. The lower the oxygen content in the deposited metal oxide semiconductor film, the worse the conductivity of the metal oxide semiconductor film, which is close to that of a semiconductor.

[0059] In this embodiment, the first metal-oxide-semiconductor layer with lower conductivity directly contacts the gate insulating layer 13 to form the channel of the thin-film transistor, making the performance of the thin-film transistor more stable. The second metal-oxide-semiconductor layer with higher conductivity contacts the source 17 and the drain 18 to reduce the contact resistance between the semiconductor layer 14 and the source 17 and the drain 18, thereby increasing the on-state current of the thin-film transistor.

[0060] Next, a thickness of [thickness value missing] is deposited by sputtering or thermal evaporation. The source / drain metal layer 15 can be selected from metals and alloys such as Cr, W, Ti, Ta, and Mo, and can be a single layer or multiple layers. In one possible embodiment, the source / drain metal layer 15 includes a copper barrier layer 151 and a copper layer 152 covering the copper barrier layer 151. The copper barrier layer 151 can be made of Cr, W, Ti, Ta, Mo, Mo alloy, Ti alloy, etc. The copper barrier layer 151 serves as a barrier layer for the copper layer 152, preventing the copper layer 152 from diffusing into the semiconductor layer 14, while also increasing the adhesion of the copper layer 152. The thickness of the copper barrier layer 151 is 1 / 20 to 1 / 10 of the thickness of the copper layer 152; specifically, the thickness of the copper barrier layer 151 is approximately... The thickness of the copper layer 152 is approximately

[0061] Optionally, the source / drain metal layer 15 may further include a copper protective layer (not shown in the figure) covering the copper layer 152. The copper protective layer may be made of Cr, W, Ti, Ta, Mo, Mo alloy, Ti alloy, etc., and may be made of the same material as the copper barrier layer 151. The copper protective layer serves to protect the copper layer 152 and prevent the color filter resist layer and silicon oxide protective layer formed in subsequent steps from affecting the performance of the copper layer 152.

[0062] Specifically, the second photolithography step is performed using either a halftone mask process or a single gray-tone mask process. A halftone mask (HTM) uses a semi-transparent film on the mask to partially expose the photoresist. A gray-tone mask uses grayscale areas on the mask to block light and also partially expose the photoresist.

[0063] Continue to refer to Figure 4As shown, after exposure and development using a photomask, the array substrate is divided into a fully transparent region 251, a partially transparent region 252, and an opaque region 253. The opaque region 253 has a thicker photoresist 25, the partially transparent region 252 has a thinner photoresist 25, and the fully transparent region 251 has no photoresist 25. The opaque region 253 corresponds to the area where the source 17, drain 18, and data line 19 are located, the partially transparent region 252 corresponds to the channel region 20, and the fully transparent region 251 corresponds to the area excluding the opaque region 253 and the partially transparent region 252.

[0064] Figure 5 This is a cross-sectional view along the AB direction of the array substrate after the first etching in the second photolithography process provided in this embodiment of the invention, with reference to... Figure 5 As shown, in Figure 4 Based on this, a first etching is performed, etching away the source / drain metal layer 15 and semiconductor layer 14 corresponding to the fully transparent region 251, so that only the gate insulating layer 13 and the portion below it remain in the fully transparent region 251. After the first etching is completed, the semiconductor layer 14 forms an active island, the source / drain metal layer 15 above the active island is retained, and the semiconductor layer 14 and source / drain metal layer 15 outside the active island are etched away.

[0065] Figure 6 This is a cross-sectional view along the AB direction of the array substrate after ashing in the second photolithography process provided in this embodiment of the invention, with reference to... Figure 6 As shown, in Figure 5 Based on this, a photolithography ashing process is performed to remove part of the photoresist 25 in the light-transmitting area 252, while the thickness of the photoresist 25 in the opaque area 251 becomes thinner.

[0066] Figure 7 A cross-sectional view along the AB direction of the array substrate after the second photolithography process provided in this embodiment of the invention, with reference to... Figure 7 As shown, in Figure 6 Based on this, a second etching is performed to etch away part of the source and drain metal layer 15 in the light-transmitting area 252 to form the channel area 20; at the same time, the source and drain metal layer 15 corresponding to the opaque area 253 is retained, forming the source 17, drain 18, and data line 19.

[0067] It should be noted that during the second etching, the second metal oxide semiconductor layer in the channel region 20 can be etched away, while the first metal oxide semiconductor layer in the channel region 20 is retained. The low conductivity of the first metal oxide semiconductor layer can make the performance of the thin film transistor more stable.

[0068] Furthermore, in order to improve the performance of the thin-film transistor, the surface of the first metal oxide semiconductor layer in the channel region 20 can be treated, such as by using nitrous oxide treatment, to repair the damage and contamination of the first metal oxide semiconductor layer during etching.

[0069] S103. Apply the color filter color resist layer 21 by suspension coating process, and then expose and develop it.

[0070] Figure 8 This is a cross-sectional view along the AB direction of the array substrate provided in an embodiment of the present invention after the color filter resist layer has been coated. Figure 8 As shown, in Figure 7 Based on this, a color filter resist material is coated using a suspension coating process, and then formed through an exposure and development process, such as... Figure 8 The color filter resist layer 21 is located in the thin-film transistor. The color filter resist layer 21 can absorb light and improve the stability of the thin-film transistor under illumination.

[0071] Figure 9 This is a cross-sectional view of the array substrate at the data line after the color filter resist layer has been coated, as provided in the embodiment of the present invention. Figure 9 As shown, a color filter color resist layer 21 is covered above the data line 19 to prevent the copper metal layer of the data line 19 from being oxidized by the silicon oxide protective layer formed in subsequent steps.

[0072] S104, depositing protective layer 22, and through the third photolithography process, forming conductive vias 23 on the protective layer 22 above the drain electrode 18 and the color filter color resist layer 21.

[0073] Figure 10 A cross-sectional view along the AB direction of the array substrate after the third photolithography process provided in this embodiment of the invention, with reference to... Figure 10 As shown, specifically, in Figure 8 Based on this, a continuous deposition thickness of [thickness value missing] is achieved using plasma-enhanced chemical vapor deposition. The protective layer 22 can be an oxide, nitride, or oxynitride compound, and can be a single layer or multiple layers. The reaction gases corresponding to silicon oxides can be SiH4 or N2O, while the reaction gases corresponding to nitrides or oxynitride compounds can be SiH4, NH3, N2, or SiH2C. l2 , NH3, N2.

[0074] After the protective layer is deposited, a third photolithography process is required to form conductive vias 23 on the protective layer 22 and the color filter resist layer 21. The conductive vias 23 are located above the drain electrode 18 and are used to connect the drain electrode 18 and the pixel electrode 24.

[0075] S105. Deposit a transparent conductive layer. Through the fourth photolithography process, the transparent conductive layer forms the pixel electrode 24 and connects the pixel electrode 24 and the drain electrode 18 through the conductive via 23.

[0076] Figure 11 A cross-sectional view along the AB direction of the array substrate after the fourth photolithography process provided in this embodiment of the invention, with reference to... Figure 11 As shown, specifically, based on the completion of S104, a layer with a thickness of approximately [thickness missing] is continuously deposited by sputtering or thermal evaporation. The transparent conductive layer can be indium tin oxide (ITO), indium zinc oxide (IZO), or other transparent metal oxides. Through a fourth photolithography process, the transparent conductive layer forms the pixel electrode 24, and the pixel electrode 24 is connected to the drain electrode 18 through a conductive via 23.

[0077] Figure 12 This is a cross-sectional view of the data lines on the array substrate after the fourth photolithography process provided in an embodiment of the present invention, with reference to... Figure 12 As shown, above the data line 19, there is a color filter color resist layer 21 and a protective layer 22, but no pixel electrode 24. The color filter color resist layer 21 serves to protect the copper layer of the data line 19 and prevent the copper from being oxidized when the protective layer 22 is formed.

[0078] The array substrate fabrication method and array substrate provided in this invention employ a metal-oxide-slim thin-film transistor (MTBT) structure. After forming the source and drain electrodes in the second photolithography process, a step of coating a color filter resist layer is added. This allows the color filter resist layer at the TSBT to absorb light, thereby improving the photoluminescence stability of the TSBT. Simultaneously, the color filter resist layer above the data lines protects the copper layer in the data lines from oxidation during the formation of the protective layer. Furthermore, in this embodiment, the data lines, source, and drain electrodes all adopt a double-layer structure: a bottom barrier layer and an upper copper layer. The barrier layer prevents copper from diffusing into the semiconductor layer and increases the adhesion of the copper layer. In addition, the second photolithography process uses a halftone or grayscale mask to simultaneously form the metal-oxide-slim semiconductor layer pattern, source and drain metal electrodes, data scan lines, and the channel region between the source and drain electrodes, saving two photolithography processes and improving production efficiency.

[0079] In the description of this invention, it should be understood that the terms "center," "length," "width," "thickness," "top," "bottom," "upper," "lower," "left," "right," "front," "rear," "vertical," "horizontal," "inner," "outer," "axial," and "circumferential," etc., used to indicate orientation or positional relationships are based on the orientation or positional relationships shown in the accompanying drawings and are only for the convenience of describing this invention and simplifying the description, and are not intended to indicate or imply that the indicated position or component must have a specific orientation, or a specific structure and operation, and therefore should not be construed as a limitation of this invention.

[0080] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0081] In this invention, unless otherwise explicitly specified and limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection, an electrical connection, or a connection that allows communication between them; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0082] In this invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0083] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for fabricating an array substrate, characterized in that, include: A gate metal layer is deposited on a substrate, and the gate metal layer forms the gate and scan line through a first photolithography process; A gate insulating layer, a semiconductor layer, and a source / drain metal layer are deposited sequentially. A second photolithography process is used to form an active island in the semiconductor layer, and the source / drain metal layer forms the source, drain, and data lines. A channel region is formed between the source and the drain. The source / drain metal layer includes a copper barrier layer and a copper layer covering the copper barrier layer. A color filter resist layer is coated using a suspension coating process, followed by exposure and development. A silicon oxide-containing protective layer is deposited, and conductive vias are formed on the protective layer above the drain and the color filter resist layer through a third photolithography process. A transparent conductive layer is deposited, and a fourth photolithography process is used to form a pixel electrode in the transparent conductive layer and connect the pixel electrode to the drain through the conductive via. The color filter color resist layer is used to absorb light and separate the metallic copper and the protective layer.

2. The manufacturing method according to claim 1, characterized in that, The source / drain metal layer also includes a copper protective layer covering the copper metal layer.

3. The manufacturing method according to claim 2, characterized in that, Both the copper barrier layer and the copper protective layer comprise chromium, tungsten, tantalum, molybdenum, or titanium.

4. The manufacturing method according to claim 1, characterized in that, The thickness of the copper barrier layer is 1 / 20 to 1 / 10 of the thickness of the metallic copper layer.

5. The manufacturing method according to claim 1, characterized in that, The second photolithography process includes a grayscale mask process or a halftone mask process.

6. The manufacturing method according to claim 5, characterized in that, The second photolithography process specifically includes: By exposing and developing a photomask, a fully transparent area, a partially transparent area, and an opaque area are formed. The opaque area corresponds to the source, the drain, and the data line, and the partially transparent area corresponds to the channel area. The first etching is performed to etch away the source / drain metal layer and the semiconductor layer corresponding to the fully transparent area; A photolithography ashing process is performed to remove the photoresist in the partially transparent area; a second etching process is performed to etch away the source / drain metal layer in the partially transparent area to form the channel region. The source and drain metal layers corresponding to the opaque areas are retained to form the source, the drain, and the data lines.

7. The manufacturing method according to claim 1, characterized in that, The gate metal layer includes an adhesion layer and a copper layer covering the adhesion layer.

8. The manufacturing method according to claim 1, characterized in that, The semiconductor layer includes a first metal oxide semiconductor layer and a second metal oxide semiconductor layer covering the first metal oxide semiconductor layer, wherein the conductivity of the first metal oxide semiconductor layer is lower than the conductivity of the second metal oxide semiconductor layer.

9. An array substrate, characterized in that, The array substrate is manufactured by the manufacturing method described in any one of claims 1-8.

Images