A 22KHz signal anti-interference tuning and amplifying circuit for a front-end tuner

Abstract

The present invention discloses a 22KHz signal anti-interference tuning and amplifying circuit for a high-frequency head, which includes a tuning and amplifying circuit, a peak detection circuit and a data limiter circuit; the peak detection circuit is connected to the tuning and amplifying circuit, and the peak detection circuit is connected to the data limiter circuit; the signal is input from the tuning and amplifying circuit and output from the data limiter circuit; the tuning and amplifying circuit is used for tuning and amplifying analog signals; the peak detection circuit extracts and holds the peak value of the tuned and amplified signal; the data limiter circuit is used for converting the amplitude-modulated wave envelope signal extracted by the peak detection circuit into a digital signal; this anti-interference tuning and amplifying circuit has the characteristics of using fewer components, improving the anti-noise ability and reducing the error rate in signal conversion.

Description

Technical Field

[0001] The present invention relates to the field of electronic circuits, and particularly to a 22KHz signal anti-interference tuning amplifier circuit for a tuner head. Background Art

[0002] In the prior art 22KHz signal anti-interference tuning amplifier circuit, the involved amplifier, tuning, and data limiter circuits are designed using operational amplifiers, comparators, and digital circuits, or using an amplifier and tuning each individual 22kHz cycle. The latter is very expensive, requires a large PCB area, and the amplification and pulse counting processes are prone to errors.

[0003] In view of the above problems, the present invention designs a 22KHz signal anti-interference tuning amplifier circuit for a tuner head, and this case is thus generated. Summary of the Invention

[0004] The present invention provides a 22KHz signal anti-interference tuning amplifier circuit for a tuner head, and the anti-interference tuning amplifier circuit has the characteristics of using fewer components, improving the anti-noise ability, and reducing the error rate in signal conversion; specifically, the present invention is realized through the following technical solutions:

[0005] A 22KHz signal anti-interference tuning amplifier circuit for a tuner head includes a tuning amplifier circuit, a peak detection circuit, and a data limiter circuit; the peak detection circuit is connected to the tuning amplifier circuit, and the peak detection circuit is connected to the data limiter circuit; the signal is input from the tuning amplifier circuit and output from the data limiter circuit; the tuning amplifier circuit is used for tuning and amplifying an analog signal; the peak detection circuit extracts and holds the peak of the tuned and amplified signal; the data limiter circuit is used for converting the amplitude-modulated wave envelope signal extracted by the peak detection circuit into a digital signal.

[0006] The purpose of tuning and amplifying the analog signal is achieved through the tuning amplifier circuit; the peak of the tuned and amplified signal is extracted and held through the peak detection circuit to form an amplitude-modulated wave envelope signal; the amplitude-modulated wave envelope signal extracted by the peak detection circuit is converted into a digital signal through the data limiter circuit.

[0007] Further, the tuning amplifier circuit includes an NPN-type triode Q1. The base of the triode Q1 is connected to a capacitor C1, and the signal passes through the capacitor C1 and is input to the triode Q1; the emitter of the triode Q1 is grounded, and a resistor R2 and a capacitor C2 are connected in parallel between the base and the collector of the triode Q1; the collector of the triode Q1 is connected to the power supply V1; a resistor R3 is connected in series between the collector of the triode Q1 and the power supply V1.

[0008] Further, the peak detection circuit includes an NPN transistor Q2, a resistor R3, and a capacitor C3; the base of the transistor Q2 is connected to the collector of the transistor Q1 in the tuned amplification circuit; the collector of the transistor Q2 is connected to the base, the emitter of the transistor Q2 is connected to the resistor R4 and then grounded, and the emitter of the transistor Q2 is connected to the capacitor C3 and then grounded.

[0009] Further, the data limiter circuit includes an NPN transistor Q3 and an NPN transistor Q4; the base of the transistor Q3 is connected to the emitter of the transistor Q2 in the peak detection circuit, and a resistor R5 is connected in series between the two; the collector of the transistor Q3 is connected in series to the power supply V1, and a resistor R6 is connected in series between the collector of the transistor Q3 and the power supply V1; the emitter of the transistor Q3 is connected to the resistor R7 and then grounded, and the emitter of the transistor Q3 is connected to the emitter of the transistor Q4; the collector of the transistor Q3 is connected to the base of the transistor Q4, and a resistor R9 is connected in series between the two; the base of the transistor Q4 is connected to the resistor R10 and then grounded; the collector of the transistor Q4 is connected to the power supply V1, and a resistor R8 is connected in series between the collector of the transistor Q4 and the power supply V1.

[0010] The envelope signal of the amplitude-modulated wave passes through the transistors Q3 and Q4 and is converted into a binary signal and output from the collector of the transistor Q4.

[0011] Among the above three circuits, expensive components such as operational amplifiers and comparators are not used. Transistors are used, which have a very small PCB area occupation and extremely low cost. At the same time, the above circuits have a high level of anti-interference ability and can resist large changes in the Diseqc signal and the glitches caused by the Diseqc signal. The circuit can also tune the tone and the presence of voltage signaling and decode the data control message at the same time.

[0012] Further, the data limiter circuit is connected to the MCU.

[0013] Preferably, the resistance value of R1 is 4K7, the resistance value of R2 is 68K, the resistance value of R3 is 4K7, the resistance value of R4 is 33K, the resistance value of R5 is 1K, the resistance value of R6 is 15K, the resistance value of R7 is 1K, the resistance value of R8 is 47K, the resistance value of R9 is 6K8, and the resistance value of R10 is 20K; the capacitance of C1 is 3.3 nF, the capacitance of C2 is 22 pF, and the capacitance of C3 is 4.7 nF; the power supply V1 is a 6V DC power supply.

[0014] Further, the NPN transistors Q1, Q2, Q3, and Q4 are all NXP type two dual-transistor packages PUMX1.

[0015] The 22KHz signal anti-interference tuning amplifier circuit of the present invention provides a high level of anti-noise ability and can withstand large variations in data control signals and faults that occur in data control information. It requires fewer and smaller components, some of which are dual-transistor packages, with very small PCB area occupancy and extremely low cost. The circuit can also tune to the presence of tone and voltage signaling while decoding data control messages. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 FIG. is a schematic diagram of an embodiment of a 22KHz signal anti-interference tuning amplifier circuit for a high-frequency head provided by the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0017] The present invention will be further described below in conjunction with the drawings and specific embodiments.

[0018] As Figure 1 shown, a 22KHz signal anti-interference tuning amplifier circuit for a high-frequency head includes a tuning amplifier circuit 11, a peak detection circuit 22, and a data limiter circuit 33 connected in sequence; the signal is input from the tuning amplifier circuit 11 and output from the data limiter circuit 33, and the data limiter circuit 33 is connected to the MCU, and the output signal enters the MCU.

[0019] The tuning amplifier circuit 11 is used to tune and amplify the Dsicqc 1.0 signal centered at 22KHz. The peak detection circuit 22 extracts and holds the peak of the tuned and amplified signal. The data limiter circuit 33 converts the amplitude-modulated wave envelope signal extracted by the peak detection circuit 22 into a digital signal.

[0020] Among them, the tuning amplifier circuit 11 includes an NPN-type triode Q1. The base of the triode Q1 is connected to a capacitor C1, and the capacitor C1 is connected to a resistor R1; the emitter of the triode Q1 is grounded, and a resistor R2 and a capacitor C2 are connected in parallel between the base and the collector of the triode Q1. The collector of the triode Q1 is connected to the power supply V1. A resistor R3 is connected in series between the collector of the triode Q1 and the power supply V1. The signal enters from one end of the resistor R1, is tuned by the capacitor C1, amplified by the triode Q1, and then output from the collector terminal of the triode Q1.

[0021] The peak detection circuit 22 includes an NPN-type triode Q2, a resistor R3, and a capacitor C3. Among them, the base of the triode Q2 is connected to the collector of the triode Q1 in the tuning amplifier circuit 11. The collector of the triode Q2 is connected to the base, the emitter of the triode Q2 is connected to the resistor R4 and then grounded, and the emitter of the triode Q2 is connected to the capacitor C3 and then grounded. The signal enters from the base of the triode Q2 and is output from the emitter of the triode Q2.

[0022] The data limiter circuit 33 includes an NPN transistor Q3 and an NPN transistor Q4; wherein the base of the transistor Q3 is connected to the emitter of the transistor Q2 in the peak detection circuit 22, and a resistor R5 is connected in series between the two; the collector of the transistor Q3 is connected in series to the power supply V1, and a resistor R6 is connected in series between the collector of the transistor Q3 and the power supply V1; the emitter of the transistor Q3 is connected to the resistor R7 and then grounded, and the emitter of the transistor Q3 is connected to the emitter-collector of the transistor Q4; the collector of the transistor Q3 is connected to the base of the transistor Q4, and a resistor R9 is connected in series between the two; the base of the transistor Q4 is connected to the resistor R10 and then grounded; the collector of the transistor Q4 is connected to the power supply V1, and a resistor R8 is connected in series between the collector of the transistor Q4 and the power supply V1; the envelope signal of the amplitude-modulated wave passes through the transistor Q3 and the transistor Q4, and is converted into a binary signal and output from the collector of the transistor Q4.

[0023] Among them, the components in the above circuit are selected with the following specifications: R1 = 4K7, R2 = 68K, R3 = 4K7, R4 = 33K, R5 = 1K, R6 = 15K, R7 = 1K, R8 = 47K, R9 = 6K8, R10 = 20K;

[0024] C1 = 3.3nF, C2 = 22pF, C3 = 4.7nF;

[0025] The NPN transistors Q1, Q2, Q3, and Q4 are all two NXP-type dual-transistor packages PUMX1.

[0026] The power supply V1 is a 6V DC power supply.

[0027] The above is the preferred embodiment of the present invention. Under the premise of the inventive concept of the present invention, several other simple substitutions and modifications should be regarded as belonging to the protection scope of the present invention.

Claims

1. A 22KHz signal anti-interference tuning and amplifying circuit for a front end, characterized in that: It includes a tuning amplifier circuit, a peak detection circuit, and a data limiter circuit; the peak detection circuit is connected to the tuning amplifier circuit, and the peak detection circuit is connected to the data limiter circuit; the signal is input from the tuning amplifier circuit and output from the data limiter circuit; The tuning amplifier circuit is used to tune and amplify the analog signal; the peak detection circuit extracts and holds the peak value of the tuned and amplified signal; the data limiter circuit is used to convert the amplitude-modulated wave envelope signal extracted by the peak detection circuit into a digital signal; the tuning amplifier circuit includes an NPN transistor Q1, the base of the transistor Q1 is connected to a capacitor C1, the signal passes through the capacitor C1 and is input to the transistor Q1; the emitter of the transistor Q1 is grounded, a resistor R2 and a capacitor C2 are connected in parallel between the base and the collector of the transistor Q1; the collector of the transistor Q1 is connected to the power supply V1; a resistor R3 is connected in series between the collector of the transistor Q1 and the power supply V1; the peak detection circuit includes an NPN transistor Q2, a resistor R3, and a capacitor C3; the base of the transistor Q2 is connected to the collector of the transistor Q1 in the tuning amplifier circuit; the collector of the transistor Q2 is connected to the base, the emitter of the transistor Q2 is connected to the resistor R4 and then grounded, and the emitter of the transistor Q2 is connected to the capacitor C3 and then grounded; the data limiter circuit includes an NPN transistor Q3 and an NPN transistor Q4; the base of the transistor Q3 is connected to the emitter of the transistor Q2 in the peak detection circuit, and a resistor R5 is connected in series between them; the collector of the transistor Q3 is connected in series to the power supply V1, and a resistor R6 is connected in series between the collector of the transistor Q3 and the power supply V1; the emitter of the transistor Q3 is connected to the resistor R7 and then grounded, and the emitter of the transistor Q3 is connected to the emitter-collector of the transistor Q4; the collector of the transistor Q3 is connected to the base of the transistor Q4, and a resistor R9 is connected in series between them; the base of the transistor Q4 is connected to the resistor R10 and then grounded; the collector of the transistor Q4 is connected to the power supply V1, and a resistor R8 is connected in series between the collector of the transistor Q4 and the power supply V1; the data limiter circuit is connected to the MCU; the NPN transistors Q1, Q2, Q3, and Q4 are all NXP type two dual-transistor packages PUMX1.

2. The 22KHz signal anti-interference tuning amplifier circuit for a RF head according to claim 1, wherein: The resistance value of R1 is 4K7, the resistance value of R2 is 68K, the resistance value of R3 is 4K7, the resistance value of R4 is 33K, the resistance value of R5 is 1K, the resistance value of R6 is 15K, the resistance value of R7 is 1K, the resistance value of R8 is 47K, the resistance value of R9 is 6K8, and the resistance value of R10 is 20K; the capacitance of C1 is 3.3nF, the capacitance of C2 is 22pF, the capacitance of C3 is 4.7nF; the power supply V1 is a 6V DC power supply.

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