Level shift circuit and source driver including the same

Abstract

The present disclosure discloses a source driver including a level shift circuit. The source driver may include a level shift circuit that outputs a second logic signal and a third logic signal by shifting the level of a first logic signal, and a multiplexer that transmits a first source signal or a second source signal to a first pad or a second pad in response to the second logic signal and the third logic signal. The level shift circuit may include a first level shifter that outputs a first input signal and a second input signal by shifting the level of the first logic signal, a second level shifter that outputs a third input signal and a fourth input signal by shifting the level of the first logic signal, and an output circuit that outputs a second logic signal in response to the second input signal and the fourth input signal, and outputs a third logic signal in response to the first input signal and the third input signal.

Description

Technical Field

[0001] The present disclosure relates to a display device, and more particularly, to a level shift circuit and a source driver including the same. Background Art

[0002] Generally, a source driver of a display device is required to have low resistance in its source output stage in order to display an image with high resolution at high speed. To this end, a known source driver includes an output circuit using a multiplexer composed of high voltage elements operating in a high voltage range.

[0003] From the viewpoint of the chip size of the source driver, a multiplexer composed of high-voltage components becomes a burden. For this reason, the source driver keeps the source output stage at a low resistance by adopting a multiplexer composed of intermediate voltage components operating in an intermediate voltage range to reduce the chip size.

[0004] Multiplexers require logic signals that swing in a high voltage range to reduce the resistance of the source output stage. A level shift circuit with high voltage components can be used to provide logic signals that swing in a high voltage range to the multiplexer.

[0005] In addition, the source signal output from the multiplexer to the source output stage also swings within the high voltage range. Therefore, the source signal can be output using an input clamp circuit and an output clamp circuit with a high voltage element operating within the high voltage range, and the swing range of the source signal can be clamped to the high voltage range.

[0006] Therefore, the conventional source driver has a problem of increasing the chip size since a circuit is configured using high voltage elements. Summary of the invention

[0007] Various embodiments are directed to providing a level shift circuit capable of processing a logic signal having a high voltage range by using only an intermediate voltage element operating in an intermediate voltage range, and a source driver including the same.

[0008] In an embodiment, a source driver may include: a level shift circuit configured to output a second logic signal and a third logic signal by shifting a level of a first logic signal; and a multiplexer configured to transmit a first source signal or a second source signal to a first pad or a second pad in response to the second logic signal and the third logic signal. The level shift circuit may include: a first level shifter configured to output a first input signal and a second input signal by shifting a level of the first logic signal; a second level shifter configured to output a third input signal and a fourth input signal by shifting a level of the first logic signal; and an output circuit configured to output a second logic signal in response to the second input signal and the fourth input signal, and output a third logic signal in response to the first input signal and the third input signal.

[0009] In an embodiment, a level shift circuit may include: a first level shifter configured to output a first input signal and a second input signal by shifting a level of a first logic signal; a second level shifter configured to output a third input signal and a fourth input signal by shifting a level of the first logic signal; and an output circuit configured to output a second logic signal in response to the second input signal and the fourth input signal, and output a third logic signal in response to the first input signal and the third input signal. The output circuit may output a second logic signal and a third logic signal each having a third voltage range including the first voltage range and the second voltage range by using a pull-up element operating in the first voltage range and a pull-down element operating in the second voltage range.

[0010] According to an embodiment, since a circuit capable of processing a logic signal having a high voltage range is configured using only intermediate voltage elements operating within an intermediate voltage range, a chip size may be reduced.

[0011] In addition, since a high voltage mask layer can be omitted in the process, the production cost can be reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 is a block diagram of a source driver according to an embodiment.

[0013] Figure 2 A source driver including a level shift circuit according to an embodiment is shown.

[0014] Figure 3 An output circuit of a level shift circuit according to an embodiment is shown.

[0015] Figure 4 is a diagram illustrating the operation of the level shift circuit according to the embodiment. DETAILED DESCRIPTION

[0016] Embodiments are directed to providing a level shift circuit capable of processing a signal having a high voltage range by using only an intermediate voltage element operating in an intermediate voltage range, and a source driver including the same.

[0017] In an embodiment, the intermediate voltage range can be defined as the swing range of the first source signal output by the positive amplifier, or can be defined as the swing range of the second source signal output by the negative amplifier. In this case, the swing range of the first source signal can be named as the first voltage range, and the swing range of the second source signal can be named as the second voltage range.

[0018] In an embodiment, the high voltage range may be defined as a voltage range from the highest voltage of the first voltage range to the lowest voltage of the second voltage range. In this case, the high voltage range may be named as a third voltage range.

[0019] In an implementation, an intermediate voltage element may be defined as an element operating in a first voltage range or in a second voltage range.

[0020] Figure 1 is a block diagram of a source driver 100 according to an embodiment. In this case, only an example in which a pair of source signals S1 and S2 are provided to a display panel (not shown) through a pair of channels is shown, but this is for convenience of description and the present disclosure is not limited thereto.

[0021] Reference Figure 1 , the source driver 100 may include a positive amplifier PAMP, a negative amplifier NAMP, a multiplexer MV_MUX, a level shift circuit 10, and clamp circuits 20a and 20b.

[0022] The positive amplifier PAMP may amplify the positive data PDATA and output the amplified data as a first source signal S1. The negative amplifier NAMP may amplify the negative data NDATA and output the amplified data as a second source signal S2. In this case, the positive amplifier PAMP may operate within a first voltage range. The negative amplifier NAMP may operate within a second voltage range.

[0023] Although not shown, the source driver 100 may further include a latch circuit latching the image data and a digital-to-analog converter converting the image data into positive data PDATA and negative data NDATA by using gray voltages.

[0024] The multiplexer MV_MUX may output the first source signal S1 as the first output signal OUT1 and may output the second source signal S2 as the second output signal OUT2. Alternatively, the multiplexer MV_MUX may output the first source signal S1 as the second output signal OUT2 and may output the second source signal S2 as the first output signal OUT1.

[0025] The multiplexer MV_MUX can output the first source signal S1 and the second source signal S2 as the first output signal OUT1 and the second output signal OUT2, respectively, or output the first source signal S1 and the second source signal S2 as the second output signal OUT2 and the first output signal OUT1, respectively, based on the logic levels of the logic signal CS2 and the logic signal CS2B provided by the level shift circuit 10.

[0026] The multiplexer MV_MUX may be configured using an intermediate voltage element operating within the first voltage range or an intermediate voltage element operating within the second voltage range. For example, the multiplexer MV_MUX may include a first positive switch circuit that converts a first source signal S1 into a first output signal OUT1, a second positive switch circuit that converts the first source signal S1 into a second output signal OUT2, a first negative switch circuit that converts the second source signal S2 into the second output signal OUT2, and a second negative switch circuit that converts the second source signal S2 into the first output signal OUT1.

[0027] In addition, each switch circuit of the multiplexer MV_MUX may include switches that operate within an intermediate voltage range and are connected in series. Each switch may be turned on or off in response to the logic signal CS2 and the logic signal CS2B.

[0028] The level shift circuit 10 may output the second logic signal CS2 and the third logic signal CS2B to the multiplexer MV_MUX by shifting the level of the first logic signal CS1 having a low voltage level. In this case, the third logic signal CS2B may be an inversion signal of the second logic signal CS2.

[0029] The clamp circuit 20a and the clamp circuit 20b can clamp the first output signal OUT1 and the second output signal OUT2 to the first voltage range or the second voltage range. For example, each of the clamp circuit 20a and the clamp circuit 20b may include a diode connected in series. Each diode may be configured using an element operating in an intermediate voltage range.

[0030] Figure 2 A source driver 100 including a level shift circuit 10 according to an embodiment is shown.

[0031] refer to Figure 2The level shift circuit 10 may include a first level shifter 12 a, a second level shifter 12 b and an output circuit 14 .

[0032] The first level shifter 12a can output the first input signal PIN and the second input signal PINB by shifting the level of the first logic signal CS1. The second input signal PINB can be an inverted signal of the first input signal PIN. The first level shifter 12a can operate within a first voltage range (i.e., a swing range of the first source signal S1).

[0033] The second level shifter 12b can output the third input signal NIN and the fourth input signal NINB by shifting the level of the first logic signal CS1. The fourth input signal NINB can be an inverted signal of the third input signal NIN. The second level shifter 12b can operate within a second voltage range (i.e., a swing range of the second source signal S2).

[0034] The output circuit 14 may output the second logic signal CS2 in response to the second input signal PINB and the fourth input signal NINB, and may output the third logic signal CS2B in response to the first input signal PIN and the third input signal NIN.

[0035] The output circuit 14 may include a pull-up element operating within the first voltage range, and may include a pull-down element operating within the second voltage range. In addition, the output circuit 14 may output a second logic signal CS2 and a third logic signal CS2B, which may swing within a third voltage range from the highest voltage of the first voltage range to the lowest voltage of the second voltage range.

[0036] The positive amplifier PAMP may amplify the positive data PDATA and output the amplified data as a first source signal S1. The negative amplifier NAMP may amplify the negative data NDATA and output the amplified data as a second source signal S2. In this case, the positive amplifier PAMP may operate within a first voltage range, and the negative amplifier NAMP may operate within a second voltage range.

[0037] The multiplexer MV_MUX can output the first source signal S1 and the second source signal S2 as the first output signal OUT1 and the second output signal OUT2, respectively, or output the first source signal S1 and the second source signal S2 as the second output signal OUT2 and the first output signal OUT1, respectively, based on the logic levels of the second logic signal CS2 and the third logic signal CS2B.

[0038] The multiplexer MV_MUX may include a first positive switch circuit, a second positive switch circuit, a first negative switch circuit, and a second negative switch circuit. The first positive switch circuit may transmit the first source signal S1 as a first output signal OUT1 to the first pad. The second positive switch circuit may transmit the first source signal S1 as a second output signal OUT2 to the second pad. The first negative switch circuit may transmit the second source signal S2 as a second output signal OUT2 to the second pad. The second negative switch circuit may transmit the second source signal S2 as a first output signal OUT1 to the first pad.

[0039] Each of the first positive switch circuit, the second positive switch circuit, the first negative switch circuit, and the second negative switch circuit may include switches operating within an intermediate voltage range and connected in series. Each switch may be configured as at least one NMOS transistor or a PMOS transistor.

[0040] The first clamping circuit 20 a may be coupled between the multiplexer MV_MUX and the first pad, and may clamp the first output signal OUT1 output to the first pad to a first voltage range or a second voltage range.

[0041] The second clamping circuit 20 b may be coupled between the multiplexer MV_MUX and the second pad, and may clamp the second output signal OUT2 output to the second pad to the first voltage range or the second voltage range.

[0042] The first clamping circuit 20a and the second clamping circuit 20b may include first and second diodes connected in series and third and fourth diodes connected in series.

[0043] The first diode and the second diode may clamp the first output signal OUT1 or the second output signal OUT2 to a first voltage range. The third diode and the fourth diode may clamp the first output signal OUT1 or the second output signal OUT2 to a second voltage range.

[0044] Figure 3 The output circuit 14 of the level shift circuit 10 according to the embodiment is shown.

[0045] Reference Figure 3 The output circuit 14 of the level shift circuit 10 may include a first output circuit 30, which outputs the second logic signal CS2 through a pull-up operation or a pull-down operation based on the logic levels of the second input signal PINB and the fourth input signal NINB, and may include a second output circuit 40, which outputs the third logic signal CS2B through a pull-up operation or a pull-down operation based on the logic levels of the first input signal PIN and the third input signal NIN.

[0046] The first output circuit 30 may include a first pull-up circuit 32 configured to pull up and drive the second logic signal CS2 in response to the second input signal PINB, a first voltage divider circuit 34 connected between the first pull-up circuit 32 and a first output stage from which the second logic signal CS2 is output, a first pull-down circuit 38 configured to pull down and drive the second logic signal CS2 in response to a fourth input signal NINB, and a second voltage divider circuit 36 ​​connected between the first pull-down circuit 38 and the first output stage.

[0047] The first pull-up circuit 32 may include a first PMOS element and a second PMOS element connected in series. The first PMOS element and the second PMOS element may have a source terminal and a body terminal connected in common, and may have a gate terminal to which a second input signal PINB is applied. The first pull-up circuit 32 may operate within a first voltage range.

[0048] The first pull-down circuit 38 may include a first NMOS element and a second NMOS element connected in series. The first NMOS element and the second NMOS element may have a source terminal and a body terminal connected in common, and may have a gate terminal to which a fourth input signal NINB is applied. The first pull-down circuit 38 may operate within a second voltage range.

[0049] The first voltage divider circuit 34 may include a third PMOS element and a fourth PMOS element connected in series. Each of the third PMOS element and the fourth PMOS element may have a source terminal and a body terminal connected in common, and may have a gate terminal to which a ground voltage GND is applied. The first voltage divider circuit 34 may operate in a first voltage range or in a second voltage range based on the logic levels of the second input signal PINB and the fourth input signal NINB.

[0050] The second voltage divider circuit 36 ​​may include a third NMOS element and a fourth NMOS element connected in series. Each of the third NMOS element and the fourth NMOS element may have a source terminal and a body terminal connected in common, and may have a gate terminal to which a ground voltage GND is applied. The second voltage divider circuit 36 ​​may operate in a first voltage range or in a second voltage range based on the logic levels of the second input signal PINB and the fourth input signal NINB.

[0051] The second output circuit 40 may include a second pull-up circuit 42 configured to pull-up drive the third logic signal CS2B in response to the first input signal PIN, a third voltage divider circuit 44 connected between the second pull-up circuit 42 and a second output stage from which the third logic signal CS2B is output, a second pull-down circuit 48 configured to pull-down drive the third logic signal CS2B in response to the third input signal NIN, and a fourth voltage divider circuit 46 connected between the second pull-down circuit 48 and the second output stage.

[0052] The second pull-up circuit 42 may include a first PMOS element and a second PMOS element connected in series. The first PMOS element and the second PMOS element may have a source terminal and a body terminal connected in common, and may have a gate terminal to which a first input signal PIN is applied. The second pull-up circuit 42 may operate within a first voltage range.

[0053] The second pull-down circuit 48 may include a first NMOS element and a second NMOS element connected in series. The first NMOS element and the second NMOS element may have a source terminal and a body terminal connected in common, and may have a gate terminal to which a third input signal NIN is applied. The second pull-down circuit 48 may operate within a second voltage range.

[0054] The third voltage divider circuit 44 may include a third PMOS element and a fourth PMOS element connected in series. Each of the third PMOS element and the fourth PMOS element may have a source terminal and a body terminal connected in common, and may have a gate terminal to which a ground voltage GDND is applied. The third voltage divider circuit 44 may operate in a first voltage range or in a second voltage range based on the logic levels of the first input signal PIN and the third input signal NIN.

[0055] The fourth voltage divider circuit 46 may include a third NMOS element and a fourth NMOS element connected in series. Each of the third NMOS element and the fourth NMOS element may have a source terminal and a body terminal connected in common, and may have a gate terminal to which a ground voltage GNDN is applied. The fourth voltage divider circuit 46 may operate in a first voltage range or in a second voltage range based on the logic levels of the first input signal PIN and the third input signal NIN.

[0056] Figure 4 is a diagram illustrating the operation of the level shift circuit according to the embodiment.

[0057] Figure 4The operation of the first output circuit 30 of the pull-up driving second logic signal CS2 and the operation of the second output circuit 40 of the pull-down driving third logic signal CS2B are shown. In this case, the second logic signal CS2 may have the highest voltage level of the first voltage range, and the third logic signal CS2B may have the lowest voltage level of the second voltage range.

[0058] The operation of the first output circuit 30 is described as follows. The first pull-up circuit 32 may be turned on in response to the second input signal PINB. The first voltage divider circuit 34 may be turned on in response to the ground voltage. In addition, in response to the ground voltage, the first pull-down circuit 38 of the first output circuit 30 may be turned off, and the second voltage divider circuit 36 ​​of the first output circuit 30 may be turned off. In this case, the second voltage divider circuit 36 ​​may prevent the intermediate voltage element from being damaged by the second logic signal CS2 having the highest voltage level of the first voltage range.

[0059] The operation of the second output circuit 40 is described as follows. The second pull-up circuit 42 can be turned off in response to the first input signal PIN. The third voltage divider circuit 44 can be turned off in response to the ground voltage. In addition, in response to the ground voltage, the second pull-down circuit 48 of the second output circuit 40 can be turned on, and the fourth voltage divider circuit 46 of the second output circuit 40 can be turned on. In this case, the third voltage divider circuit 44 can prevent the intermediate voltage element from being damaged due to the third logic signal CS2B having the lowest voltage level of the second voltage range.

[0060] like Figures 1 to 4 In the embodiment shown in , the first voltage range is shown as 8V to 0V, the second voltage range is shown as 0V to -8V, and the third voltage range is shown as 8V to -8V, but the present disclosure is not limited thereto.

[0061] As described above, since a circuit capable of processing a signal having a high voltage range can be configured using only intermediate voltage elements operating in the intermediate voltage range, embodiments can reduce chip size. In addition, since a high voltage mask layer can be omitted in the process, embodiments can reduce production costs.

Claims

1. Source driver, including: a level shift circuit configured to output a second logic signal and a third logic signal by shifting a level of the first logic signal; as well as a multiplexer configured to transmit the first source signal or the second source signal to the first pad or the second pad in response to the second logic signal and the third logic signal; Wherein, the level shift circuit comprises: a first level shifter configured to output a first input signal and a second input signal by shifting a level of the first logic signal; a second level shifter configured to output a third input signal and a fourth input signal by shifting a level of the first logic signal; and an output circuit configured to output the second logic signal in response to the second input signal and the fourth input signal, and to output the third logic signal in response to the first input signal and the third input signal, Wherein, the output circuit comprises: a first output circuit configured to output the second logic signal through a pull-up operation or a pull-down operation based on logic levels of the second input signal and the fourth input signal; and a second output circuit configured to output the third logic signal through a pull-up operation or a pull-down operation based on the logic levels of the first input signal and the third input signal, Wherein, the first output circuit comprises: a first pull-up circuit configured to pull-up drive the second logic signal in response to the second input signal; a first voltage divider circuit connected between the first pull-up circuit and a first output stage, the second logic signal being output from the first output stage; a first pull-down circuit configured to pull-down drive the second logic signal in response to the fourth input signal; and The second voltage divider circuit is connected between the first pull-down circuit and the first output stage.

2. The source driver according to claim 1, wherein: The output circuit outputs the second logic signal and the third logic signal by using a pull-up element operating within a first voltage range and a pull-down element operating within a second voltage range, the second logic signal and the third logic signal each having a third voltage range including the first voltage range and the second voltage range, the first voltage range being a swing range of the first source signal, and the second voltage range being a swing range of the second source signal.

3. The source driver according to claim 2, wherein: the first level shifter operates within the first voltage range, the second level shifter operates within the second voltage range, and The output circuit operates within the third voltage range.

4. The source driver according to claim 1, wherein: The second output circuit comprises: a second pull-up circuit configured to pull-up drive the third logic signal in response to the first input signal; a third voltage divider circuit connected between the second pull-up circuit and the second output stage, the third logic signal being output from the second output stage; a second pull-down circuit configured to pull-down drive the third logic signal in response to the third input signal; and A fourth voltage divider circuit is connected between the second pull-down circuit and the second output stage.

5. The source driver according to claim 1, further comprising: a first clamping circuit coupled between the multiplexer and the first pad and configured to clamp a first output signal output to the first pad to a first voltage range or a second voltage range; as well as The second clamping circuit is coupled between the multiplexer and the second pad and is configured to clamp a second output signal output to the second pad to the first voltage range or the second voltage range.

6. Level shift circuit, including: a first level shifter configured to output a first input signal and a second input signal by shifting a level of a first logic signal; a second level shifter configured to output a third input signal and a fourth input signal by shifting the level of the first logic signal; as well as an output circuit configured to output a second logic signal in response to the second input signal and the fourth input signal, and to output a third logic signal in response to the first input signal and the third input signal, Wherein, the output circuit comprises: a first output circuit configured to output the second logic signal; and a second output circuit configured to output the third logic signal, Wherein, the first output circuit comprises: a first pull-up circuit configured to pull-up drive the second logic signal in response to the second input signal; a first voltage divider circuit connected between the first pull-up circuit and a first output stage, the second logic signal being output from the first output stage; a first pull-down circuit configured to pull-down drive the second logic signal in response to the fourth input signal; and The second voltage divider circuit is connected between the first pull-down circuit and the first output stage.

7. The level shift circuit according to claim 6, wherein: The output circuit outputs the second logic signal and the third logic signal each having a third voltage range including the first voltage range and the second voltage range by using a pull-up element operating in a first voltage range and a pull-down element operating in a second voltage range.

8. The level shift circuit according to claim 7, wherein: the first level shifter operates within the first voltage range, the second level shifter operates within the second voltage range, and The output circuit operates within the third voltage range.

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