Drivers for power distribution switches

Abstract

Embodiments of the present disclosure relate to a driver for a power distribution switch. A circuit for controlling electric power is described herein. According to one embodiment, the circuit includes: a circuit node operably connected to a channel element, the channel element being configured to be switched on and off according to a drive signal applied at the circuit node; a communication interface configured to receive data from an external controller, the external controller being operably connected to the communication interface; and a control circuit configured to generate a drive signal in a first operating mode, depending on parameters of a first parameter set and based on data received via the communication interface, and, in a second operating mode, generating a drive signal depending on parameters of a second parameter set while discarding data received via the communication interface.

Description

Technical Field

[0001] The present disclosure relates to a circuit for driving an electronic switch, particularly for safety-critical applications. Background Art

[0002] Electronic switches are increasingly being used in a variety of applications. For example, the on-board energy supply of a car can be considered as a (power) network for distributing electrical energy to various electrical loads via a plurality of electronic switches. The energy supply network can consist of several subnetworks, which can be coupled via electronic switches. In addition, individual loads (within a subnetwork) can also be supplied via electronic switches. In this regard, electronic switches can serve a variety of purposes. When individual loads or subnetworks are not needed, they can be intentionally turned off in order to avoid high standby currents that may discharge the car battery. In addition, electronic switches can be used instead of conventional fuses to protect wires or entire subnetworks from overcurrents caused by short circuits or other electrical faults.

[0003] In many applications, shutting down electrical loads or subnetworks can be an appropriate emergency measure and a reaction to a detected potentially dangerous fault. However, in applications such as autonomous vehicles or advanced driver assistance systems (ADAS), certain safety-related standards (e.g., ISO 26262) must be adhered to; and these standards require that electrical loads or subnetworks remain functional at least for a certain period of time. In other words, safety-critical electrical loads or subnetworks (e.g., radar sensors, automatic steering systems, etc.) must be permanently supplied with electrical energy even in the event of a failure of one or more components. In other words, a "fail-operable" system design is a design goal for the on-board energy supply network.

[0004] Electronic switches consist of transistors (e.g., MOS field effect transistors, insulated gate bipolar transistors, etc.) and corresponding control circuits. In this context, transistors do not have to be used as on / off switches, but depending on the specific function of the control circuit, they can also be used as current regulators, voltage regulators, electronic fuses, etc. Power transistors and corresponding control circuits can be integrated in the same semiconductor die or can be integrated in separate semiconductor dies.

[0005] Electronic switches, and in particular their control circuits, typically receive input signals from a superior controller (such as a microcontroller or the like), which may execute specialized software (firmware). The communication between the control circuit of the electronic switch and the superior controller may be a single point of failure. As described above, single point failures may not be desirable in a system design intended to maintain functionality (i.e., fail-operation) in the event of failure of one or more components. Typically, single point failures are avoided using redundancy, which increases cost and reduces electrical efficiency. Therefore, there is a need to improve currently known electronic switches, and in particular their control circuits. Summary of the invention

[0006] A circuit for controlling electrical power is described herein. According to one embodiment, the circuit includes: a circuit node operably connected to a channel element, the channel element being configured to be switched on and off according to a drive signal applied at the circuit node; a communication interface configured to receive data from an external controller, the external controller being operably connected to the communication interface; and a control circuit configured to generate the drive signal in a first operating mode depending on parameters of a first parameter set and based on data received via the communication interface, and in a second operating mode depending on parameters of a second parameter set while discarding the parameters received via the communication interface.

[0007] In addition, a method for operating a semiconductor device is described herein. According to one embodiment, the method includes: using a communication interface of the semiconductor device and receiving data from an external controller operably connected to the semiconductor device; using a control circuit of the semiconductor device and in a first operating mode, depending on parameters of a first parameter set and based on the data received via the communication interface, generating a drive signal for a channel element; the channel element is included in the semiconductor device or coupled to the semiconductor device; and using the control circuit and in a second operating mode, depending on parameters of a second parameter set, generating the drive signal while discarding the data received via the communication interface. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The present invention may be better understood with reference to the following drawings and description. The components in the drawings are not necessarily drawn to scale; instead, emphasis is placed on illustrating the principles of the present invention. Additionally, in the drawings, like reference numerals designate corresponding parts. In the drawings:

[0009] Figure 1 A first example of an electronic switch consisting of a power transistor and a control circuit is shown, wherein the control circuit can communicate with a higher-level controller.

[0010] Figure 2-Figure 4 A further embodiment of an electronic switch consisting of a power transistor and a control circuit is shown, which can be regarded as Figure 1Modifications / enhancements of the examples.

[0011] Figure 5 is a flow chart illustrating one embodiment of a method performed by an electronic switch. DETAILED DESCRIPTION

[0012] Figure 1 shows that the power transistor T L A first example of an electronic switch 1 consisting of a power transistor and a control circuit 10, wherein the control circuit 10 is coupled to a communication interface (I / F) 13 for communicating with a superior controller 2. In the example described, the power transistor T L , control circuit 10 and communication interface 13 are integrated in a single semiconductor die, which is generally referred to as an "intelligent switch" or "intelligent semiconductor switch". However, it should be understood that in some embodiments, the power transistor T L The and control circuit 10 is implemented in a separate semiconductor die included in a separate chip package.

[0013] Furthermore, in the described example, the power transistor T L is operated as a high-side switch. That is, the power transistor TL is coupled to provide a positive supply voltage V S It should be understood that in some embodiments, the power transistor T L can be operated as a low-side switch. In this case, the power transistor T L is coupled to provide a reference voltage V GND Between a circuit node (e.g., a ground node at ground potential) and an electrical load to be powered. The examples and concepts described herein are not limited to transistors in a high-side configuration and can also be easily applied to low-side transistors. In addition, note that the power transistor T L does not have to be used as an on / off switch. In some embodiments, the power transistor can also be used for load current regulation or output voltage regulation. Figure 1 It is not explicitly shown, but a corresponding regulator circuit may be included in the control circuit 10. In this specification, transistors are generally referred to as controllable channel elements, regardless of their application being switches, current or voltage regulators, electronic fuses, etc.

[0014] according to Figure 1 , the control circuit 10 is configured to provide for the power transistor T L The driving signal V G In an embodiment where the power transistor is implemented as a MOS transistor, the drive signal V G is the gate voltage. The gate voltage V applied to the gate of the power transistor GControls the conduction state of the power transistor. In this example, the drive signal V is provided by the gate driver 12 included in the control circuit 10. G Note that the implementation and functionality of the gate driver is well known and therefore will not be discussed further here.

[0015] In this example, the gate driver 12 is controlled by the control signal V ON Generate drive signal V G , control signal V ON It can be a binary signal and is provided by a logic circuit 11, which is also included in the control circuit 10. Note that in the power transistor T L Basically configured for on / off switching applications, the control signal V ON It can be a binary signal. In other applications where the transistor can be used for current regulation or voltage regulation, the control signal V ON It can be a continuous signal over a limited voltage (or current) range. In this case, a more complex regulator circuit will be required to replace the logic circuit 11. In some applications, the control signal V ON It may be a modulated signal, such as a PWM (Pulse Width Modulation) signal.

[0016] exist Figure 1 In this example, the logic circuit 11 is configured to communicate with the upper controller 2 via a communication interface 13, which may also be part of the control circuit. The upper controller 2 may be a microcontroller, which is configured to execute software instructions and whose functions are mainly determined by software (also commonly referred to as firmware). The communication interface 13 may be a digital communication interface (such as a serial peripheral interface (SPI)), which may be typically used in conjunction with a microcontroller. However, any other communication interface (I 2 C interface, local interconnect bus, parallel interface, etc.) are also applicable. The control circuit 10, in particular the logic circuit 11, can be configured to receive commands and additional data from the microcontroller 2 via the communication interface, and generate a control signal V for the gate driver 12 based on and in response to one or more specific commands and (optionally) additional data received via the communication interface. ON In a simple embodiment, the commands received from the microcontroller may be on and off commands (ON / OFF), which cause the control logic 11 to generate a signal suitable for turning on or off the transistor T L The control signal V ON .

[0017] When the control signal V ON When the logic circuit 11 receives a switch-on command via the communication interface, it may generate a corresponding control signal VON However, the control signal V ON It may further depend on one or more parameters of the parameter set mentioned, wherein the parameter set may include parameters such as an overvoltage threshold, an undervoltage threshold, an overcurrent threshold, an overtemperature threshold, a parameter representing a desired conversion rate, etc. For example, these parameters may be set by the microcontroller 2. That is, the control circuit receives data representing these parameters via the communication interface and stores the received parameters in a (e.g., non-volatile) memory. The parameter set used (see Figure 1 , the parameter set PAR1, PAR2) may depend on the current operating mode, which will be further explained below.

[0018] As described above, the control circuit 10 generates the control logic for the power transistor T based on and in response to the commands and data received from the microcontroller 2. L The driving signal V G , the functionality of the microcontroller 2 depends on software. Obviously, the software-controlled communication between the microcontroller 2 and the control circuit 10 is safety critical. As mentioned above, the entire system should be designed to maintain functionality even if one or more components fail. Complex, software-controlled subsystems (such as, microcontroller 2) are considered to be potentially error-prone, so if the microcontroller 2 fails or exhibits some unexpected / erroneous behavior, safety measures need to be taken.

[0019] One known safety measure is to use a so-called watchdog circuit which is configured to continuously test whether another monitored circuit is still functioning. Figure 1 In the example of FIG. 1 , the watchdog circuit 3 is configured to continuously monitor the microcontroller by testing whether the microcontroller 2 is operational and to issue a signal if this is not the case. For example, the watchdog 3 may send a test signal to the microcontroller 2 and wait for a specific response signal from the microcontroller 2. In the event that the watchdog 3 does not receive a correct response signal from the microcontroller, an alarm signal V is generated. SAM , alarm signal V SAM A fault signal is issued to the microcontroller 2. The implementation, function and use of the watchdog circuit are well known and therefore will not be described further here. Figure 1 In the example of FIG. 1 , the watchdog circuit 3 may be a dedicated integrated circuit (in its own chip package) separate from the microcontroller 2 and the electronic switch 1. In another embodiment, the watchdog circuit 3 may be integrated in the same semiconductor die as the control circuit 10. In some embodiments, two watchdog circuits may be used to provide some redundancy; the external watchdog circuit 3 and the additional watchdog circuit may be integrated in the same semiconductor die as the control circuit 10 (see FIG. 1 ). Figure 3 , watchdog circuit 15).

[0020] As described above, the control circuit 10 can be configured to operate in two or more different operation modes, wherein in the first mode (referred to as the normal mode), when the control signal V is generated ON and the corresponding drive signal V G When the control signal V is generated, the first parameter set PAR1 is used. As described above, the first parameter set PAR1 may include ON One or more parameters (such as an over-current threshold, an over-temperature threshold, etc.) that are considered (i.e., processed) when the control signal V is set, thereby potentially (i.e., in certain circumstances) affecting the control signal V ON In normal mode, the electronic switch (particularly the control circuit 10) responds to data received via the communication interface 13. That is, the drive signal V G The generation of may depend on the received data, and the drive signal may include a control command (STATUS) for controlling the state of the electronic switch.

[0021] In the embodiments described herein, the control circuit 10 can also operate in a second operating mode, which is hereinafter referred to as SAM (Safe Availability Mode). In the second operating mode (i.e., under SAM), the control circuit uses a second parameter set PAR2, which includes parameter values ​​different from the first parameter set PAR1 used in the normal mode. It should be noted that the parameter sets PAR1 and PAR2 are not necessarily different in all parameter values. However, one or more parameters of the parameter set PAR2 have different values ​​from the corresponding parameters in the first parameter set PAR1. The two parameter sets can be stored in a (e.g., non-volatile) memory included in the control circuit 10.

[0022] When operating in the second operating mode, any data received via the communication interface 13 is discarded (e.g., ignored or blocked) by the communication interface. As will be explained further below, the second operating mode (SAM) is essentially only active when the superordinate controller 2 fails or exhibits some abnormal / unexpected behavior. In order to maintain functionality at least for a period of time, it is important for some applications that the normal operation of the electronic switch is not jeopardized by erroneous data received via the communication interface 13 in the event that the microcontroller 2 exhibits unpredictable behavior. When (based on the modified parameters, due to the use of the second parameter set PAR2) the transistor T is maintained LIn the second operating mode, discarding / ignoring received data can help improve the functional safety of the entire system (i.e., maintaining operation despite failure of one or more components). In one embodiment, for example, reception of data can be blocked in the communication interface by setting a lock bit, which, when set, prevents registers storing received data from being modified.

[0023] The transition to the second mode may be triggered by the detection of one or more conditions. The semiconductor chip including the control circuit 10 may have a dedicated chip pin, which is also marked as SAM in the drawings and is also referred to as a SAM pin. The transition may be triggered when a specific signal level (e.g., a high level) of a mode switching signal received at the SAM pin is detected (a first condition). In the example described herein, the alarm signal V generated by the watchdog circuit 3 in response to detecting that the microcontroller is unresponsive is SAM is supplied to the SAM pin, where the signal V SAM A high level of may indicate an unresponsive microcontroller. Therefore, the transition to the second mode (SAM) is initiated by the watchdog circuit 3 generating a signal V SAM The trigger signal V SAM Has a signal level that indicates the microcontroller is not responding.

[0024] In addition, the communication interface 13 can trigger a conversion to the second mode (SAM) when it is detected that the data received from the microcontroller 2 is damaged (second condition), and send a signal to the control circuit 10 that the damaged data is detected. For example, the data word or data frame sent by the microcontroller may include redundant data, which allows the detection of erroneous data. Such redundant data can be, for example, parity bits, bits generated by a cyclic redundancy check (CRC), etc. In addition or alternatively, the control circuit 10 can detect abnormal or unexpected behavior of the microcontroller based on the content of the received data (although the data transmission may be error-free). In this case, the received data may also be classified as damaged. For example, if the received data is meaningless and therefore cannot be processed by the control circuit 10, the received data can be classified as damaged, with the result that the conversion to the second mode (SAM) is triggered. Note that a single occurrence of damaged data does not usually result in a conversion to the second mode. However, if the control circuit (via the communication interface 13) repeatedly (e.g., for a specific time interval) receives damaged data, the conversion to the second mode can be triggered.

[0025] Optionally, the semiconductor chip comprising the control circuit 10 may also comprise an additional (internal) watchdog circuit for monitoring the microcontroller 2. When the microcontroller 3 is unresponsive (third condition), the internal watchdog may send a signal to the control circuit 10, and the control circuit 10 may trigger a transition to the second mode in response thereto. The function of the internal watchdog will be described below with reference to Figure 3 Further explanation: Note that satisfying only one of the above conditions is sufficient to trigger the transition to the second mode (SAM).

[0026] In some embodiments, the control circuit 10 is configured to notify the microcontroller of its operation in the second mode. For example, the control circuit 10 may repeatedly send a status message (e.g., a specific data word or data frame) to the microcontroller via the communication interface 13 indicating that the second mode (SAM) is active. For example, if the microcontroller 2 restarts after a failure, it may receive the status message and respond to it.

[0027] According to some embodiments, when operating in the second mode (SAM), the control circuit 10 may change back to the normal mode when the following two conditions are gradually satisfied: first, receiving data including a mode switching command from the microcontroller 2 via the communication interface 13, and second, the mode switching signal V at the SAM pin SAM has a level indicating a mode switch to normal mode. In order for this to happen, the watchdog circuit 3 must determine that the microcontroller 2 is responsive (again) and generate a signal V with a corresponding signal level (eg low level). SAM Furthermore, the microcontroller 2 must be functional and able to receive the above-mentioned status message (informing the microcontroller that the control circuit 10 is operating in SAM) and send a mode switch command to the control circuit 10 in order to instruct the control circuit to resume operation in normal mode.

[0028] Figure 2-Figure 4 Shown as Figure 1 In most cases, these embodiments are identical, so the focus in the following description is on Figure 2-Figure 4 of the embodiments, not in Figure 1 It should be understood that Figure 2-Figure 4 Additional features shown in can be combined to create further embodiments.

[0029] In some embodiments, the control circuit can be configured to operate in a third operation mode, which is also referred to as a safe state mode. When entering the safe state mode, the control circuit 10 generates a control signal V having a signal level ON, this signal level causes the gate driver 12 to output a signal suitable for turning off the power transistor T L The driving signal V G (gate voltage). That is, the power transistor T L During the transition to the safe state mode, the power transistor T is turned off and remains off during the safe state mode. Generally, a transistor being turned off means that the transistor is in a non-conducting state, while being turned on means that the transistor is in a conducting state. Depending on the application, the "safe state" may also refer to a state in which the power transistor T L In some embodiments, the safe state mode is characterized by bypassing the logic circuit and directly enabling or disabling the gate driver circuit 12 without adjacent (complex and potentially error-prone) logic circuits. Figure 4 As shown, the signal V (received at pin OFF) OFF directly affects transistor T (e.g., by deactivating the output stage of gate driver 12). L gate, and the logic circuit 11 is bypassed.

[0030] Depending on whether different conditions are met, the transition to the safe state mode may be triggered. First, the semiconductor chip including the control circuit 10 may have a dedicated pin (e.g., solder pin, solder ball, etc.) configured to receive a mode switching signal from an external device. Figure 2 In this example, the pin is marked as OFF, and the mode switching signal supplied to the OFF pin is represented as V OFF . Mode switching signal V OFF can be a binary signal, and the mode switching signal V OFF The low level of can cause the control circuit 10 to change to the safe state mode. Figure 2 In the example of FIG. 1 , the mode switching signal V is generated by the system basis chip (SBC) 4. OFF However, the mode switching signal V may be generated by any other suitable external device. OFF Note that in some embodiments, the system basis chip 4 may also include a watchdog circuit 3 .

[0031] Figure 3 A further example is shown, in which the semiconductor chip comprising the control circuit also comprises a further (internal) watchdog circuit 15. The internal watchdog 15 is configured to periodically send data words or data frames with messages to the microcontroller 2 via the communication interface 13, and to receive corresponding response messages from the microcontroller 2. If the watchdog circuit 15 determines that the microcontroller 2 is unresponsive, the control circuit 10 is accordingly notified by appropriate signals, and the control circuit can change to the second mode (SAM) as explained in detail above.

[0032] exist Figure 4 In the example shown, the control circuit 10 includes a timer 14. The timer is used to trigger a change from the second operating mode (SAM) to the third operating mode (safe state). That is, in response to the timer 14 indicating that a predefined time span has passed since entering the second operating mode, the transition to the safe state mode is triggered. In other words, the predefined time span determines the time available to solve the problem that caused the transition to the second mode (SAM). If the problem is not solved within the predefined time span (for example, by restarting the microcontroller and changing back to normal mode), the control mode continues to operate in the safe state mode and turns off the transistor T L .

[0033] As mentioned, the parameter sets PAR1 and PAR2 may be stored in a memory included in the control circuit 10. In some embodiments, the control circuit 10 may include a non-volatile memory and an additional volatile memory, wherein when a specific operating mode is entered, the parameter set used in the current operating mode is loaded from the non-volatile memory into the volatile memory. The control circuit 10 (in particular the logic circuit 11 included therein) may be configured to (e.g., periodically or from time to time) check whether the parameter set stored in the volatile memory is consistent with the corresponding parameter set stored in the non-volatile memory, and when an inconsistency is detected, correct the parameter set stored in the volatile memory. This feature can further improve the robustness of the entire system.

[0034] Figure 5 1 is a flow chart showing an example of a method implemented by the above-mentioned electronic switch. As mentioned, the electronic switch can be constructed to include a control circuit 10, a communication interface 13, a gate driver, and a power transistor T L Alternatively, the circuits forming the semiconductor device are integrated in different semiconductor chips. L The control circuit 10 and the communication interface 13 may be integrated in one semiconductor chip, and the remaining circuits (control circuit 10, communication interface 13, etc.) may be integrated in another semiconductor chip. Figure 5 The method includes receiving data from an external controller using a communication interface of the semiconductor device (eg, also including a control circuit), the external controller being connected to the semiconductor device at least during operation (see Figure 5 , step S1). Further steps depend on the operating mode, wherein at least two operating modes are provided. In a first operating mode (normal mode), the control circuit of the semiconductor device depends on a first parameter set (see Figure 1-4, PAR1) and based on the data received via the communication interface, generates a drive signal for the power transistor. The control circuit of the semiconductor device depends on the parameters of the second parameter set in the second operating mode (SAM) (see Figure 1-4 , PAR2) generates a drive signal for the power transistor while discarding / ignoring data received via the communication interface. Transistor T L Can be included in a semiconductor device (single chip solution, also called smart switch) or coupled to a semiconductor device (transistor integrated in a separate chip). The conditions for mode switching have been referenced above. Figure 1-Figure 4 discussed in detail and therefore will not be repeated here.

[0035] Note that the functionality provided by the electronic switch and in particular by the control circuits described herein may be implemented in a variety of ways. For example, the control circuit 10 (see Figure 1-Figure 4 ) may include a finite state machine for implementing different operating modes. As will be appreciated by those skilled in the art, there are various suitable ways to implement the finite state machine and auxiliary circuit devices used in the control circuit 10, and implementation details are not discussed further herein. Furthermore, it should be understood that those skilled in the art will be able to combine and / or modify the technical features described herein in conjunction with specific embodiments to create further embodiments.

Claims

1. A circuit for controlling electric power, comprising: A circuit node is operably connected to a channel element (T L ), the channel element (T L ) is configured to be driven according to a drive signal (V G ) and is turned on and off; a communication interface (13) configured to receive data from an external controller (2), the external controller (2) being operatively connected to the communication interface; as well as A control circuit (10) comprises a non-volatile memory configured to store a first parameter set and a second parameter set, wherein the control circuit is configured to: In a first operating mode, the drive signal (V G );as well as In the second operating mode, the drive signal (V G ), while discarding data indicating switch-on and switch-off commands received via the communication interface (13), wherein the first parameter set and the second parameter set include one or more of an overvoltage threshold, an undervoltage threshold, an overcurrent threshold, an overtemperature threshold, and a parameter representing a desired conversion rate, and wherein a first parameter of the first parameter set includes a value different from a second parameter in the second parameter set, and the second parameter corresponds to the first parameter.

2. The circuit according to claim 1, The control circuit (10) is configured to change from the first operation mode to the second operation mode in response to at least one of the following: A mode switching signal (V SAM ); The communication interface (13) detects that the received data is damaged.

3. The circuit according to claim 2, The control circuit (10) is configured to change from the second operation mode back to the first operation mode in response to: receiving data via the communication interface (13), the data comprising a mode switching command; and A mode switching signal (V) indicating a mode switch to the first operating mode is detected at the first input pin of the circuit. SAM ).

4. The circuit according to any one of claims 1 to 3, further comprising: A watchdog circuit is configured to monitor the external controller by requesting a response from the external controller (2) and receiving the requested response.

5. The circuit according to claim 4, The control circuit (10) is further configured to: in response to the watchdog circuit signaling that the external controller is unresponsive, change from the first operating mode to the second operating mode.

6. The circuit according to claim 1, The control circuit (10) is configured to communicate with the external controller (2) via the communication interface (13) to switch to the second operation mode.

7. The circuit according to claim 1, further comprising: A timer is configured to measure a time that the circuit operates in the second operation mode.

8. The circuit according to claim 7, wherein the control circuit (10) is configured to: in response to the timer indicating that a predefined time span has elapsed since entering the second operating mode, change from the second operating mode to a third operating mode, and The control circuit (10) is further configured to: when changing to the third operation mode, generate a signal having a function suitable for switching the channel element (T L ) is switched to a non-conducting state. G ).

9. The circuit according to claim 8, wherein the control circuit (10) is configured to: change from the second operation mode to the third operation mode in response to receiving a further mode switching signal from an external device indicating a mode switch to the third operation mode; The control circuit (10) is further configured to: when changing to the third operation mode, generate a signal suitable for shutting down the channel element (T L ) of the driving signal level (V G ).

10. The circuit according to claim 9, Wherein the further mode switch signal is received at a second input pin of the circuit.

11. The circuit according to claim 1, The control circuit comprises a non-volatile memory, wherein the first parameter set (PAR1) and the second parameter set (PAR2) are stored in the non-volatile memory.

12. The circuit according to claim 11, wherein the control circuit (10) comprises a volatile memory, the volatile memory comprising a currently used parameter set, and The control circuit (10) is configured to check whether the parameter set stored in the volatile memory is consistent with the corresponding parameter set stored in the non-volatile memory, and when inconsistency is detected, correct the parameter set stored in the volatile memory.

13. A method for controlling electrical power, comprising: using a communication interface of a semiconductor device and receiving data from an external controller (2) operatively connected to the semiconductor device; as well as Using the control circuit (10) of the semiconductor device and in a first operating mode, a control circuit for a channel element (T) is generated depending on the parameters of a first parameter set (PAR1) and based on data indicating switch-on and switch-off commands received via the communication interface (13). L ) driving signal (V G ); the channel element (T L ) is included in or coupled to the semiconductor device; as well as The drive signal (V) is generated by the control circuit (10) in a second operating mode depending on the parameters of a second parameter set (PAR2). G ), while discarding data indicating switch-on and switch-off commands received via the communication interface (13), wherein the first parameter set and the second parameter set include one or more of an overvoltage threshold, an undervoltage threshold, an overcurrent threshold, an overtemperature threshold, and a parameter representing a desired conversion rate, and wherein a first parameter of the first parameter set includes a value different from a second parameter in the second parameter set, and the second parameter corresponds to the first parameter.

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