Display device

Abstract

A display device is provided. The display device includes: a substrate; and a plurality of sub-pixels arranged on the substrate and including a light-emitting element and a sub-pixel circuit that drives the light-emitting element. The sub-pixel circuit includes: a drive transistor that controls a drive current flowing through the light-emitting element; a first transistor and a second transistor that are connected in series between a first node that serves as a drain electrode of the drive transistor and a second node that serves as a gate electrode of the drive transistor; and a gate auxiliary electrode that is arranged on the gate electrode of the first transistor or the gate electrode of the second transistor. The gate auxiliary electrode is connected to the gate electrode of the first transistor or the gate electrode of the second transistor.

Description

Technical Field

[0001] The present disclosure relates to a display device, and more particularly, to a display device in which an electric field is formed at a floating source / drain node of a dual transistor disposed between a drain electrode and a gate electrode of a driving transistor. Background Art

[0002] Since the beginning of the information age, the demand for display devices for displaying images has been steadily increasing in various forms. Display devices are integrated into various electronic devices such as smartphones, digital cameras, laptops, navigation systems, and smart TVs. The display device can be a flat panel display device such as a liquid crystal display device, a field emission display device, or a light-emitting display device. Because the light-emitting display device among flat panel display devices includes a light-emitting element in which each pixel in the display panel emits light, it can display images without a backlight unit that provides light to the display panel.

[0003] Each pixel in a display panel may include multiple thin-film transistors. Each of the multiple thin-film transistors can be turned on based on a signal applied to a gate electrode. However, when the thin-film transistor switches from an on state to an off state, leakage current may flow through the electric field between the channel region and the source / drain region of the thin-film transistor, and this leakage current may degrade the brightness of the pixel. Therefore, a novel display device for reducing leakage current flowing through the thin-film transistor is needed to prevent degradation of the brightness of the pixel. Summary of the Invention

[0004] Aspects of the present disclosure provide a display device in which an electric field is formed at a floating source / drain node of a dual transistor disposed between a drain electrode and a gate electrode of a driving transistor, thereby reducing leakage current flowing through the dual transistor and preventing a decrease in luminance of a subpixel.

[0005] However, aspects of the present disclosure are not limited to the aspects set forth herein. The above and other aspects of the present disclosure will become more apparent to those skilled in the art by referring to the detailed description of the present disclosure given below.

[0006] According to an embodiment of the present disclosure, a display device includes: a substrate; and a plurality of sub-pixels, the plurality of sub-pixels being arranged on the substrate and including a light-emitting element and a sub-pixel circuit for driving the light-emitting element. The sub-pixel circuit includes: a driving transistor that controls a driving current flowing through the light-emitting element; a first transistor and a second transistor that are connected in series and arranged between a first node serving as a drain electrode of the driving transistor and a second node serving as a gate electrode of the driving transistor to receive the same scan signal from the same scan line; and a gate auxiliary electrode that is arranged on the gate electrode of the first transistor or the gate electrode of the second transistor. The gate auxiliary electrode is connected to the gate electrode of the first transistor or the gate electrode of the second transistor.

[0007] The gate auxiliary electrode may overlap with the drain electrode of the first transistor or the source electrode of the second transistor disposed between the active region of the first transistor and the active region of the second transistor in a thickness direction.

[0008] The display device may further include: an active layer disposed on the substrate; and a first gate layer disposed on the active layer. The active region of each of the driving transistor, the first transistor, and the second transistor may be disposed in the active layer. The gate electrode of each of the driving transistor, the first transistor, and the second transistor may be disposed in the first gate layer.

[0009] The display device may further include: a second gate layer disposed on the first gate layer. The gate auxiliary electrode may be disposed in the second gate layer.

[0010] The display device may further include: a gate insulating film that insulates a gate electrode of each of the first transistor and the second transistor from an active region of each of the first transistor and the second transistor; and an interlayer insulating film that is disposed between the first gate layer and the second gate layer and includes at least one contact hole. The gate auxiliary electrode may be connected to the gate electrode of the first transistor or the gate electrode of the second transistor through the at least one contact hole of the interlayer insulating film.

[0011] The first transistor may include a source electrode connected to the first node and a drain electrode connected to the second transistor.The second transistor may include a source electrode connected to the drain electrode of the first transistor and a drain electrode connected to the second node.

[0012] The gate auxiliary electrode may overlap with the drain electrode of the first transistor or the source electrode of the second transistor in a thickness direction.

[0013] The first transistor may further include: a first doped region arranged between an active region of the first transistor and a source electrode of the first transistor, and a second doped region arranged between the active region of the first transistor and a drain electrode of the first transistor. The second transistor may further include: a third doped region arranged between the active region of the second transistor and the source electrode of the second transistor, and a fourth doped region arranged between the active region of the second transistor and the drain electrode of the second transistor.

[0014] A doping concentration of each of the first doping region, the second doping region, the third doping region, and the fourth doping region may be higher than a doping concentration of an active region of the first transistor or an active region of the second transistor.

[0015] A doping concentration of each of the first, second, third, and fourth doping regions may be lower than a doping concentration of each of the source and drain electrodes of the first transistor and the source and drain electrodes of the second transistor.

[0016] The gate auxiliary electrode may overlap the second doping region of the first transistor or the third doping region of the second transistor in a thickness direction.

[0017] The gate auxiliary electrode may overlap at least one of the second doping region and the drain electrode of the first transistor and the third doping region and the source electrode of the second transistor in a thickness direction.

[0018] The sub-pixel circuit may further include a third transistor that selectively supplies the data voltage to a third node that is a source electrode of the driving transistor. The first transistor, the second transistor, and the third transistor may receive the same scan signal.

[0019] According to an embodiment of the present disclosure, a display device includes: a substrate; and a plurality of sub-pixels, the plurality of sub-pixels being arranged on the substrate and including a light-emitting element and a sub-pixel circuit for driving the light-emitting element. The sub-pixel circuit includes: a driving transistor that controls a driving current flowing through the light-emitting element; a first transistor that includes a first electrode connected to a first node serving as a drain electrode of the driving transistor and a second electrode selectively connected to a second node serving as a gate electrode of the driving transistor; a second transistor that includes a first electrode connected to the second electrode of the first transistor and a second electrode connected to the second node; and a gate auxiliary electrode that is arranged on the gate electrode of the first transistor or the gate electrode of the second transistor and overlaps with the second electrode of the first transistor or the first electrode of the second transistor in a thickness direction. The gate auxiliary electrode is connected to the gate electrode of the first transistor or the gate electrode of the second transistor.

[0020] The display device may further include: an active layer disposed on the substrate; and a first gate layer disposed on the active layer. The active region of each of the driving transistor, the first transistor, and the second transistor may be disposed in the active layer. The gate electrode of each of the driving transistor, the first transistor, and the second transistor may be disposed in the first gate layer.

[0021] The display device may further include: a second gate layer disposed on the first gate layer. The gate auxiliary electrode may be disposed in the second gate layer.

[0022] The display device may further include: a gate insulating film that insulates a gate electrode of each of the first transistor and the second transistor from an active region of each of the first transistor and the second transistor; and an interlayer insulating film that is disposed between the first gate layer and the second gate layer and includes at least one contact hole. The gate auxiliary electrode may be connected to the gate electrode of the first transistor or the gate electrode of the second transistor through the at least one contact hole of the interlayer insulating film.

[0023] The first transistor may further include: a first doped region arranged between an active region of the first transistor and a first electrode of the first transistor, and a second doped region arranged between the active region of the first transistor and a second electrode of the first transistor. The second transistor may further include: a third doped region arranged between the active region of the second transistor and the first electrode of the second transistor, and a fourth doped region arranged between the active region of the second transistor and the second electrode of the second transistor.

[0024] The gate auxiliary electrode may overlap the second doping region of the first transistor or the third doping region of the second transistor in a thickness direction.

[0025] The gate auxiliary electrode may overlap at least one of the second doping region and the second electrode of the first transistor and the third doping region and the first electrode of the second transistor in a thickness direction. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The above and other aspects and features of the present disclosure will become more apparent by describing in detail example embodiments thereof with reference to the accompanying drawings, in which:

[0027] Figure 1 is a perspective view of a display device according to an embodiment;

[0028] Figure 2 is an exploded perspective view of a display device according to an embodiment;

[0029] Figure 3 is a plan view of a display panel according to an embodiment;

[0030] Figure 4 is a block diagram illustrating a display panel and a display driver according to an embodiment;

[0031] Figure 5 depicts sub-pixel circuitry for a sub-pixel according to an embodiment;

[0032] Figure 6 is transmitted to Figure 5 : a waveform diagram of a signal of a sub-pixel shown in FIG;

[0033] Figure 7 It is an icon Figure 5 A plan view of an example of a sub-pixel as illustrated in FIG;

[0034] Figure 8 It is along Figure 7 A cross-sectional view taken along line II' in FIG.

[0035] Figure 9 yes Figure 7 An enlarged view of area A1 in FIG;

[0036] Figure 10 It is along Figure 9 A cross-sectional view taken along line II-II';

[0037] Figure 11 It is an icon Figure 5 A plan view of another example of a sub-pixel shown in FIG;

[0038] Figure 12 yes Figure 11 An enlarged view of area A2 in FIG.

[0039] Figure 13 It is along Figure 12 A cross-sectional view taken along line III-III';

[0040] Figure 14 It is an icon Figure 5 A plan view of another example of a sub-pixel shown in FIG;

[0041] Figure 15 yes Figure 14 an enlarged view of area A3 in FIG; and

[0042] Figure 16 It is along Figure 15 A cross-sectional view taken along line IV-IV'. DETAILED DESCRIPTION

[0043] In the following description, for the purpose of explanation, several specific details are set forth in order to provide a thorough understanding of the various example embodiments or implementations of the present disclosure. As used herein, "embodiment" and "implementation" are interchangeable terms that are non-limiting examples of one or more devices or methods employing the inventive concepts disclosed herein. However, it is apparent that various example embodiments may be practiced without these specific details or with one or more equivalent arrangements. In other cases, well-known structures and devices are shown in block diagram form in order to avoid unnecessarily obscuring the various example embodiments. Further, the various example embodiments may be different, but need not be exclusive. For example, the specific shape, configuration, and characteristics of the example embodiment may be used or implemented in another example embodiment without departing from the inventive concept.

[0044] Unless otherwise specified, the illustrated example embodiments are to be understood as providing example features of varying details of some of the ways in which the inventive concept may be actually implemented. Therefore, unless otherwise specified, the features, components, modules, layers, films, panels, regions and / or aspects of the various embodiments (hereinafter, individually or collectively referred to as "elements") may be further combined, separated, interchanged and / or rearranged.

[0045] The use of cross hatching and / or shading in the drawings is generally provided to clarify the boundaries between adjacent elements. Therefore, the presence or absence of cross hatching or shading does not convey or indicate any preference or requirement for specific materials, material properties, dimensions, proportions, commonalities between the illustrated elements and / or any other characteristics, properties, attributes, etc. of the elements, unless so specified. Further, in the drawings, the size and relative sizes of the elements may be exaggerated for clarity and / or descriptive purposes. When the example embodiments can be implemented differently, a specific process sequence can be performed differently from the described sequence. For example, two processes described in succession can be performed substantially simultaneously or in an order opposite to the described sequence. In addition, the same reference numerals represent the same elements.

[0046] When an element such as a layer is referred to as being "on", "connected" or "coupled" to another element or layer, it can be directly on the other element or layer or directly connected or directly coupled to the other element or layer, or there can be an intermediate element or layer. However, when an element or layer is referred to as being "directly" "on", "directly connected to" or "directly coupled to" another element or layer, there is no intermediate element or layer. For this reason, the term "connected" can refer to a physical connection, electrical connection and / or fluid connection with or without an intermediate element. Further, the X-axis, Y-axis and Z-axis are not limited to the three axes of a rectangular coordinate system (such as an x-axis, a y-axis and a z-axis) and can be interpreted in a broader sense. For example, the X-axis, Y-axis and Z-axis can be perpendicular to each other, or can represent different directions that are not perpendicular to each other. For the purposes of this disclosure, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" may be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z, such as, for example, XYZ, XYY, YZ, and ZZ. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0047] Although the terms "first," "second," etc., may be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. Thus, the first element discussed below may be referred to as the second element without departing from the teachings of the present disclosure.

[0048] Spatially relative terms such as "below," "beneath," "under," "above," "upper," "higher," "side" (e.g., in "sidewall"), etc. may be used herein for descriptive purposes, and thereby, to describe the relationship of one element to another element as illustrated in the accompanying drawings. Spatially relative terms are intended to encompass different orientations of the device in use, operation, and / or manufacture in addition to the orientation depicted in the accompanying drawings. For example, if the device in the drawings is turned over, an element described as "below" or "beneath" other elements or features would subsequently be oriented "above" the other elements or features. Thus, the example term "below" can include both orientations of above and below. Furthermore, the device may be otherwise oriented (e.g., rotated 90 degrees or in other orientations), and therefore, the spatially relative descriptors used herein are interpreted accordingly.

[0049] The terms used herein are for the purpose of describing specific embodiments and are not intended to be limiting. As used herein, the singular forms "a" and "the" are intended to also include the plural forms, unless the context clearly indicates otherwise. Moreover, when used in the specification, the terms "comprise" and / or "include" specify the presence of the features, integers, steps, operations, elements, parts and / or groups thereof, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups thereof. It should also be noted that, as used herein, the terms "substantially", "approximately" and other similar terms are used as approximate terms and not as terms of degree, and therefore, are utilized to take into account the inherent deviations in the values ​​measured, calculated and / or provided that will be recognized by those of ordinary skill in the art.

[0050] Various example embodiments are described herein with reference to cross-sections and / or exploded views that are schematic illustrations of idealized example embodiments and / or intermediate structures. Thus, variations from the illustrated shapes as a result of, for example, manufacturing techniques and / or tolerances are contemplated. Therefore, the example embodiments disclosed herein should not be construed as limited to the specific illustrated shapes of regions, but rather are intended to include deviations in shapes that result, for example, from manufacturing. In this manner, the regions illustrated in the accompanying drawings may be schematic in nature, and the shapes of these regions may not reflect the actual shapes of regions of the device and, therefore, are not necessarily intended to be limiting.

[0051] According to the convention of the art, some example embodiments are described and illustrated in the accompanying drawings according to functional blocks, units and / or modules. It will be appreciated by those skilled in the art that these blocks, units and / or modules are physically implemented by electronic (or optical) circuits, such as logic circuits, discrete components, microprocessors, hard-wired circuits, memory elements, wiring connections, etc. that can be formed using semiconductor-based manufacturing technology or other manufacturing technologies. In the case where blocks, units and / or modules are implemented by microprocessors or other similar hardware, software (e.g., microcode) can be used to program and control them to perform the various functions discussed herein, and they can be optionally driven by firmware and / or software. It is also contemplated that each block, unit and / or module can be implemented by dedicated hardware, or as a combination of dedicated hardware that performs some functions and a processor (e.g., one or more programmed microprocessors and associated circuits) that performs other functions. In addition, each block, unit and / or module of some example embodiments can be physically separated into two or more interacting and discrete blocks, units and / or modules without departing from the scope of the present invention. Further, the blocks, units and / or modules of some example embodiments may be physically combined into more complex blocks, units and / or modules without departing from the scope of the inventive concept.

[0052] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure is a part. Terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and should not be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0053] Figure 1 is a perspective view of a display device according to an embodiment, and Figure 2 is an exploded perspective view of a display device according to an embodiment.

[0054] Reference Figure 1 and Figure 2 , the display device 10 according to the embodiment includes a cover window 100 , a display panel 300 , a bracket 600 , a main circuit board 700 , and a lower cover 900 .

[0055] In this specification, "upper," "above," "top," "upper side," or "upper surface" refers to the upward direction relative to the display device 10, that is, the Z-axis direction, and "lower," "below," "under," "bottom," "lower side," or "lower surface" refers to the downward direction relative to the display device 10, that is, the direction opposite to the Z-axis. Furthermore, "left," "right," "upper," and "lower" refer to directions when the display device 10 is viewed from a plane. For example, "left" refers to the direction opposite to the X-axis direction, "right" refers to the X-axis direction, "upper" refers to the Z-axis direction, and "lower" refers to the direction opposite to the Z-axis direction.

[0056] The display device 10, which is a device for displaying moving images or still images, can be used as a display screen for various products such as televisions, laptop computers, monitors, billboards, the Internet of Things (IoT), and portable electronic devices such as mobile phones, smartphones, tablet personal computers (tablet PCs), smart watches, watch phones, mobile communication terminals, electronic notebooks, electronic books, portable multimedia players (PMPs), navigation systems, and ultra-mobile PCs (UMPCs).

[0057] The display device 10 may be formed in a rectangular shape when viewed in a plan view. Figure 1 and Figure 2As shown in , the display device 10 may have a rectangular planar shape having a short side in a first direction (X-axis direction) and a long side in a second direction (Y-axis direction). The corner where the short side in the first direction (X-axis direction) intersects the long side in the second direction (Y-axis direction) may be formed to have a right angle shape or a circular shape with a predetermined curvature. The planar shape of the display device 10 is not limited to a rectangular shape, and may be formed in another polygonal shape, a circular shape, or an elliptical shape.

[0058] The cover window 100 may be disposed on the display panel 300 to cover an upper surface of the display panel 300. The cover window 100 may protect the upper surface of the display panel 300.

[0059] The cover window 100 may include a first light-transmitting portion DA1 and a second light-transmitting portion DA2 corresponding to the display panel 300 and a light-blocking area LBA corresponding to an area other than the display panel 300. The second light-transmitting portion DA2 may be disposed on one side of the first light-transmitting portion DA1 (eg, as shown in FIG. 2 ). Figure 1 and Figure 2 As shown in FIG, at the upper side of the first light-transmitting portion DA1. The light-shielding area LBA may be formed to be opaque. Alternatively, the light-shielding area LBA may be formed as a decorative layer having a pattern visible to the user when no image is displayed.

[0060] The display panel 300 may be disposed under the cover window 100 . Therefore, an image of the display panel 300 may be viewed from the upper surface of the display device 10 through the cover window 100 .

[0061] The display panel 300 may be a light-emitting display panel including a light-emitting element. Examples of the display panel 300 may include an organic light-emitting display panel using an organic light-emitting diode including an organic light-emitting layer, an ultra-fine light-emitting diode display panel using an ultra-fine light-emitting diode (ultra-fine LED), a quantum dot light-emitting diode display panel using a quantum dot light-emitting diode including a quantum dot light-emitting layer, and an inorganic light-emitting display panel using an inorganic light-emitting diode including an inorganic semiconductor. Hereinafter, it is assumed that the display panel 300 is an organic light-emitting display panel.

[0062] The display panel 300 may include a main area MA and a second non-display area PA protruding from one side of the main area MA.

[0063] The main area MA may include a first display area MDA, a second display area SDA, and a first non-display area NDA.

[0064] The first display area MDA may be arranged to overlap the first light-transmitting portion DA1 of the cover window 100. The second display area SDA may be arranged to overlap the second light-transmitting portion DA2 of the cover window 100. The second display area SDA may be arranged on one side of the first display area MDA (eg, as shown in FIG. 1 ). Figure 2 As shown in FIG, the upper side of the first display area MDA is located at the top of the first display area MDA, but the present disclosure is not limited thereto. As another example, the second display area SDA may be arranged to be surrounded by the first display area MDA and may be arranged adjacent to a corner of the display panel 300. Figure 2 3. The display panel 300 is shown to include one second display area SDA, but the present disclosure is not limited thereto. For example, the display panel 300 may include a plurality of second display areas SDA.

[0065] Each of the first display area MDA and the second display area SDA may include a plurality of pixels, scan lines, data lines, and power lines. Each of the plurality of pixels includes a plurality of sub-pixels. The plurality of sub-pixels are connected to the scan lines, data lines, and power lines.

[0066] The first non-display area NDA may be defined as an edge area of ​​the display panel 300. The first non-display area NDA may include a scan driver for applying a scan signal to the scan line and a link line connecting the data line to the display driver 310.

[0067] The second non-display area PA may protrude from one side of the main area MA. Figure 2 As shown in , the second non-display area PA may protrude from the lower side of the first display area MDA. For example, the length of the second non-display area PA in the first direction (X-axis direction) may be smaller than the length of the main area MA in the first direction (X-axis direction).

[0068] The second non-display area PA may include a bending area and a pad area. In this case, the pad area may be arranged on one side of the bending area, and the main area MA may be arranged on the other side of the bending area. For example, the pad area may be arranged on the lower side of the bending area, and the main area MA may be arranged on the upper side of the bending area.

[0069] The display panel 300 may be flexibly formed to bend, warp, bend, fold, or curl. Thus, the display panel 300 may be bent in a thickness direction (Z-axis direction) in a bending region.

[0070] The display panel 300 may include a display driver 310 , a circuit board 320 , a power supply unit 330 , and a touch driver 340 .

[0071] The display driver 310 may output signals and voltages for driving the display panel 300. For example, the display driver 310 may supply data voltages to data lines. In addition, the display driver 310 may supply power voltages to power lines and may supply scan control signals to a scan driver.

[0072] The circuit board 320 may be attached to the pads using an anisotropic conductive film (ACF). The leads of the circuit board 320 may be electrically connected to the pads of the display panel 300. For example, the circuit board 320 may be a flexible printed circuit board (FPCB), a printed circuit board (PCB), or a flexible film such as a chip on film (COF).

[0073] The power supply unit 330 may be arranged on the circuit board 320 to supply a driving voltage to the display driver 310 and the display panel 300. Specifically, the power supply unit 330 may generate a first driving voltage and supply the first driving voltage to a first driving voltage line, and may generate a second driving voltage and supply the second driving voltage to a second driving voltage line. Further, the power supply unit 330 may generate a third driving voltage and supply the third driving voltage to the cathode electrode of the organic light emitting diode of each of the first sub-pixel and the second sub-pixel. For example, the first driving voltage and the second driving voltage may be high potential voltages for driving a light emitting element (e.g., an organic light emitting diode), and the second driving voltage may be a high potential voltage greater than the first driving voltage. The third driving voltage may be a low potential voltage for driving an organic light emitting diode.

[0074] The touch driver 340 may be arranged on the circuit board 320 to measure the capacitance of the touch electrodes. For example, the touch driver 340 may determine a user's touch and the user's touch location based on changes in the capacitance of the touch electrodes. Here, a user's touch means that an object, such as a user's finger or a pen, directly contacts a surface of the display device 10 arranged on the touch sensing layer. The touch driver 340 may determine the user's touch location by distinguishing between portions of the multiple touch electrodes where the user has touched and portions where the user has not touched.

[0075] The bracket 600 may be disposed below the display panel 300. A first camera hole CMH1 is defined in the bracket 600, into which the first camera sensor 720 is inserted. Also defined in the bracket 600 are a battery hole BH, into which a battery is disposed, a cable hole CAH, through which cables connected to the display driver 310 or the circuit board 320 pass, and a sensor hole SH, into which the sensor devices 740, 750, 760, and 770 are disposed. As another example, instead of including the sensor hole SH, the bracket 600 may be formed so as not to overlap with the second display area SDA of the display panel 300.

[0076] The main circuit board 700 and the battery 790 may be disposed under the bracket 600. The main circuit board 700 may be a printed circuit board or a flexible printed circuit board.

[0077] The main circuit board 700 may include a main processor 710, a first camera sensor 720, a main connector 730, and a plurality of sensor devices 740, 750, 760, and 770. The first camera sensor 720 may be arranged on both the upper and lower surfaces of the main circuit board 700, the main processor 710 may be arranged on the upper surface of the main circuit board 700, and the main connector 730 may be arranged on the lower surface of the main circuit board 700. The plurality of sensor devices 740, 750, 760, and 770 may be arranged on the upper surface of the main circuit board 700.

[0078] The main processor 710 can control all functions of the display device 10. For example, the main processor 710 can output digital video data to the display driver 310 so that the display panel 300 displays an image. Furthermore, the main processor 710 can receive touch data from the touch driver 340, determine the user's touch coordinates, and then execute the application indicated by the icon displayed at the user's touch coordinates.

[0079] The main processor 710 may control the display device 10 based on sensor signals input from the plurality of sensor devices 740, 750, 760, and 770. For example, the main processor 710 may determine whether an object is positioned close to the upper surface of the display device 10 based on the proximity sensor signal input from the proximity sensor 740. When the object is positioned close to the upper surface of the display device 10 in the call mode, the main processor 710 may not execute an application indicated by an icon displayed at the touch coordinates even if a touch is performed by the user.

[0080] The main processor 710 may determine the brightness of the upper surface of the display device 10 according to the illuminance sensor signal input from the illuminance sensor 750. The main processor 710 may adjust the brightness of the image displayed by the display panel 300 according to the brightness of the upper surface of the display device 10.

[0081] The main processor 710 may determine whether the user's iris image is identical to an iris image previously stored in the memory based on the iris sensor signal input from the iris sensor 760. When the user's iris image is identical to the iris image previously stored in the memory, the main processor 710 may unlock the display device 10 and display the home screen on the display panel 300.

[0082] The first camera sensor 720 can process image frames such as still images or moving images obtained by the image sensor and output the processed image frames to the main processor 710. For example, the first camera sensor 720 can be a CMOS image sensor or a CCD sensor, but is not necessarily limited. The first camera sensor 720 can be exposed to the lower surface of the lower cover 900 through the second camera hole CMH2 and can take pictures of objects or backgrounds arranged under the display device 10.

[0083] The cable having passed through the cable hole CAH of the bracket 600 may be connected to the main connector 730. Thus, the main circuit board 700 may be electrically connected to the display driver 310 or the circuit board 320.

[0084] The plurality of sensor devices may include a proximity sensor 740 , an illumination sensor 750 , an iris sensor 760 , and a second camera sensor 770 .

[0085] The proximity sensor 740 can detect whether an object is positioned close to the upper surface of the display device 10. For example, the proximity sensor 740 may include a light source that outputs light and a light receiver that receives light reflected by the object. The proximity sensor 740 can determine whether an object positioned close to the upper surface of the display device 10 exists based on the amount of light reflected by the object. Because the proximity sensor 740 is arranged to overlap with the sensor hole SH, the second display area SDA of the display panel 300, and the second light-transmitting portion DA2 of the cover window 100 in the thickness direction (Z-axis direction) of the display panel 300, the proximity sensor 740 can generate a proximity sensor signal depending on whether an object positioned close to the upper surface of the display device 10 exists, and can output the proximity signal to the main processor 710.

[0086] The illuminance sensor 750 can detect the brightness of the upper surface of the display device. The illuminance sensor 750 may include a resistor whose resistance value changes depending on the brightness of the incident light. The illuminance sensor 750 can determine the brightness of the upper surface of the display device based on the resistance value of the resistor. Because the illuminance sensor 750 is arranged to overlap with the sensor hole SH, the second display area SDA of the display panel 300, and the second light-transmitting portion DA2 of the cover window 100 in the thickness direction (Z-axis direction) of the display panel 300, the illuminance sensor 750 can generate an illuminance sensor signal based on the brightness of the upper surface of the display device and can output the illuminance sensor signal to the main processor 710.

[0087] The iris sensor 760 may detect whether the image of the user's iris is identical to an iris image previously stored in the memory. The iris sensor 760 may generate an iris sensor signal depending on whether the image of the user's iris is identical to an iris image previously stored in the memory, and may output the iris sensor signal to the main processor 710.

[0088] The second camera sensor 770 can process image frames such as still images or moving images obtained by the image sensor and output the processed image frames to the main processor 710. For example, the second camera sensor 770 can be a CMOS image sensor or a CCD sensor, but is not necessarily limited. The number of pixels in the second camera sensor 770 can be smaller than the number of pixels in the first camera sensor 720, and the size of the second camera sensor 770 can be smaller than the size of the first camera sensor 720. Because the second camera sensor 770 is arranged to overlap with the sensor hole SH, the second display area SDA of the display panel 300, and the second light-transmitting portion DA2 of the cover window 100 in the thickness direction (Z-axis direction) of the display panel 300, the second camera sensor 770 can take pictures of objects or backgrounds arranged on the display device 10.

[0089] The battery 790 may be arranged not to overlap with the main circuit board 700 in the third direction (Z-axis direction). That is, the battery 790 is aligned with the battery hole BH of the bracket 600 so that the battery 790 can overlap with the battery hole BH of the bracket 600.

[0090] The main circuit board 700 may include a mobile communication module capable of transmitting and receiving radio signals to and from at least one of a base station, an external terminal, and a server. The radio signals may include various types of data depending on voice signals, voice call signals, or text / multimedia message transmission / reception.

[0091] The lower cover 900 may be disposed under the main circuit board 700 and the battery 790. The lower cover 900 may be fixedly coupled to the bracket 600. The lower cover 900 may form a lower surface appearance of the display device 10. The lower cover 900 may be made of plastic, metal, or a combination of plastic and metal.

[0092] A second camera hole CMH2 through which the lower surface of the first camera sensor 720 is exposed is defined in the lower cover 900. The position of the first camera sensor 720 and the positions of the first camera hole CMH1 and the second camera hole CMH2 corresponding to the first camera sensor 720 are not limited to Figure 2 The embodiment shown in .

[0093] Figure 3is a plan view of a display panel according to an embodiment, and Figure 4 is a block diagram illustrating a display panel and a display driver according to an embodiment.

[0094] Reference Figure 3 and Figure 4 , the display panel 300 may include a first display area MDA, a second display area SDA, and a first non-display area NDA.

[0095] The first display area MDA includes a plurality of first sub-pixels SP1 , a driving voltage line VDDL connected to the plurality of first sub-pixels SP1 , a scan line SL, an emission control line EML, and a data line DL.

[0096] Each of the plurality of first sub-pixels SP1 may be connected to at least one scan line SL, at least one data line DL, at least one emission control line EML, and at least one driving voltage line VDDL. Figure 3 and Figure 4 , each of the plurality of first sub-pixels SP1 may be connected to two scan lines SL, one data line DL, one emission control line EML, and one driving voltage line VDDL, but the present disclosure is not limited thereto. For example, each of the plurality of first sub-pixels SP1 may be connected to three or more scan lines SL.

[0097] Each of the plurality of first sub-pixels SP1 may include a driving transistor, at least one switching transistor, a light emitting element, and a capacitor.

[0098] The first sub-pixels SP1 may receive a driving voltage through a driving voltage line VDDL. Here, the driving voltage may be a high potential voltage for driving the light emitting elements of the plurality of first sub-pixels SP1.

[0099] The scan lines SL and the emission control lines EML may extend in a first direction (X-axis direction) and may be spaced apart from each other in a second direction (Y-axis direction) crossing the first direction (X-axis direction).

[0100] The data line DL and the driving voltage line VDDL may extend in the second direction (Y-axis direction) and may be spaced apart from each other in the first direction (X-axis direction).

[0101] The second display area SDA may include the second sub-pixels SP2 , a driving voltage line VDDL connected to the plurality of second sub-pixels SP2 , a scan line SL, an emission control line EML, and a data line DL.

[0102] Each of the plurality of second sub-pixels SP2 may be connected to at least one scan line SL, at least one data line DL, at least one emission control line EML, and at least one driving voltage line VDDL. Figure 3 and Figure 4 , each of the plurality of second sub-pixels SP2 may be connected to two scan lines SL, one data line DL, one emission control line EML, and one driving voltage line VDDL, but the present disclosure is not limited thereto. For example, each of the second sub-pixels SP2 may be connected to three or more scan lines SL.

[0103] Each of the second sub-pixels SP2 may include a driving transistor, at least one switching transistor, a light emitting element, and a capacitor.

[0104] The second sub-pixel SP2 may receive a driving voltage through a driving voltage line VDDL. Here, the driving voltage may be a high potential voltage for driving the light emitting element of the second sub-pixel SP2.

[0105] For example, the number of first subpixels SP1 per unit area of ​​the first display area MDA can be greater than the number of second subpixels SP2 per unit area of ​​the second display area SDA. The first display area MDA is an area for displaying images, which is the main function of the display device 10, and the first subpixels SP1 can be densely arranged in the first display area MDA. The second display area SDA can include a pixel area in which the second subpixels SP2 are arranged, and a transmissive area that transmits light. Therefore, as the area of ​​the transmissive area of ​​the second display area SDA increases, the number of second subpixels SP2 per unit area can be less than the number of first subpixels SP1 per unit area.

[0106] The first non-display area NDA may be defined as a remaining area of ​​the display panel 300 that is not part of the first display area MDA or the second display area SDA. The first non-display area NDA may include a scan driver 410 for applying scan signals to the scan lines SL, an emission control driver 420 for applying emission signals to the emission control lines EML, fan-out lines FL for connecting the data lines DL and the display driver 310, and pads DP connected to the circuit board 320. The display driver 310 and the pads DP may be arranged in a pad area of ​​the display panel 300. The pads DP may be arranged closer to one edge of the pad area than the display driver 310.

[0107] like Figure 4 As shown in , the display driver 310 may include a timing controller 311 and a data driver 312 .

[0108] The timing controller 311 can receive digital video data DATA and timing signals from the circuit board 320. Based on the timing signals, the timing controller 311 can generate a scan control signal SCS to control the operation timing of the scan driver 410, generate an emission control signal ECS to control the operation timing of the emission control driver 420, and generate a data control signal DCS to control the operation timing of the data driver 312. The timing controller 311 can output the scan control signal SCS to the scan driver 410 via a first scan control line SCL1. The timing controller 311 can output the emission control signal ECS to the emission control driver 420 via a second scan control line SCL2. The timing controller 311 can supply the digital video data DATA and the data control signal DCS to the data driver 312.

[0109] The data driver 312 may convert the digital video data DATA into an analog data voltage and output the analog data voltage to the data line DL through the fan-out line FL. The scan signal of the scan driver 410 may select a pixel SP to which the data voltage is to be supplied, and the data driver 312 may supply the data voltage to the selected pixel SP. As used herein, "pixel SP" is intended to mean the first subpixel SP1 or the second subpixel SP2.

[0110] like Figure 3 As shown in FIG, the scan driver 410 may be arranged on one side of the first display area MDA and outside one side of the second display area SDA, or on one side of the first non-display area NDA. The emission control driver 420 may be arranged on the other side of the first display area MDA and outside the other side of the second display area SDA, or on the other side of the first non-display area NDA. As another example, both the scan driver 410 and the emission control driver 420 may be arranged on one side of the first display area MDA and outside one side of the second display area SDA.

[0111] The scan driver 410 may include a plurality of thin film transistors for generating scan signals based on the scan control signal SCS, and the emission control driver 420 may include a plurality of thin film transistors for generating emission signals based on the emission control signal ECS. For example, the thin film transistors of the scan driver 410 and the thin film transistors of the emission control driver 420 may be formed on the same layer as the thin film transistors of the first sub-pixel SP1 and the thin film transistors of the second sub-pixel SP2, respectively.

[0112] Figure 5 depicts a sub-pixel circuit of a sub-pixel according to an embodiment, and Figure 6 is transmitted to Figure 5 Here, Figure 5 The sub-pixel SP shown in FIG. Figure 3 and Figure 4 It corresponds to the first sub-pixel SP1 or the second sub-pixel SP2 shown in FIG.

[0113] Reference Figure 5 and Figure 6 , the display panel 300 may include a plurality of subpixels SP arranged along the k-th row (k is a natural number) and the j-th column (j is a natural number). For example, the first display area MDA of the display panel 300 may include a first subpixel SP1, and the second display area SDA of the display panel 300 may include a second subpixel SP2. The first subpixel SP1 or the second subpixel SP2 arranged in the k-th row may be connected to the k-th scan line SLk, the k-1-th scan line SLk-1, the emission control line EML, the data line DL, the driving voltage line VDDL, and the initialization voltage line VIL.

[0114] Each of the first and second subpixels SP1 and SP2 may include a driving transistor DT, a light emitting element EL, a plurality of switching elements, and a first capacitor C1. The switching elements may include first to sixth transistors ST1, ST2, ST3, ST4, ST5, and ST6.

[0115] The driving transistor DT may include a gate electrode, a source electrode, and a drain electrode. The drain electrode of the driving transistor DT may be connected to a first node N1, the gate electrode of the driving transistor DT may be connected to a second node N2, and the source electrode of the driving transistor DT may be connected to a third node N3. The driving transistor DT controls a source-drain current Isd (hereinafter, referred to as a "driving current") based on a data voltage (hereinafter, represented as "Vdata") applied to the gate electrode. The driving current Isd flowing through the channel of the driving transistor DT is proportional to the square of the difference between the gate-source voltage Vsg and the threshold voltage Vth of the first transistor T1 (Isd = k' × (Vsg - Vth) 2 ). Here, k′ refers to a proportionality coefficient determined by the structure and physical characteristics of the driving transistor DT, Vsg refers to a source-gate voltage of the driving transistor DT, and Vth refers to a threshold voltage of the driving transistor DT.

[0116] The light emitting element EL may receive the driving current Isd to emit light. The emission amount or brightness of the light emitting element EL may be proportional to the intensity of the driving current Isd.

[0117] The light-emitting element EL may be an organic light-emitting diode including an anode electrode, a cathode electrode, and an organic light-emitting layer disposed between the anode electrode and the cathode electrode. Alternatively, the light-emitting element EL may be an inorganic light-emitting element including an anode electrode, a cathode electrode, and an inorganic semiconductor layer disposed between the anode electrode and the cathode electrode. Alternatively, the light-emitting element EL may be a quantum dot light-emitting element including an anode electrode, a cathode electrode, and a quantum dot light-emitting layer disposed between the anode electrode and the cathode electrode. Alternatively, the light-emitting element EL may be a micro light-emitting diode.

[0118] The anode electrode of the light-emitting element EL may be connected to the fourth node N4. The anode electrode of the light-emitting element EL may be connected to the drain electrode of the fifth transistor ST5 and the drain electrode of the sixth transistor ST6 through the fourth node N4. The cathode electrode of the light-emitting element EL may be connected to the low potential line VSSL. Parasitic capacitance may be formed between the anode electrode and the cathode electrode of the light-emitting element EL.

[0119] The first transistor ST1 can be turned on by a scan signal SCk of a corresponding scan line SLk to connect a first node N1, which is the drain electrode of the drive transistor DT, to a second node N2, which is the gate electrode of the drive transistor DT. For example, the first transistor ST1 can be a dual transistor including a 1st transistor ST1-1 and a 1st-2 transistor ST1-2. The gate electrode of the 1st transistor ST1-1 can be connected to the scan line SLk of the corresponding stage, the source electrode of the 1st transistor ST1-1 can be connected to the first node N1, and the drain electrode of the 1st transistor ST1-1 can be connected to the source electrode of the 1st-2 transistor ST1-2. The gate electrode of the 1st-2 transistor ST1-2 can be connected to the scan line SLk of the corresponding stage, the source electrode of the 1st-2 transistor ST1-2 can be connected to the drain electrode of the 1st transistor ST1-1, and the drain electrode of the 1st-2 transistor ST1-2 can be connected to the second node N2.

[0120] The second transistor ST2 can be turned on by the scan signal SCk-1 of the scan line SLk-1 of the previous stage to connect the initialization voltage line VIL to the second node N2 serving as the gate electrode of the drive transistor DT. For example, the second transistor ST2 can be a dual transistor including a 2-1 transistor ST2-1 and a 2-2 transistor ST2-2. The 2-1 transistor ST2-1 and the 2-2 transistor ST2-2 can be turned on based on the scan signal SCk-1 of the previous stage to discharge the gate electrode of the drive transistor DT with the initialization voltage V1. The gate electrode of the 2-1 transistor ST2-1 can be connected to the scan line SLk-1 of the previous stage, the source electrode of the 2-1 transistor ST2-1 can be connected to the initialization voltage line VIL, and the drain electrode of the 2-1 transistor ST2-1 can be connected to the source electrode of the 2-2 transistor ST2-2. A gate electrode of the 2-2 transistor ST2-2 may be connected to the scan line SLk-1 of the previous stage, a source electrode thereof may be connected to the drain electrode of the 2-1 transistor ST2-1, and a drain electrode thereof may be connected to the second node N2.

[0121] The third transistor ST3 can be turned on by a scan signal SCk of a scan line SLk of a corresponding stage to connect the data line DL to a third node N3, which serves as the source electrode of the drive transistor DT. The third transistor ST3 can be turned on based on the scan signal SCk to supply a data voltage Vdata to the third node N3. A gate electrode of the third transistor ST3 can be connected to the scan line SLk of the corresponding stage, a source electrode of the third transistor ST3 can be connected to the data line DL, and a drain electrode of the third transistor ST3 can be connected to the third node N3. The drain electrode of the third transistor ST3 can be connected to the source electrode of the drive transistor DT and the drain electrode of the fourth transistor ST4 via the third node N3.

[0122] The fourth transistor ST4 can be turned on by an emission signal EM of the emission control line EML to connect the driving voltage line VDDL to the third node N3, which serves as the source electrode of the driving transistor DT. The gate electrode of the fourth transistor ST4 can be connected to the emission control line EML, the source electrode of the fourth transistor ST4 can be connected to the driving voltage line VDDL, and the drain electrode of the fourth transistor ST4 can be connected to the third node N3. The drain electrode of the fourth transistor ST4 can be connected to the source electrode of the driving transistor DT and the drain electrode of the third transistor ST3 via the third node N3.

[0123] The fifth transistor ST5 can be turned on by an emission signal EM of the emission control line EML to connect the first node N1, which serves as the drain electrode of the drive transistor DT, to the fourth node N4, which serves as the anode electrode of the light-emitting element EL. The gate electrode of the fifth transistor ST5 can be connected to the emission control line EML, the source electrode of the fifth transistor ST5 can be connected to the first node N1, and the drain electrode of the fifth transistor ST5 can be connected to the fourth node N4. The source electrode of the fifth transistor ST5 can be connected to the drain electrode of the drive transistor DT and the source electrode of the (1-1) transistor ST1-1 through the first node N1. The drain electrode of the fifth transistor ST5 can be connected to the anode electrode of the light-emitting element EL and the drain electrode of the sixth transistor ST6 through the fourth node N4.

[0124] When all of the fourth transistor ST4 , the driving transistor DT, and the fifth transistor ST5 are turned on, a driving current may be supplied to the light emitting element EL.

[0125] The sixth transistor ST6 can be turned on by a scan signal SCk of the scan line SLk of the corresponding stage to connect the initialization voltage line VIL to the fourth node N4, which is the anode electrode of the light-emitting element EL. The sixth transistor ST6 can be turned on based on the scan signal SCk to discharge the anode electrode of the light-emitting element EL with the initialization voltage V1. The gate electrode of the sixth transistor ST6 can be connected to the scan line SLk of the corresponding stage, the source electrode of the sixth transistor ST6 can be connected to the initialization voltage line VIL, and the drain electrode of the sixth transistor ST6 can be connected to the fourth node N4. The drain electrode of the sixth transistor ST6 can be connected to the anode electrode of the light-emitting element EL and the drain electrode of the fifth transistor ST5 through the fourth node N4.

[0126] Each of the driving transistor DT and the first to sixth transistors ST1, ST2, ST3, ST4, ST5, and ST6 may include a silicon-based active layer. For example, the driving transistor DT and the first to sixth transistors ST1, ST2, ST3, ST4, ST5, and ST6 may include an active layer made of low-temperature polysilicon (LTPS). The active layer made of low-temperature polysilicon may have high electron mobility and excellent conduction characteristics. Thus, the display device 10 can stably and efficiently drive multiple sub-pixels SP by including the driving transistor DT and the first to sixth transistors ST1, ST2, ST3, ST4, ST5, and ST6 having excellent conduction characteristics.

[0127] Each of the driving transistor DT and the first to sixth transistors ST1, ST2, ST3, ST4, ST5, and ST6 may correspond to a p-type transistor. For example, the driving transistor DT and the first to sixth transistors ST1, ST2, ST3, ST4, ST5, and ST6 may output a current flowing into a source electrode to a drain electrode based on a gate low voltage applied to the gate electrode.

[0128] The first capacitor C1 may be connectedly arranged between the second node N2, which is the gate electrode of the driving transistor DT, and the driving voltage line VDDL. For example, a first electrode of the first capacitor C1 may be connected to the second node N2, and a second electrode of the first capacitor C1 may be connected to the driving voltage line VDDL, thereby maintaining a potential difference between the driving voltage line VDDL and the gate electrode of the driving transistor DT.

[0129] Reference Figure 6 Together Figure 5 , the display device 10 can be driven through the first to third periods t1, t2, and t3 of one frame. The second transistor ST2 can receive the low-level scan signal SCk-1 of the previous stage during the first period t1 of the Nth frame (N is a natural number of 2 or greater). The second transistor ST2 can be turned on based on the low-level scan signal SCk-1 and can supply the initialization voltage V1 to the second node N2, which is the gate electrode of the driving transistor DT. Thus, the second transistor ST2 can initialize the gate electrode of the driving transistor DT during the first period t1.

[0130] The first transistor ST1 may receive a low-level scan signal SCk of a corresponding stage during the second period t2. The first transistor ST1 may be turned on based on the low-level scan signal SCk and may connect the first node N1 and the second node N2.

[0131] The third transistor ST3 may receive a low-level scan signal SCk of a corresponding stage during the second period t2 , and may be turned on based on the low-level scan signal SCk and supply the data voltage Vdata to the third node N3 serving as the source electrode of the driving transistor DT.

[0132] When the source electrode of the driving transistor DT receives the data voltage Vdata, the source-gate voltage Vsg of the driving transistor DT may correspond to the voltage difference Vdata-VI between the data voltage Vdata and the initialization voltage V1, and the source-gate voltage Vsg may become greater than a threshold voltage (hereinafter, referred to as "Vth") (Vdata-VI>Vth) to allow the driving transistor DT to be turned on. Thus, at the moment when the driving transistor DT is turned on during the second period t2, the source-drain current Isd of the driving transistor DT may be determined based on the data voltage Vdata, the initialization voltage V1, and the threshold voltage Vth of the driving transistor DT (Isd=k'*(Vdata-VI-Vth) 2 ). The driving transistor DT may supply the source-drain current Isd to the first node N1 until the source-gate voltage Vsg reaches the threshold voltage Vth of the driving transistor DT. Further, the first transistor ST1 may be turned on during the second period t2 to supply the voltage of the first node N1 to the second node N2. In this manner, when the driving transistor DT is turned on, the voltage of the second node N2 and the source-drain current Isd of the driving transistor DT may be changed, and the voltage of the second node N2 may converge to the voltage difference Vdata-Vth between the data voltage Vdata and the threshold voltage Vth of the driving transistor DT.

[0133] The sixth transistor ST6 may receive a low-level scan signal SCk of a corresponding stage during the second period t2. The sixth transistor ST6 may be turned on based on the low-level scan signal SCk and may supply an initialization voltage V1 to the fourth node N4, which is the anode electrode of the light-emitting element EL. Therefore, the sixth transistor ST6 may initialize the anode electrode of the light-emitting element EL during the second period t2.

[0134] The emission signal EM may have a gate low voltage during the third period t3. When the emission signal EM has a low level, the fourth transistor ST4 and the fifth transistor ST5 are turned on to supply a driving current to the light emitting element EL.

[0135] Figure 7 It is an icon Figure 5 A plan view of an example of a sub-pixel illustrated in FIG, and Figure 8 It is along Figure 7 A cross-sectional view taken along line II' in FIG.

[0136] Reference Figure 7 and Figure 8Each of the first subpixel SP1 of the first display area MDA and the second subpixel SP2 of the second display area SDA may include a driving transistor DT, a light emitting element EL, first to sixth transistors ST1, ST2, ST3, ST4, ST5 and ST6, and a first capacitor C1.

[0137] The driving transistor DT may include an active region DT-ACT, a gate electrode DT-G, a source electrode DT-S, and a drain electrode DT-D. The active region DT-ACT of the driving transistor DT may overlap with the gate electrode DT-G of the driving transistor DT disposed in the first gate layer GTL1.

[0138] The gate electrode DT-G of the drive transistor DT may be connected to the first connection electrode BE1 via a first contact hole CNT1, and the first connection electrode BE1 may be connected to the drain electrode D1-2 of the 1-2 transistor ST1-2 and the drain electrode D2-2 of the 2-2 transistor ST2-2 via a sixth contact hole CNT6. Furthermore, a region of the gate electrode DT-G of the drive transistor DT that overlaps with the second gate layer GTL2 may correspond to the first electrode CE11 of the first capacitor C1.

[0139] The source electrode DT-S of the driving transistor DT may be connected to the drain electrode D3 of the third transistor ST3 and the drain electrode D4 of the fourth transistor ST4 .

[0140] The drain electrode DT-D of the driving transistor DT may be connected to the source electrode S1 - 1 of the 1-1th transistor ST1 - 1 and the source electrode S5 of the fifth transistor ST5 .

[0141] The first transistor ST1 may be a dual transistor including a 1-1th transistor ST1 - 1 and a 1-2th transistor ST1 - 2 .

[0142] The 1-1 transistor ST1-1 may include an active region ACT1-1, a gate electrode G1-1, a source electrode S1-1, and a drain electrode D1-1. The active region ACT1-1 of the 1-1 transistor ST1-1 may overlap with the gate electrode G1-1 of the 1-1 transistor ST1-1. The gate electrode G1-1 of the 1-1 transistor ST1-1, which is a portion of the scan line SLk of the corresponding stage, may correspond to a region of the scan line SLk of the corresponding stage that overlaps with the active region ACT1-1.

[0143] The source electrode S1 - 1 of the 1-1th transistor ST1 - 1 may be connected to the drain electrode DT-D of the driving transistor DT and the source electrode S5 of the fifth transistor ST5 .

[0144] The drain electrode D1 - 1 of the 1-1th transistor ST1 - 1 may be connected to the source electrode S1 - 2 of the 1-2th transistor ST1 - 2 .

[0145] The 1-2 transistor ST1-2 may include an active region ACT1-2, a gate electrode G1-2, a source electrode S1-2, and a drain electrode D1-2. The active region ACT1-2 of the 1-2 transistor ST1-2 may overlap with the gate electrode G1-2 of the 1-2 transistor ST1-2. The gate electrode G1-2 of the 1-2 transistor ST1-2, which is a portion of the scan line SLk of the corresponding stage, may correspond to a region of the scan line SLk of the corresponding stage that overlaps with the active region ACT1-2.

[0146] The source electrode S1 - 2 of the 1-2 th transistor ST1 - 2 may be connected to the drain electrode D1 - 1 of the 1-1 th transistor ST1 - 1 .

[0147] The drain electrode D1-2 of the 1-2 transistor ST1-2 may be connected to the first connection electrode BE1 through the sixth contact hole CNT6, and the first connection electrode BE1 may be connected to the gate electrode DT-G of the driving transistor DT through the first contact hole CNT1. Furthermore, the drain electrode D1-2 of the 1-2 transistor ST1-2 may be connected to the drain electrode D2-2 of the 2-2 transistor ST2-2.

[0148] The gate auxiliary electrode GAE may be disposed in the second gate layer GTL2. For example, the gate electrode G1-1 of the 1st transistor ST1-1 and the gate electrode G1-2 of the 1st transistor ST1-2 may be disposed in the first gate layer GTL1, and the second gate layer GTL2 may be disposed on the first gate layer GTL1. The gate auxiliary electrode GAE may be connected to the gate electrode G1-1 of the 1st transistor ST1-1 or the gate electrode G1-2 of the 1st transistor ST1-2. For example, the gate auxiliary electrode GAE may be connected to the gate electrode G1-1 of the 1st transistor ST1-1 through the fifth contact hole CNT5. Thus, when the gate electrode G1-1 of the 1st transistor ST1-1 receives the scan signal SCk of the corresponding stage, the scan signal SCk may be supplied to the gate auxiliary electrode GAE.

[0149] At least a portion of the gate auxiliary electrode GAE may be arranged in the second gate layer GTL2 between the active area ACT1-1 of the 1-1st transistor ST1-1 and the active area ACT1-2 of the 1-2nd transistor ST1-2. The gate auxiliary electrode GAE may overlap with the source electrode or the drain electrode arranged between the active area ACT1-1 of the 1-1st transistor ST1-1 and the active area ACT1-2 of the 1-2nd transistor ST1-2 in the thickness direction (Z-axis direction). For example, when the drain electrode D1-1 of the 1-1st transistor ST1-1 is in direct contact with the source electrode S1-2 of the 1-2nd transistor ST1-2, the gate auxiliary electrode GAE may overlap with at least one of the drain electrode D1-1 of the 1-1st transistor ST1-1 and the source electrode S1-2 of the 1-2nd transistor ST1-2 in the thickness direction (Z-axis direction). Thus, an electric field may be formed between the gate auxiliary electrode GAE and the drain electrode D1 - 1 of the 1-1th transistor ST1 - 1 or between the gate auxiliary electrode GAE and the source electrode S1 - 2 of the 1-2th transistor ST1 - 2 .

[0150] For example, the gate auxiliary electrode GAE may be connected to the gate electrode G1-1 of the 1-1 transistor ST1-1 through the fifth contact hole CNT5 and may overlap with the drain electrode D1-1 of the 1-1 transistor ST1-1 and the source electrode S1-2 of the 1-2 transistor ST1-2 in the thickness direction (Z-axis direction). An electric field formed at a node between the 1-1 transistor ST1-1 and the 1-2 transistor ST1-2 may be affected by the electric field between the gate electrode G1-1 of the 1-1 transistor ST1-1 and the drain electrode D1-1 of the 1-1 transistor ST1-1, the electric field between the gate electrode G1-2 of the 1-2 transistor ST1-2 and the source electrode S1-2 of the 1-2 transistor ST1-2, and the electric field between the gate auxiliary electrode GAE and the drain electrode D1-1 of the 1-1 transistor ST1-1. Here, when the 1-1st transistor ST1 - 1 and the 1-2nd transistor ST1 - 2 are turned off, a node between the 1-1st transistor ST1 - 1 and the 1-2nd transistor ST1 - 2 may correspond to a floating source / drain node.

[0151] The second transistor ST2 may be a dual transistor including a 2-1st transistor ST2-1 and a 2-2nd transistor ST2-2.

[0152] The 2-1st transistor ST2-1 may include an active region ACT2-1, a gate electrode G2-1, a source electrode S2-1, and a drain electrode D2-1. The active region ACT2-1 of the 2-1st transistor ST2-1 may overlap with the gate electrode G2-1 of the 2-1st transistor ST2-1. The gate electrode G2-1 of the 2-1st transistor ST2-1, which is a portion of the scan line SLk-1 of the previous stage, may correspond to a region of the scan line SLk-1 of the previous stage that overlaps with the active region ACT2-1.

[0153] The source electrode S2-1 of the 2-1st transistor ST2-1 may be connected to the second link electrode BE2 through the eighth contact hole CNT8, and the second link electrode BE2 may be connected to the initialization voltage line VIL through the seventh contact hole CNT7. The source electrode S2-1 of the 2-1st transistor ST2-1 may be connected to the initialization voltage line VIL to receive the initialization voltage V1.

[0154] The drain electrode D2 - 1 of the 2-1st transistor ST2 - 1 may be connected to the source electrode S2 - 2 of the 2-2nd transistor ST2 - 2 .

[0155] The 2-2nd transistor ST2-2 may include an active region ACT2-2, a gate electrode G2-2, a source electrode S2-2, and a drain electrode D2-2.

[0156] The active region ACT2-2 of the 2-2 transistor ST2-2 may overlap with the gate electrode G2-2 of the 2-2 transistor ST2-2. The gate electrode G2-2 of the 2-2 transistor ST2-2, which is a portion of the scan line SLk-1 of the previous stage, may correspond to a region of the scan line SLk-1 of the previous stage that overlaps with the active region ACT2-2.

[0157] The source electrode S2 - 2 of the 2-2 th transistor ST2 - 2 may be connected to the drain electrode D2 - 1 of the 2-1 th transistor ST2 - 1 .

[0158] The drain electrode D2-2 of the 2-2 transistor ST2-2 may be connected to the first connection electrode BE1 through the sixth contact hole CNT6, and the first connection electrode BE1 may be connected to the gate electrode DT-G of the driving transistor DT through the first contact hole CNT1. Further, the drain electrode D2-2 of the 2-2 transistor ST2-2 may be connected to the drain electrode D1-2 of the 1-2 transistor ST1-2.

[0159] The third transistor ST3 may include an active region ACT3, a gate electrode G3, a source electrode S3, and a drain electrode D3. The active region ACT3 of the third transistor ST3 may overlap with the gate electrode G3 of the third transistor ST3. The gate electrode G3 of the third transistor ST3, which is a portion of the scan line SLk of the corresponding stage, may correspond to a region of the scan line SLk of the corresponding stage that overlaps with the active region ACT3.

[0160] The source electrode S3 of the third transistor ST3 may be connected to the data line DL through the second contact hole CNT2. Therefore, the source electrode S3 of the third transistor ST3 may receive the data voltage Vdata from the data line DL.

[0161] The drain electrode D3 of the third transistor ST3 may be connected to the source electrode DT-S of the driving transistor DT and the drain electrode D4 of the fourth transistor ST4 .

[0162] The fourth transistor ST4 may include an active region ACT4, a gate electrode G4, a source electrode S4, and a drain electrode D4. The active region ACT4 of the fourth transistor ST4 may overlap with the gate electrode G4 of the fourth transistor ST4. The gate electrode G4 of the fourth transistor ST4, which is part of the emission control line EML, may correspond to a region of the emission control line EML that overlaps with the active region ACT4.

[0163] The source electrode S4 of the fourth transistor ST4 may be connected to the second driving voltage line VDDL2 through the ninth contact hole CNT9. Thus, the source electrode S4 of the fourth transistor ST4 may receive the driving voltage from the second driving voltage line VDDL2.

[0164] The drain electrode D4 of the fourth transistor ST4 may be connected to the source electrode DT-S of the driving transistor DT and the drain electrode D3 of the third transistor ST3 .

[0165] The fifth transistor ST5 may include an active region ACT5, a gate electrode G5, a source electrode S5, and a drain electrode D5. The active region ACT5 of the fifth transistor ST5 may overlap with the gate electrode G5 of the fifth transistor ST5. The gate electrode G5 of the fifth transistor ST5, which is part of the emission control line EML, may correspond to a region of the emission control line EML that overlaps with the active region ACT5.

[0166] The source electrode S5 of the fifth transistor ST5 may be connected to the drain electrode DT-D of the driving transistor DT and the source electrode S2 - 1 of the 2-1st transistor ST2 - 1 .

[0167] The drain electrode D5 of the fifth transistor ST5 may be connected to the fourth connection electrode BE4 through the fourth contact hole CNT4, and the fourth connection electrode BE4 may be connected to the anode connection electrode ANDE through the twelfth contact hole CNT12. The anode connection electrode ANDE may be connected to the anode electrode of the light emitting element EL.

[0168] The sixth transistor ST6 may include an active region ACT6, a gate electrode G6, a drain electrode D6, and a source electrode S6. The active region ACT6 of the sixth transistor ST6 may overlap with the gate electrode G6 of the sixth transistor ST6. The gate electrode G6 of the sixth transistor ST6, which is a portion of the scan line SLk of the corresponding stage, may correspond to a region of the scan line SLk of the corresponding stage that overlaps with the active region ACT6.

[0169] The source electrode S6 of the sixth transistor ST6 is connected to the third link electrode BE3 through the eleventh contact hole CNT11, and the third link electrode BE3 is connected to the initialization voltage line VIL through the tenth contact hole CNT10. The source electrode S6 of the sixth transistor ST6 is connected to the initialization voltage line VIL to receive the initialization voltage V1.

[0170] The drain electrode D6 of the sixth transistor ST6 may be connected to the fourth connection electrode BE4 through the fourth contact hole CNT4, and the fourth connection electrode BE4 may be connected to the anode connection electrode ANDE through the twelfth contact hole CNT12. The anode connection electrode ANDE may be connected to the anode electrode of the light emitting element EL.

[0171] The first capacitor C1 may include a first electrode CE11 and a second electrode CE12. The first electrode CE11 of the first capacitor C1, which is a portion of the gate electrode DT-G of the drive transistor DT, may correspond to a region of the gate electrode DT-G of the drive transistor DT that overlaps with the second gate layer GTL2. The first electrode CE11 of the first capacitor C1 may be connected to the first connection electrode BE1 through a first contact hole CNT1, and the first connection electrode BE1 may be connected to the drain electrode D1-2 of the 1-2 transistor ST1-2 and the drain electrode D2-2 of the 2-2 transistor ST2-2 through a sixth contact hole CNT6.

[0172] The driving voltage line VDDL may include a first driving voltage line VDDL1 and a second driving voltage line VDDL2. For example, the first driving voltage line VDDL1 may be disposed in the second gate layer GTL2, and the second driving voltage line VDDL2 may be disposed on the source-drain layer SDL. The first driving voltage line VDDL1 may be connected to the second driving voltage line VDDL2 via a third contact hole CNT3.

[0173] The second electrode CE12 of the first capacitor C1 , which is a portion of the first driving voltage line VDDL1 , may correspond to a region of the first driving voltage line overlapping the gate electrode DT-G of the driving transistor DT.

[0174] Reference Figure 7 Together Figure 8 The display panel 300 includes a substrate SUB, a buffer layer BF, an active layer ACTL, a gate insulating film GI, a first gate layer GTL1, a first interlayer insulating film ILD1, a second gate layer GTL2, a second interlayer insulating film ILD2, a source-drain layer SDL, and a passivation layer PAS.

[0175] The substrate SUB may be a base substrate and may be made of an insulating material such as a polymer resin. For example, the substrate SUB may be a flexible substrate that can be bent, folded, rolled, or the like.

[0176] The buffer layer BF may be disposed on the substrate SUB. For example, the buffer layer BF may include a plurality of inorganic films and may be formed on the entire upper surface of the substrate SUB to block moisture from penetrating into the light emitting element EL through the substrate SUB.

[0177] The active layer ACTL may be disposed on the buffer layer BF. The active layer ACTL may be made of a silicon-based material. For example, the active layer ACTL may be made of low-temperature polysilicon (LTPS). The driving transistor DT and the active regions DT-ACT and ACT1, ACT2, ACT3, ACT4, ACT5, and ACT6 of the first to sixth transistors ST1, ST2, ST3, ST4, ST5, and ST6, the source electrodes DT-S and S1, S2, S3, S4, S5, and S6, and the drain electrodes DT-D and D1, D2, D3, D4, D5, and D6 may be disposed in the active layer ACTL.

[0178] The gate insulating film GI may cover the buffer layer BF and the active layer ACTL, and may insulate the active layer ACTL from the first gate layer GTL1.

[0179] A first gate layer GTL1 may be disposed on the gate insulating film GI. A gate electrode DT-G of the driving transistor DT, a scan line SLk-1 of a previous stage, a scan line SLk of a corresponding stage, and an emission control line EML may be disposed in the first gate layer GTL1.

[0180] A portion of the gate electrode DT-G of the driving transistor DT may form a first electrode CE11 of the first capacitor C1 overlapping the second electrode CE12 of the first capacitor C1 disposed in the second gate layer GTL2 .

[0181] A portion of the scan line SLk of the corresponding stage may overlap with the active area ACT1-1 of the 1-1 transistor ST1-1 and the active area ACT1-2 of the 1-2 transistor ST1-2 to form the gate electrode G1-1 of the 1-1 transistor ST1-1 and the gate electrode G1-2 of the 1-2 transistor ST1-2, respectively. Another portion of the scan line SLk of the corresponding stage may overlap with the active area ACT3 of the third transistor ST3 to form the gate electrode G3 of the third transistor ST3. Another portion of the scan line SLk of the corresponding stage may overlap with the active area ACT6 of the sixth transistor to form the gate electrode G6 of the sixth transistor ST6.

[0182] A portion of the scan line SLk-1 of the previous stage may overlap the active area ACT2-1 of the 2-1st transistor ST2-1 and the active area ACT2-2 of the 2-2nd transistor ST2-2 to form the gate electrode G2-1 of the 2-1st transistor ST2-1 and the gate electrode G2-2 of the 2-2nd transistor ST2-2, respectively.

[0183] A portion of the emission control line EML may overlap the active region ACT4 of the fourth transistor ST4 to form a gate electrode G4 of the fourth transistor ST4. Another portion of the emission control line EML may overlap the active region ACT5 of the fifth transistor ST5 to form a gate electrode G5 of the fifth transistor ST5.

[0184] The first interlayer insulating film ILD1 may cover the first gate layer GTL1 and the gate insulating film GI. The first interlayer insulating film ILD1 may insulate the first gate layer GTL1 from the second gate layer GTL2.

[0185] The second gate layer GTL2 may be disposed on the first interlayer insulating film ILD1. A portion of the second gate layer GTL2 may overlap with the first electrode CE11 disposed in the first gate layer GTL1 to form the second electrode CE12 of the first capacitor C1. Another portion of the second gate layer GTL2 may form the first driving voltage line VDDL1. Another portion of the second gate layer GTL2 may form the gate auxiliary electrode GAE. An initialization voltage line VIL may be disposed in the second gate layer GTL2.

[0186] The second interlayer insulating film ILD2 may cover the second gate layer GTL2 and the first interlayer insulating film ILD1. The second interlayer insulating film ILD2 may insulate the second gate layer GTL2 from the source-drain layer SDL.

[0187] A source-drain layer SDL may be disposed on the second interlayer insulating film ILD2 , and first to fourth connection electrodes BE1 , BE2 , BE3 , and BE4 , a data line DL, and a second driving voltage line VDDL2 may be disposed on the source-drain layer SDL.

[0188] The passivation layer PAS may cover the source-drain layer SDL and the second interlayer insulating film ILD2 . The passivation layer PAS may insulate the anode connection electrode ANDE from the source-drain layer SDL.

[0189] Figure 9 yes Figure 7 An enlarged view of area A1 in FIG. 1 , and Figure 10 It is along Figure 9 A cross-sectional view taken along line II-II'.

[0190] Reference Figure 9 and Figure 10 , the first transistor ST1 may be a double transistor including a 1-1th transistor ST1 - 1 and a 1-2th transistor ST1 - 2 .

[0191] The gate auxiliary electrode GAE may be disposed in the second gate layer GTL2. For example, the gate electrode G1-1 of the 1st transistor ST1-1 and the gate electrode G1-2 of the 1st transistor ST1-2 may be disposed in the first gate layer GTL1, and the second gate layer GTL2 may be disposed on the first gate layer GTL1. The gate auxiliary electrode GAE may be connected to the gate electrode G1-1 of the 1st transistor ST1-1 or the gate electrode G1-2 of the 1st transistor ST1-2. For example, the gate auxiliary electrode GAE may be connected to the gate electrode G1-1 of the 1st transistor ST1-1 through the fifth contact hole CNT5. Thus, when the gate electrode G1-1 of the 1st transistor ST1-1 receives the scan signal SCk of the corresponding stage, the scan signal SCk may be supplied to the gate auxiliary electrode GAE.

[0192] At least a portion of the gate auxiliary electrode GAE may be arranged in the second gate layer GTL2 between the active area ACT1-1 of the 1-1st transistor ST1-1 and the active area ACT1-2 of the 1-2nd transistor ST1-2. The gate auxiliary electrode GAE may overlap with the source electrode or the drain electrode arranged between the active area ACT1-1 of the 1-1st transistor ST1-1 and the active area ACT1-2 of the 1-2nd transistor ST1-2 in the thickness direction (Z-axis direction). For example, when the drain electrode D1-1 of the 1-1st transistor ST1-1 is in direct contact with the source electrode S1-2 of the 1-2nd transistor ST1-2, the gate auxiliary electrode GAE may overlap with at least one of the drain electrode D1-1 of the 1-1st transistor ST1-1 and the source electrode S1-2 of the 1-2nd transistor ST1-2 in the thickness direction (Z-axis direction). Thus, an electric field may be formed between the gate auxiliary electrode GAE and the drain electrode D1 - 1 of the 1-1th transistor ST1 - 1 or between the gate auxiliary electrode GAE and the source electrode S1 - 2 of the 1-2th transistor ST1 - 2 .

[0193] For example, the gate auxiliary electrode GAE may be connected to the gate electrode G1-1 of the 1-1 transistor ST1-1 through the fifth contact hole CNT5 and may overlap with the drain electrode D1-1 of the 1-1 transistor ST1-1 and the source electrode S1-2 of the 1-2 transistor ST1-2 in the thickness direction (Z-axis direction). An electric field formed at a node between the 1-1 transistor ST1-1 and the 1-2 transistor ST1-2 may be affected by the electric field between the gate electrode G1-1 of the 1-1 transistor ST1-1 and the drain electrode D1-1 of the 1-1 transistor ST1-1, the electric field between the gate electrode G1-2 of the 1-2 transistor ST1-2 and the source electrode S1-2 of the 1-2 transistor ST1-2, and the electric field between the gate auxiliary electrode GAE and the drain electrode D1-1 of the 1-1 transistor ST1-1.

[0194] The strength of the electric field can be proportional to the potential difference between the electrodes and can be inversely proportional to the distance between the electrodes. For example, the distance TGI2 between the gate auxiliary electrode GAE and the drain electrode D1-1 of the 1-1 transistor ST1-1 can be longer than the distance TGI1 between the gate electrode G1-1 and the drain electrode D1-1 of the 1-1 transistor ST1-1. The strength of the electric field between the gate auxiliary electrode GAE and the drain electrode D1-1 of the 1-1 transistor ST1-1 can be lower than the strength of the electric field between the gate electrode G1-1 and the drain electrode D1-1 of the 1-1 transistor ST1-1. Therefore, when the gate auxiliary electrode GAE is connected to the gate electrode G1-1 of the 1-1 transistor ST1-1, the electric field between the gate auxiliary electrode GAE and the drain electrode D1-1 of the 1-1 transistor ST1-1 can be reduced, and the electric field formed at the node between the 1-1 transistor ST1-1 and the 1-2 transistor ST1-2 can be reduced. When the electric field formed at the node between the 1-1 transistor ST1-1 and the 1-2 transistor ST1-2 is reduced, leakage current flowing through the 1-1 transistor ST1-1 and the 1-2 transistor ST1-2 can be reduced, and a decrease in luminance of the subpixel SP can be prevented.

[0195] Figure 11 It is an icon Figure 5 A plan view of another example of a sub-pixel shown in FIG. Figure 12 yes Figure 11 An enlarged view of area A2 in FIG. 1 , and Figure 13 It is along Figure 12 A cross-sectional view taken along line III-III'. Figure 11 、 Figure 12 and Figure 13 The sub-pixel and Figure 7 、 Figure 8 、 Figure 9 and Figure 10The sub-pixel of FIG4 is different in that it further includes a first doping region, a second doping region, a third doping region, and a fourth doping region. Therefore, components identical to those previously described will be briefly described or omitted.

[0196] Reference Figure 11 、 Figure 12 and Figure 13 The first transistor ST1 can be turned on by a scan signal SCk of a scan line SLk of a corresponding stage to connect a first node N1, which is a drain electrode of the driving transistor DT, to a second node N2, which is a gate electrode of the driving transistor DT. The first transistor ST1 can be a dual transistor including a 1-1 transistor ST1-1 and a 1-2 transistor ST1-2.

[0197] The 1-1 transistor ST1-1 may include an active region ACT1-1, a gate electrode G1-1, a source electrode S1-1, a drain electrode D1-1, a first doped region LDD1, and a second doped region LDD2. The active region ACT1-1 of the 1-1 transistor ST1-1 may overlap with the gate electrode G1-1 of the 1-1 transistor ST1-1. The gate electrode G1-1 of the 1-1 transistor ST1-1, which is a portion of the scan line SLk of the corresponding stage, may correspond to a region of the scan line SLk of the corresponding stage that overlaps with the active region ACT1-1.

[0198] The source electrode S1 - 1 of the 1-1th transistor ST1 - 1 may be connected to the drain electrode DT-D of the driving transistor DT and the source electrode S5 of the fifth transistor ST5 .

[0199] The drain electrode D1 - 1 of the 1-1th transistor ST1 - 1 may be connected to the source electrode S1 - 2 of the 1-2th transistor ST1 - 2 .

[0200] The first doping region LDD1 of the 1-1 transistor ST1-1 may be arranged between the active region ACT1-1 and the source electrode S1-1 of the 1-1 transistor ST1-1. For example, the doping concentration of the first doping region LDD1 may be higher than the doping concentration of each of the active region ACT1-1 of the 1-1 transistor ST1-1 and the active region ACT1-2 of the 1-2 transistor ST1-2. The doping concentration of the first doping region LDD1 may be lower than the doping concentration of each of the source electrode S1-1 and the drain electrode D1-1 of the 1-1 transistor ST1-1. The doping concentration of the first doping region LDD1 may be lower than the doping concentration of each of the source electrode S1-2 and the drain electrode D1-2 of the 1-2 transistor ST1-2.

[0201] The second doping region LDD2 of the 1-1 transistor ST1-1 may be arranged between the active region ACT1-1 and the drain electrode D1-1 of the 1-1 transistor ST1-1. For example, the doping concentration of the second doping region LDD2 may be higher than the doping concentration of each of the active region ACT1-1 of the 1-1 transistor ST1-1 and the active region ACT1-2 of the 1-2 transistor ST1-2. The doping concentration of the second doping region LDD2 may be lower than the doping concentration of each of the source electrode S1-1 and the drain electrode D1-1 of the 1-1 transistor ST1-1. The doping concentration of the second doping region LDD2 may be lower than the doping concentration of each of the source electrode S1-2 and the drain electrode D1-2 of the 1-2 transistor ST1-2.

[0202] The 1-2 transistor ST1-2 may include an active region ACT1-2, a gate electrode G1-2, a source electrode S1-2, a drain electrode D1-2, a third doped region LDD3, and a fourth doped region LDD4. The active region ACT1-2 of the 1-2 transistor ST1-2 may overlap with the gate electrode G1-2 of the 1-2 transistor ST1-2. The gate electrode G1-2 of the 1-2 transistor ST1-2, which is a portion of the scan line SLk of the corresponding stage, may correspond to a region of the scan line SLk of the corresponding stage that overlaps with the active region ACT1-2.

[0203] The source electrode S1 - 2 of the 1-2 th transistor ST1 - 2 may be connected to the drain electrode D1 - 1 of the 1-1 th transistor ST1 - 1 .

[0204] The drain electrode D1-2 of the 1-2 transistor ST1-2 may be connected to the first connection electrode BE1 through the sixth contact hole CNT6, and the first connection electrode BE1 may be connected to the gate electrode DT-G of the driving transistor DT through the first contact hole CNT1. Furthermore, the drain electrode D1-2 of the 1-2 transistor ST1-2 may be connected to the drain electrode D2-2 of the 2-2 transistor ST2-2.

[0205] The third doping region LDD3 of the 1-2 transistor ST1-2 may be arranged between the active region ACT1-2 and the source electrode S1-2 of the 1-2 transistor ST1-2. For example, the doping concentration of the third doping region LDD3 may be higher than the doping concentration of each of the active region ACT1-1 of the 1-1 transistor ST1-1 and the active region ACT1-2 of the 1-2 transistor ST1-2. The doping concentration of the third doping region LDD3 may be lower than the doping concentration of each of the source electrode S1-1 and the drain electrode D1-1 of the 1-1 transistor ST1-1. The doping concentration of the third doping region LDD3 may be lower than the doping concentration of each of the source electrode S1-2 and the drain electrode D1-2 of the 1-2 transistor ST1-2.

[0206] The fourth doping region LDD4 of the 1-2 transistor ST1-2 may be disposed between the active region ACT1-2 and the drain electrode D1-2 of the 1-2 transistor ST1-2. For example, the doping concentration of the fourth doping region LDD4 may be higher than the doping concentration of each of the active region ACT1-1 of the 1-1 transistor ST1-1 and the active region ACT1-2 of the 1-2 transistor ST1-2. The doping concentration of the fourth doping region LDD4 may be lower than the doping concentration of each of the source electrode S1-1 and the drain electrode D1-1 of the 1-1 transistor ST1-1. The doping concentration of the fourth doping region LDD4 may be lower than the doping concentration of each of the source electrode S1-2 and the drain electrode D1-2 of the 1-2 transistor ST1-2.

[0207] The gate auxiliary electrode GAE may be disposed in the second gate layer GTL2. For example, the gate electrode G1-1 of the 1st transistor ST1-1 and the gate electrode G1-2 of the 1st transistor ST1-2 may be disposed in the first gate layer GTL1, and the second gate layer GTL2 may be disposed on the first gate layer GTL1. The gate auxiliary electrode GAE may be connected to the gate electrode G1-1 of the 1st transistor ST1-1 or the gate electrode G1-2 of the 1st transistor ST1-2. For example, the gate auxiliary electrode GAE may be connected to the gate electrode G1-1 of the 1st transistor ST1-1 through the fifth contact hole CNT5. Thus, when the gate electrode G1-1 of the 1st transistor ST1-1 receives the scan signal SCk of the corresponding stage, the scan signal SCk may be supplied to the gate auxiliary electrode GAE.

[0208] At least a portion of the gate auxiliary electrode GAE may be arranged in the second gate layer GTL2 between the active area ACT1-1 of the 1-1st transistor ST1-1 and the active area ACT1-2 of the 1-2nd transistor ST1-2. The gate auxiliary electrode GAE may overlap with the source electrode or the drain electrode arranged between the active area ACT1-1 of the 1-1st transistor ST1-1 and the active area ACT1-2 of the 1-2nd transistor ST1-2 in the thickness direction (Z-axis direction). For example, when the drain electrode D1-1 of the 1-1st transistor ST1-1 is in direct contact with the source electrode S1-2 of the 1-2nd transistor ST1-2, the gate auxiliary electrode GAE may overlap with at least one of the drain electrode D1-1 of the 1-1st transistor ST1-1 and the source electrode S1-2 of the 1-2nd transistor ST1-2 in the thickness direction (Z-axis direction). Thus, an electric field may be formed between the gate auxiliary electrode GAE and the drain electrode D1 - 1 of the 1-1th transistor ST1 - 1 or between the gate auxiliary electrode GAE and the source electrode S1 - 2 of the 1-2th transistor ST1 - 2 .

[0209] The gate auxiliary electrode GAE may overlap with the second doped region LDD2 of the 1-1 transistor ST1-1 or the third doped region LDD3 of the 1-2 transistor ST1-2 in the thickness direction (Z-axis direction). For example, the gate auxiliary electrode GAE may be connected to the gate electrode G1-1 of the 1-1 transistor ST1-1 through the fifth contact hole CNT5 and may overlap with the drain electrode D1-1 of the 1-1 transistor ST1-1, the source electrode S1-2 of the 1-2 transistor ST1-2, and the second doped region LDD2 in the thickness direction (Z-axis direction). The electric field formed at the node between the 1-1 transistor ST1-1 and the 1-2 transistor ST1-2 may be affected by the electric field between the gate electrode G1-1 of the 1-1 transistor ST1-1 and the drain electrode D1-1 of the 1-1 transistor ST1-1, the electric field between the gate electrode G1-2 of the 1-2 transistor ST1-2 and the source electrode S1-2 of the 1-2 transistor ST1-2, and the electric field between the gate auxiliary electrode GAE and the source electrode S1-2 of the 1-2 transistor ST1-2. For another example, the arrangement of the gate auxiliary electrode GAE is not limited to Figure 11 、 Figure 12 and Figure 13 As shown in FIG, the gate auxiliary electrode GAE may also overlap with the third doped region LDD3.

[0210] The strength of the electric field can be proportional to the potential difference between the electrodes and inversely proportional to the distance between the electrodes. For example, the distance TGI2 between the gate auxiliary electrode GAE and the drain electrode D1-1 of the 1-1 transistor ST1-1 can be longer than the distance TGI1 between the gate electrode G1-1 and the drain electrode D1-1 of the 1-1 transistor ST1-1. In this case, the distance TGI1 is tilted because the gate electrode G1-1 does not overlap with the drain electrode D1-1 of the 1-1 transistor ST1-1 due to the second doped region LDD2 arranged between the active region ACT1-1 and the drain electrode D1-1. The strength of the electric field between the gate auxiliary electrode GAE and the drain electrode D1-1 of the 1-1 transistor ST1-1 can be lower than the strength of the electric field between the gate electrode G1-1 and the drain electrode D1-1 of the 1-1 transistor ST1-1. Thus, when the gate auxiliary electrode GAE is connected to the gate electrode G1-1 of the 1-1st transistor ST1-1, the electric field between the gate auxiliary electrode GAE and the drain electrode D1-1 of the 1-1st transistor ST1-1 can be reduced, and the electric field formed at the node between the 1-1st transistor ST1-1 and the 1-2nd transistor ST1-2 can be reduced. When the electric field formed at the node between the 1-1st transistor ST1-1 and the 1-2nd transistor ST1-2 is reduced, leakage current flowing through the 1-1st transistor ST1-1 and the 1-2nd transistor ST1-2 can be reduced, and a decrease in the luminance of the sub-pixel SP can be prevented.

[0211] because Figure 11 、 Figure 12 and Figure 13 The 1-1th transistor ST1-1 further includes a second doped region LDD2, so Figure 11 、 Figure 12 and Figure 13 The distance TGI1 between the gate electrode G1-1 and the drain electrode D1-1 of the 1-1th transistor ST1-1 may be greater than Figure 7 、 Figure 8 、 Figure 9 and Figure 10 The distance TGI1 between the gate electrode G1-1 and the drain electrode D1-1 of the 1-1 transistor ST1-1 is long. Figure 11 、 Figure 12 and Figure 13 The intensity of the electric field between the gate electrode G1-1 and the drain electrode D1-1 of the 1-1 transistor ST1-1 can be greater than Figure 7 、 Figure 8 、 Figure 9 and Figure 10 The intensity of the electric field between the gate electrode G1-1 and the drain electrode D1-1 of the 1-1st transistor ST1-1 is low. Figure 7 、 Figure 8 、 Figure 9 and Figure 10 Compared with the electric field at the node between the 1-1 transistor ST1-1 and the 1-2 transistor ST1-2, the electric field formed at the node can be further reduced. Figure 11 、 Figure 12 and Figure 13 When the electric field formed at the node between the 1-1 transistor ST1-1 and the 1-2 transistor ST1-2 is reduced, leakage current flowing through the 1-1 transistor ST1-1 and the 1-2 transistor ST1-2 can be reduced, and a decrease in the luminance of the sub-pixel SP can be prevented.

[0212] Figure 14 It is an icon Figure 5 A plan view of another example of a sub-pixel shown in FIG. Figure 15 yes Figure 14 An enlarged view of area A3 in FIG. 1 is shown, and Figure 16 It is along Figure 15 A cross-sectional view taken along line IV-IV'. Figure 14 、 Figure 15 and Figure 16 The sub-pixel has the same configuration of the gate auxiliary electrode GAE as Figure 7 、 Figure 8 、 Figure 9 and Figure 10 Therefore, the same components as those previously described will be briefly described or omitted.

[0213] Reference Figure 14 、 Figure 15 and Figure 16 The first transistor ST1 can be turned on by a scan signal SCk of a scan line SLk of a corresponding stage to connect a first node N1, which is a drain electrode of the driving transistor DT, to a second node N2, which is a gate electrode of the driving transistor DT. The first transistor ST1 can be a dual transistor including a 1-1 transistor ST1-1 and a 1-2 transistor ST1-2.

[0214] The gate auxiliary electrode GAE may be arranged in the second gate layer GTL2. For example, the gate electrode G1-1 of the 1st transistor ST1-1 and the gate electrode G1-2 of the 1st transistor ST1-2 may be arranged in the first gate layer GTL1, and the second gate layer GTL2 may be arranged on the first gate layer GTL1. The gate auxiliary electrode GAE may be connected to the scan line SLk of the corresponding stage. The gate auxiliary electrode GAE may be connected to the scan line SLk of the corresponding stage through the fifth contact hole CNT5. The fifth contact hole CNT5 may not overlap with the active area ACT1-1 of the 1st transistor ST1-1, but the present disclosure is not limited thereto. For example, the gate auxiliary electrode GAE may extend from the fifth contact hole CNT5 in a direction perpendicular to the extension direction of the scan line SLk and may bend toward the drain electrode D1-1 of the 1st transistor ST1-1 or the source electrode S1-2 of the 1st transistor ST1-2. The gate auxiliary electrode GAE may have an "L" shape, but its shape is not limited thereto.

[0215] At least a portion of the gate auxiliary electrode GAE may be arranged in the second gate layer GTL2 between the active area ACT1-1 of the 1-1st transistor ST1-1 and the active area ACT1-2 of the 1-2nd transistor ST1-2. The gate auxiliary electrode GAE may overlap with the source electrode or the drain electrode arranged between the active area ACT1-1 of the 1-1st transistor ST1-1 and the active area ACT1-2 of the 1-2nd transistor ST1-2 in the thickness direction (Z-axis direction). For example, when the drain electrode D1-1 of the 1-1st transistor ST1-1 is in direct contact with the source electrode S1-2 of the 1-2nd transistor ST1-2, the gate auxiliary electrode GAE may overlap with at least one of the drain electrode D1-1 of the 1-1st transistor ST1-1 and the source electrode S1-2 of the 1-2nd transistor ST1-2 in the thickness direction (Z-axis direction). Thus, an electric field may be formed between the gate auxiliary electrode GAE and the drain electrode D1 - 1 of the 1-1th transistor ST1 - 1 or between the gate auxiliary electrode GAE and the source electrode S1 - 2 of the 1-2th transistor ST1 - 2 .

[0216] The strength of the electric field can be proportional to the potential difference between the electrodes and inversely proportional to the distance between the electrodes. For example, the distance TGI2 between the gate auxiliary electrode GAE and the drain electrode D1-1 of the 1-1 transistor ST1-1 can be longer than the distance TGI1 between the gate electrode G1-1 and the drain electrode D1-1 of the 1-1 transistor ST1-1. The strength of the electric field between the gate auxiliary electrode GAE and the drain electrode D1-1 of the 1-1 transistor ST1-1 can be lower than the strength of the electric field between the gate electrode G1-1 and the drain electrode D1-1 of the 1-1 transistor ST1-1. Thus, when the gate auxiliary electrode GAE is connected to the scan line SLk of the corresponding stage, the electric field between the gate auxiliary electrode GAE and the drain electrode D1-1 of the 1-1 transistor ST1-1 can be reduced, and the electric field formed at the node between the 1-1 transistor ST1-1 and the 1-2 transistor ST1-2 can be reduced. When the electric field formed at the node between the 1-1 transistor ST1-1 and the 1-2 transistor ST1-2 is reduced, leakage current flowing through the 1-1 transistor ST1-1 and the 1-2 transistor ST1-2 can be reduced, and a decrease in luminance of the subpixel SP can be prevented.

[0217] According to an embodiment of the present invention, the display device may include a gate auxiliary electrode that overlaps with a floating source / drain node of a dual transistor disposed between a drain electrode and a gate electrode of a driving transistor and is connected to the gate electrode of at least one of the dual transistors. Thus, the display device can reduce the electric field formed at the floating source / drain node and reduce leakage current flowing through the dual transistors, thereby preventing a decrease in the luminance of the sub-pixel.

[0218] In a display device according to an embodiment, at least one of the dual transistors may further include a doped region disposed between the active region and the source / drain electrodes. The doping concentration of the doped region may be higher than that of the active region and lower than that of the source / drain electrodes. Thus, the display device can reduce the electric field formed at the floating source / drain node and the leakage current flowing through the dual transistor, thereby preventing a decrease in the brightness of the sub-pixel.

[0219] The effects of the present disclosure are not limited to the foregoing, and other various effects are expected herein.

[0220] Although the preferred embodiments of the present disclosure have been disclosed for illustrative purposes, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the disclosure as disclosed in the accompanying claims.

Claims

1. A display device comprising: substrate; as well as a plurality of sub-pixels arranged on the substrate and including light-emitting elements and sub-pixel circuits for driving the light-emitting elements, Wherein, the sub-pixel circuit includes: a driving transistor, the driving transistor controlling a driving current flowing through the light emitting element; a first transistor and a second transistor connected in series and arranged between a first node which is a drain electrode of the driving transistor and a second node which is a gate electrode of the driving transistor to receive the same scan signal from the same scan line; and a gate auxiliary electrode disposed on the gate electrode of the first transistor or the gate electrode of the second transistor and connected to the gate electrode of the first transistor or the gate electrode of the second transistor, and The gate auxiliary electrode overlaps with the drain electrode of the first transistor or the source electrode of the second transistor in a thickness direction.

2. The display device according to claim 1, in, The drain electrode of the first transistor or the source electrode of the second transistor is arranged between an active region of the first transistor and an active region of the second transistor.

3. The display device according to claim 1, further comprising: an active layer disposed on the substrate; as well as a first gate layer disposed on the active layer, wherein an active region of each of the driving transistor, the first transistor, and the second transistor is arranged in the active layer, and The gate electrode of each of the driving transistor, the first transistor, and the second transistor is disposed in the first gate layer.

4. The display device according to claim 3, further comprising: a second gate layer disposed on the first gate layer, Wherein, the gate auxiliary electrode is arranged in the second gate layer.

5. The display device according to claim 4, further comprising: a gate insulating film that insulates the gate electrode of each of the first transistor and the second transistor from the active region of each of the first transistor and the second transistor; as well as an interlayer insulating film disposed between the first gate layer and the second gate layer and including at least one contact hole, The gate auxiliary electrode is connected to the gate electrode of the first transistor or the gate electrode of the second transistor through the at least one contact hole of the interlayer insulating film.

6. The display device according to claim 1, in, A source electrode of the first transistor is connected to the first node, and the drain electrode of the first transistor is connected to the second transistor, and The source electrode of the second transistor is connected to the drain electrode of the first transistor, and the drain electrode of the second transistor is connected to the second node.

7. The display device according to claim 6, in, The first transistor further includes a first doped region disposed between an active region of the first transistor and the source electrode of the first transistor, and a second doped region disposed between the active region of the first transistor and the drain electrode of the first transistor, and The second transistor further includes a third doped region disposed between an active region of the second transistor and the source electrode of the second transistor, and a fourth doped region disposed between the active region of the second transistor and the drain electrode of the second transistor.

8. The display device according to claim 7, in, A doping concentration of each of the first doping region, the second doping region, the third doping region, and the fourth doping region is higher than a doping concentration of the active region of the first transistor or the active region of the second transistor.

9. The display device according to claim 7, in, A doping concentration of each of the first doping region, the second doping region, the third doping region, and the fourth doping region is lower than a doping concentration of each of the source electrode and the drain electrode of the first transistor and the source electrode and the drain electrode of the second transistor.

10. The display device according to claim 7, in, The gate auxiliary electrode overlaps with the second doping region of the first transistor or the third doping region of the second transistor in the thickness direction.

11. The display device according to claim 7, in, The gate auxiliary electrode overlaps at least one of the second doping region and the drain electrode of the first transistor and the third doping region and the source electrode of the second transistor in the thickness direction.

12. The display device according to claim 1, wherein The sub-pixel circuit further includes a third transistor that selectively supplies a data voltage to a third node that is a source electrode of the driving transistor. The first transistor, the second transistor and the third transistor receive the same scan signal.

13. A display device comprising: substrate; as well as a plurality of sub-pixels arranged on the substrate and including light-emitting elements and sub-pixel circuits for driving the light-emitting elements, Wherein, the sub-pixel circuit includes: a driving transistor, the driving transistor controlling a driving current flowing through the light emitting element; a first transistor including a first electrode connected to a first node serving as a drain electrode of the drive transistor and a second electrode selectively connected to a second node serving as a gate electrode of the drive transistor; a second transistor including a first electrode connected to the second electrode of the first transistor and a second electrode connected to the second node; and a gate auxiliary electrode, the gate auxiliary electrode being arranged on the gate electrode of the first transistor or the gate electrode of the second transistor and overlapping with the second electrode of the first transistor or the first electrode of the second transistor in a thickness direction, The gate auxiliary electrode is connected to the gate electrode of the first transistor or the gate electrode of the second transistor.

14. The display device according to claim 13, further comprising: an active layer disposed on the substrate; as well as a first gate layer disposed on the active layer, wherein an active region of each of the driving transistor, the first transistor, and the second transistor is arranged in the active layer, and The gate electrode of each of the driving transistor, the first transistor, and the second transistor is disposed in the first gate layer.

15. The display device according to claim 14, further comprising: a second gate layer disposed on the first gate layer, Wherein, the gate auxiliary electrode is arranged in the second gate layer.

16. The display device according to claim 15, further comprising: a gate insulating film that insulates the gate electrode of each of the first transistor and the second transistor from the active region of each of the first transistor and the second transistor; as well as an interlayer insulating film disposed between the first gate layer and the second gate layer and including at least one contact hole, The gate auxiliary electrode is connected to the gate electrode of the first transistor or the gate electrode of the second transistor through the at least one contact hole of the interlayer insulating film.

17. The display device according to claim 13, in, The first transistor further includes a first doped region disposed between an active region of the first transistor and the first electrode of the first transistor, and a second doped region disposed between the active region of the first transistor and the second electrode of the first transistor, and The second transistor further includes a third doped region disposed between an active region of the second transistor and the first electrode of the second transistor, and a fourth doped region disposed between the active region of the second transistor and the second electrode of the second transistor.

18. The display device according to claim 17, in, The gate auxiliary electrode overlaps with the second doping region of the first transistor or the third doping region of the second transistor in the thickness direction.

19. The display device according to claim 17, in, The gate auxiliary electrode overlaps at least one of the second doping region and the second electrode of the first transistor and the third doping region and the first electrode of the second transistor in the thickness direction.

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