Integrated circuit with isolated interface and packaging method thereof

Abstract

The present invention provides an isolated interface integrated circuit and method, belonging to the field of integrated circuit technology. It includes a digital channel primary end chip DIE1 and a power channel primary end chip DIE5 arranged on a first base island, a digital channel isolation device chip DIE2, a digital channel secondary end chip DIE3 and a bus interface chip DIE4 arranged on a second base island, and a power channel isolation device chip DIE6 and a power channel secondary end chip DIE7 arranged on a third base island; the first base island, the second base island and the third base island are isolated from each other. The present invention provides a packaging method for a multi-DIE integrated isolated interface with simple process and low cost. The present invention integrates an isolated DC-DC power supply with an isolated interface chip, so that the chip only needs to be powered at the primary end, and no additional power is required at the secondary end. The chip processing technology using the solution of the present invention is simple to implement and the cost is low.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuits, and in particular relates to an integrated circuit with an isolated interface and a packaging method thereof. Background Art

[0002] In order to effectively communicate between different electronic devices or between different electronic components in the same device, certain bus standards must be followed at the same time. Some bus standards, such as RS-485, RS-232, RS-422, CAN and other standards, specify the electrical characteristics of the bus interface, and the integrated circuit chip with such electrical characteristics is called the bus interface chip. In order to effectively reduce the interference and noise between devices, between electronic components and introduced by the bus, the bus interface chip can be used in conjunction with a digital isolator to eliminate the interference. There are two ways to achieve the combination of the bus interface chip and the digital isolator: one is to package the bus interface chip die and the digital isolator chip die separately, and then make electrical connections on the circuit board. The disadvantage of this method is that it is large in size and low in integration; the other method is to integrate the bus interface chip die and the digital isolator chip die in the same package to make an isolated interface chip. The advantage of this method is high integration and small size, but it also puts forward requirements on the size of the package.

[0003] However, for the isolated interface chip with multiple DIE integrated packaging, the existing design method is to arrange all DIEs in a direction perpendicular to the pin arrangement direction (such as Figure 1 ). Figure 1 In the figure, DIE1, DIE2 and DIE3 are chipsets for realizing the digital isolator function, and DIE4 is an interface chip. In order to ensure the isolation capability, a certain distance needs to be maintained between base island A and base island B. At the same time, the rectangular bare chips DIE1, DIE2, DIE3 and DIE4 themselves have a certain width, which makes the distance between the two columns of pins too large, and the width of the chip too large. Even if the SOIC wide body package is used, it is difficult to meet the requirements. At the same time, the package does not integrate an isolated DC-DC power supply, so both the primary and secondary ends of the chip need to provide power. In many fields such as power automation, instrumentation, motor control, industrial measurement, automotive body communication, aerospace, and medical care, many data interfaces and power modules of electronic systems need to use isolators to protect the core circuits. The isolated circuits are required to withstand a certain voltage difference (1KV~5KV) and be able to transmit signals in isolation. At the same time, for the sake of miniaturization, there are certain requirements for chip size. Summary of the invention

[0004] In view of the above-mentioned deficiencies in the prior art, the present invention provides an isolated interface integrated circuit and a packaging method thereof, which integrate an isolated DC-DC power supply with an isolated interface chip, so that the chip only needs to be powered at the primary end and no additional power is required at the secondary end.

[0005] In order to achieve the above purpose, the technical solution adopted by the present invention is:

[0006] The present solution provides an isolated interface integrated circuit, comprising a digital channel primary end chip DIE1 and a power channel primary end chip DIE5 arranged on a first base island, a digital channel isolation device chip DIE2, a digital channel secondary end chip DIE3 and a bus interface chip DIE4 arranged on a second base island, and a power channel isolation device chip DIE6 and a power channel secondary end chip DIE7 arranged on a third base island;

[0007] The first base island, the second base island and the third base island are isolated from each other; a circuit connection is formed between the digital channel primary end chip DIE1 and the digital channel isolation device chip DIE2; a circuit connection is formed between the digital channel isolation device chip DIE2 and the digital channel secondary end chip DIE3; a circuit connection is formed between the digital channel secondary end chip DIE3 and the bus interface chip DIE4; a circuit connection is formed between the power channel primary end chip DIE5 and the power channel isolation device chip DIE6; a circuit connection is formed between the power channel isolation device chip DIE6 and the power channel secondary end chip DIE7.

[0008] Furthermore, the digital channel primary end chip DIE1, the digital channel isolation device chip DIE2, the digital channel secondary end chip DIE3, the bus interface chip DIE4, the power channel primary end chip DIE5, the power channel isolation device chip DIE6 and the power channel secondary end chip DIE7 are all rectangular chips.

[0009] Furthermore, the arrangement directions of the digital channel primary chip DIE1, the digital channel isolation device chip DIE2 and the digital channel secondary chip DIE3 are parallel to the sides where the integrated circuit pins are located, and the long sides of the rectangles of the digital channel primary chip DIE1, the digital channel isolation device chip DIE2 and the digital channel secondary chip DIE3 are perpendicular to the sides where the integrated circuit pins are located.

[0010] Furthermore, the bus interface chip DIE4 is placed next to the digital channel isolation device chip DIE2 and the digital channel secondary end chip DIE3, and the long sides of the rectangle of the bus interface chip DIE4 are parallel to the arrangement directions of the digital channel primary end chip DIE1, the digital channel isolation device chip DIE2 and the digital channel secondary end chip DIE3.

[0011] Furthermore, the power channel primary end chip DIE5, the power channel isolation device chip DIE6 and the power channel secondary end chip DIE7 are arranged side by side, and the arrangement direction is perpendicular to the side where the integrated circuit pins are located, and the long side direction of the rectangle of the power channel primary end chip DIE5, the power channel isolation device chip DIE6 and the power channel secondary end chip DIE7 is parallel to the side where the integrated circuit pins are located.

[0012] Furthermore, the primary end chip DIE1 of the digital channel has VCC pin, RxD pin, RE pin, DE pin, TxD pin and GND1 pin respectively; the secondary end chip DIE3 of the digital channel has GND2 pin respectively; the bus interface chip DIE4 has VCC2IN pin, A pin, B pin, Z pin, Y pin and GND2 pin respectively; the primary end chip DIE5 of the power channel has VCC pin and GND1 pin respectively; the secondary end chip DIE7 of the power channel has VCC2OUT pin and GND2 pin respectively.

[0013] Furthermore, the power channel secondary end chip DIE7 and the power channel isolation device chip DIE6 are isolated DC-DC power supplies, and provide power for the digital channel secondary end chip DIE3 and the bus interface chip DIE4.

[0014] The present invention also discloses an isolated interface integrated circuit packaging method, comprising the following steps:

[0015] S1, respectively divide the primary end chip DIE1 of the digital channel, the digital channel isolation device chip DIE2, the secondary end chip DIE3 of the digital channel, the bus interface chip DIE4, the primary end chip DIE5 of the power channel, the secondary end chip DIE7 of the power channel and the isolation device chip DIE6 of the power channel into three groups;

[0016] S2, installing the first group, the second group and the third group on mutually isolated base islands respectively;

[0017] S3, placing the digital channel primary end chip DIE1 and the power channel primary end chip DIE5 on the first base island, placing the digital channel isolation device chip DIE2, the digital channel secondary end chip DIE3 and the bus interface chip DIE4 on the second base island, and placing the power channel isolation device chip DIE6 and the power channel secondary end chip DIE7 on the third base island;

[0018] S4, setting the arrangement direction of the primary end chip DIE1 of the digital channel, the digital channel isolation device chip DIE2 and the secondary end chip DIE3 of the digital channel to be parallel to the side where the integrated circuit pins are located, and ensuring that the long side direction of the rectangle of the primary end chip DIE1 of the digital channel, the digital channel isolation device chip DIE2 and the secondary end chip DIE3 of the digital channel is perpendicular to the side where the integrated circuit pins are located;

[0019] S5, placing the bus interface chip DIE4 next to the digital channel isolation device chip DIE2 and the digital channel secondary end chip DIE3, and ensuring that the long sides of the rectangle of the bus interface chip DIE4 are parallel to the arrangement directions of the digital channel primary end chip DIE1, the digital channel isolation device chip DIE2 and the digital channel secondary end chip DIE3;

[0020] S6, arranging the power channel primary end chip DIE5, the power channel isolation device chip DIE6 and the power channel secondary end chip DIE7 in parallel, and the arrangement direction is perpendicular to the side where the integrated circuit pins are located, and ensuring that the rectangular long side direction of the power channel primary end chip DIE5, the power channel isolation device chip DIE6 and the power channel secondary end chip DIE7 is parallel to the side where the integrated circuit pins are located;

[0021] S7. Use the power channel secondary end chip DIE7 and the power channel isolation device chip DIE6 to supply power to the digital channel secondary end chip DIE3 and the bus interface chip DIE4, and complete the packaging of the isolated interface integrated circuit.

[0022] Furthermore, the digital channel primary end chip DIE1, the digital channel isolation device chip DIE2, the digital channel secondary end chip DIE3, the bus interface chip DIE4, the power channel primary end chip DIE5, the power channel isolation device chip DIE6 and the power channel secondary end chip DIE7 are all rectangular chips.

[0023] Furthermore, a circuit connection is formed between the digital channel primary end chip DIE1 and the digital channel isolation device chip DIE2; a circuit connection is formed between the digital channel isolation device chip DIE2 and the digital channel secondary end chip DIE3; a circuit connection is formed between the digital channel secondary end chip DIE3 and the bus interface chip DIE4; a circuit connection is formed between the power channel primary end chip DIE5 and the power channel isolation device chip DIE6; and a circuit connection is formed between the power channel isolation device chip DIE6 and the power channel secondary end chip DIE7.

[0024] Beneficial effects of the present invention:

[0025] (1) The present invention provides a packaging method for a multi-DIE integrated isolated interface with simple process and low cost. The present invention integrates an isolated DC-DC power supply with an isolated interface chip, so that the chip only needs to be powered at the primary end, without providing additional power at the secondary end.

[0026] (2) In the present invention, the arrangement direction of the digital channel primary end chip DIE1, the digital channel isolation device chip DIE2 and the digital channel secondary end chip DIE3 is parallel to the arrangement direction of the pins, which can provide space for the placement of the bus interface chip DIE4 without making the distance between the left and right columns of pins too large.

[0027] (3) In the present invention, the bus interface chip DIE4 is placed next to the digital channel isolation device chip DIE2 and the digital channel secondary end chip DIE3, and the long side of its rectangle is parallel to the arrangement direction of the digital channel primary end chip DIE1, the digital channel isolation device chip DIE2 and the digital channel secondary end chip DIE3. Under the premise of meeting the packaging requirements of multiple DIE chips, the distance between the base island 1 and the base island 2 can be guaranteed, so that the isolation voltage of the chip can reach 2500Vrms or above.

[0028] (4) Since the arrangement directions of the digital channel primary chip DIE1, the digital channel isolation device chip DIE2 and the digital channel secondary chip DIE3 are parallel to the arrangement directions of the pins, while ensuring the isolation voltage capability (ensuring the isolation capability requires a certain distance between the two base islands), the distance between the two rows of pins is greatly reduced, making it easier to meet the package size requirements of SOIC, which is better than the existing technology. Some existing technologies make two chips into one chip, and the processing technology is difficult. The solution of the present invention is simple to implement in terms of chip processing technology and low cost.

[0029] (5) The present invention places different chips in groups on different base islands, and there is a sufficient isolation distance between the base islands to meet the requirements of voltage isolation capability.

[0030] (6) Compared with the prior art, the present invention adds a third base island for placing the power channel isolation device chip DIE6 and the power channel secondary end chip DIE7 of the isolated DC-DC power supply, providing a built-in isolated power supply integrated inside the chip for the secondary end of the isolated interface chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 It is a schematic diagram of the packaging method of the prior art.

[0032] Figure 2 It is a schematic diagram of the packaging method of the present invention.

[0033] Figure 3The figure is a flow chart of the packaging method of the present invention. DETAILED DESCRIPTION

[0034] The specific implementation modes of the present invention are described below so that those skilled in the art can understand the present invention. However, it should be clear that the present invention is not limited to the scope of the specific implementation modes. For those of ordinary skill in the art, as long as various changes are within the spirit and scope of the present invention as defined and determined by the attached claims, these changes are obvious, and all inventions and creations utilizing the concept of the present invention are protected.

[0035] Example 1

[0036] like Figure 2As shown, the present invention provides an isolated interface integrated circuit, comprising a digital channel primary end chip DIE1 and a power channel primary end chip DIE5 arranged on a first base island, a digital channel isolation device chip DIE2, a digital channel secondary end chip DIE3 and a bus interface chip DIE4 arranged on a second base island, and a power channel isolation device chip DIE6 and a power channel secondary end chip DIE7 arranged on a third base island; the first base island, the second base island and the third base island are isolated from each other; a circuit connection is formed between the digital channel primary end chip DIE1 and the digital channel isolation device chip DIE2; a circuit connection is formed between the digital channel isolation device chip DIE2 and the digital channel secondary end chip DIE3; a circuit connection is formed between the digital channel secondary end chip DIE3 and the bus interface chip DIE4; a circuit connection is formed between the power channel primary end chip DIE5 and the power channel isolation device chip DIE6; a circuit connection is formed between the power channel isolation device chip DIE6 and the power channel secondary end chip DIE7. The digital channel primary end chip DIE1, the digital channel isolation device chip DIE2, the digital channel secondary end chip DIE3, the bus interface chip DIE4, the power channel primary end chip DIE5, the power channel isolation device chip DIE6 and the power channel secondary end chip DIE7 are all rectangular chips. The arrangement directions of the digital channel primary end chip DIE1, the digital channel isolation device chip DIE2 and the digital channel secondary end chip DIE3 are parallel to the sides where the integrated circuit pins are located, and the rectangular long sides of the digital channel primary end chip DIE1, the digital channel isolation device chip DIE2 and the digital channel secondary end chip DIE3 are perpendicular to the sides where the integrated circuit pins are located. The bus interface chip DIE4 is placed next to the digital channel isolation device chip DIE2 and the digital channel secondary end chip DIE3, and the rectangular long sides of the bus interface chip DIE4 are parallel to the arrangement directions of the digital channel primary end chip DIE1, the digital channel isolation device chip DIE2 and the digital channel secondary end chip DIE3. The power channel primary end chip DIE5, the power channel isolation device chip DIE6 and the power channel secondary end chip DIE7 are arranged side by side, and the arrangement direction is perpendicular to the side where the integrated circuit pins are located. The long side direction of the rectangle of the power channel primary end chip DIE5, the power channel isolation device chip DIE6 and the power channel secondary end chip DIE7 is parallel to the side where the integrated circuit pins are located.The primary end chip DIE1 of the digital channel leads out VCC pin, RxD pin, RE pin, DE pin, TxD pin and GND1 pin respectively; the secondary end chip DIE3 of the digital channel leads out GND2 pin; the bus interface chip DIE4 leads out VCC2IN pin, A pin, B pin, Z pin, Y pin and GND2 pin respectively; the primary end chip DIE5 of the power channel leads out VCC pin and GND1 pin respectively; the secondary end chip DIE7 of the power channel leads out VCC2OUT pin and GND2 pin respectively. The secondary end chip DIE7 of the power channel and the isolation device chip DIE6 of the power channel are isolated DC-DC power supplies, and supply power to the secondary end chip DIE3 of the digital channel and the bus interface chip DIE4.

[0037] In this embodiment, the isolated DC-DC power supply is integrated with the isolated interface chip, so that the chip only needs to be powered at the primary end and does not need to provide additional power at the secondary end.

[0038] In this embodiment, the arrangement direction of the digital channel primary chip DIE1, the digital channel isolation device chip DIE2 and the digital channel secondary chip DIE3 is parallel to the arrangement direction of the pins, which can provide space for the placement of the bus interface chip DIE4 without making the distance between the left and right columns of pins too large.

[0039] In this embodiment, the bus interface chip DIE4 is placed next to the digital channel isolation device chip DIE2 and the digital channel secondary end chip DIE3, and the long side of its rectangle is parallel to the arrangement direction of the digital channel primary end chip DIE1, the digital channel isolation device chip DIE2 and the digital channel secondary end chip DIE3. On the premise of meeting the packaging requirements of multiple DIE chips, the distance between the base island 1 and the base island 2 can be guaranteed, so that the isolation voltage of the chip can reach 2500Vrms or above.

[0040] In the present embodiment, since the arrangement directions of the digital channel primary chip DIE1, the digital channel isolation device chip DIE2 and the digital channel secondary chip DIE3 are parallel to the arrangement direction of the pins, while ensuring the isolation voltage capability (ensuring the isolation capability requires a certain distance between the two base islands), the distance between the two rows of pins is greatly reduced, making it easier to meet the package size requirements of SOIC, which is superior to the prior art. Some prior arts make two chips into one chip, and the processing technology is difficult. The chip processing technology of the solution of the present invention is simple to implement and low in cost.

[0041] In this embodiment, different chips are grouped and placed on different base islands, and there is a sufficient isolation distance between the base islands to meet the voltage isolation capability requirement.

[0042] In this embodiment, a third base island is added to place the power channel isolation device chip DIE6 and the power channel secondary end chip DIE7 of the isolated DC-DC power supply, providing a built-in isolated power supply integrated in the chip for the secondary end of the isolated interface chip.

[0043] Example 2

[0044] like Figure 3 As shown, the present invention provides an isolated interface integrated circuit packaging method, and its implementation method is as follows:

[0045] S1, respectively divide the primary end chip DIE1 of the digital channel, the digital channel isolation device chip DIE2, the secondary end chip DIE3 of the digital channel, the bus interface chip DIE4, the primary end chip DIE5 of the power channel, the secondary end chip DIE7 of the power channel and the isolation device chip DIE6 of the power channel into three groups;

[0046] S2, installing the first group, the second group and the third group on mutually isolated base islands respectively;

[0047] S3, placing the digital channel primary end chip DIE1 and the power channel primary end chip DIE5 on the first base island, placing the digital channel isolation device chip DIE2, the digital channel secondary end chip DIE3 and the bus interface chip DIE4 on the second base island, and placing the power channel isolation device chip DIE6 and the power channel secondary end chip DIE7 on the third base island;

[0048] S4, setting the arrangement direction of the primary end chip DIE1 of the digital channel, the digital channel isolation device chip DIE2 and the secondary end chip DIE3 of the digital channel to be parallel to the side where the integrated circuit pins are located, and ensuring that the long side direction of the rectangle of the primary end chip DIE1 of the digital channel, the digital channel isolation device chip DIE2 and the secondary end chip DIE3 of the digital channel is perpendicular to the side where the integrated circuit pins are located;

[0049] S5, placing the bus interface chip DIE4 next to the digital channel isolation device chip DIE2 and the digital channel secondary end chip DIE3, and ensuring that the long sides of the rectangle of the bus interface chip DIE4 are parallel to the arrangement directions of the digital channel primary end chip DIE1, the digital channel isolation device chip DIE2 and the digital channel secondary end chip DIE3;

[0050] S6, arranging the power channel primary end chip DIE5, the power channel isolation device chip DIE6 and the power channel secondary end chip DIE7 in parallel, and the arrangement direction is perpendicular to the side where the integrated circuit pins are located, and ensuring that the rectangular long side direction of the power channel primary end chip DIE5, the power channel isolation device chip DIE6 and the power channel secondary end chip DIE7 is parallel to the side where the integrated circuit pins are located;

[0051] S7. Use the power channel secondary end chip DIE7 and the power channel isolation device chip DIE6 to supply power to the digital channel secondary end chip DIE3 and the bus interface chip DIE4, and complete the packaging of the isolated interface integrated circuit.

[0052] In this embodiment, Figure 1 For the isolation device of the prior art, the arrangement direction of the digital channel primary end chip DIE1, the digital channel isolation device chip DIE2, the digital channel secondary end chip DIE3 and the bus interface chip DIE4 is perpendicular to the side where the integrated circuit pins are located, resulting in a large distance between the two columns of pins, making it difficult to meet the size requirements of the SOIC package. At the same time, the packaging form does not provide a packaging position for the isolated power supply DC-DC. The present invention places different chip groups on different base islands, and there is a sufficient isolation distance between the base islands to meet the requirements of voltage isolation capability. At the same time, the arrangement direction of the digital channel primary end chip DIE1, the digital channel isolation device chip DIE2 and the digital channel secondary end chip DIE3 is parallel to the side where the circuit pins are located, thus providing space for the placement of the bus interface chip DIE4 in the direction perpendicular to the pin arrangement, so that the packaging of the isolated interface chip does not exceed the cavity size of the SOIC standard packaging shell.

[0053] In this embodiment, a third base island is added to place the power channel isolation device chip DIE6 and the power channel secondary end chip DIE7 of the isolated DC-DC power supply, providing a built-in isolated power supply integrated inside the chip for the secondary end of the isolated interface chip, so that the chip only needs to be powered at the primary end and no additional power is required at the secondary end.

[0054] In this embodiment, different chips are grouped and placed on different base islands, and there is a sufficient isolation distance between the base islands to meet the voltage isolation capability requirement.

[0055] In this embodiment, the present invention arranges the digital channel primary end chip DIE1 and the power channel primary end chip DIE5 on the first base island, the digital channel isolation device chip DIE2, the digital channel secondary end chip DIE3 and the bus interface chip DIE4 on the second base island, the power channel isolation device chip DIE6 and the power channel secondary end chip DIE7 on the third base island, and the three base islands are isolated from each other. Figure 2As shown. A circuit connection is formed between the digital channel primary end chip DIE1 and the digital channel isolation device chip DIE2; a circuit connection is formed between the digital channel isolation device chip DIE2 and the digital channel secondary end chip DIE3; a circuit connection is formed between the digital channel secondary end chip DIE3 and the bus interface chip DIE4; a circuit connection is formed between the power channel primary end chip DIE5 and the power channel isolation device chip DIE6; a circuit connection is formed between the power channel isolation device chip DIE6 and the power channel secondary end chip DIE7.

[0056] In this embodiment, all chips are rectangular chips, the primary end chip DIE1 of the digital channel, the digital channel isolation device chip DIE2 and the secondary end chip DIE3 of the digital channel are arranged in parallel, and the long sides of the rectangles of the three chips are perpendicular to the sides where the integrated circuit pins are located, and the arrangement direction of the three chips is parallel to the sides where the circuit pins are located. While ensuring the isolation voltage capability (ensuring the isolation capability requires a certain distance between the two base islands), the distance between the two rows of pins is greatly reduced, and it is easier to meet the packaging size requirements of SOIC, which is better than the existing technology. Some existing technologies make two chips into one chip, and the processing technology is difficult. The chip processing technology of the scheme of the present invention is simple to implement and low in cost. At the same time, the bus interface chip DIE4 is placed next to the digital channel isolation device chip DIE2 and the secondary end chip DIE3 of the digital channel, and its long side of the rectangle is parallel to the side where the circuit pins are located. Under the premise of meeting the packaging requirements of multiple DIE chips, the distance between the first base island and the second base island can be guaranteed, so that the isolation voltage of the chip can reach 2500Vrms or above.

Claims

1. An isolated interface integrated circuit, characterized in that: It includes a digital channel primary end chip DIE1 and a power channel primary end chip DIE5 arranged on the first base island, a digital channel isolation device chip DIE2, a digital channel secondary end chip DIE3 and a bus interface chip DIE4 arranged on the second base island, and a power channel isolation device chip DIE6 and a power channel secondary end chip DIE7 arranged on the third base island; The first base island, the second base island and the third base island are isolated from each other; a circuit connection is formed between the digital channel primary end chip DIE1 and the digital channel isolation device chip DIE2; a circuit connection is formed between the digital channel isolation device chip DIE2 and the digital channel secondary end chip DIE3; a circuit connection is formed between the digital channel secondary end chip DIE3 and the bus interface chip DIE4; a circuit connection is formed between the power channel primary end chip DIE5 and the power channel isolation device chip DIE6; a circuit connection is formed between the power channel isolation device chip DIE6 and the power channel secondary end chip DIE7.

2. The isolated interface integrated circuit according to claim 1, characterized in that: The digital channel primary end chip DIE1, the digital channel isolation device chip DIE2, the digital channel secondary end chip DIE3, the bus interface chip DIE4, the power channel primary end chip DIE5, the power channel isolation device chip DIE6 and the power channel secondary end chip DIE7 are all rectangular chips.

3. The isolated interface integrated circuit according to claim 2, characterized in that: The arrangement directions of the digital channel primary chip DIE1, the digital channel isolation device chip DIE2 and the digital channel secondary chip DIE3 are all parallel to the sides where the integrated circuit pins are located, and the long sides of the rectangles of the digital channel primary chip DIE1, the digital channel isolation device chip DIE2 and the digital channel secondary chip DIE3 are perpendicular to the sides where the integrated circuit pins are located.

4. The isolated interface integrated circuit according to claim 3, characterized in that: The bus interface chip DIE4 is placed next to the digital channel isolation device chip DIE2 and the digital channel secondary end chip DIE3, and the rectangular long sides of the bus interface chip DIE4 are parallel to the arrangement directions of the digital channel primary end chip DIE1, the digital channel isolation device chip DIE2 and the digital channel secondary end chip DIE3.

5. The isolated interface integrated circuit according to claim 4, characterized in that: The power channel primary end chip DIE5, the power channel isolation device chip DIE6 and the power channel secondary end chip DIE7 are arranged side by side, and the arrangement direction is perpendicular to the side where the integrated circuit pins are located. The long side direction of the rectangle of the power channel primary end chip DIE5, the power channel isolation device chip DIE6 and the power channel secondary end chip DIE7 is parallel to the side where the integrated circuit pins are located.

6. The isolated interface integrated circuit according to claim 5, characterized in that: The primary end chip DIE1 of the digital channel has VCC pin, RxD pin, RE pin, DE pin, TxD pin and GND1 pin respectively; the secondary end chip DIE3 of the digital channel has GND2 pin respectively; the bus interface chip DIE4 has VCC2IN pin, A pin, B pin, Z pin, Y pin and GND2 pin respectively; the primary end chip DIE5 of the power channel has VCC pin and GND1 pin respectively; the secondary end chip DIE7 of the power channel has VCC2OUT pin and GND2 pin respectively.

7. The isolated interface integrated circuit according to claim 6, characterized in that: The power channel secondary end chip DIE7 and the power channel isolation device chip DIE6 are isolated DC-DC power supplies, and provide power for the digital channel secondary end chip DIE3 and the bus interface chip DIE4.

8. An isolated interface integrated circuit packaging method, characterized in that: The following steps are involved: S1, respectively divide the primary end chip DIE1 of the digital channel, the digital channel isolation device chip DIE2, the secondary end chip DIE3 of the digital channel, the bus interface chip DIE4, the primary end chip DIE5 of the power channel, the secondary end chip DIE7 of the power channel and the isolation device chip DIE6 of the power channel into three groups; S2, installing the first group, the second group and the third group on mutually isolated base islands respectively; S3, placing the digital channel primary end chip DIE1 and the power channel primary end chip DIE5 on the first base island, placing the digital channel isolation device chip DIE2, the digital channel secondary end chip DIE3 and the bus interface chip DIE4 on the second base island, and placing the power channel isolation device chip DIE6 and the power channel secondary end chip DIE7 on the third base island; S4, setting the arrangement direction of the primary end chip DIE1 of the digital channel, the digital channel isolation device chip DIE2 and the secondary end chip DIE3 of the digital channel to be parallel to the side where the integrated circuit pins are located, and ensuring that the long side direction of the rectangle of the primary end chip DIE1 of the digital channel, the digital channel isolation device chip DIE2 and the secondary end chip DIE3 of the digital channel is perpendicular to the side where the integrated circuit pins are located; S5, placing the bus interface chip DIE4 next to the digital channel isolation device chip DIE2 and the digital channel secondary end chip DIE3, and ensuring that the long sides of the rectangle of the bus interface chip DIE4 are parallel to the arrangement directions of the digital channel primary end chip DIE1, the digital channel isolation device chip DIE2 and the digital channel secondary end chip DIE3; S6, arranging the power channel primary end chip DIE5, the power channel isolation device chip DIE6 and the power channel secondary end chip DIE7 in parallel, and the arrangement direction is perpendicular to the side where the integrated circuit pins are located, and ensuring that the rectangular long side direction of the power channel primary end chip DIE5, the power channel isolation device chip DIE6 and the power channel secondary end chip DIE7 is parallel to the side where the integrated circuit pins are located; S7. Use the power channel secondary end chip DIE7 and the power channel isolation device chip DIE6 to supply power to the digital channel secondary end chip DIE3 and the bus interface chip DIE4, and complete the packaging of the isolated interface integrated circuit.

9. The isolated interface integrated circuit packaging method according to claim 8, characterized in that: The digital channel primary end chip DIE1, the digital channel isolation device chip DIE2, the digital channel secondary end chip DIE3, the bus interface chip DIE4, the power channel primary end chip DIE5, the power channel isolation device chip DIE6 and the power channel secondary end chip DIE7 are all rectangular chips.

10. The isolated interface integrated circuit packaging method according to claim 9, characterized in that: A circuit connection is formed between the digital channel primary end chip DIE1 and the digital channel isolation device chip DIE2; a circuit connection is formed between the digital channel isolation device chip DIE2 and the digital channel secondary end chip DIE3; a circuit connection is formed between the digital channel secondary end chip DIE3 and the bus interface chip DIE4; a circuit connection is formed between the power channel primary end chip DIE5 and the power channel isolation device chip DIE6; a circuit connection is formed between the power channel isolation device chip DIE6 and the power channel secondary end chip DIE7.

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