Microprocessor and prefetch instruction adjustment method

Abstract

The present invention relates to microprocessors and prefetch pointer adjustment methods. In one embodiment, the microprocessor includes first logic configured to dynamically adjust a maximum prefetch pointer count based on a total count of predicted taken branches over a predetermined number of cache lines, and second logic configured to prefetch a pointer to an instruction based on the adjusted maximum prefetch pointer count.

Description

Technical Field

[0001] This invention generally relates to microprocessors, and more particularly to prefetching instructions in microprocessors. Background Technology

[0002] When a microprocessor executes program instructions, it uses the processor bus to fetch instructions from memory into the microprocessor. The time required to fetch instructions from memory can consume many clock cycles (e.g., hundreds of clock cycles). To mitigate this problem, microprocessors include cache memory. Cache memory (typically much smaller than system memory) is memory within the microprocessor (or processor core) used to store a subset of instructions located in system memory. While prefetching is important for both instructions and data, the focus here is on the instruction cache. When the microprocessor fetches instructions, it checks to see if the instruction exists in the cache and is valid. If so, the instruction can be executed much faster than if it had to be retrieved from system memory. In other words, the microprocessor does not have to wait while using the processor bus to fetch instructions from memory into the cache. A situation where the microprocessor detects that an instruction exists in the cache and is valid is generally called a cache hit. A situation where the referenced instruction does not exist in the cache is generally called a cache miss. When the referenced instruction is already in cache memory, significant time savings are achieved by avoiding the extra clock cycles required to retrieve the instruction from external memory.

[0003] Cache prefetching is a technique used by microprocessors to further improve execution performance by fetching instructions from external memory into cache memory before the microprocessor actually needs them. Instruction cache fetching typically looks forward sequentially by a predefined number of cache lines (e.g., fetching the first ten (10) cache lines or four (4) cache lines, etc.). Successful instruction prefetching avoids the latency encountered when instructions must be retrieved from external memory (avoiding the consumption of bus bandwidth or bandwidth to other caches, as explained below).

[0004] There is a fundamental trade-off in prefetching. As mentioned above, prefetching can improve performance by reducing latency (by fetching instructions into the cache before they are actually needed). On the other hand, if too much information is prefetched (e.g., too many cache lines), the prefetcher's efficiency may decrease, and other system resources and bandwidth may become overburdened. Furthermore, if the cache is full, prefetching new cache lines into that cache can lead to the eviction of other cache lines. Therefore, cache lines that were previously needed may be evicted by lines that may only be needed in the future.

[0005] In some microprocessors, the cache actually consists of multiple caches. These caches are arranged in a multi-level hierarchy. For example, a microprocessor may have two caches, called the lower Level 1 (L1) cache and the higher Level 2 (L2) cache. The L1 cache is closer to the microprocessor's computing element than the L2 cache. That is, the L1 cache can serve instructions to the computing element faster than the L2 cache. The L2 cache is usually larger than the L1 cache, although this is not necessary. Some microprocessors may have a third cache (L3), which may be larger than the L2 cache. Due to cache misses, fetch time increases as instructions are fetched from the L1, L2, L3 caches and system memory (e.g., 10-20 clock cycles for example when fetching from L2, and 20-30 clock cycles for example when fetching from L3), and therefore, from a latency perspective, it is desirable to intelligently store instructions in the L1 cache.

[0006] Microprocessors use various instruction types, including branch instructions, or simply branches. Branches include unconditional branches (e.g., branches that are always taken) and conditional branches (e.g., branches that are taken or not taken depending on the evaluation of a specified condition). The prefetch scheme should take these various instruction types into account to ensure the efficiency of pipelined operations and, more specifically, reduce the wasted cycles consumed in the instruction fetch. Summary of the Invention

[0007] In one embodiment, a microprocessor includes: first logic configured to dynamically adjust a maximum prefetch count based on the total count of predicted branches taken on a predetermined number of cache lines; and second logic configured to prefetch instructions based on the adjusted maximum prefetch count.

[0008] Other systems, methods, features, and advantages of the present invention will be apparent to those skilled in the art upon review of the following drawings and detailed description. All such additional systems, methods, features, and advantages are intended to be included within this specification, within the scope of the invention, and protected by the appended claims. Attached Figure Description

[0009] The various aspects of the invention can be better understood by referring to the following accompanying drawings. The components in the drawings are not necessarily drawn to scale; rather, the focus is on clearly illustrating the principles of the invention. Furthermore, in the drawings, the same reference numerals denote corresponding parts in multiple views.

[0010] Figure 1A This is a block diagram illustrating an example branch unit pipeline of a microprocessor implementing an adjustable prefetch system.

[0011] Figure 1B It is shown Figure 1A The diagram shows an example front end of a branch unit pipeline.

[0012] Figure 2 This is a schematic diagram illustrating an example of branch density logic and instruction cache control logic of an embodiment of an adjustable prefetch system.

[0013] Figure 3 This is a flowchart illustrating an example method for adjusting a prefetching instruction in an embodiment of an adjustable prefetching instruction system.

[0014] Figure 4 This is a flowchart illustrating an example of an adjustable prefetch method. Detailed Implementation

[0015] Some embodiments of an adjustable prefetch system and method for a microprocessor are disclosed, which monitors the branch instruction density in the instruction currently being fetched and throttles the prefetch of instructions based on that density. In one embodiment, the adjustable prefetch system includes branch density logic, instruction cache control logic, and prefetch logic. The branch density logic is configured to determine a branch density value and communicate that value to the instruction cache control logic, wherein the branch density value includes the predicted number of branch instructions to be taken for a predefined number of cache lines. The instruction cache control logic includes adjustable logic and determines whether to adjust the maximum prefetch count based on the determined count. The adjusted maximum count is provided to the prefetch logic, which in turn adjusts the prefetch of instructions based on the adjusted maximum prefetch count and loads the prefetched instructions into the instruction cache.

[0016] In short, modern microprocessors can use a predetermined instruction prefetch count for all instruction applications. The prefetch count refers to the number of instructions fetched for a given size (e.g., 16 bytes, or other values ​​in some embodiments). When prefetching is performed for code that heavily relies on sequential instruction fetching, the predetermined prefetch count plays a good role in ensuring a stable instruction flow in the instruction cache. However, for a given span of cache lines, as the density of branch instructions (especially predicted branches) increases, instructions loaded into the instruction cache based on the prefetch scheme are removed and replaced from the target instruction. This means that bus bandwidth or bandwidth to higher-level caches (e.g., L2, L3) is unnecessarily consumed for cache lines that are now evicted. Furthermore, cache lines that may be needed in the near future may no longer be available, again wasting bus bandwidth to memory or higher-level caches. Instead, some embodiments of adjustable prefetch systems monitor the density of predicted branches and dynamically adjust the prefetch scheme based on the branch instruction density (e.g., branch density value or count) to ensure efficient use of fetch bandwidth and without unnecessary consumption.

[0017] Having summarized certain features of the adjustable prefetch system of the present invention, reference will now be made in detail to the description of the adjustable prefetch system illustrated in the accompanying drawings. While the adjustable prefetch system will be described in conjunction with these drawings, it is not intended to limit it to the embodiments disclosed herein. That is, while the invention is readily adaptable to various modifications and alternatives, specific embodiments thereof are shown by way of example in the drawings and will be described in detail herein in a manner sufficient for those skilled in the art to understand. However, it should be understood that the drawings and their detailed description are not intended to limit the invention to the specific forms disclosed. Rather, it is intended to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the appended claims. As used herein, the word “may” is used in a permissive sense (i.e., meaning possible) rather than a mandatory sense (i.e., meaning must). Similarly, the word “comprising” means including, but not limited to, the specific embodiments disclosed herein.

[0018] Various units, modules, circuits, logic, or other components can be described as being "configured" to perform one or more tasks. In this context, "configured" is a broad description of the structure, generally meaning "having a circuit or other physical structure that performs or is capable of performing one or more tasks during operation." A circuit can be a dedicated circuit or a more general processing circuit operating under the control of coded instructions. That is, terms such as "unit," "module," "circuit," "logic," and "component" are used herein when describing certain aspects or features of various implementations of the invention. Those skilled in the art will understand that the corresponding features are implemented using circuits, whether the circuit is a dedicated circuit or a more general circuit operating under the control of microcoded instructions.

[0019] Furthermore, units / modules / circuits / logic / components can be configured to perform tasks even when the unit / module / circuit / logic / component is not currently in operation. The description of units / modules / circuits / logic / components configured to perform one or more tasks is explicitly not intended to functionally limit the unit / module / circuit / logic / component. In this regard, those skilled in the art will understand that the specific structure or interconnection of circuit elements will generally be determined by the compiler of design automation tools, such as a register-transfer language (RTL) compiler. An RTL compiler runs on a script that is very similar to assembly language code to compile that script into a form for the layout or fabrication of the final circuit.

[0020] In other words, more advanced software tools are used to design integrated circuits (such as those of this invention) to model the desired functional operation of the circuit. Electronic Design Automation (or EDA) is a class of software tools used to design electronic systems such as integrated circuits. EDA tools are also used to program design functions into field-programmable gate arrays (FPGAs). Hardware descriptor languages ​​(HDLs) such as Verilog and Very High Speed ​​Integrated Circuits (VHDL) are used to create a high-level representation of the circuit, from which lower-level representations and the final actual wiring can be inferred. In practice, EDA tools are considered essential for the design of modern semiconductor chips, which can contain billions of components. In practice, circuit designers use programming languages ​​such as C / C++ to specify operational functions. EDA software tools translate this specified function into RTL. A hardware descriptor language (e.g., Verilog) then translates the RTL into a discrete netlist of gates. This netlist defines the actual circuit produced by, for example, a foundry. These tools are well-known and understood for their role and use in facilitating the design process of electronic and digital systems, and therefore need not be described here.

[0021] Figure 1AAn embodiment of an example branch unit pipeline used by microprocessor 10 is shown. It should be understood that certain known components of microprocessor 10 are omitted herein for brevity and ease of illustration. As is well known, pipelined architectures provide multiple instructions that overlap during execution, with each stage referred to as a pipeline stage. The blocks shown in the branch unit pipeline can each be implemented according to one or more stages, which are shown to the left of the block and, in the depicted embodiment, are represented by the uppercase letters C, I, B, U, L, M, F, G, W, X, E, S, W, Y, and Z, which proceed sequentially from top to bottom and are redirected (as indicated by arrows). Those skilled in the art will understand that... Figure 1A The number and / or arrangement of stages depicted herein are merely illustrative of one example embodiment, and in some embodiments, different numbers and / or arrangements of stages may be implemented, and are therefore contemplated within the scope of the invention. Those skilled in the art will also understand that these blocks provide a general description of the functionality of the branch pipeline, and for brevity, related logic or circuitry known to those skilled in the art is omitted herein. For example, those skilled in the art will understand that, as is known, the stages of a pipeline can be separated by a clock pipeline register or latch. As another example, although in Figure 1A While not explicitly shown, those skilled in the art will understand that operations at the front end involve data exchange or interaction with the instruction cache. Of particular note is that the logic used for instruction prefetching is intended to demonstrate operations that run concurrently with the pipeline's front-end operations, as further explained below.

[0022] An instruction cache is a random access memory device within a microprocessor, in which the microprocessor recently fetches and / or prefetches instructions from a larger cache (e.g., L2 cache, L3 cache) or system memory (e.g., fetches and / or prefetches instructions from DRAM by a bus interface unit) and places instructions (such as x86 ISA machine language instructions) of an ISA machine language program executed by the microprocessor 10 during the execution of the ISA machine language program into this random access memory device. An ISA defines an instruction address register (defined by the x86 ISA as the instruction pointer register (IP), but sometimes called the program counter (PC)) to hold the memory address of the next ISA instruction to be executed, and the microprocessor updates the contents of the instruction address register as it runs the machine language program to control program flow. To subsequently fetch ISA instructions from the instruction cache rather than from system memory more quickly based on the contents of the instruction address register during the next machine language program flow, the ISA instructions are cached such that the register holds the memory address of the ISA instructions present in the instruction cache. Specifically, the instruction cache is accessed based on the memory address held in the instruction address register (e.g., IP), rather than exclusively based on the memory address specified by the load or store instruction. Therefore, a dedicated data cache that holds ISA instructions as data (such as those that may reside in the hardware portion of a system employing a software translator) and is accessed exclusively based on the load / store address rather than through the instruction address register value is not an instruction cache. Furthermore, for the purposes of this invention, a unified cache that caches both instructions and data (i.e., accessed based on both the instruction address register value and the load / store address, rather than exclusively based on the load / store address) is intended to be included in the definition of an instruction cache.

[0023] Special attention Figure 1A The microprocessor 10 includes a branch unit pipeline, wherein the microprocessor 10 comprises a pipelined microprocessor, and in one embodiment, the instruction set of the pipelined microprocessor substantially conforms to the x86 architecture instruction set. Based on the description provided herein, those skilled in the art will understand that the present invention can be implemented in a variety of different circuit structures and architectures, and Figure 1AThe architecture shown is just one of many suitable architectures. Example microprocessor 10 includes a fast predictor 12, a branch target address cache (BTAC) 14, an instruction byte queue (XIB) 16, a branch decoder 18, a formatted instruction queue (FIQ) / circular queue 20, an instruction translator 22, a register alias table (RAT) / reservation station (RS) 24, functional units (e.g., integer units, floating-point units, etc.) 26, and a branch table updater 28. The digitally marked blocks of microprocessor 10 each correspond to logic implemented on corresponding multiple stages C, I, B, U, L, M, F, G, W, X, E, S, W, Y, and Z, where the pipelined architecture implements a different set of instructions at each stage. In one embodiment, four or more instructions can be executed at each stage, where control signals mark each stage along the pipeline. The stages associated with the fast predictor 12, BTAC 14, and XIB 16 involve the instruction cache (I cache, Figure 1A Access (not shown in the image).

[0024] The fast predictor 12 includes a single-cycle branch predictor that provides single-cycle prediction (e.g., taking one cycle to generate the target address, a prediction provided in stage I in one embodiment). In one embodiment, the fast predictor 12 includes a table (also referred to herein as an array or target array) storing the branch target addresses of previously executed branch instructions, which enables branch prediction when the stored branch instructions are subsequently encountered. In one embodiment, the table includes 128 entries, but in some embodiments other sizes (e.g., 64 entries, 32 entries, etc.) may be used. The table is organized as an n-way (e.g., n is an integer greater than 1) set-associative cache. In one embodiment, each entry stores eight (8) 3-bit counters and the current local branch mode, which is selected by the 3-bit local branch mode. The fast predictor 12 also includes a conditional branch predictor that is accessed in parallel with the table and provides take / not take direction for conditional branches. The fast predictor 12 also includes a return stack that can provide targets instead of the table. In one embodiment, the return stack includes four (4) entries and provides targets for return instructions. Note that the specifications listed above are merely illustrative, and some embodiments may be implemented under different specifications, and are therefore contemplated within the scope of this invention. The fast predictor 12 is configured to deliver predicted branch targets immediately (within a single cycle) without imposing branch penalties. In some embodiments, the fast predictor 12 may operate according to other specifications of its prediction mechanism and / or table configuration, or in some embodiments, may be omitted. Most branches are correctly predicted by the fast predictor 12. In some embodiments, where the fast predictor 12 provides branch predictions that differ from those of BTAC 14 (e.g., different in direction and / or target) based on the same fetched branch instruction, BTAC 14 utilizes the branch prediction information provided by BTAC 14 (e.g., direction, target address, branch prediction type) to overwrite the branch predictions of the fast predictor 12 and update the fast predictor table within a set of phases of BTAC 14 (e.g., in phase U).

[0025] The I-stage and / or B-stage correspond to various tables in the branch unit pipeline (including I cache, tag array, translation back buffer (TLB) array, BTAC array, return stack array, etc.), (e.g., tag-based) providing direction or path through multiplexing, and reading instructions.

[0026] BTAC 14 maintains information about previously executed branch instructions used to predict the target address, direction, and type during subsequent execution. BTAC 14 includes one or more tables much larger than the tables of the fast predictor 12. In one embodiment, BTAC 14 includes a 4k-entry, m-way group association table (also referred to herein as an array or target array), where m is an integer greater than 1. Each entry in BTAC 14 includes a valid bit, a branch target address prediction, a direction prediction, and a branch type. The branch type specifies whether the branch instruction is a call / return, an indirect branch, a conditional relative branch, or an unconditional relative branch. In one embodiment, BTAC 14 includes or collaborates with a conditional relative branch predictor with a multi-entry (e.g., 12k) Tag Geometry Length (TAGE) based predictor, multiple tables, multiple bits (e.g., 3 bits), a take / not take (T / NT) counter, and a multi-bit global branch history. As another example, indirect prediction includes a multi-entry (e.g., 1.5k) TAGE predictor and uses table entries for static indirect branches. Note that in some embodiments, other types of prediction mechanisms may be used, including correlation-based prediction mechanisms, predictors using a combination of global and local branch histories, etc. For each portion of a cache line of the instruction cache (e.g., 64 bytes as a non-limiting example) or a fetch (e.g., 16 bytes as a non-limiting example), BTAC 14 may maintain three entries (e.g., edges A, B, and C, although in some embodiments fewer edges may be used to store prediction information for fewer branch instructions). These three entries may hold prediction information for up to three branch instructions that may exist in a portion of the cache line. BTAC 14 includes operation through a set of stages (e.g., stage I, stage B, and stage U). In practice, the stage U of a branch instruction is used as the stage C of the target (e.g., the arrow from stage B to stage C reflects the branch instruction at stage B, and the next clock is the stage C of the target (or, in this case, the cache address), resulting in a two-clock delay for BTAC prediction.

[0027] BTAC 14 features a two-clock taken penalty, which also reveals the benefit of the fast predictor 12 in providing fast branch prediction (without taken penalty) by immediately directing new cache addresses to the target. In one embodiment, BTAC 14 (larger than the fast predictor 12 and with a more sophisticated branch prediction mechanism) is configured to overwrite the branch prediction of the fast predictor 12 when there is a divergence in branch prediction (e.g., the branch prediction determined by BTAC 14 differs from the taken decision and / or branch target address determined by the fast predictor 12) (e.g., always). In some embodiments, BTAC 14 is configured to update the fast predictor 12 during one of the BTAC phases (e.g., the U phase) by writing branch prediction information to the tables of the fast predictor 12 (and also to the tables of BTAC 14). In some embodiments, updates to BTAC 14 are deferred until the branch is executed or committed, wherein updates to BTAC 14 involve writing to the BTAC table and / or the TAGE table. In one embodiment, the update involves target information and / or counter updates. However, updates to the fast predictor 12 do not wait that long; they occur during the BTAC phase. Note that branches not in the fast predictor 12 are written to the fast predictor 12 two cycles later at a time corresponding to the BTAC phase (e.g., during the BTAC phase).

[0028] XIB 16 is an entry queue where each entry holds 16 bytes of data from the instruction cache. For example, cached data from XIB 16 is simply a stream of instruction bytes in 16-byte blocks, and in the case of a given instruction having a variable length, it is unknown where a given x86 instruction begins or ends within the stream or within a given block. XIB 16 includes known logic for determining and marking the start and end bytes of each instruction within the stream, thereby decomposing the byte stream into a stream of x86 instructions, which is provided to and stored in FIQ / circular queue 20 for processing by the remainder of the microprocessor pipeline. In the L (length) stage, XIB 16 determines the instruction length. Information relating to branch length marking (to the extent that such information is supplementary and consistent with the teachings of the invention) can be found in U.S. Patent No. 8,473,862, which is incorporated herein by reference. In one embodiment, the pre-decoder ( Figure 1AThe branch decoder 18 (not shown) is implemented in the U stage and configured to detect potential branch instructions, thus marking potential branch instructions for each instruction byte in the queue. It is worth noting that at this stage, there is ambiguity regarding whether a given byte is the start of an instruction. If the byte is the opcode byte of a branch instruction determined later (in the M stage), the instruction is confirmed as a branch instruction. For example, the branch decoder 18 includes an instruction multiplexer (not shown) for multiplexing instructions in a multiplexer or in the M stage, where branch instructions are thus confirmed.

[0029] In stage F, as described above, the instruction is formatted. In one embodiment, the formatting instructions include instructions that substantially conform to the x86 architecture instruction set. Additionally, in stage M, it is determined whether a given instruction (which may have been pre-marked by the pre-decoder) is indeed a branch. For example, in the event of a miss at fast predictor 12 or BTAC 14 (e.g., at initial startup), branch decoder 18 (e.g., instruction multiplexer) determines that the current instruction is a branch and redirects the cache address to the new target in stage G, and updates the tables in the front end of microprocessor 10. In effect, branch decoder 18 provides branch prediction in the event of a miss at fast predictor 12 or BTAC 14, where the branch instruction is redirected to the target in stage C. In some cases, such as when there are more than a finite or predetermined maximum number of branches at BTAC 14 for each fetch (e.g., more than three branches for every 16-byte fetch), branch prediction for the additional branches is delayed until the decoding time. Information relating to the M and F phases (to the extent that such information is supplementary and consistent with the teachings of the invention) can be found in U.S. Patent No. 8,473,862, which is incorporated herein by reference.

[0030] FIQ / Circular Queue 20 receives and buffers formatting instructions until they can be translated into microinstructions. FIQ / Circular Queue 20 also provides preliminary decoding and fast looping functionality (e.g., on a BTAC loop branch, activating the circular queue and repeatedly sending loop instructions), the latter indicated by the arrow on the right side of Block 20.

[0031] The W stage provides an optional additional timing clock.

[0032] In the X phase, the instruction translator 22 (in the X phase or translation phase) translates the formatted instructions stored in the FIQ / circular queue 20 into microinstructions.

[0033] Instructions are provided to the Register Alias ​​Table / Reservation Table (RAT / RS) 24 in program order. The RAT function of RAT / RS 24 maintains and generates dependency information for each instruction. The RAT function of RAT / RS 24 renames the source and destination of instructions to internal registers and dispatches instructions to the reservation stations of RAT / RS 24, which (possibly out of program order) issue instructions to function unit 26. Function or execution unit 26, including integer units, executes branch instructions in stage E (execution). Here, execution unit, branch unit, and integer unit are interchangeable terms. In one embodiment, execution unit 26 (e.g., two execution units) executes two branches in a single clock cycle. Execution unit 26 also indicates to BTAC 14 whether the branch instructions have been correctly predicted.

[0034] In one embodiment, the results of the execution are provided to a reordering cache (not shown), which includes information about the instructions that have been executed. It is well known that reordering caches maintain the original program order of instructions after they have been issued and allow for result serialization during the commit / exit phase.

[0035] Branch table update 28 comprises stages S, W, Y, and Z, and is configured to update various tables (e.g., BTAC, TAGE) at the front end with information related to the fully decoded and executed branch instructions (e.g., the final result of the branch) (e.g., in stage S). In stages S, W, Y, and Z, updates may involve table reads, target address writes, and counter increments or decrements, which may involve some latency.

[0036] The microprocessor 10 also includes additional logic related to prefetching and monitoring branch density or predicted branch instruction density. It is well known that prefetching instructions to load them into an instruction cache allows for faster, bandwidth-constrained instruction access, compared to retrieving instructions via the processor bus from higher-level cache memories (e.g., L2, L3) or system memory. Prefetching can be implemented at least in part using known software and / or (as highlighted herein) hardware prefetching schemes, primarily including next-line or sequential prefetching, but in some embodiments, it may include one or more of straddle prefetching (e.g., IP-based, cache block address-based, including streaming cache), location-based prefetching, content-based prefetching, correlation-based prefetching, pre-computed or execution-based prefetching, etc. In one embodiment, an adjustable prefetching system includes prefetching logic 40, branch density logic 42, and instruction cache (I cache) control logic 44.

[0037] The prefetch logic 40 can implement any one or a combination of the known prefetch schemes indicated above, and is used to prefetch instructions (e.g., from a higher-level cache or system memory) to fill the instruction cache.

[0038] Branch density logic 42 includes functionality for monitoring branch density, or more specifically, for predicting branch instructions to be taken for a given parameter. In one embodiment, the given parameter may be a predefined (predetermined) number of cache lines (e.g., 16 cache lines, 32 cache lines, etc.), where each cache line includes one or more x86 instructions. Branch density logic 42 receives input from branch prediction logic including one or a combination of fast predictor 12 and BTAC 14. The branch prediction logic (e.g., at the U stage) provides an indication of whether to take a branch or not, and the U stage also provides an indication of whether sequential fetching is being processed. Thus, branch density logic 42 can determine whether the fetch of the last predefined span or group includes a high branch density portion of the code, where throttling the prefetch can reduce the number of wasted instructions (because if a branch is predicted to be taken, a sequential instruction-based prefetch scheme would make cached instructions unsuitable, as instructions after the target need to be cached and previous instructions evicted from the instruction cache). In other words, during the consumption of a predefined number or span of cache lines with high-density predicted branch instructions, the branch density logic 42 is configured to detect these high branch density conditions and calculate the count of predicted branches to prevent the microprocessor 10 (specifically the prefetch logic 40) from wasting bandwidth by prefetching from higher-level caches or system memory when fetching code with high branch density.

[0039] As shown below Figure 2-3 As further explained in connection, the I cache control logic 44 includes control logic that coordinates prefetching instructions (e.g., in one embodiment, starting after a cache miss) and loading them into the instruction cache based on a maximum prefetch instruction count and an adjusted prefetch instruction count (variably adjusted based on branch density). In one embodiment, the I cache control logic 44 includes adjustment logic configured to adjust the maximum prefetch instruction count based on a branch density value (e.g., a count) determined according to branch density logic 42. In some embodiments, the I cache control logic 44 also includes a register (e.g., a feature control register) for maintaining the maximum prefetch instruction count.

[0040] Now we will continue to refer to Figure 1A In case of reference Figure 1B Example fast predictor 12 is shown, and it is used for... Figure 1AOther example sources used at the front end 30 of the branch unit pipeline shown in the microprocessor 10. The front end 30 includes an instruction fetch unit 32 (e.g., including a multiplexer and a clock register), a translation back buffer (TLB) 34, an instruction cache (I cache data) 36, I cache tags 38 (or a tag array), a BTAC 14, and a fast predictor 12. The instruction fetch unit 32 receives multiple cached instruction address sources, including (e.g., from the I stage) sequential instruction addresses, (e.g., from the S stage) corrected instruction addresses, (e.g., from the G stage) decode-time instruction addresses, and addresses from the BTAC 14 and the fast predictor 12. The output of the instruction fetch unit 32 is provided as input to the TLB 34, I cache data 36, ​​I cache tags 38, BTAC 14, and the fast predictor 12 for accessing the cached address of the next instruction for the I cache data 36.

[0041] Under the management of the memory management unit (not shown), TLB 34 provides virtual-to-physical page address translation as is known. That is, TLB 34 stores the physical address of the most recently used virtual address. TLB 34 receives a linear address from a segmentation unit (which translates logical addresses from the program into linear addresses), and a portion of that linear address is compared with entries in TLB 34 to find a match. If a match is found, the physical address is calculated based on the TLB entry. If no match is found, the page table entry from memory is fetched and placed into TLB 34.

[0042] I cache data 36 includes a Level 1 cache for fetching or prefetching instructions from L2 or L3 cache memory or main memory. I cache data 36 includes multiple clock registers.

[0043] I cache tag 38 includes an array of tags corresponding to instructions in I cache data 36, ​​and includes multiple clock registers for determining the match between information associated with the fetched cache instruction (e.g., tag or portion of cache address) and I cache data 36 and BTAC 14.

[0044] The above combination Figure 1ALet's illustrate BTAC 14, which has multiple clock registers and a two (2) clock take penalty. Also as explained above, the fast predictor 12 has a zero (0) clock take penalty. For example, suppose that instruction fetching occurs along the I cache at 16 bytes per cycle, and suppose that there are branch instructions from cache address 20 to cache address 95. Note that the address descriptions in this example imply hexadecimal notation (e.g., 0x0, 0x10, 0x20, etc.). Thus, the fetch occurs at cache address 0, cache address 10, cache address 20 (fetch branch instructions, but this is not yet resolved due to the multiple cycles of reading and multiplexing in BTAC 14, which in some embodiments is the same timing as the I cache), cache address 30 (relative clock 1), cache address 40 (relative clock 2), and then on the third clock (relative clock 3), the cache instruction fetch is redirected to cache address 95. Therefore, in this example, the branch penalty includes two clock cycles because cache addresses 30 and 40 appear after the branch. In other words, without the fast predictor 12, the branch penalty for this particular design example would always be two clock cycles. Using the smaller and faster fast predictor 12, in the above example, cache address fetches include 0, 10, 20, and 95, and there is no latency on the cache addresses with zero penalty. As mentioned above, in some embodiments, the fast predictor 12 can be omitted.

[0045] Continue to refer to Figure 1A-1B In this case, turn attention to Figure 2 This illustrates an example embodiment of the branch density logic 42 and the I cache control logic 44 of an adjustable prefetch instruction system. Those skilled in the art will understand that... Figure 2 The schematic diagram depicted is an example of an exemplary embodiment, and some embodiments may provide different logic and / or different logic arrangements than the depicted logic to perform similar functionality. In one embodiment, branch density logic 42 includes shift register 46 and adder logic 48, and cache control logic 44 includes adjustment logic 50. Generally, branch density logic 42 shifts in one entry for each predicted branch (and shifts in zero values ​​for sequential fetches at the end of cache lines), and performs bitwise addition of register values ​​for the last predefined number (as an illustrative, non-limiting example, such as 16, 32) of cache lines to provide a branch density value or count of how many predicted branch instructions are in the predefined number of cache lines. The branch density value is then provided to adjustment logic 50, which adjusts (if necessary) the maximum prefetch count, which serves as the basis for prefetching instructions via prefetch logic 40.

[0046] More specifically, shift register 46 (e.g., branch prediction logic including fast predictor 12 and / or BTAC 14) receives input at stage U, providing an indication of sequential fetch or predicted branch instruction. As further described below, shift register 46 includes a multiplexer that selects between shift and hold, and is generally configured to store the history of whether a given cache line contains a predicted branch. The multiplexer selects or captures a signal activated in the case of a predicted branch or a sequential fetch at the end of a cache line. (E.g., provided by the branch prediction logic) The signal at stage U indicates whether a branch is fetched or not and whether a sequential fetch is currently being processed. Shift register 46 counts the predicted branches for each cache line. Shift register 46 shifts at the end of a cache line (e.g., the last cache line with a predefined number of bytes, such as 16 or 32 bytes) or at a predicted branch. For example, shift register 46 fetches and shifts in bit values ​​(e.g., one (1)) for the taken branch and for the end of the cache line, and shifts in zero (0) if no branch is predicted to be taken. Therefore, shift register 46 provides the state for the last predefined number of cache lines and can at any time represent the register value that has increased, decreased, or remained unchanged (compared to previous register values) based on the shifted-in and shifted-out bit values. Further, if no branch is taken or the end of the cache line has not yet been reached, shift register 46 is fed only with its current value. This event or operation is represented as... Figure 2 The "hold" in this context. In some embodiments, the clock can simply be turned off, which has a similar effect. The shift path (in...) Figure 2 The term "shift" indicates that the earliest bit (e.g., bit 31) was discarded, which represents the bit from the previous 33rd cache line. Figure 2 The illustrative representation indicates that, in the presence of a hit on a branch taken for prediction, a bit value of 1 is shifted in, resulting in a shift of bits from 0:30 to 1:31. In the presence of a sequential fetch at the end of a cache line, a bit value of zero (0) is shifted.

[0047] Bitwise addition is performed by adder logic 48 (or simply adder). In one embodiment, adder logic 48 adds the number of bits of the predicted 1 value (for the predicted take) in the thirty-two (32) bits of shift register 46. For example, there may be two to four 1 or valid (1) bits counted, which may reflect a low branch density; or there may be twenty to thirty 1 (1) bits counted, which may reflect a high branch density. Thus, in one embodiment, the 6-bit field can hold the result reflecting the amount of predicted branches taken in the thirty-two (32) cache lines.

[0048] In another embodiment, the 5-bit field can hold the result of the bitwise addition operation performed by adder logic 48. In other words, the result can be the number of branches predicted to be taken in sixteen (16) cache lines.

[0049] The adjustment logic 50 of the I cache control logic 44 is configured to provide an adjustment from a default or previous maximum prefetch pointer count to an adjusted maximum prefetch pointer count. In one embodiment, the adjustment logic 50 includes a table of scaling values, wherein the default maximum prefetch pointer count of the feature control register is used to select a row of scaling values. The adjustment logic 50 also includes a multiplexer, wherein a branch density value is used to select which entry in the row is used for the adjusted maximum prefetch pointer count. The maximum prefetch pointer count can be set at runtime using bits (e.g., a three (3)-bit field) in the I cache control logic 44. In some embodiments, the feature control register of the I cache control logic 44 can be programmatically set at the chip fabrication plant or elsewhere based on the performance best suited for the application (e.g., sometimes referred to as a fuse, which can be adjusted via software or physically).

[0050] In one example operation, the maximum prefetch count can be set at seven (7) cache lines. Through chip computation, branch density logic 42 can determine, for example, the predicted branches for each of the last sixteen (16) cache lines as 15-16 branches. Therefore, adjustment logic 50 can adjust the maximum prefetch count to a lower number (e.g., zero) because it appears that there are branches at almost every cache line (e.g., high branch density), which means (if assumed to be sequential line fetching) wasted prefetching (and too much bandwidth consumed in prefetching from higher caches or memory). With this adjustment, communication is made via I-cache control logic 44 to prefetch logic 40, which prefetches according to the adjusted prefetch scheme (e.g., zero prefetching), thus improving performance (e.g., less wasted prefetching, reduced fetch bandwidth, reduced latency) because instructions that would otherwise be evicted are not cached. If branch density logic 42 determines that the predicted branch count is 0-2 branches per sixteen (16) cache lines (e.g., a lower branch density), the maximum prefetch pointer count may be adjusted or not adjusted (e.g., preserved or maintained (e.g., at full scale), or increased). Some cases of branch density, for example, between these two examples, may lead to throttling of the prefetch pointer scheme in a scaling manner to maintain a given performance metric. In general, adjustment logic 50 scales the maximum prefetch pointer count (e.g., initially provided via a feature control register) based on the branch density value (count) provided by branch density logic 42, where the scaled value can be any value selected from a range of branch density values, and / or in some embodiments, the selection may be based on a specific branch density value. To further illustrate with some examples, if the maximum prefetch pointer count is seven (7) fetches, and if the branch density value or count is, for example, sixteen (16), the scaled or adjusted maximum prefetch pointer count may be determined by adjustment logic 50 to be three (3). In other words, the branch density count corresponds to the scaled maximum prefetch pointer count. As another example, if the branch density count is fourteen (14) or fifteen (15) (e.g., falling within a given range), the scaled maximum prefetch pointer count can be four (4), and this can continue in this manner (e.g., if the branch density value is one (1) or two (2), the scaled maximum prefetch pointer count can be nine). Then, if the branch density value is zero (0), the scaled maximum prefetch pointer count can be ten (10). In other words, the scaled maximum prefetch pointer count determined by the adjustment logic 50 can be generated from a single value, a range of values, or a combination thereof. The chosen value can be based on a previous performance metric.In one embodiment, the maximum prefetch pointer count is any value chosen between 0 and 7 (inclusive), and the scaled or adjusted maximum prefetch pointer count is any value chosen between 0 and 10 (inclusive). Note that the values ​​described herein are for illustrative purposes only, and other values ​​may be used.

[0051] Example embodiments and corresponding operations of branch density logic 42 and I cache control logic 44 have been described (see further reference). Figure 2 In the case of) turning attention to Figure 3 This illustrates an example of a prefetch adjustment method for an embodiment of an adjustable prefetch system. In one embodiment, the prefetch adjustment method, denoted as method 52, can be implemented via branch density logic 42. Prefetch adjustment method 52 receives input (54). As indicated above, the input may be a signal at stage U indicating a sequential fetch or predicted branch instruction received at shift register 46. Prefetch adjustment method 52 provides an initial count (56) of the valid bits in shift register 46, i.e., the branch to be taken for a given parameter (e.g., a predefined number of cache lines). Prefetch adjustment method 52 determines whether there is a sequential fetch or predicted branch at the end of a cache line (58). If not (58 is "No"), this reflects a state where neither a predicted branch nor a sequential fetch at the end of a cache line exists, and the shift register holds (60), and then proceeds to (64) as described below. If present (58 is "yes"), the shift register shifts in a bit value (62) (e.g., for a predictive take, shift in a bit value of one (1), or for a sequential fetch at the end of a cache line, shift in a bit value of zero (0)), and then proceeds to (64).

[0052] At (64), the prefetch instruction adjustment method 52 determines the branch density value (branch density count) via adder logic 48, and at (66) provides the branch density value to the I cache control logic 44 to make possible adjustments based on the maximum prefetch instruction count, as explained above. Method 52 continues in a continuous manner (e.g., receiving the next input (54) for the next set of cache lines).

[0053] Note that in some embodiments... Figure 3 The order of some of the steps described can be switched between each other or performed simultaneously. In some embodiments, some steps may be omitted or additional steps may be included.

[0054] Having described certain embodiments of the adjustable prefetch system and method, it should be understood that, (in Figure 4An embodiment of the example prefetch instruction adjustment method (represented as method 68) includes: receiving input (70) corresponding to each sequential fetch and each predicted branch taken on a predetermined number of cache lines; and throttling the number of prefetched instructions based on the total count of predicted branches taken on the predetermined number of cache lines (72).

[0055] Any process description or block in the flowchart should be understood as representing a module, segment, logic, or part of code (which includes one or more executable instructions for implementing a particular logical function or step in the process), and alternative implementations are included within the scope of the embodiments, wherein, as those skilled in the art will understand, functions may be performed in a different order than shown or discussed (including substantially simultaneously or in a different order), depending on the functions involved.

[0056] Although the invention has been shown and described in detail in the accompanying drawings and the foregoing description, such drawings and descriptions should be considered illustrative or exemplary, not restrictive; the invention is not limited to the disclosed embodiments. Other variations of the disclosed embodiments will be understood and implemented by those skilled in the art in practicing the claimed invention upon study of the drawings, the disclosure, and the appended claims.

[0057] Note that various combinations of the disclosed embodiments can be used, therefore referring to an embodiment or one embodiment does not imply that the features of that embodiment are excluded from use in other embodiments. In the claims, the word "comprising" does not exclude other elements or steps.

Claims

1. A microprocessor, comprising: Instruction cache; Branch prediction logic is configured to redirect instruction fetch to a target address in the instruction cache based on the branch instruction; Branch density logic is configured to determine a branch density value based on input from the branch prediction logic by counting the number of branch instructions predicted to be taken on a predefined number of cache lines. as well as The prefetch logic is configured to load dynamically changing prefetched instructions into the instruction cache based on the determination of branch density values ​​by the branch density logic.

2. The microprocessor according to claim 1, wherein, The branch density logic is configured to determine the branch density value by counting only the branch instructions predicted to be taken on the predefined number of cache lines.

3. The microprocessor according to claim 1, wherein, The branch density logic includes a shift register configured to shift in bits of 1 for the predicted branch instruction and shift in bits of 0 for the sequential fetch at the end of the cache line.

4. The microprocessor according to claim 3, wherein, The branch density logic also includes adder logic configured to provide bitwise addition of the output of the shift register.

5. The microprocessor of claim 4 further includes instruction cache control logic, the instruction cache control logic being configured to adjust the maximum prefetch instruction count based on the determination made by the branch density logic.

6. The microprocessor according to claim 1, wherein, The prefetch logic is configured to operate based on the maximum prefetch count before the determination and based on the adjusted maximum prefetch count after the determination.

7. The microprocessor according to claim 6, wherein, The adjusted maximum prefetch count includes any value selected from multiple values ​​or a range of branch density values ​​based on the branch density value.

8. The microprocessor according to claim 1, wherein, The branch prediction logic includes a fast predictor, a branch table access cache, or a combination of the fast predictor and the branch table access cache.

9. A prefetching adjustment method for microprocessor implementation, the prefetching adjustment method comprising: Receives input corresponding to each sequential fetch and each predicted branch instruction on a predetermined number of cache lines; as well as The number of prefetched instructions is throttled based on the total count of branch instructions predicted on the predetermined number of cache lines.

10. The prefetching adjustment method according to claim 9 further includes: Load the instruction cache based on the number of prefetched instructions that are throttled.

11. The prefetching adjustment method according to claim 9, further comprising: For each instance of the predicted branch instruction on the predetermined number of cache lines, the bit value is shifted into the shift register.

12. The prefetching adjustment method according to claim 11 further includes: Perform bitwise addition on the output of the shift register's bit values.

13. The prefetching adjustment method according to claim 12 further includes: The predetermined maximum prefetch count is adjusted based on the bitwise addition.

14. The prefetching adjustment method according to claim 13, wherein, The adjustment is performed via adjustment logic.

15. The prefetch adjustment method according to claim 9 further includes: Prefetching is performed based on the maximum prefetch count before the throttling, and prefetching is performed based on the adjusted maximum prefetch count after the throttling.

16. The prefetch adjustment method according to claim 15, wherein, The adjusted maximum prefetch count includes any value selected from multiple values ​​or a range of branch density values ​​based on the branch density value.

17. The prefetching adjustment method according to claim 9, wherein, Receiving the input includes receiving instructions from the branch prediction logic for each sequential fetch and each prediction to take a branch instruction.

18. The prefetching adjustment method according to claim 17, wherein, The branch prediction logic includes a fast predictor, a branch table access cache, or a combination of the fast predictor and the branch table access cache.

19. A microprocessor, comprising: The first logic is configured to dynamically adjust the maximum prefetch instruction count based on the total count of predicted branch instructions on a predetermined number of cache lines. as well as The second logic is configured to prefetch instructions based on the adjusted maximum prefetch count.

20. The microprocessor of claim 19, further comprising an instruction cache configured to receive prefetched instructions and third logic configured to count the predicted branch instructions.

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