Dithering fmcw radar parameters to attenuate spurious signals

Abstract

A method (1200) for a radar system includes transmitting, by a transmit channel of the radar system, a frame including a first chirp, a second chirp, and a third chirp (1202). Each chirp has a chirp start frequency, and the chirp start frequencies of the transmitted chirps are dithered (1206). The method also includes receiving, by a receive channel of the radar system, a frame of reflected chirps based on the transmitted frame, and generating a digital intermediate frequency (IF) signal (1204).

Description

SUMMARY

[0001] According to at least one example of the disclosure, a method for a radar system includes transmitting, by a transmit channel of the radar system, a frame including a first chirp, a second chirp, and a third chirp. Each chirp has a chirp start frequency, and the chirp start frequencies of the transmitted chirps are dithered. The method also includes receiving, by a receive channel of the radar system, a frame of reflected chirps based on the transmitted frame, and generating a digital intermediate frequency (IF) signal.

[0002] According to another example of the disclosure, a radar system includes a radar transceiver integrated circuit (IC) having a timing engine and a local oscillator coupled to the timing engine, the timing engine configured to generate one or more chirp control signals to control generation of chirps in the radar transceiver IC. The local oscillator is configured to receive the one or more chirp control signals and generate a frame including a first chirp, a second chirp, and a third chirp, each chirp having a chirp start frequency, wherein the frame also has an idle time between the chirps. The radar transceiver IC also includes a control module coupled to the timing engine. The control module is configured to dither the start frequencies of the chirps.

[0003] According to yet another example of the disclosure, a method for a radar system includes dithering, by a control module of the radar system, chirp start frequencies of a plurality of transmitted chirps. The method also includes dithering, by the control module, sample window start times of reflected chirps generated by the transmitted chirps. Finally, the method includes dithering, by the control module, idle times between the transmitted chirps. BRIEF DESCRIPTION OF DRAWINGS

[0004] For a detailed description of various examples, reference will now be made to the accompanying drawings in which:

[0005] Figure 1 A block diagram of a radar system is shown in accordance with various examples;

[0006] Figure 2 A block diagram of a radar transceiver integrated circuit is shown in accordance with various examples;

[0007] Figure 3 Frequency versus time and amplitude versus frequency plots for chirps and spurious signals (spurs) are shown in accordance with various examples;

[0008] Figure 4 Frequency versus time and amplitude versus frequency plots for chirp and spur components of an intermediate frequency (IF) signal are shown in accordance with various examples;

[0009] Figure 5 Range-velocity plots for chirp and spur components of an IF signal are shown in accordance with various examples;

[0010] Figures 6a and 6b show the transmitter and receiver path output waveforms for various examples of chirp start frequencies with jitter and spurious chirps.

[0011] Figures 7a and 7b show additional range-velocity diagrams observed from multiple angles related to the examples in Figures 6a and 6b, based on various examples;

[0012] Figure 8 The transmitter path output waveforms for chirped start frequencies and sampling window start times with jitter are shown according to various examples.

[0013] Figures 9a-1, 9a-2, and 9b illustrate examples of the relationship between... Figure 8 Additional range-velocity plots with multiple perspectives related to the example;

[0014] Figures 10a and 10b show the transmitter path output waveforms of the chirp before and after jitter for adding idle time between chirps, according to various examples.

[0015] Figures 11a and 11b illustrate various examples related to Figures 6a and 6b. Figure 8 Additional range-velocity diagrams related to the example in Figure 10b; and

[0016] Figure 12 A flowchart illustrating the methods based on various examples is shown. Detailed Implementation

[0017] Frequency modulated continuous wave (FMCW) radar systems can be embedded in a variety of applications, such as industrial and automotive applications. For example, embedded FMCW radar systems can be included in vehicles to provide data for adaptive cruise control, collision warning, blind spot assist / warning, lane change assist, and parking assist. In other examples, embedded FMCW radar systems in industrial applications can provide data to help navigate autonomous facilities and track motion in factories.

[0018] FMCW radar systems can transmit frames containing a series of frequency ramps called chirps. These chirps can be reflected back to the FMCW radar system by target objects. Upon receiving a signal containing the reflected chirps, the FMCW radar system can down-convert, digitize, and process the received signal to determine the characteristics of the target object. When the target object is within the field of view of the FMCW radar system, these characteristics can include the target object's range, velocity, angle of arrival, etc.

[0019] In at least some FMCW radar systems, a plurality of chirp sequences (e.g., a continuous sequence of equally spaced chirps) are transmitted and reflections of these chirps are received to generate radar signals. There can be some idle time (e.g., inter-frame idle time) after each chirp sequence to allow for processing of the radar signals produced by the reflected chirps. The acquisition time of a chirp sequence and the subsequent inter-frame idle time can together form a radar frame. In at least one example, the reflected signals received by each antenna of the FMCW radar system are mixed with the transmitted signals to generate intermediate frequency (IF) signals that are filtered and digitized. The resulting digital IF signals (e.g., one digital IF signal for each receive antenna in the FMCW radar system) can then be subjected to signal processing to extract any one or more of the range, velocity, and / or angle of potential objects in the radar field of view. For example, the IF signal frequency can be directly proportional to the distance of an object, while the IF signal phase change across a chirp can be indicative of the velocity of an object.

[0020] Spurious signals (spurs) are unintended signals caused by harmonics, intermodulation, frequency conversion, or electromagnetic interference (EMI). For example, spurs are inserted into the transmitter path as fixed frequency signals by coupling higher order harmonics of a clock signal to a voltage controlled oscillator (VCO) or low noise amplifier (LNA). However, when the reflected fixed frequency spurs are mixed with the transmitted signals (chirps) to generate IF signals, the resulting IF signal frequencies vary over time, which can be incorrectly interpreted as multiple targets at different distances. Furthermore, for example, the IF signals corresponding to spurs from the clock signal experience a continuous phase shift between chirps, and thus can also be incorrectly interpreted as targets with constant velocity. In summary, while IF components corresponding to objects can have fixed frequencies, indicating objects at particular distances, IF components of spurs can have varying frequencies, incorrectly indicating objects at different distances. Similarly, while IF components corresponding to objects can have fixed phases, indicating stationary objects, IF components of spurs can have phases that shift constantly over time, incorrectly indicating objects with constant velocity.

[0021] In examples of the present disclosure, considering FMCW radar systems, one or more FMCW transmit and / or receive parameters are dithered to reduce or mitigate the effects of spurs on analyzing (an) object(s). In some examples, the chirp start frequency (i.e., the frequency at which the frequency ramp starts) or the “chirp start frequency” is dithered from one chirp to the next. This effectively dithers the IF frequency of the spurs and dithers or breaks the phase coherence of the IF component of the spur signal. As a result, the IF component of the spur signal, which as explained above has been distributed across multiple range bins, is also distributed across velocity bins. Thus, the effects of spurs on subsequent object range / velocity determinations are mitigated. However, due to the incoherence introduced by the difference in effective frequency at the sampling start time from chirp to chirp, the IF component corresponding to an object also leaks to different velocities.

[0022] To address the above issues, in addition to dithering the chirp start frequency, in some examples, the analog-to-digital conversion (ADC) sampling window start time is also dithered from one chirp to the next. When the ADC sampling window of the receiver path starts simultaneously relative to each chirp transmission, due to the chirp frequency itself being dithered, the effective start frequency of each ADC sampling window varies from chirp to chirp. To avoid signal incoherence, the ADC sampling window start time is also dithered so that the effective start frequency of the ADC sampling window is approximately the same between chirps. Thus, for objects that are stationary relative to the radar, the IF signal does not leak to other velocities. However, for objects that are moving relative to the radar, due to the variable chirp-to-chirp interval time caused by the variable ADC sampling window start time, the IF signal is falsely leaked to other velocities.

[0023] To address the above issues, in addition to dithering the chirp start frequency and the sampling window start time, in some examples, the idle time between chirps (i.e., the time from stopping transmission of one chirp to starting transmission of a subsequent chirp) is also dithered. When the idle time between chirps is fixed, due to the ADC sampling window start time varying from chirp to chirp, the effective chirp-to-chirp interval time (i.e., the time from starting the first chirp sampling window to starting the subsequent chirp sampling window) varies between chirps. In this case, due to the effective chirp-to-chirp interval time being variable, the phase of the IF signal corresponding to any moving object becomes incoherent across chirps instead of varying linearly, which is undesirable. To provide a more uniform chirp-to-chirp interval time, the idle time between chirps is also dithered. As a result, false leakage of the IF signal to other velocities is avoided for both stationary and moving objects, and the effects of spurs on subsequent object range / velocity determinations remain mitigated as above. Furthermore, in examples, the effects of synchronous spurs, asynchronous spurs, a group of multiple spurs, narrow-band noise, and other similar signals in subsequent object range / velocity determinations are also mitigated.

[0024] Figure 1 A block diagram illustrating an illustrative FMCW radar system 100 is shown. In at least one example, the FMCW radar system 100 includes a radar transceiver IC 105 and a processing unit 110. In some examples, the FMCW radar system 100 also includes a transmit antenna 115 and a receive antenna 120, while in other examples, the FMCW radar system 100 does not include but is configured to be coupled to the transmit antenna 115 and the receive antenna 120. An illustrative architecture of the radar transceiver IC 105 is illustrated in Figure 2 and described below.

[0025] In at least one example, the radar transceiver IC 105 can be referred to as a front-end of the FMCW radar system 100 and the processing unit 110 can be referred to as a back-end of the FMCW radar system 100. In at least one example, the radar transceiver IC 105 and the processing unit 110 are implemented separately and can be configured to be coupled together, while in other examples, the radar transceiver IC 105 and the processing unit 110 are implemented together, e.g., in a single chip package. In at least one example, the processing unit 110 is coupled to the radar transceiver IC 105 via an interface 125, which can facilitate any suitable communication method (e.g., a serial interface or a parallel interface) and is configured to receive data from and / or send data to the radar transceiver IC 105.

[0026] In at least one example, the interface 125 can be a high-speed serial interface such as a low-voltage differential signaling (LVDS) interface. In another example, the interface 125 can be a low-speed interface such as a serial peripheral interface (SPI). In at least one example, the radar transceiver IC 105 includes functionality to generate one or more digital IF signals (alternatively referred to as dechirped signals, beat signals, or raw radar signals) from a reflected chirp received via the receive antenna 120. Further, in at least one example, the radar transceiver IC 105 includes functionality to perform at least a portion of signal processing on radar signals (e.g., the reflected chirp and / or the digital IF signals) received in the radar transceiver IC 105 and provide results of that signal processing to the processing unit 110 via the interface 125. In at least one example, the radar transceiver IC 105 performs a range Fast Fourier Transform (FFT) on each receive frame (e.g., each chirp sequence of a frame) of the radar transceiver IC 105. In at least some examples, the radar transceiver IC 105 also performs a Doppler FFT on each receive frame of the radar transceiver IC 105 (e.g., after performing the range FFT and on results of the range FFT). The combination of the range FFT and the Doppler FFT can be referred to as a two-dimensional (2D) FFT (or 2D FFT processing).

[0027] In at least one example, the processing unit 110 includes functionality to process data received from the radar transceiver IC 105 to, for example, determine any one or more of a distance, a velocity, and / or an angle of any objects detected by the FMCW radar system 100. In some examples, the processing unit 110 can also or instead include functionality to perform post-processing of information regarding detected objects, such as tracking objects, determining rates and directions of motion, etc. In at least one example, the processing unit 110 determines a distance and a velocity of a detected object, for example, in accordance with various aspects of the present disclosure, in which parameters of the FMCW radar system 100 are dithered. Examples of the present disclosure can include dithering a chirp start frequency from one chirp to the next, dithering an ADC sample window start time from one chirp to the next, and dithering an idle time between chirps. As a result of dithering various parameters of the FMCW radar system 100, IF signal leakage to other velocities is avoided for both stationary and moving objects, which mitigates the impact of spurious signals on object distance / velocity determinations. In various examples, the processing unit 110 includes any one or more suitable processors or combinations of processors needed to process data received from and / or provide data to the radar transceiver IC 105. For example, the processing unit 110 can include one or more of a digital signal processor (DSP), a microcontroller, a system-on-a-chip (SOC) incorporating DSP and microcontroller processing, a field programmable gate array (FPGA), or any combination of the above.

[0028] Reference is now made to Figure 2 , which shows a block diagram of an illustrative radar transceiver IC 200. In at least some examples, the radar transceiver IC 200 is suitable for implementation as the radar transceiver IC 105 of the FMCW radar system 100 of Figure 1 . In other examples, the radar transceiver IC 200 is suitable for implementation in other radar systems. In at least one example, the radar transceiver IC 200 includes one or more transmit channels 204 and one or more receive channels 202A-202N (where N is any positive integer). Each of the transmit channel 204 and the receive channels 202A-202N can be individually coupled to a transmit antenna or a receive antenna, respectively, such as the transmit antennas 115 or the receive antennas 120, as discussed above with respect to Figure 1 and not shown in Figure 2 . Although illustrated as including two receive channels 202A and 202N and one transmit channel 204 for simplicity, in various examples, the radar transceiver IC 200 can include any suitable number of receive channels 202N and / or any suitable number of transmit channels 204. Further, the number of receive channels 202N and the number of transmit channels 204 can be different numbers.

[0029] In at least one example, the transmit channel 204 includes a power amplifier (PA) 207 coupled between a transmit antenna (not shown) and the I / Q modulator 250 to amplify an output of the I / Q modulator 250 for transmission via the transmit antenna. In at least some examples, each additional transmit channel 204 can be substantially similar and can be coupled to its own respective transmit antenna (not shown) or to the same transmit antenna.

[0030] In at least one example, the first receive channel 202A includes a low noise amplifier (LNA) 203A coupled between a receive antenna (not shown) and the mixer 206A to amplify a radio frequency (RF) signal (e.g., a reflected chirp) received via the receive antenna prior to providing the amplified signal to the mixer 206A. In at least one example, the mixer 206A is coupled to the clock multiplier 240 and configured to receive a clock signal from the clock multiplier 240, e.g., to mix with the received RF signal to generate an IF signal. In at least one example, a baseband bandpass filter 210A is coupled to the mixer 206A and configured to filter the IF signal, a variable gain amplifier (VGA) 214A is coupled to the baseband bandpass filter 210A and configured to amplify the filtered IF signal, and an analog-to-digital converter (ADC) 218A is coupled to the VGA 214A and configured to convert the analog IF signal to a digital IF signal. The baseband bandpass filter 210A, the VGA 214A, and the ADC 218A of the respective receive channel 202A can be collectively referred to as an analog baseband, a baseband chain, a complex baseband, or a baseband filter chain. Further, the baseband bandpass filter 210A and the VGA 214A can be collectively referred to as an IF amplifier (IFA). In at least some examples, each additional receive channel 202N can be substantially similar to the first receive channel 202A and can be coupled to its own respective receive antenna (not shown) or to the same receive antenna. In at least one example, the ADC 218A is coupled to a digital front end (DFE) 222, e.g., to provide the digital IF signal to the DFE 222. In at least one example, the DFE 222 (which can also be referred to as a digital baseband) includes functionality to perform decimation filtering or other processing operations on the digital intermediate frequency signal, e.g., to reduce a data transfer rate of the digital IF signal. In various examples, the DFE 222 can also perform other operations on the digital IF signal, such as direct current (DC) offset removal and / or compensation for non-idealities in the receive channels 202A-202N (e.g., digital compensation), such as inter-receiver gain imbalance non-idealities, inter-receiver phase imbalance non-idealities, etc. In at least one example, the DFE 222 is coupled to the signal processor 244 and configured to provide an output of the DFE 222 to the signal processor 244.

[0031] In at least one example, the signal processor 244 is configured to perform at least a portion of signal processing on the digital IF signals produced by the received radar frames and transmit the results of that signal processing via the terminals 252 and / or 254. In at least one example, the signal processor 244 transmits the results of the signal processing to a processing unit (not shown), such as the processing unit 110 described above with respect to Figure 1 In various examples, the results are provided from the signal processor 244 to the terminals 252 and / or 254 via the high-speed interface 224 and / or the SPI 228, respectively. In at least one example, the signal processor 244 performs a range FFT on each chirp sequence in the received radar frames to generate a range array. In at least one example, the signal processor 244 additionally performs a Doppler FFT on the results of the range FFT to generate a range-Doppler array.

[0032] The signal processor 244 can include any suitable processor or combination of processors. For example, the signal processor 244 can be a DSP, a microcontroller, an FFT engine, a DSP plus microcontroller processor, an FPGA, or an application specific integrated circuit (ASIC). In at least one example, the signal processor 244 is coupled to the memory 248, such as to store intermediate results of the portion of signal processing performed on the digital IF signals in the memory 248 and / or to read instructions from the memory 248 for execution by the signal processor 244.

[0033] In at least one example, the memory 248 provides on-chip storage (e.g., a computer readable medium) that can be used, for example, to transfer data between various components of the radar transceiver IC 200, to store software programs executed by processors on the radar transceiver IC 200, etc. The memory 248 can include any suitable combination of read-only memory (ROM) and / or random access memory (RAM), such as static RAM. In at least one example, a direct memory access (DMA) component 246 is coupled to the memory 248 to perform data transfers from the memory 248 to the high-speed interface 224 and / or the SPI 228.

[0034] In at least one example, the SPI 228 provides an interface for communication between the radar transceiver IC 200 and another device (e.g., a processing unit of the processing unit 110, such as the processing unit 110 described above with respect to Figure 1 For example, the radar transceiver IC 200 can receive control information via the SPI 228, such as the timing and frequency of chirps, output power levels, triggers for monitoring functions, etc. In at least one example, the radar transceiver IC 200 can transmit test data to the processing unit 110 via the SPI 228, for example.

[0035] In at least one example, the control module 226 includes functionality to control at least a portion of the operation of the radar transceiver IC 200. The control module 226 can include, for example, a microcontroller executing firmware to control the operation of the radar transceiver IC 200. The control can be, for example, to provide data parameters to other components of the radar transceiver IC 200 and / or to provide control signals to other components of the radar transceiver IC 200.

[0036] In at least one example, the programmable timing engine 242 includes functionality to receive chirp parameter values for a series of chirps in a radar frame from the control module 226 and generate chirp control signals that control transmission and reception of the chirps in the frame based on the parameter values. In some examples, the chirp parameters are defined by the radar system architecture and can include, for example, transmitter enable parameters to indicate which transmit channels are enabled, a chirp frequency start value, a chirp frequency slope, an ADC sample time, a ramp end time, a transmitter start time, etc. In examples of the present disclosure, the control module 226 and the programmable timing engine 242 are configured to dither the chirp start frequency, the ADC sample window start time (e.g., when to start sampling data received from the ADC 218A), and / or the idle time between chirps. For example, when dithering the chirp start frequency, the control module 226 causes the programmable timing engine 242 to initiate a first chirp at a first chirp frequency start value and a second chirp at a second chirp frequency start value that is different than the first chirp frequency start value. In another example, when dithering the ADC sample window start time, the control module 226 causes the programmable timing engine 242 to start sampling data received from the ADC 218 at different times relative to the first chirp and the second chirp such that the effective start frequency of the ADC sample window from chirp to chirp is approximately the same when considering the dithered chirp start frequency, as described above. In yet another example, when dithering the idle time between chirps, the control module 226 causes the programmable timing engine 242 to vary the idle time between chirps such that a first idle time between the first chirp and the second chirp is different than a second idle time between the second chirp and a third chirp such that the effective chirp interval time from chirp to chirp is approximately the same when considering the dithered chirp start frequency and the ADC sample window start time, as described above.

[0037] In at least one example, radio frequency synthesizer (RFSYNTH) 230 includes functionality to generate signals for transmission (e.g., chirps and / or sequences of chirps) based on chirp control signals received from programmable timing engine 242. In some examples, RFSYNTH 230 includes a phase-locked loop (PLL) having a voltage-controlled oscillator (VCO). In at least one example, RFSYNTH 230 can be referred to as a local oscillator (LO). Control module 226 and programmable timing engine 242 are configured to control RFSYNTH 230 to dither a chirp start frequency, e.g., to generate a first chirp having a first chirp frequency start value and to generate a second chirp having a second chirp frequency start value different from the first chirp frequency start value.

[0038] In at least one example, multiplexer 232 is coupled to RFSYNTH 230 and input buffer 236 and is configurable to select between a signal received from input buffer 236 of an external component (not shown) and a signal generated by RFSYNTH 230. In at least one example, output buffer 238 is coupled to multiplexer 232 and can, for example, provide a signal selected by multiplexer 232 to an input buffer of another radar transceiver IC (not shown). In at least one example, multiplexer 232 is controlled by control module 226 via selection of a signal.

[0039] In at least one example, clock multiplier 240 increases a frequency of an output of multiplexer 232 (e.g., an output of RFSYNTH 230) to an operating frequency of mixer 206A. In at least one example, clean-up PLL 234 is configured to increase a frequency of a signal of an external low frequency reference clock (not shown) received by radar transceiver IC 200 to a frequency of RFSYNTH 230 and to filter out reference clock phase noise in the reference clock signal.

[0040] In at least one example, I / Q modulator 250 is further coupled to digital-to-analog converters (DACs) 356 and 358, each of which can be coupled to control module 326.

[0041] Figure 3A frequency versus time plot 302 is shown for the transmitted chirp 304 and the spur 306. A corresponding amplitude versus frequency plot 310 is also shown for the chirp 304 (shown at times a-f) and the spur 306. Referring to plot 302, as described above, the transmitted chirp 304 is a linear frequency ramp as a function of time. The spur 306, on the other hand, is a fixed frequency component. Plot 310 reinforces this distinction, where the spur 306 comprises a single frequency component, while the transmitted chirp frequency varies over time, denoted as 304a-f, which can correspond to, for example, the amplitude of the transmitted chirp 304 frequency at 0 us, 1 us, 2 us, 3 us, 4 us, and 5 us, respectively.

[0042] As one example, the chirp 304 can have a starting frequency of 77 GHz and a slope of 10 MHz / us, while the spur 306 can have a fixed frequency of approximately 77.03 GHz. As an example of the mixer 206 generating an IF signal in the absence of the spur 306, assume that the chirp plot 304 is reflected off an object from the perspective of the FMCW radar system 100 and the round trip is 0.2 us (e.g., the object distance is approximately 30 meters). The difference between the transmitted chirp 304 frequency (or transmitter path output frequency) and the reflected chirp 304 frequency (receiver path input frequency) will be 2 MHz, or 10 MHz / us of the chirp 304 slope * 0.2 us of round trip time. Thus, in the absence of the spur 306, a 2 MHz IF signal frequency component corresponds to a 0.2 us round trip time and an object distance of approximately 30 meters. However, as described above, the presence of the fixed frequency spur 306 results in multiple additional frequency components in the resulting IF signal that erroneously appear as objects at different distances.

[0043] Figure 4 the distance-based problems caused by the spur 306 of Figure 3 . Figure 4 A frequency versus time plot 402 is shown for an IF component 404 corresponding to an object (assume a stationary object) and an IF component 406 corresponding to the spur. As described above, for a stationary object, the IF component 404 frequency corresponding to the object is also fixed. The IF component 406 frequency corresponding to the spur, on the other hand, increases linearly over time because the transmitter path output frequency (i.e., the generated chirp) is a linear ramp, while the reflected spur component remains at a fixed frequency.

[0044] Figure 4Also shown is an amplitude versus frequency plot 410 of the IF component 404 corresponding to the object and the IF component 406 corresponding to the clutter (shown at times a-e). The frequency of the IF component 404 corresponding to the object represents the distance of the stationary object (30 meters in the example above). However, the presence of the IF components 406a-e corresponding to the time-varying clutter results in false determinations or identifications of objects at multiple distances. Furthermore, while the IF components 406a-e corresponding to the clutter are shown as discrete, in reality these can be continuous as the transmitter path output frequency is constantly increasing linearly over time while the receiver path input frequency (i.e. fixed frequency clutter) remains constant. The IF components 406 corresponding to the clutter also experience a constant phase shift, which as described above, causes it to appear as an object moving at a constant velocity.

[0045] Figure 5 A range-velocity plot 500 is shown as a function of receiver path output power (dB) further indicating the false range-based and velocity-based issues caused by the IF components 406 of the clutter 306 as described above. The range-velocity plot 500 includes an object peak 502 as a result of the IF component 404 corresponding to the object with a velocity of 0 m / s at a fixed distance. The range-velocity plot 500 also includes clutter ridges 504, 506 as a result of the IF component(s) 406 corresponding to the clutter. As described above, the IF component(s) 406 appear as objects at multiple distances, reflected by the ridges 504, 506 spanning multiple bins on the range axis. Furthermore, the IF component(s) 406 appear as objects with constant velocities, reflected by the position of the ridges 504, 506 along the velocity axis. These false “objects” created by the clutter 306 and the IF components 406 are problematic in various radar applications. Figure 4 Figure 4 Figure 3 The IF components 406 corresponding to the clutter 306 of the radar system 100 as described above. The range-velocity plot 500 includes an object peak 502 as a result of the IF component 404 corresponding to the object with a velocity of 0 m / s at a fixed distance. The range-velocity plot 500 also includes clutter ridges 504, 506 as a result of the IF component(s) 406 corresponding to the clutter. As described above, the IF component(s) 406 appear as objects at multiple distances, reflected by the ridges 504, 506 spanning multiple bins on the range axis. Furthermore, the IF component(s) 406 appear as objects with constant velocities, reflected by the position of the ridges 504, 506 along the velocity axis. These false “objects” created by the clutter 306 and the IF components 406 are problematic in various radar applications.

[0046] As described above, the chirp start frequency is dithered from one chirp to the next, which effectively dithers the frequency of the IF component of the clutter signal and dithers or destroys the phase coherence of the IF component of the clutter signal. FIG. 6a shows a frequency versus time plot 600 including a first transmitted chirp 602, a second transmitted chirp 604, and a third transmitted chirp 606, where the chirp start frequency is dithered from one chirp to the next. Furthermore, the clutter 608 is shown and explained above as a fixed frequency clutter.

[0047] FIG. 6b shows a frequency versus time plot 700 of the IF component 702 of the radar system 100 of FIG. 1, including the first transmitted chirp 602, the second transmitted chirp 604, and the third transmitted chirp 606, where the chirp start frequency is dithered from one chirp to the next. Furthermore, the clutter 608 is shown and explained above as a fixed frequency clutter. Figure 6A ​​The frequency and time diagram 610 illustrates the receiver path IF signal generated by the jittered chirps 602, 604, 606 and the fixed-frequency spurious signal 608. Specifically, assuming a static object, the reflected chirps will all have a constant difference from the transmitted chirps 602, 604, 606, and therefore the IF component 612 corresponding to the chirp will also be constant (e.g., 2 MHz in the example above). However, since the fixed-frequency spurious signal 608 is being compared with or (e.g., mixed by mixer 206) the jittered frequency chirps 602, 604, 606, the resulting IF components 614, 616, 618 corresponding to the spurious signal are also jittered. As a result of the jittered IF components 614, 616, 618, the phase coherence of the IF components 614, 616, 618 is also jittered or disrupted. For example, the jittered chirp initiation rate causes the initial phase of the signal in each range interval to jitter within the chirp. Because the phase difference between the intervals from one chirp to the next is non-uniform, it no longer appears as a constant velocity signal, but rather as a signal with different velocities from chirp to chirp. Breaking the phase consistency of the IF components 614, 616, and 618, corresponding to spurious signals, spreads their effects across the velocity intervals, thus mitigating the effects such as… Figure 5 The effects of spines 504 and 506 shown and described above.

[0048] Figures 7a and 7b show a comparison of range-velocity plots as a function of receiver path output power (dBm) before and after the chirp-start frequency jitter 700 and after the chirp-start frequency jitter 720. Range-velocity plot 700 vs. Figure 5 The same as Figure 500 in the figure is reproduced here for clarity. Figures 7a and 7b also show a comparison of speed versus output power plots before the chirp initiation frequency jitter 710 and after the chirp initiation frequency jitter 730. In the speed versus output power plot before the chirp initiation frequency jitter 710, peak 712 corresponds to the IF component corresponding to the chirp (and is similar to...). Figure 5 Peak 502 (viewed along the velocity axis), while peaks 714 and 716 correspond to the stray IF components (and are similar to...). Figure 5 Ridges 504 and 506 (observed along the velocity axis). As shown in the range-velocity plot after the chirping initiation frequency jitter of 720, Figure 5 The ridges present in (504, 506) have been mitigated or diffused across various velocity values. However, the velocity versus output power plot after the chirp-initiated frequency jitter of 730 indicates that the IF component corresponding to the chirp has leaked into other velocity values ​​(e.g., due to the aforementioned effect of jitter on phase coherence), even though, in reality, the object represented by the IF signal is stationary.

[0049] As mentioned above, in addition to dithering the chirp start frequency, in some examples, the ADC sample window start time is also dithered from one chirp to the next. Figure 8 A frequency versus time plot 600 is shown of Figure 6a with different ADC sample window start times 802, 804, 806 for the chirps 602, 604, 606 respectively. In particular, the ADC sample window start times 802, 804, 806 are selected relative to each chirp 602, 604, 606 so that the effective start frequency of each ADC sample window is approximately the same, as indicated by the frequency intercept line 810, which avoids signal inconsistency. In an example, by dithering the ADC sample window start time together with the chirp start frequency, phase coherence from chirp to chirp can be maintained for the IF signal even if the chirp start frequency is dithered.

[0050] Figures 9a-1 and 9a-2 show a comparison of range-velocity plots 700, 900 as a function of receiver path output power (dBm) before (700) and after (900) dithering of the chirp start frequency and sample window start time. Figures 9a-1 and 9a-2 also show a comparison of velocity versus output power plots 710, 910 before (710) and after (910) dithering of the chirp start frequency and sample window start time. The range-velocity plots 700 and velocity versus output power plots 710 are the same as in Figures 7a and 7b. As the range-velocity plot 900 and velocity versus output power plot 910 demonstrate, the effects of spurs are still mitigated as before. In addition, as best depicted in the velocity versus output power plot 910, for stationary objects, the chirp components no longer leak to other velocity values, and the signal coherence / consistency is improved due to the dithering of the sample start window time as relative to the chirp start frequency. Figure 8 The described dithering of the sample start window time results in an improvement.

[0051] Figure 9b shows a comparison of velocity versus output power plots before and after dithering 920, 930 of the chirp start frequency and sample window start time respectively, but in this case for moving objects. Dithering the chirp start frequency and sample window start time solves the problem of leakage to other velocities for stationary objects. However, as can be seen by comparing the plot 930 and the plot 920, this double dithering approach still results in signal leakage to other velocities for moving objects. This signal leakage is due to unintentional modulation of the chirp interval time, which will be explained more fully below.

[0052] FIG. 10a shows a frequency versus time plot of a frame 1000 (or portion of a frame) including chirps 1002, 1012, 1022. In frame 1000, the chirp start frequency and the ADC sample window start time are dithered, as described above. For example, chirp 1002 starts at frequency Fl, while chirp 1012 starts at frequency F3 and chirp 1022 starts at frequency F2.

[0053] With respect to the dithered ADC sample window start times, the sample window for chirp 1002 starts at point 1004, which is relatively far in time from the start of chirp 1002, and ends at point 1006. The sample window for chirp 1012 starts at point 1014, which is relatively close in time to the start of chirp 1012, and ends at point 1016. The sample window for chirp 1022 starts at point 1024, which is delayed from the start of chirp 1022, approximately between the delays from the start of the previous two chirps 1002, 1012 at points 1004 and 1014, respectively. The sample window for chirp 1022 ends at point 1026. As described above, the sample window start times at points 1004, 1014, 1024 are chosen such that the frequencies at those times for the respective chirps 1002, 1012, 1022 are approximately equal (e.g., at frequency F4).

[0054] In FIG. 10a, the idle times between chirps 1002, 1012, 1022 are approximately equal. For example, the idle time 1034 between the end of chirp 1002 and the start of chirp 1012 is approximately equal to the idle time 1036 between the end of chirp 1012 and the start of chirp 1022. As a result, the chirp interval time, or the time from the sample window start time of one chirp to the sample window start time of the next chirp, varies between chirps. For example, the chirp interval time 1030 between the sample window start time at point 1004 of chirp 1002 and the sample window start time at point 1014 of chirp 1012 is less than the chirp interval time 1032 between the sample window start time at point 1014 of chirp 1012 and the sample window start time at point 1024 of chirp 1022. As described above, this unintentional modulation of the chirp interval times 1030, 1032 results in signal leakage to other velocities of the moving object. For example, a constant velocity moving object moves an uneven distance from one chirp sample to the next chirp sample, and thus the phase of the IF signal of the constant velocity moving object also changes between one chirp sample to the next chirp sample, resulting in leakage in the velocity axis.

[0055] Figure 10b shows a frequency versus time plot of a frame 1050 (or a portion of a frame) in which the idle time between chirps is also dithered. Frame 1050 includes chirps 1052, 1062, 1072. In frame 1050, the chirp start frequency and the ADC sample window start time are also dithered, as explained above with respect to Figure 10a. In addition, in frame 1050, the idle time between chirps is dithered, so the idle time 1084 between chirps 1052, 1062 is longer in duration than the idle time 1086 between chirps 1062, 1072. As a result, while the dithering of the chirp start frequency and the ADC sample window start time alone would cause unintentional modulation of the chirp interval time, the chirp interval time 1080 between the sample window start time 1054 of chirp 1052 and the sample window start time 1064 of chirp 1062 is approximately equal to the chirp interval time 1082 between the sample window start time 1064 of chirp 1062 and the sample window start time 1074 of chirp 1072.

[0056] Figures 11a and 11b show a comparison of range-velocity plots 1100, 1110, 1120, 1130 as a function of receiver path output power (dBm) without dithering (1100); dithering the chirp start frequency (1110, single dithering example); dithering the chirp start frequency and the ADC sample window start time (1120, double dithering example); dithering the chirp start frequency, the ADC sample window start time, and the idle time between chirps (1130, triple dithering example). As explained above with respect to Figures 7a and 7b, in the undithered plot 1100, the spur appears as a ridge that spans multiple range bins at a particular constant velocity. In addition, as described with respect to Figures 7a and 7b, in the single dithered plot 1110, the spur is spread out in the velocity bins, mitigating their impact on the range-velocity plot. However, the IF component corresponding to the object leaks to other velocities. In the exemplary double dithered plot 1120 (shown here for a moving object), the IF component corresponding to the object still leaks to other velocities, although this is not the case for a stationary object. Finally, in the exemplary triple dithered plot 1130, the spur remains mitigated, and the IF component corresponding to the object no longer leaks to other velocities. In short, when triple dithering is applied, the IF component corresponding to the object is easily identifiable in plot 1130, without being affected by the spur. Figure 5

[0057] Figure 12 A flowchart showing an example method 1200 for mitigating spurious signals in a FMCW radar system 100, including a radar system 100 as described above with respect to Figures 1-10, is shown. The method 1200 includes dithering 1202 a chirp start frequency of a chirp in a range of frequencies. The method 1200 also includes dithering 1204 an ADC sample window start time of the chirp in a range of times. The method 1200 also includes dithering 1206 an idle time between the chirp and a next chirp in the range of times. Figure 1 Figure 2 ​​The radar transceiver IC 200 described in the middle. The method 1200 begins in block 1202, transmitting a frame including a first chirp, a second chirp, and a third chirp. For example, the transmit channel 204 transmits the first chirp, the second chirp, and the third chirp based on input from the control module 226, the timing engine 242, and the RFSYNTH 230. As described above, each chirp has a chirp start frequency and the frame includes an idle time between the chirps. The method 1200 continues in block 1204, receiving a frame of reflected chirps based on the transmitted frame and generating a digital intermediate frequency (IF) signal. For example, the receive channel 202 receives the reflected chirps and the mixer 206 mixes a clock signal from the clock multiplier 240 with a received RF signal corresponding to the reflected chirps to generate the IF signal. Each first reflected chirp, second reflected chirp, and third reflected chirp has a sampling window start time.

[0058] The method 1200 continues in block 1206, dithering the chirp start frequencies of the transmitted chirps. For example, the control module 226 causes the programmable timing engine 242 to initiate the first chirp at a first chirp frequency start value and the second chirp at a second chirp frequency start value different from the first chirp frequency start value. In some examples, the method 1200 further continues in block 1208, dithering the sampling window start times of the reflected chirps. For example, the control module 226 starts sampling data received from the ADC 218 at different times relative to the first chirp and the second chirp, such that the effective start frequency of the ADC sampling window is approximately the same from chirp to chirp when considering the dithered chirp start frequencies. In another example, the method 1200 continues in block 1210, dithering the idle times between the transmitted chirps. For example, the control module 226 causes the programmable timing engine 242 to vary the idle times between the chirps, such that a first idle time between the first chirp and the second chirp is different from a second idle time between the second chirp and the third chirp, such that the effective inter-chirp interval time is approximately the same from chirp to chirp when considering the dithered chirp start frequencies and the ADC sampling window start times.

[0059] While the above discussion generally relates to synchronous clutter, the described dithering radar parameters can also mitigate similar effects caused by asynchronous clutter, a group of multiple clutters, narrowband noise, and other similar signals on subsequent object range / velocity determinations. In the above discussion and claims, the term“including” is used in the sense of“including, but not limited to,” such that an item listed is not the only item encompassed by the term. Furthermore, the term“coupled” is intended to mean either an indirect or direct connection. Thus, if a first device is coupled to a second device, that connection can be through a direct connection or through an indirect connection via other devices and connections. Similarly, a device coupled between a first component or location and a second component or location can be coupled through a direct connection or through an indirect connection via other devices and connections. An element or feature that is“configured to” perform a task or function can either be manufactured to perform that function or be reconfigurable to perform that function, e.g., having a structure that is changed from a default configuration to perform the function or having a structure that is changed dynamically to perform the function. A device configured to perform a task can also be referred to as being programmed to perform the task. The configuration can be through firmware and / or software programming of the device, through a construction and / or layout of hardware components of the device, or a combination thereof. Furthermore, the phrase“ground” or similar phrase as used in the above discussion is intended to encompass chassis ground, earth ground, floating ground, virtual ground, digital ground, common ground, and / or any other form of grounding appropriate or suitable to the teachings of the present disclosure. Unless otherwise stated, “about,”“approximately,” or“substantially” preceding a value means + / - 10% of the stated value.

[0060] The above discussion is intended to explain the principles of the present disclosure and various embodiments. Many variations and modifications will become apparent to those skilled in the art upon reading the above discussion, which is intended to be illustrative only. The claims are intended to cover all such variations and modifications.

Claims

1. A method for a radar system, the method comprising: transmitting, by a transmit channel of the radar system, a frame comprising a first chirp, a second chirp, and a third chirp, each chirp having a chirp start frequency, wherein the chirp start frequencies of the transmitted chirps are dithered; receiving, by a receive channel of the radar system, a frame of reflected chirps based on the transmitted frame and generating a digital intermediate frequency (IF) signal; and dithering a sample window start time of the reflected chirps such that a first duration between a sample window start time of a first reflected chirp and a sample window start time of a second reflected chirp is within 10% of a second duration between the sample window start time of the second reflected chirp and a sample window start time of a third reflected chirp.

2. The method of claim 1, wherein the frame of transmitted chirps has a first idle time between an end of a first transmitted chirp and a start of a second transmitted chirp and a second idle time between an end of the second transmitted chirp and a start of a third transmitted chirp, wherein the method further comprises setting the first idle time and the second idle time such that a difference between the first idle time and the second idle time is within 10% of the first idle time.

3. The method of claim 1, wherein at each sample window start time, a difference between a frequency of the first reflected chirp and a frequency of the second reflected chirp is within 10% of the frequency of the first reflected chirp and a difference between the frequency of the first reflected chirp and a frequency of the third reflected chirp is within 10% of the frequency of the first reflected chirp.

4. The method of claim 1, wherein, the frame of transmitted chirps further has an idle time between the transmitted chirps, the method further comprising dithering the idle time between the transmitted chirps.

5. The method of claim 1, further comprising: performing a range fast Fourier transform (FFT) on the digital IF signal to generate a range array.

6. The method of claim 1, further comprising: performing a two-dimensional FFT on the digital IF signal to generate a range Doppler array.

7. A radar system comprising: a radar transceiver integrated circuit (IC) comprising: a timing engine configured to generate one or more chirp control signals for controlling generation of chirps in the radar transceiver IC; a local oscillator coupled to the timing engine, the local oscillator configured to: receive the one or more chirp control signals; and transmit a frame comprising a first chirp, a second chirp, and a third chirp, each chirp having a chirp start frequency; and a control module coupled to the timing engine, the control module configured to dither the chirp start frequencies of the chirps and to dither a sample window start time of an analog-to-digital converter (ADC) for reflected chirps received by the radar transceiver IC; wherein the control module is configured to jitter the sampling window start times such that a first duration between a sampling window start time of a first reflected chirp and a sampling window start time of a second reflected chirp and a second duration between the sampling window start time of the second reflected chirp and a sampling window start time of a third reflected chirp are within 10% of the first duration; wherein at each sampling window start time, a difference between a frequency of the first reflected chirp and a frequency of the second reflected chirp is within 10% of the frequency of the first reflected chirp and a difference between the frequency of the first reflected chirp and a frequency of the third reflected chirp is within 10% of the frequency of the first reflected chirp.

8. The radar system of claim 7, wherein, a frame of transmitted chirps has a first idle time between an end of a first transmitted chirp and a start of a second transmitted chirp and a second idle time between an end of the second transmitted chirp and a start of a third transmitted chirp, wherein the first idle time and the second idle time are set such that a difference between the first idle time and the second idle time is within 10% of the first idle time.

9. The radar system of claim 8, wherein, the control module is further configured to jitter the idle times between the transmitted chirps.

10. The radar system of claim 9, further comprising a processing unit coupled to the radar transceiver IC, the processing unit configured to perform a range Fast Fourier Transform (FFT) on a digital intermediate frequency (IF) signal received from the ADC to generate a range array.

11. The radar system of claim 10, wherein the processing unit is further configured to perform a two-dimensional FFT on the digital IF signal to generate a range Doppler array.

12. A method for a radar system, comprising: jittering, by a control module of the radar system, a chirp start frequency of a plurality of transmitted chirps; and jittering, by the control module, a sampling window start time of each of a plurality of reflected chirps corresponding to the plurality of transmitted chirps such that a first duration between a sampling window start time of a first reflected chirp and a sampling window start time of a second reflected chirp and a second duration between the sampling window start time of the second reflected chirp and a sampling window start time of a third reflected chirp are within 10% of the first duration; wherein at each sampling window start time, a difference between a frequency of the first reflected chirp and a frequency of the second reflected chirp is within 10% of the frequency of the first reflected chirp and a difference between the frequency of the first reflected chirp and a frequency of the third reflected chirp is within 10% of the frequency of the first reflected chirp.

13. The method of claim 12, further comprising: generating a digital intermediate frequency (IF) signal based on the reflected chirps; and performing a range Fast Fourier Transform (FFT) on the digital IF signal to generate a range array.

14. The method of claim 12, further comprising: generating a digital intermediate frequency (IF) signal based on the reflected chirps; and performing a two-dimensional FFT on the digital IF signal to generate a range Doppler array.

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