Intra prediction mode partitioning

Abstract

A method and apparatus for performing intra-frame prediction mode partitioning, wherein pixels of a video coding block are predicted using multiple intra-frame prediction modes across multiple regions of the video coding block. The prediction can be based on a reference array using at least one reference row above the block to be decoded and / or using at least one reference column to the left of the block to be decoded. Different prediction modes are used in different regions of the coding block. In at least one embodiment, in addition to having multiple intra-frame prediction modes for different regions of the block, the video coding block is also divided into multiple partitions. Signaling enables a decoder to determine the number of regions within a coding block. In at least another embodiment, the allowable prediction modes within a region of the video coding block differ by an angular position.

Description

Technical Field

[0001] At least one embodiment of the present invention generally relates to a method or apparatus for video encoding or decoding. Background Art

[0002] To achieve high compression efficiency, image and video coding schemes typically employ prediction (including spatial and / or motion vector prediction) and transforms to exploit spatial and temporal redundancy in video content. Typically, intra-frame or inter-frame prediction is used to exploit intra-frame or inter-frame correlations, followed by transforming, quantizing, and entropy decoding the difference between the original image and the predicted image, typically represented as a prediction error or prediction residual. To reconstruct the video, the compressed data is decoded through the inverse processes corresponding to entropy decoding, quantization, transforming, and prediction. Summary of the Invention

[0003] The shortcomings and disadvantages of the prior art are addressed by the main aspects described herein, which relate to intra prediction mode partitioning in encoding and decoding.

[0004] According to a first aspect, a method for encoding a video data block is provided, comprising the steps of: predicting pixels in a plurality of regions of the video data block by intra prediction, wherein corresponding regions use different intra prediction modes; and encoding the plurality of regions using the predictions.

[0005] According to a second aspect, a method for encoding a video data block is provided, comprising the steps of predicting pixels in a plurality of regions of the video data block by intra prediction, wherein corresponding regions use different intra prediction modes; and encoding the plurality of regions using the predictions.

[0006] According to another aspect, a device is provided. The device includes a processor. The processor can be configured to encode a block of video or decode a bitstream by performing any of the above methods.

[0007] According to another main aspect of at least one embodiment, there is provided an apparatus comprising the apparatus according to any of the decoding embodiments; and at least one of: (i) an antenna configured to receive a signal comprising the video block, (ii) a band limiter configured to limit the received signal to a frequency band comprising the video block, or (iii) a display configured to display an output representing the video block.

[0008] According to another main aspect of at least one embodiment, a non-transitory computer-readable medium is provided that contains data content according to any of the described encoding embodiments or variations.

[0009] According to another main aspect of at least one embodiment, there is provided a signal comprising video data generated according to any of the described encoding embodiments or variations.

[0010] According to another main aspect of at least one embodiment, a bitstream is formatted to include data content generated according to any of the described encoding embodiments or variations.

[0011] According to another main aspect of at least one embodiment, there is provided a computer program product comprising instructions that, when executed by a computer, cause the computer to perform any of the described decoding embodiments or variations.

[0012] These and other aspects, features and advantages of the principal aspects will become apparent from the following detailed description of exemplary embodiments which is to be read in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 Reference samples used for intra prediction in VTM are shown.

[0014] Figure 2 Multiple reference lines used for intra prediction in VTM are shown.

[0015] Figure 3 The intra prediction directions in the VTM for a square target block are shown.

[0016] Figure 4 An example of partitioning a block according to the described general aspects is shown.

[0017] Figure 5 Another example of partitioning a block according to the described general aspects is shown.

[0018] Figure 6 A symmetrical horizontal and vertical split into two parts is shown according to the described general aspects.

[0019] Figure 7 An asymmetric horizontal partitioning according to the described general aspects is shown.

[0020] Figure 8 Examples of horizontal partitioning into three or four parts using vertical prediction mode according to the described general aspects are shown.

[0021] Figure 9 An example of intra prediction in mode partitioning according to the described general aspects is shown.

[0022] Figure 10An example of a block with horizontal ISP partitioning using vertical prediction mode and horizontal ISP partitioning using horizontal prediction mode is shown.

[0023] Figure 11 An embodiment of an encoding method according to the described main aspects is shown.

[0024] Figure 12 An embodiment of a decoding method according to the main aspects described is shown.

[0025] Figure 13 One embodiment of an apparatus for encoding or decoding using intra-prediction mode extension is shown.

[0026] Figure 14 A general standard encoding scheme is shown.

[0027] Figure 15 A general standard decoding scheme is shown.

[0028] Figure 16 Shown is a typical processor arrangement in which the described embodiments may be implemented. DETAILED DESCRIPTION

[0029] The embodiments described herein belong to the field of video compression and relate to video compression as well as video encoding and decoding. In the Versatile Video Coding (VVC) Test Model (VTM), any target block in intra prediction can have one of 67 prediction modes. Similar to HEVC, one is PLANAR mode, one is DC mode, and the remaining 65 are directional modes. The 65 directional modes are selected from 95 directions, which include 65 regular angles spanning from 45 degrees to -135 degrees if the target block is a square, and 28 wide angle directions when the target block is a rectangle. VTM encodes the prediction mode of a block using a most probable mode (MPM) set, which consists of 6 prediction modes. If the prediction mode does not belong to the MPM set, it is truncated binary encoded with 5 or 6 bits.

[0030] Past video coding standards such as H.264 / AVC, HEVC, and the upcoming Versatile Video Coding (VVC) all employ intra-frame prediction, where the prediction direction in a coding block remains the same across the entire block. The basic idea is that object directionality remains constant across the coding block. This is an oversimplified model, as object directionality in natural images can vary. Using a single prediction direction across a coding block results in smaller coding blocks after rate-distortion (RD) optimization, which finds the best trade-off between higher block sizes and less accurate prediction models, with smaller block sizes providing a higher amount of side information for encoding partitions into smaller blocks.

[0031] A better idea is to use multiple prediction directions on the same decoding block, where these directions are close to the main direction and are applied to different partitions. This will allow the prediction direction within the decoding block to be changed in a structured way so that the direction matches the real-world image more closely. This paper proposes several methods to explore this idea and presents results in the context of the current VVC decoding test model (VTM).

[0032] Intra-frame prediction is a core coding tool in all video compression standards (e.g., H.264 / AVC, HEVC, and VVC). The basic idea is to exploit spatial correlations in frames of an image sequence by predicting a block of pixels based on already decoded causal neighboring blocks. The prediction residual at the encoder is then transformed using a block transform, the transform coefficients are quantized, and then binary encoded. At the decoder, the block is reconstructed by adding the prediction to the decoded residual, which is produced by the inverse process of binary decoding, inverse quantization, and inverse transformation.

[0033] For the purpose of prediction, the standard defines several models called prediction modes. For example, HEVC defines 35 prediction modes, one of which is a PLANAR mode, one is a DC mode, and the remaining 33 are angular modes. The PLANAR and DC modes are intended to model slowly and gradually changing intensity regions, while the angular modes are intended to model different object directionality. On the other hand, VVC defines 67 regular intra prediction modes, which include the 35 prediction modes from HEVC and an additional 32 angular modes. VVC also defines 28 wide angle modes for use with rectangular decoding blocks. The encoder prediction tool selects the prediction mode that is best in terms of rate-distortion performance and signals it to the decoder using a mode coding scheme. The decoder prediction tool decodes the prediction mode and uses the decoded pixels from neighboring blocks to predict the current block using that mode.

[0034] The usual process of intra prediction consists of first constructing two reference arrays for the current block, one to the left and the other above, using decoded samples from neighboring blocks. For any directional mode, the reference samples on the top and / or left reference arrays are repeated inside the current block along the associated directions. Here, the basic assumption is that the directionality of the object remains linear throughout the block and that the intensity values ​​do not vary much along these directions. This model seems to work well, especially when the block size is small. When the block is large, as allowed by VVC, the directionality can change gradually. The general aspects described here propose a simple way to model this phenomenon. Before introducing the method, a brief description of intra prediction in the VVC test model VTM is first given. For easier reference, the terms "CU" (coding unit) and "block" are used interchangeably throughout the text.

[0035] The intra prediction process in VTM consists of three steps: (1) reference sample generation, (2) intra sample prediction, and (3) post-processing of predicted samples. Figure 1 The reference sample generation process is shown in Figure 1, which shows the reference samples used for intra prediction in VTM. The reference pixel value at coordinate (x, y) is represented by R(x, y) in the figure. H and W represent the height and width of the current block, respectively. For a CU of size HxW, a row of 2W decoded samples on the top is formed from the previously reconstructed top and top right pixels of the current CU. Similarly, a column of 2H samples on the left is formed from the reconstructed left and bottom left pixels. The corner pixel at the top left position is also used to fill the gap between the top row and left column references. If some of the top or left samples are not available because the corresponding CU is not in the same slice, or the current CU is at a frame boundary, etc., a method called reference sample replacement can be performed, in which the missing samples are copied from the available samples in a clockwise direction. Then, depending on the current CU size and prediction mode, the reference samples can be filtered using a low-pass filter with coefficients [1 / 4, 1 / 2, 1 / 4], which is applied vertically to the left reference column and horizontally to the top reference row.

[0036] VTM 4.0 also supports intra prediction with multiple reference lines (MRL). The idea is based on Figure 2 Several sets of reference lines are predicted as shown, and the reference line that gives the best rate-distortion performance is selected. Figure 2 The multiple reference lines used for intra prediction in VTM are shown. The reference lines are indexed in the order of their distance from the target block. For example, the reference line closest to the target block is indexed as 0. For example, the other two reference lines used for prediction in this example are indexed as 1 and 3. The reference lines used are signaled to the decoder in a variable length code. For example, Figure 2The three reference rows in the MRL are used in VTM 4.0, with reference rows with indices 0, 1, and 3 signaled with bits "0," "10," and "11," respectively. Furthermore, to limit the increased complexity of searching for the best prediction mode, only reference rows 1 and 3 are tested using the six angular prediction modes, which are derived in the same manner as the modes in the MPM list, but with the PLANAR and DC modes excluded. It should be noted that reference row 2 is not used for MRL in VTM 4.0 and is shown here for illustrative purposes only.

[0037] The next step (i.e., intra-sample prediction) consists in predicting the pixels of the target CU based on the reference samples. As mentioned before, in order to efficiently predict different kinds of content, VTM supports a range of prediction models. Planar and DC prediction modes are used to predict smooth and gradually changing areas, while angular prediction modes are used to capture different directional structures. VTM supports 93 directional prediction modes, which are indexed from -14 to -1 and from 2 to 80. For square CUs, only prediction modes 2-66 are used. These prediction modes correspond to different prediction directions from 45 degrees to -135 degrees in the clockwise direction, such as Figure 3 As illustrated in FIG, which shows the intra prediction directions in the VTM for a square target block. The numbers represent the prediction mode index associated with the corresponding direction. Modes 2 to 33 indicate horizontal prediction, while modes 34 to 66 indicate vertical prediction.

[0038] Modes indexed from -14 to -1 and 67 to 80 are wide angle modes, used for rectangular blocks of different shapes. Modes -14 to -1 are defined as exceeding mode 2 (exceeding an angle of 45 degrees) and are used for tall rectangular blocks (blocks whose height is greater than their width). Similarly, modes 67 to 80 are defined as exceeding mode 66 (exceeding an angle of -135 degrees) and are used for flat rectangular blocks (blocks whose width is greater than their height). The number of wide angle modes used for rectangular blocks depends on the aspect ratio of the block. In any case, the total number of angle modes used for any block is 65, and these modes are always continuous in direction. The angle prediction modes used for different block shapes are summarized in Table 1.

[0039]

[0040] Table 1: Range of intra prediction modes for different target block shapes in VTM. W / H refers to the ratio of the width to the height of the block.

[0041] VTM 4.0 also supports intra prediction with sub-partitioning (ISP). As shown in Table 2, the tool divides the luma intra prediction block into 2 or 4 sub-partitions vertically or horizontally depending on the block size dimension.

[0042] Block size Number of subpartitions 4×4 1 4×8 and 8×4 2 All other cases 4

[0043] Table 2: Number of subpartitions depending on block size

[0044] A subpartition must have at least 16 pixels. Thus, a block of size 4×4 is not divided into subpartitions, while blocks of size 4×8 and 8×4 have only two subpartitions. Blocks of all other sizes have only four subpartitions. Subpartitions can be horizontal or vertical. Figure 4 and Figure 5 Examples of two possibilities are shown. Figure 4 Examples of partitioning into 4x8 and 8x4 blocks are shown. Figure 5 Examples of partitioning are shown for all blocks except 4x8, 8x4, and 4x4. The type of partitioning is coded as 0 (no partitioning), or 1 (horizontal partitioning), or 2 (vertical partitioning).

[0045] Prediction in each subpartition uses the prediction mode of the parent CU. The subpartitions are processed in normal increasing order, regardless of the intra mode and partitioning used. In VTM 4.0, ISP is only applied to blocks using the first reference line. Therefore, if a block has MRL index 1 or 3, the ISP coding mode will be inferred to be 0 and therefore not encoded.

[0046] Furthermore, to reduce coding complexity, the ISP algorithm is tested using only intra modes that are part of the MPM list, which consists of six different prediction modes out of 67. For any block tested with ISP, the MPM list is also modified to exclude DC mode and prioritize horizontal intra mode for horizontal partitioning and vertical intra mode for vertical partitioning.

[0047] In intra prediction, each coded block is associated with a prediction mode. If the prediction mode is angular, all pixels in the current block are predicted in the same direction, even in the case of MRL. In the case of ISP, all sub-partitions use the same prediction mode. Using the same direction for all pixels is very effective in simulating straight edges or other linear object features. To allow for nonlinear features such as curvature, it is useful to account for variations in prediction direction across the coded block.

[0048] For generality, we will assume that rectangular blocks have width W and height H in the following. Square target blocks are a special case of W = H. To make it easier to understand, we will give the theory assuming no MRL and no ISP at the beginning. Subsequently, we will describe different embodiments, in which we will present different ways of combining the proposed method with MRL and ISP.

[0049] To start with the simplest case of intra prediction mode partitioning, we will consider the case of a coding block with two prediction modes. In the general setting, these two modes can be arbitrary, but our goal is to only consider modes that are directional close together. This requirement follows from the assumption that the directionality of an object can change only slightly, if not remain constant, within the coding block. Therefore, we will only consider two adjacent prediction directions, such as V and V+1, or V and V-1, where V represents the angular prediction mode being considered. We will assume this simple case as it will require the least amount of signaling, but the ideas presented are not limited to just two intra prediction mode partitions.

[0050] Secondly, we will also assume that the two prediction modes are applied on two non-overlapping areas of the coding block. The simplest approach is to split the block into two parts horizontally or vertically, since the coding block is rectangular or square. Although the split can occur at any pixel position and with any number of splits, we will only consider structured splits. That is, we will only consider splits in the middle (one split has parts of equal size), or splits at one-quarter and three-quarters of a dimension (asymmetric splits). These are in Figure 6 and Figure 7 Shown in. Figure 6 A symmetrical horizontal and vertical partitioning into two parts is shown. In the case where prediction mode V is vertical, horizontal partitioning is applied. In the case where prediction mode V is horizontal, vertical partitioning is applied. In the horizontal partitioning case (top), the top part has prediction mode V and the bottom part has prediction mode (V-1) or (V+1). This can be reversed, with the bottom having prediction mode V and the top having prediction mode (V-1) or (V+1). Similar situations apply to the vertical partitioning case. We apply horizontal partitioning to the vertical prediction direction and vertical partitioning to the horizontal prediction direction, although other partitionings are possible under the current general aspects.

[0051] Figure 7 An asymmetric horizontal partitioning is shown. In one case, the pixels in the smaller portion have prediction mode V, while the pixels in the larger portion have prediction mode (V-1) or (V+1) (top two figures). In another case, the pixels in the larger portion have prediction mode V, while the pixels in the smaller portion have prediction mode (V-1) or (V+1) (bottom two figures). When the prediction mode is horizontal, a similar partitioning can be performed in the vertical direction.

[0052] It is not mandatory to have only two non-overlapping parts in the coded block for both prediction modes. We can have a higher number of parts, where each part can have one of the two prediction modes used. Figure 8 Cases with three and four partitions are shown. Figure 8 Examples are shown for horizontal partitioning into three or four parts using vertical prediction mode. In both cases, we assume that the block has at most two prediction modes. Similar examples can be given with vertical partitioning when the prediction mode is horizontal.

[0053] The prediction process with mode partitioning uses the same two reference arrays of the decoded block, one at the top and the other on the left. If the same reference sample array is used for the entire block for different intra prediction mode areas, all pixels in the current block can be predicted simultaneously. This is different from ISP, where different partitions are processed sequentially. Figure 9 The prediction process with a single reference row is shown in . Figure 9 Intra-frame prediction in pattern partitioning is shown. The target pixels in the second part are predicted by considering the prediction modes of the pixels in the first and second parts. Note that the target pixels in the second part are not predicted directly using their prediction modes, but are also predicted by considering the prediction mode of the pixels in the first part. That is, the predictor of the target pixel in the second part will be determined based on both the prediction modes of the second part and the first part. In other words, when predicting the second part, it is still necessary to consider what the prediction direction on the first part is in order to map the appropriate reference samples at each pixel position. If the current prediction direction is considered, it is possible that the wrong position of the reference array will be targeted, such as Figure 9 This is shown by the long straight arrow in , where the correct mapping is shown by the shorter arrow. The same applies if we consider a partition into three or four parts. The predictor of the target pixel in a certain part is determined by using the prediction mode of all previous parts and the prediction mode of the part under consideration.

[0054] In a practical coding scenario, the number of mode partitions will be limited. The encoder will check the rate-distortion performance of all available mode partitions and will then signal the best mode partition to the decoder so that the decoder knows the partition adopted by the encoder. The higher the number of partitions, the greater the number of signaling bits required. As described here, we will consider, but not be limited to, three candidates with two partitions: (1) no partition, (2) when V is a vertical (horizontal) mode, the top (left) part with prediction mode (V-1) and the bottom (right) part with prediction mode V, (3) when V is a vertical (horizontal) mode, the top (left) part with prediction mode (V+1) and the bottom (right) part with prediction mode V. Alternatively, we can also consider the same partitioning where the modes are swapped between the two parts. The three candidates can be decoded using a variable length code, where no partition is encoded as 0, and the other two candidates are encoded as 10 and 11, respectively.

[0055] It should be noted that the choice of the number of partitions and encoding scheme can be generalized and does not need to be as specific as in the above example. For example, we can consider four prediction candidates, where the first prediction candidate has no partitioning, and the remaining three candidates consider three different types of partitioning depending on the direction of the prediction mode. These four candidates can be simply encoded using a fixed-length decoding scheme that only requires two bits per candidate.

[0056] When intra prediction allows multiple reference lines (MRLs), as in VTM 4.0, the proposed method can be restricted to blocks using the first reference line, or blocks using the second or fourth reference lines, or both. Within the general aspects described, other schemes are conceivable. In the first two cases, the signaling regarding the mode partition will depend on the MRL index, so for some blocks that do not use a specific reference line, this signaling does not need to be sent. In the latter case, the signaling is required for all blocks, regardless of the MRL index value.

[0057] Just like MRL, when ISP is allowed for intra prediction, as in VTM 4.0, the proposed method can be restricted to blocks that do not use ISP (i.e., ISP index = 0) or blocks that use ISP (ISP index non-zero) or both. In the first case, the application of the proposed method does not require any modifications since the blocks are not split into sub-partitions. However, in the second case, the application of the proposed method with sub-partitions may be tricky. Since ISP allows both horizontal and vertical sub-partitioning of blocks without considering the directionality of the prediction mode (the directionality used by the proposed method), directly applying the two modes on different sub-partitions will not work as desired. The sub-partitions in the ISP need to have one or two prediction modes, depending on the directionality of the prediction mode considered. In the examples described here, for simplicity, we assume that the proposed prediction method is applied to blocks that do not use ISP (i.e., blocks with ISP index = 0). The second case can be considered as an extension of the described idea.

[0058] In the following, we assume the VVC Test Model VTM 4.0 codec. However, since the proposed method is quite general, it can be applied in the context of any previous standard, such as H.264 / AVC, HEVC, etc., which use multiple directional prediction modes for intra-frame prediction. In all embodiments, we only assume three prediction methods with mode partitioning: (1) no partitioning, where the same prediction mode V is used for all target pixels, (2) 2 partitions, where the prediction mode of one part is V and the prediction mode of the other part is (V-1). (3) 2 partitions, where the prediction mode of one part is V and the prediction mode of the other part is (V+1). In cases (2) and (3), we assume that the same part uses prediction mode V. When V is a vertical mode, the partitioning is horizontal, and when V is a horizontal mode, the partitioning is vertical. The partitioning can be symmetric or asymmetric. For a block as specified in the different embodiments below, the encoder checks the three prediction methods and selects the best method. The best prediction method is signaled by an index value equal to 0, 1 or 2, depending on the method, which is binarized and context encoded.

[0059] Example 1: In this embodiment, only blocks using the second or fourth reference row are processed with the proposed prediction method. Therefore, if the current block has an MRL index equal to 0, there is no encoding for the mode partition. If the decoded value of the MRL index is 0, the decoder will assume the value to be zero (no split for the mode partition). In this case, there is no ISP conflict since the ISP is only applied to blocks with MRL index 0. Note that the MRL index is encoded before the ISP index. We propose to encode the mode partition index after the ISP index. The decoder therefore first decodes the MRL index and then decodes the ISP index if the MRL index is equal to zero, otherwise it decodes the mode partition index.

[0060] Embodiment 2: In this embodiment, blocks that only use the first reference row but are not partitioned with the ISP are processed with the proposed prediction method. Therefore, if the current block has an MRL index equal to 1 or 3, there is no encoding for pattern partitioning. If the MRL index is 0, but the ISP index is 1 or 2, there is also no encoding for pattern partitioning. The pattern partition index is encoded only for blocks with an MRL index equal to zero and an ISP index equal to 0. If the decoded value of the MRL index is non-zero, or if the decoded value of the ISP index is non-zero, the decoder will assume a zero value (for pattern partitioning not partitioned). In this case, there is also no conflict of ISPs, because the ISP has no partitioning of the blocks that are checked for pattern partitioning. In this method, the pattern partition index must be encoded after the MRL index and the ISP index. The decoder therefore decodes the MRL index and the ISP index before decoding the index for pattern partitioning. If the MRL index or the ISP index is non-zero, the pattern partition index will be assumed to be 0 and will not be decoded.

[0061] Embodiment 3: In this embodiment, blocks using only the first reference row are processed using the proposed prediction method, regardless of the value of the ISP index. If the ISP index value is 0, processing is performed as in Embodiment 2. Otherwise, each subpartition is processed as no mode partition or two mode partition, depending on the ISP index value, depending on the prediction direction and the type of subpartition. For example, if the prediction mode is vertical and the ISP partition is horizontal, the prediction mode of the subpartition is selected from V-1 and V (or V+1 and V) according to the mode partition index value. A similar situation applies to vertical subpartitions with horizontal prediction mode. Figure 10 An example of this is shown. If the block is partitioned according to the ISP and the prediction direction is consistent with the partitioning (e.g., horizontal partitioning and vertical mode), then the ISP partitioning is maintained and the direction of the second block is modified (+1 or -1) as shown in the figure.

[0062] However, if the direction is, for example, horizontal and the segmentation is also (bottom image below), the proposed tool will segment according to the predicted direction and end up with subpartitions as shown in the bottom right image.

[0063] But if the subpartition is horizontal and the prediction mode is horizontal, or if the subpartition is vertical and the prediction mode is vertical, then each subpartition can have two prediction modes, such as Figure 10 As shown in .

[0064] Embodiment 4: In this embodiment, all blocks are processed with the proposed prediction method regardless of the values ​​of the MRL index and the ISP index. Therefore, for each block, the decoder will decode the mode partition index.

[0065] The proposed method was implemented by incorporating it into the VTM 4.0 software. The proposed prediction method was applied only to blocks using the second or fourth reference row, as described in Example 1. That is, only blocks with non-zero MRL indices were processed for pattern partitioning. The BD-rate performance of the tested method is shown in Table 3.

[0066]

[0067] Table 3: BD-rate performance of Example 1 compared to VTM 4.0 anchor.

[0068] The present invention aims to improve intra prediction efficiency by allowing multiple intra prediction modes within the same target block. The idea is to capture the real-world object directionality within the target block. The advantage is higher compression efficiency without much additional complexity.

[0069] Figure 11 One embodiment of a method 1100 for encoding a block of video data using the general aspects described herein is shown. The method begins at a start block 1101, and control proceeds to a function block 1110 for predicting pixels in a plurality of regions of a block of video data using intra prediction, wherein each region uses a different intra prediction mode. Control then proceeds from block 1110 to block 1120 for encoding the plurality of regions using the predictions from the intra prediction modes.

[0070] Figure 12 One embodiment of a method 1200 for encoding a block of video data using the general aspects described herein is shown. The method begins at start block 1201, and control passes to function block 1210 for predicting pixels in a plurality of regions of a block of video data using intra-frame prediction, wherein each region uses a different intra-frame prediction mode. Control then passes from block 1210 to block 1220 for decoding the plurality of regions using the predictions from the intra-frame prediction mode.

[0071] Figure 13 One embodiment of an apparatus 1300 for encoding or decoding a block of video data is shown. The apparatus includes a processor 1310 and may be interconnected via at least one port to a memory 1320. Both the processor 1310 and the memory 1320 may also have one or more additional interconnections to external connections.

[0072] Processor 1310 is configured to encode or decode video data using the extended prediction mode and to encode or decode the video data block using prediction in the extended intra coding mode.

[0073] This application describes a number of aspects, including tools, features, embodiments, models, methods, etc. Many of these aspects are described as having specificity, and at least in order to illustrate individual characteristics, are usually described in a manner that may sound limited. However, this is for the purpose of describing clearly, and does not limit the application or scope of those aspects. In fact, all different aspects can be combined and interchanged to provide other aspects. In addition, these aspects can also be combined and interchanged with the aspects described in earlier documents.

[0074] The aspects described and contemplated in this application can be implemented in many different forms. Figure 14 、 15 and 16 provide some embodiments, but other embodiments are contemplated and are not intended to be construed as Figure 14 、 15 The discussion of 16 does not limit the breadth of implementation. At least one of the aspects generally relates to video encoding and decoding, and at least one other aspect generally relates to transmitting the generated or encoded bitstream. These and other aspects can be implemented as methods, apparatus, computer-readable storage media having stored thereon instructions for encoding or decoding video data according to any of the described methods, and / or computer-readable storage media having stored thereon bitstreams generated according to any of the described methods.

[0075] In this application, the terms "reconstruction" and "decoding" are used interchangeably, the terms "pixel" and "sample" are used interchangeably, and the terms "image", "picture", and "frame" are used interchangeably. Usually, but not necessarily, the term "reconstruction" is used on the encoder side, while "decoding" is used on the decoder side.

[0076] Various methods are described herein, and each method includes one or more steps or actions for achieving the described method. Unless a specific order of steps or actions is required for proper operation of the method, the order and / or use of specific steps and / or actions may be modified or combined.

[0077] Various methods and other aspects described in this application can be used to modify modules, e.g. Figure 14 and Figure 15 Intra prediction, entropy coding and / or decoding modules (160, 360, 145, 330) of the video encoder 100 and decoder 200 are shown. Furthermore, the present invention is not limited to VVC or HEVC and is applicable, for example, to other standards and proposals (whether pre-existing or developed in the future) and extensions of any such standards and proposals (including VVC and HEVC). Unless otherwise indicated or technically excluded, the aspects described in this application may be used alone or in combination.

[0078] Various numerical values ​​are used in this application. The specific values ​​are for illustrative purposes, and the described aspects are not limited to these specific values.

[0079] Figure 14 An encoder 100 is shown. Variations of the encoder 100 are contemplated, but for clarity, the encoder 100 is described below without describing all contemplated variations.

[0080] Before being encoded, the video sequence may undergo a pre-encoding process (101), for example, applying a color transform to the input color picture (e.g., conversion from RGB 4:4:4 to YCbCr 4:2:0), or performing a remapping of the input picture components in order to obtain a signal distribution that is more resilient to compression (e.g., using histogram equalization of one of the color components). Metadata may be associated with the pre-processing and appended to the bitstream.

[0081] In an encoder 100, a picture is encoded by encoder elements as described below. The picture to be encoded is partitioned (102) into units, such as CUs, and processed. Each unit is encoded using, for example, intra or inter mode. When encoding a unit in intra mode, it performs intra prediction (160). In inter mode, motion estimation (175) and compensation (170) are performed. The encoder decides (105) whether to use intra mode or inter mode to encode the unit, and indicates the intra / inter decision by, for example, a prediction mode flag. For example, a prediction residual is calculated by subtracting (110) the predicted block from the original image block.

[0082] The prediction residual is then transformed (125) and quantized (130). The quantized transform coefficients, along with motion vectors and other syntax elements, are entropy coded (145) to output a bitstream. The encoder may skip the transform and apply quantization directly to the untransformed residual signal. The encoder may bypass both transform and quantization, i.e., directly decode the residual without applying the transform or quantization process.

[0083] The encoder decodes the coded block to provide a reference for further prediction. The quantized transform coefficients are dequantized (140) and inverse transformed (150) to decode the prediction residual. The decoded prediction residual and the prediction block are combined (155) to reconstruct the image block. An in-loop filter (165) is applied to the reconstructed picture to perform, for example, deblocking / SAO (sample adaptive offset) filtering to reduce coding artifacts. The filtered image is stored in a reference picture buffer (180).

[0084] Figure 151 shows a block diagram of a video decoder 200. In the decoder 200, the bitstream is decoded by decoder elements as described below. The video decoder 200 generally performs the same operations as described below. Figure 14 The decoding process is the inverse of the encoding process described in

[0044] The encoder 100 also typically performs video decoding as part of encoding the video data.

[0085] In particular, the input to the decoder comprises a video bitstream, which may be generated by the video encoder 100. The bitstream is first entropy decoded (230) to obtain transform coefficients, motion vectors and other decoding information. Picture partition information indicates how the picture is partitioned. The decoder can then partition (235) the picture according to the decoded picture partition information. The transform coefficients are dequantized (240) and inverse transformed (250) to decode the prediction residual. The decoded prediction residual is combined (255) with a prediction block to reconstruct the image block. The prediction block may be obtained (270) from intra-frame prediction (260) or motion compensated prediction (i.e., inter-frame prediction) (275). An in-loop filter (265) is applied to the reconstructed image. The filtered image is stored in a reference picture buffer (280).

[0086] The decoded picture may further undergo post-decoding processing (285), such as an inverse color transform (e.g., conversion from YCbCr 4:2:0 to RGB 4:4:4) or performing an inverse remapping of the remapping process performed in the pre-encoding process (101). The post-decoding processing may use metadata derived in the pre-encoding process and signaled in the bitstream.

[0087] Figure 16 A block diagram showing an example of a system in which various aspects and embodiments are implemented is shown. System 1000 can be implemented as a device including the various components described below, and is configured to perform one or more aspects described herein. Examples of such devices include, but are not limited to, various electronic devices, such as personal computers, laptop computers, smart phones, tablet computers, digital multimedia set-top boxes, digital television receivers, personal video recording systems, connected home appliances and servers. The elements of system 1000 can be implemented individually or in combination in a single integrated circuit (IC), multiple ICs and / or discrete components. For example, in at least one embodiment, the processing and encoder / decoder elements of system 1000 are distributed over multiple ICs and / or discrete components. In various embodiments, the system 1000 is communicatively coupled to one or more other systems or other electronic devices via, for example, a communication bus or by dedicated input and / or output ports. In various embodiments, the system 1000 is configured to implement one or more aspects described herein.

[0088] The system 1000 includes at least one processor 1010 configured to execute instructions loaded therein for implementing various aspects described herein, for example. The processor 1010 may include embedded memory, input / output interfaces, and various other circuits known in the art. The system 1000 includes at least one memory 1020 (e.g., a volatile memory device and / or a non-volatile memory device). The system 1000 includes a storage device 1040, which may include non-volatile memory and / or volatile memory, including but not limited to electrically erasable programmable read-only memory (EEPROM), read-only memory (ROM), programmable read-only memory (PROM), random access memory (RAM), dynamic random access memory (DRAM), static random access memory (SRAM), flash memory, magnetic disk drive, and / or optical disk drive. As non-limiting examples, the storage device 1040 may include an internal storage device, an attached storage device (including a detachable storage device and a non-detachable storage device), and / or a network-accessible storage device.

[0089] System 1000 includes an encoder / decoder module 1030, which is configured to, for example, process data to provide encoded video or decoded video, and the encoder / decoder module 1030 may include its own processor and memory. The encoder / decoder module 1030 represents a module(s) that may be included in a device to perform encoding and / or decoding functions. As is known, a device may include one or both of the encoding and decoding modules. In addition, the encoder / decoder module 1030 may be implemented as a separate element of system 1000 or may be incorporated into processor 1010 as a combination of hardware and software as known to those skilled in the art.

[0090] Program code to be loaded onto the processor 1010 or encoder / decoder 1030 to perform various aspects described in this document may be stored in the storage device 1040 and subsequently loaded onto the memory 1020 for execution by the processor 1010. According to various embodiments, one or more of the processor 1010, memory 1020, storage device 1040, and encoder / decoder module 1030 may store one or more of various items during the execution of the processes described herein. These stored items may include, but are not limited to, input video, decoded video or portions of the decoded video, bitstreams, matrices, variables, and intermediate or final results from the processing of equations, formulas, operations, and operational logic.

[0091] In some embodiments, memory within the processor 1010 and / or the encoder / decoder module 1030 is used to store instructions and provide working memory for processing required during encoding or decoding. However, in other embodiments, memory external to the processing device (e.g., the processing device may be the processor 1010 or the encoder / decoder module 1030) is used for one or more of these functions. The external memory may be memory 1020 and / or storage device 1040, such as dynamic volatile memory and / or non-volatile flash memory. In some embodiments, the external non-volatile flash memory is used to store, for example, the operating system of the television. In at least one embodiment, fast external dynamic volatile memory such as RAM is used as working memory for video coding and decoding operations, such as working memory for MPEG-2 (MPEG refers to Moving Picture Experts Group, MPEG-2 is also known as ISO / IEC 13818, and 13818-1 is also known as H.222, and 13818-2 is also known as H.262), HEVC (HEVC refers to High Efficiency Video Coding, also known as H.265 and MPEG-H Part 2), or VVC (Versatile Video Coding, a new standard developed by the Joint Video Team experts JVET).

[0092] As shown in block 1130, input to the elements of system 1000 may be provided through various input devices. Such input devices include, but are not limited to: (i) a radio frequency (RF) portion that receives a radio frequency (RF) signal transmitted over the air, for example, by a broadcaster, (ii) a component (COMP) input terminal (or a set of component input terminals), (iii) a universal serial bus (USB) input terminal, and / or (iv) a high-definition multimedia interface (HDMI) input terminal. Figure 15 Other examples not shown in include composite video.

[0093] In various embodiments, the input device of block 1130 has associated corresponding input processing elements known in the art. For example, the RF section may be associated with elements suitable for: (i) selecting a desired frequency (also known as selecting a signal, or band-limiting a signal to a frequency band), (ii) down-converting the selected signal, (iii) again band-limiting the signal to a narrower frequency band to select a signal band (e.g., a channel) in some embodiments, (iv) demodulating the down-converted and band-limited signal, (v) performing error correction, and (vi) demultiplexing to select the desired data packet stream. The RF section of various embodiments includes one or more elements to perform these functions, such as a frequency selector, a signal selector, a band limiter, a channel selector, a filter, a down-converter, a demodulator, an error corrector, and a demultiplexer. The RF section may include a tuner that performs various of these functions, including, for example, down-converting a received signal to a lower frequency (e.g., an intermediate frequency or near-baseband frequency) or to baseband. In a set-top box embodiment, described RF part and relevant input processing element thereof receive the RF signal that sends by wired (for example, cable) medium, and carries out the frequency selection to desired frequency band by filtering, down-conversion and filtering again.Various embodiments rearrange the order of above-mentioned (and other) element, remove some in these elements, and / or add other element that performs similar or different functions.Adding element can be included in and inserts element between existing element, for example inserts amplifier and analog-to-digital converter.In various embodiments, described RF part comprises antenna.

[0094] In addition, the USB and / or HDMI terminals may include corresponding interface processors for connecting the system 1000 to other electronic devices via USB and / or HDMI connections. It will be appreciated that various aspects of input processing (e.g., Solomon error correction) may be implemented as needed, for example, within a separate input processing IC or within the processor 1010. Similarly, various aspects of USB or HDMI interface processing may be implemented as needed within a separate interface IC or within the processor 1010. The demodulated, error-corrected, and demultiplexed streams are provided to various processing elements, including, for example, the processor 1010 and an encoder / decoder 1030, which operate in conjunction with memory and storage elements to process the data streams as needed for presentation on an output device.

[0095] The various components of system 1000 can be arranged in an integrated housing in which the various components can be interconnected and transmit data using a suitable connection arrangement (e.g., an internal bus known in the art, including an inter-IC (I2C) bus, wiring, and a printed circuit board).

[0096] The system 1000 includes a communication interface 1050 that enables communication with other devices via a communication channel 1060. The communication interface 1050 may include, but is not limited to, a transceiver configured to send and receive data through the communication channel 1060. The communication interface 1050 may include, but is not limited to, a modem or a network card, and the communication channel 1060 may be implemented, for example, within a wired and / or wireless medium.

[0097] In various embodiments, data is streamed or otherwise provided to the system 1000 using a wireless network (e.g., a Wi-Fi network, such as IEEE 802.11 (IEEE refers to the Institute of Electrical and Electronics Engineers)). The Wi-Fi signal of these embodiments is received through a communication channel 1060 and a communication interface 1050 suitable for Wi-Fi communication. The communication channel 1060 of these embodiments is typically connected to an access point or router that provides access to external networks including the Internet to allow streaming applications and other cloud communications. Other embodiments use a set-top box that transmits data through an HDMI connection of the input box 1130 to provide streaming data to the system 1000. Still other embodiments use an RF connection of the input box 1130 to provide streaming data to the system 1000. As described above, various embodiments provide data in a non-streaming manner. In addition, various embodiments use a wireless network other than Wi-Fi, such as a cellular network or a Bluetooth network.

[0098] The system 1000 can provide output signals to various output devices, including a display 1100, speakers 1110, and other peripheral devices 1120. The display 1100 of various embodiments includes one or more of the following: for example, a touch screen display, an organic light emitting diode (OLED) display, a curved display, and / or a foldable display. The display 1100 can be used in a television, a tablet computer, a laptop computer, a cellular phone (mobile phone), or other devices. The display 1100 can also be integrated with other components (for example, as in a smartphone) or standalone (for example, an external monitor for a laptop computer). In various examples of various embodiments, the other peripheral devices 1120 include one or more of the following: a standalone digital video disk (or digital versatile disk) (DVR, for both), a disk player, a stereo system, and / or a lighting system. Various embodiments use one or more peripheral devices 1120 that provide functions based on the output of the system 1000. For example, a disk player performs the function of playing the output of the system 1000.

[0099] In various embodiments, control signals are communicated between the system 1000 and the display 1100, speaker 1110, or other peripheral devices 1120 using signaling such as AV.Link, Consumer Electronics Control (CEC), or other communication protocols that enable device-to-device control with or without user intervention. The output devices can be communicatively coupled to the system 1000 via dedicated connections through respective interfaces 1070, 1080, and 1090. Alternatively, the output devices can be connected to the system 1000 via communication interface 1050 using communication channel 1060. The display 1100 and speaker 1110 can be integrated into a single unit in an electronic device (e.g., a television) along with the other components of the system 1000. In various embodiments, the display interface 1070 includes a display driver, such as a timing controller (TCon) chip.

[0100] For example, if the RF portion of the input 1130 is part of a separate set-top box, the display 1100 and speaker 1110 may alternatively be separate from one or more of the other components. In various embodiments where the display 1100 and speaker 1110 are external components, the output signals may be provided via dedicated output connections, such as an HDMI port, a USB port, or a COMP output.

[0101] These embodiments may be implemented by the processor 1010 or by computer software implemented in hardware, or by a combination of hardware and software. As a non-limiting example, the embodiments may be implemented by one or more integrated circuits. The memory 1020 may be of any type suitable for the technical environment and may be implemented using any appropriate data storage technology, such as, as a non-limiting example, optical memory devices, magnetic memory devices, semiconductor-based memory devices, fixed memory, and removable memory. The processor 1010 may be of any type suitable for the technical environment and may include, as a non-limiting example, one or more of the following: a microprocessor, a general-purpose computer, a special-purpose computer, and a processor based on a multi-core architecture.

[0102] Various implementations involve decoding. As used herein, "decoding" may include, for example, all or part of a process performed on a received coded sequence to produce a final output suitable for display. In various embodiments, such a process includes one or more of the processes typically performed by a decoder, such as entropy decoding, inverse quantization, inverse transform, and differential decoding. In various embodiments, such a process also or alternatively includes a process performed by a decoder of the various implementations described herein.

[0103] As a further example, in one embodiment, "decoding" refers only to entropy decoding, in another embodiment, "decoding" refers only to differential decoding, and in another embodiment, "decoding" refers to a combination of entropy decoding and differential decoding. Whether the phrase "decoding process" is intended to refer specifically to a subset of operations or generally to a broader decoding process will be clear based on the context of the specific description and is believed to be well understood by those skilled in the art.

[0104] Various implementations involve encoding. In a manner similar to the discussion above regarding "decoding," "encoding," as used in this application, may include, for example, all or part of a process performed on an input video sequence to produce an encoded bitstream. In various embodiments, such processes include one or more processes typically performed by an encoder, such as partitioning, differential encoding, transforms, quantization, and entropy coding. In various embodiments, such processes also or alternatively include processes performed by an encoder of the various implementations described herein.

[0105] As a further example, in one embodiment, "encoding" refers only to entropy coding, in another embodiment, "encoding" refers only to differential coding, and in another embodiment, "encoding" refers to a combination of differential coding and entropy coding. Whether the phrase "encoding process" is intended to refer specifically to a subset of operations or generally to a broader encoding process will become clear based on the context of the specific description and is believed to be well understood by those skilled in the art.

[0106] Note that the syntax elements as used herein are descriptive terms. Therefore, they do not exclude the use of other syntax element names.

[0107] When a figure is presented as a flow chart, it should be understood that it also provides a block diagram of the corresponding apparatus. Similarly, when a figure is presented as a block diagram, it should be understood that it also provides a flow chart of the corresponding method / process.

[0108] Various embodiments may involve parameter models or rate-distortion optimization. In particular, during the encoding process, a balance or trade-off between rate and distortion is often considered, often given a computational complexity constraint. This can be measured using the rate-distortion optimization (RDO) metric, or by least mean squares (LMS), mean absolute error (MAE), or other such metrics. Rate-distortion optimization is typically formulated as minimizing a rate-distortion function, which is a weighted sum of rate and distortion. There are different approaches to solving the rate-distortion optimization problem. For example, these approaches can be based on extensive testing of all coding options, including all considered modes or decoding parameter values, and a complete evaluation of their decoding costs and the associated distortion of the reconstructed signal after decoding and decoding. Faster approaches can also be used to save coding complexity, particularly by computing approximate distortion based on the prediction or prediction residual signal rather than the reconstructed signal. A hybrid of these two approaches can also be used, for example by using approximate distortion for only some possible coding options and the full distortion for others. Other approaches only evaluate a subset of possible coding options. More generally, many approaches employ any of a variety of techniques to perform the optimization, but the optimization is not necessarily a complete evaluation of both the coding cost and the associated distortion.

[0109] The implementations and aspects described herein can be implemented in, for example, a method or process, a device, a software program, a data stream, or a signal. Even if discussed only in the context of a single form of implementation (e.g., discussed only as a method), the implementation of the features discussed can also be implemented in other forms (e.g., a device or program). For example, an apparatus can be implemented with appropriate hardware, software, and firmware. The method can be implemented in, for example, a processor, which generally refers to a processing device, including, for example, a computer, a microprocessor, an integrated circuit, or a programmable logic device. The processor also includes communication equipment, such as a computer, a cellular phone, a portable / personal digital assistant ("PDA"), and other equipment that facilitates information communication between end users.

[0110] References to "one embodiment" or "an embodiment" or "one implementation" or "an implementation" and other variations mean that a particular feature, structure, characteristic, etc. described in connection with the embodiment is included in at least one embodiment. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" or "in one implementation" or "in an implementation" and any other variations in various places throughout this application are not necessarily all referring to the same embodiment.

[0111] Additionally, this application may refer to “determining” various information. Determining the information may include, for example, one or more of: estimating the information, calculating the information, predicting the information, or retrieving the information from a memory.

[0112] Furthermore, the present application may refer to "accessing" various information. Accessing the information may include, for example, one or more of: receiving the information, retrieving the information (e.g., retrieving the information from a memory), storing the information, moving the information, copying the information, calculating the information, determining the information, predicting the information, or estimating the information.

[0113] Additionally, this application may refer to "receiving" various information. Like "accessing," receiving is intended to be a broad term. Receiving the information may include, for example, one or more of: accessing the information or retrieving the information (e.g., from a memory device). Furthermore, during operations such as storing information, processing information, sending information, moving information, copying information, erasing information, calculating information, determining information, predicting information, or estimating information, "receiving" is often involved in one way or another.

[0114] It should be understood that, for example, in the context of "A / B," "A and / or B," and "at least one of A and B," the use of any of the following " / ," "and / or," and "at least one of" is intended to encompass selection of only the first listed option (A), or only the second listed option (B), or both options (A and B). As a further example, in the context of "A, B, and / or C" and "at least one of A, B, and C," such wording is intended to include selection of only the first listed option (A), or only the second listed option (B), or only the third listed option (C), or only the first and second listed options (A and B), or only the first and third listed options (A and C), or only the second and third listed options (B and C), or all three options (A, B, and C). This can be extended to multiple items listed, as will be apparent to one of ordinary skill in this and related arts.

[0115] Furthermore, as used herein, the term "signal" specifically refers to indicating something to a corresponding decoder. For example, in certain embodiments, an encoder signals a specific one of multiple transforms, decoding modes, or flags. Thus, in one embodiment, the same transforms, parameters, or modes are used on both the encoder and decoder sides. Thus, for example, the encoder can send (explicitly signal) specific parameters to the decoder so that the decoder can use the same specific parameters. Conversely, if the decoder already has the specific parameters along with other parameters, signaling can be used instead of sending them (implicitly signaling) to simply allow the decoder to know and select the specific parameters. By avoiding the transmission of any actual functionality, bit savings are achieved in various embodiments. It should be understood that signaling can be implemented in various ways. For example, in various embodiments, one or more syntax elements, flags, etc. are used to signal information to the corresponding decoder. Although the foregoing relates to the verb form of the term "signal," the term "signal" can also be used as a noun in this document.

[0116] As will be apparent to one of ordinary skill in the art, implementations can generate various signals formatted to carry information that can be stored or transmitted, for example. The information can include, for example, instructions for performing a method, or data generated by one of the described implementations. For example, a signal can be formatted to carry a bitstream of the described embodiments. Such a signal can be formatted as, for example, an electromagnetic wave (e.g., using the radio frequency portion of the spectrum) or a baseband signal. The formatting can include, for example, encoding a data stream and modulating a carrier wave with the encoded data stream. The information carried by the signal can be, for example, analog or digital information. As is known, the signal can be transmitted over a variety of different wired or wireless links. The signal can be stored on a processor-readable medium.

[0117] We have described several embodiments that can be applied across various claim categories and types. Features of these embodiments can be provided individually or in any combination. In addition, across various claim categories and types, embodiments can include one or more of the following features, devices, or aspects, individually or in any combination:

[0118] A process or apparatus for performing intra-frame encoding and decoding using mode partitioning.

[0119] • A process or apparatus for performing intra encoding and decoding using multiple reference lines with mode partitioning.

[0120] • A process or apparatus to perform intra encoding and decoding with mode partitioning using an MPM (Most Probable Mode) list and a variable length code indicating which modes to use.

[0121] • A process or apparatus for performing intra encoding and decoding that utilizes mode partitioning and filtering of predicted pixels across block boundaries.

[0122] • A process or apparatus for performing intra encoding and decoding with mode partitioning on rectangular blocks.

[0123] • A bitstream or signal comprising one or more of the described syntax elements, or variations thereof.

[0124] • A bitstream or signal comprising syntax conveying information generated according to any of the described embodiments.

[0125] • Creating and / or sending and / or receiving and / or decoding according to any of the embodiments described.

[0126] • A method, process, apparatus, medium storing instructions, medium storing data, or signal according to any described embodiment.

[0127] • Inserting syntax elements in the signaling that enable the decoder to determine the coding mode in a manner corresponding to that used by the encoder.

[0128] • Creating and / or sending and / or receiving and / or decoding a bitstream or signal comprising one or more of the described syntax elements or variations thereof.

[0129] • A TV, set-top box, cell phone, tablet or other electronic device that performs the transformation method(s) according to any of the described embodiments.

[0130] • A TV, set-top box, cell phone, tablet, or other electronic device that performs the transformation method(s) determined according to any of the described embodiments and displays (e.g., using a monitor, screen, or other type of display) the resulting image.

[0131] A TV, set-top box, cellular phone, tablet, or other electronic device that selects, band-limits, or tunes (e.g., using a tuner) a channel to receive a signal including the encoded image and performs the transform method(s) according to any of the described embodiments.

[0132] • A TV, set-top box, cell phone, tablet, or other electronic device that receives over the air (eg, using an antenna) a signal comprising the encoded image and performs the transform method(s).

Claims

1. A method for encoding a block of video data, comprising: Predicting pixels in a plurality of regions of a video data block by intra prediction, wherein corresponding regions use different intra prediction modes; as well as encoding the plurality of regions using the prediction, wherein the prediction is made using a prediction mode of a previous portion and a prediction mode of the portion under consideration, and wherein the partitioning is horizontal when one subpartition uses vertical prediction mode and the partitioning is vertical when the subpartition uses horizontal prediction mode, and the prediction modes of the subpartitions are adjacent prediction directions, and wherein the mode partitioning is signaled in the bitstream.

2. A device comprising: A processor configured to execute: Predicting pixels in a plurality of regions of a video data block by intra prediction, wherein corresponding regions use different intra prediction modes; as well as encoding the plurality of regions using the prediction, wherein the prediction is made using a prediction mode of a previous portion and a prediction mode of the portion under consideration, and wherein the partitioning is horizontal when one subpartition uses vertical prediction mode and the partitioning is vertical when the subpartition uses horizontal prediction mode, and the prediction modes of the subpartitions are adjacent prediction directions, and wherein the mode partitioning is signaled in the bitstream.

3. A method for decoding a video data block, comprising: Predicting pixels in a plurality of regions of a video data block by intra prediction, wherein corresponding regions use different intra prediction modes; as well as decoding the plurality of regions using the predictions, wherein the predictions are made using a prediction mode of a previous portion and a prediction mode of the portion under consideration, and wherein the partitioning is horizontal when one subpartition uses a vertical prediction mode and the partitioning is vertical when the subpartition uses a horizontal prediction mode, and the prediction modes of the subpartitions are adjacent prediction directions, and wherein the mode partitioning is determined from the bitstream.

4. A device comprising: A processor configured to execute: Predicting pixels in a plurality of regions of a video data block by intra prediction, wherein corresponding regions use different intra prediction modes; as well as decoding the plurality of regions using the predictions, wherein the predictions are made using a prediction mode of a previous portion and a prediction mode of the portion under consideration, and wherein the partitioning is horizontal when one subpartition uses a vertical prediction mode and the partitioning is vertical when the subpartition uses a horizontal prediction mode, and the prediction modes of the subpartitions are adjacent prediction directions, and wherein the mode partitioning is determined from the bitstream.

5. The method according to claim 1 or 3, or the apparatus according to claim 2 or 4, wherein the intra prediction mode of a region is determined by using prediction modes of different regions of the block.

6. The method according to claim 1 or 3, or the device according to claim 2 or 4, wherein: The signaling indicates the number of regions comprising the block.

7. A method according to claim 1 or 3, or an apparatus according to claim 2 or 4, wherein the reference array used to form the prediction is pixels from at least one row of pixels above the block or from at least one column of pixels to the left of the block.

8. The method of claim 1 or 3, or the apparatus of claim 2 or 4, wherein the plurality of regions are non-overlapping.

9. The method according to claim 1 or 3 or the device according to claim 2 or 4, wherein: The block is divided into a plurality of sub-partitions.

10. The method or apparatus of claim 9, wherein sub-partitions are capable of having different intra prediction modes.

11. The method of claim 1 or 3 or the apparatus of claim 2 or 4, wherein the number of regions comprising the blocks is signaled using syntax indicating which rows or blocks comprise a reference array for forming prediction.

12. A device comprising: The device according to any one of claims 4 to 11; as well as At least one of: (i) an antenna configured to receive a signal, the signal including the video block, (ii) a band limiter configured to limit the received signal to a frequency band including the video block, and (iii) a display configured to display an output representing the video block.

13. A non-transitory computer-readable medium comprising data content generated by the method according to any one of claims 1 and 5 to 11 or by the apparatus according to any one of claims 2 and 5 to 11, for playback using a processor.

14. A computer program product comprising instructions which, when said program is executed by a computer, cause said computer to perform the method according to any one of claims 1, 3 and 5 to 11.

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