Display panel, pixel circuit, and display device

Abstract

A display panel, a pixel circuit, and a display device are disclosed. The display panel includes sub-pixels and a driver for driving the sub-pixels. Each sub-pixel includes: an emitting element; a first transistor configured to generate a driving current; a constant current control circuit configured to receive a reference voltage and a bias voltage for setting a value of the driving current, and including a first capacitor configured to store a first compensation voltage generated by adding a threshold voltage of the first transistor to a difference between the bias voltage and the reference voltage; and a pulse width control circuit configured to receive a data voltage for determining an emission duration of the emitting element, and including a second transistor and a second capacitor, the second transistor being configured to control a pulse width of the driving current according to the data voltage, and the second capacitor being configured to store a second compensation voltage corresponding to a threshold voltage of the second transistor.

Description

Technical Field

[0001] The present disclosure generally relates to displays, and more particularly to a pixel circuit and a display panel having time-division pixel compensation. Background Art

[0002] Light-emitting diodes (LEDs), particularly micro-LEDs having micron-scale dimensions and using inorganic materials as emission materials, have an emission wavelength that varies with the drive current. Therefore, compared to when the display panel includes organic light-emitting diodes, it is more difficult to use a drive method for representing gray levels by using current. Summary of the Invention

[0003] Exemplary embodiments of the present disclosure include a micro-LED that has micron-scale dimensions and uses an inorganic material as an emission material as an emission element in a display panel having a pixel circuit driven by a time-division drive method.

[0004] Exemplary embodiments include a pixel circuit for driving a light-emitting diode (LED). Exemplary embodiments include a display panel having an LED.

[0005] The disclosed technical implementations are not limited to the described exemplary embodiments, and based on the description herein, those of ordinary skill in the art can clearly understand other technical combinations not specifically shown or stated.

[0006] A display panel according to an exemplary embodiment includes a plurality of sub-pixels. Each of the plurality of sub-pixels may include an emission element and a pixel circuit. The pixel circuit may include: a first transistor configured to generate a drive current for the emission element; a constant current control circuit configured to receive a reference voltage and a bias voltage for setting a value of the drive current, and including a first capacitor configured to store a first compensation voltage generated by adding a threshold voltage of the first transistor to a difference between the bias voltage and the reference voltage; and a pulse width control circuit configured to receive a data voltage for determining an emission duration of the emission element, and including a second transistor and a second capacitor, the second transistor configured to control a pulse width of the drive current based on the data voltage, and the second capacitor configured to store a second compensation voltage corresponding to a threshold voltage of the second transistor.

[0007] A pixel circuit according to an exemplary embodiment is connected to at least one of a first power line and a second power line that respectively transmit a first driving voltage and a second driving voltage, at least one of a first control line to a fourth control line that respectively transmit a first control signal to a fourth control signal, a scan line that transmits a scan signal, a data line that transmits a data voltage synchronously with the scan signal, a bias voltage line that transmits a bias voltage, a reference voltage line that transmits a reference voltage, a cleaning voltage line that transmits a cleaning voltage that monotonically changes in a preset time period, and a light-emitting element. The pixel circuit may include: a first transistor connected to the first power line and the light-emitting element; a second transistor including a control electrode, a first connection electrode, and a second connection electrode; a second capacitor including a second electrode and a first electrode connected to the control electrode of the second transistor; a third transistor including a control electrode connected to the scan line, a first connection electrode connected to the data line, and a second connection electrode connected to the control electrode of the second transistor; a fourth transistor including a control electrode connected to the second control line, a first connection electrode connected to the gate of the first transistor, and a second connection electrode connected to the first connection electrode of the second transistor; a fifth transistor including a control electrode connected to the fourth control line, a first connection electrode connected to the second electrode of the second capacitor, and a second connection electrode connected to the second connection electrode of the second transistor; a sixth transistor including a control electrode connected to the third control line, a first connection electrode connected to the cleaning voltage line, and a second connection electrode connected to the second electrode of the second capacitor; a seventh transistor including a control electrode connected to the third control line, a first connection electrode connected to the second connection electrode of the second transistor, and a second connection electrode connected to the reference voltage line; and a third capacitor including a first electrode connected to the second connection electrode of the second transistor and a second electrode connected to the second power line.

[0008] A display device according to an exemplary embodiment includes: a plurality of pixels each including a first transistor, a second transistor connected to a control electrode of the first transistor, and a light-emitting element connected to a connection electrode of the first transistor; and a time-division controller that generates a reference signal and a bias signal, wherein the reference signal and a signal based on the bias signal are alternately connected to the control electrode of the first transistor, and wherein the signal based on the bias signal responds to a threshold voltage of the first transistor. The display device may be configured such that the time-division controller further generates a cleaning signal that monotonically increases; the reference signal and the signal based on the bias signal are alternately connected to the connection electrode of the second transistor; and a signal based on the cleaning signal is connected to the control electrode of the second transistor.

[0009] Through the following description, the above and other embodiments may become more apparent. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The above and other embodiments disclosed will be more apparent from the following description taken in conjunction with the accompanying drawings, in which:

[0011] Figure 1 is a block diagram of a display panel according to an embodiment;

[0012] Figure 2 is a block diagram of a pixel according to an embodiment;

[0013] Figure 3 is a block diagram of a pixel according to an embodiment; and

[0014] Figure 4 is during driving Figure 3 a timing diagram of one frame period when driving the pixel. Detailed Description of the Embodiments

[0015] Reference will now be made in detail to the embodiments, examples of which are illustrated in the accompanying drawings, wherein like reference numerals may always refer to like elements. In this regard, the present embodiments may have different forms and should not be construed as limited to the description set forth herein. Accordingly, the embodiments described below with reference to the accompanying drawings are merely exemplary for explaining aspects of the present description by way of example and are not to be construed as limiting. As used herein, the term "and / or" includes any combination and all combinations of one or more of the associated listed items. Throughout the disclosure, the expression "at least one of a, b, and c" may represent only a, only b, only c, both a and b, both a and c, both b and c, all of a, b, and c, or variations thereof.

[0016] Since the disclosure allows for various changes and many embodiments, specific embodiments will be shown in the drawings and described in detail in the written description. Refer to the accompanying drawings for showing the preferred embodiments of the present disclosure to obtain a full understanding of the present disclosure. However, the disclosure may be implemented in many different forms and should not be construed as limited to the embodiments set forth herein.

[0017] Hereinafter, exemplary embodiments will be described in detail with reference to the accompanying drawings. For clarity of illustration, descriptions of parts that are irrelevant to the description and / or known in the art may be omitted. The same reference numerals in the drawings may represent the same elements, and thus repeated descriptions thereof may be omitted.

[0018] It will be understood that although the terms "first", "second", etc. may be used herein to describe various components, these components should not be limited by these terms. That is, these terms are only used to distinguish one component from another and are not limited to the quantity, order, etc.

[0019] Figure 1 shows a display panel 100 according to an embodiment.

[0020] Refer toFigure 1 Figure 1 , the display panel 100 may include a display unit 110, a gate cleaning driver 120, a data driver 130, a timing controller 140, and a voltage generator 150. The gate cleaning driver 120, the data driver 130, the timing controller 140, and the voltage generator 150 may be collectively referred to as a driver or a driving circuit. In an alternative embodiment, one or more of the gate cleaning driver 120, the data driver 130, the timing controller 140, and the voltage generator 150 may be external to the display panel 100.

[0021] The display unit 110 may include pixels PX. For convenience, Figure 1 only one pixel PX is shown, but a plurality of pixels PX may be arranged in the display unit 110. The pixels PX may be arranged in a matrix form, which includes, for example, pixel rows extending in a first direction (e.g., row direction) and pixel columns extending in a second direction (e.g., column direction).

[0022] A plurality of pixels PX may form a unit pixel. Figure 1 The pixel PX of may correspond to one sub-pixel forming such a unit pixel.

[0023] The pixels PX of the display unit 110 may receive updated data voltage DATA in each frame period and emit light according to a driving current having a preset value and a pulse width corresponding to the data voltage DATA. Thus, an image corresponding to the image data DATA1 of one frame may be displayed.

[0024] The pixel PX may be connected to, for example, scan lines SL_n extending in the row direction, a cleaning voltage line VL, and first control lines CL1 to fourth control lines CL4, and may be connected to, for example, a bias voltage line BL, data lines DL, and a reference voltage line RL extending in the column direction. The pixel PX may be connected to a first power line PL1 and a second power line PL2.

[0025] When the pixels PX are arranged in a matrix form in the display unit 110, the display unit 110 may include: scan lines including scan lines SL_n, cleaning voltage lines including the cleaning voltage line VL, first control lines to fourth control lines respectively including first control lines CL1 to fourth control lines CL4, bias voltage lines including the bias voltage line BL, data lines including the data lines DL, reference voltage lines including the reference voltage line RL, and first power lines including the first power line PL1. The display unit 110 may further include a second power line, and the second power line includes the second power line PL2.

[0026] The scan lines, the cleaning voltage lines, and the first to fourth control lines may extend in, for example, the row direction and may be connected to the gate cleaning driver 120. The data lines, the bias voltage lines, and the reference voltage lines may extend in, for example, the column direction and may be connected to the data driver 130. The first power line and the second power line may be connected to the voltage generator 150. However, this is merely an example. According to another example, the cleaning voltage lines may be connected to the voltage generator 150. According to another example, the cleaning voltage lines may extend in the column direction and may be connected to the data driver 130. In addition, the bias voltage lines and / or the reference voltage lines may be connected to the voltage generator 150.

[0027] Hereinafter, the description will focus on the scan line SL_n, the cleaning voltage line VL, the first to fourth control lines CL1 to CL4, the bias voltage line BL, the data line DL, the reference voltage line RL, and the first power line PL1 and the second power line PL2 of the pixel PX.

[0028] The pixel PX may include a light-emitting element and a pixel circuit that outputs a driving current to the light-emitting element. The light-emitting element may emit light in response to the driving current. The pixel circuit includes a transistor having a first transistor and a second transistor and a capacitor having a first capacitor and a second capacitor. The pixel circuit may include a first transistor, a constant current control circuit, and a pulse width control circuit. Reference may be made to Figure 2 and Figure 3 to describe the pixel PX in more detail.

[0029] The gate cleaning driver 120 may generate a scan signal, a cleaning voltage SWP, and first to fourth control signals in response to a first driving control signal CONT1 provided from the timing controller 140. The gate cleaning driver 120 may sequentially generate the scan signal. The sequentially generated scan signal may be provided to the pixel PX through the scan lines. The pixel PX may receive the scan signal SCAN_n through the scan line SL_n.

[0030] The gate cleaning driver 120 may generate a first control signal EMP, a second control signal CON, a third control signal EM, and a fourth control signal EMB. The first control signal EMP, the second control signal CON, the third control signal EM, and the fourth control signal EMB may be provided to the pixel PX through the first to fourth control lines CL1 to CL4, respectively. The pixel PX may receive the first control signal EMP through the first control line CL1, the second control signal CON through the second control line CL2, the third control signal EM through the third control line CL3, and the fourth control signal EMB through the fourth control line CL4.

[0031] The gate cleaning driver 120 may generate a cleaning voltage SWP that changes substantially linearly during a preset time period, and may supply the generated cleaning voltage SWP to the pixel PX through a cleaning voltage line. The cleaning voltage SWP may have a value that increases or decreases substantially linearly during a preset time period (e.g., an emission duration). The cleaning voltage SWP may be a voltage having a certain value during a time period other than the preset time period (e.g., a threshold voltage storage time period and a data write time period). The pixel PX may receive the cleaning voltage SWP through the cleaning voltage line VL.

[0032] The data driver 130 may receive image data DATA2 provided from the timing controller 140 in a display mode in which the display panel 100 displays an image, and may generate a data voltage DATA, a bias voltage BIAS, and a reference voltage REF in response to a second driving control signal CONT2 provided from the timing controller 140.

[0033] The data driver 130 generates the data voltage DATA by performing at least digital-to-analog conversion on the image data DATA2 in response to the second driving control signal CONT2, and outputs the data voltage DATA to the data line DL. The data driver 130 generates the bias voltage BIAS in response to the second driving control signal CONT2, and outputs the bias voltage BIAS to the bias voltage line BL. The data driver 130 generates the reference voltage REF in response to the second driving control signal CONT2, and outputs the reference voltage REF to the reference voltage line RL.

[0034] The data voltage DATA may have a value determined based on the gray value of the image data DATA2. The bias voltage BIAS and the reference voltage REF may have values set by a user or values preset by a designer of the display panel 100.

[0035] The pixel PX may receive the data voltage DATA through the data line DL, receive the bias voltage BIAS through the bias voltage line BL, and receive the reference voltage REF through the reference voltage line RL.

[0036] The voltage generator 150 generates a first driving voltage PVDD and a second driving voltage PVSS for driving the pixel PX of the display unit 110 in response to a third driving control signal CONT3. The first driving voltage PVDD is applied to the first power line PL1, and the second driving voltage PVSS is applied to the second power line PL2. In an emission region where the emission element emits light, the voltage level of the first driving voltage PVDD may be greater than the voltage level of the second driving voltage PVSS.

[0037] According to another embodiment, the voltage generator 150 may generate at least one of a cleaning voltage SWP, a bias voltage BIAS, and a reference voltage REF.

[0038] The timing controller 140 may control the display unit 110 by controlling the gate cleaning driver 120, the data driver 130, and the voltage generator 150. The timing controller 140 receives a control signal CONT and image data DATA1 from an external device. The timing controller 140 may generate a first driving control signal CONT1 to a third driving control signal CONT3 by using the control signal CONT.

[0039] The display panel 100 may display an image by using the pixels PX of the display unit 110. The display panel 100 may display an updated image in each frame period. A frame period may sequentially include a threshold voltage storage period, a data write period, and an emission duration.

[0040] During the threshold voltage storage period, a first compensation voltage generated by adding the threshold voltage of the first transistor to the difference between the bias voltage BIAS and the reference voltage REF is stored in the first capacitor, and the threshold voltage of the second transistor is stored in the second capacitor. During the data write period, the pixel circuit receives a data voltage DATA in synchronization with a scan signal, and a second compensation voltage generated by adding the threshold voltage of the second transistor to a voltage corresponding to the data voltage DATA may be stored in the second capacitor.

[0041] During the emission duration, the first capacitor may be connected between the gate and the source of the first transistor, so that the emission element may emit light in response to a driving current. Then, a voltage generated by adding the substantially linearly varying cleaning voltage SWP to the second compensation voltage is applied to the gate of the second transistor, so that the emission element may stop emitting light after the emission duration corresponding to the pulse width of the driving current.

[0042] Although the first transistors included in the pixels PX preferably have the same characteristics, the first transistors may have different characteristics due to process errors and / or deterioration conditions, etc. When a deviation in the characteristics of the first transistor occurs, a deviation in the value of the driving current output to the emission element may be generated in the pixel circuits of each pixel PX. When a deviation in the value of the driving current occurs, the emission elements of the respective pixels PX may emit light with different brightnesses, and particularly for inorganic micro LEDs, the wavelengths of the emitted light may be different. According to this embodiment, the value deviation of the driving current caused by the deviation in the first transistor can be compensated by a pixel circuit within the pixel PX (such as a constant current control circuit within the pixel PX) without relying on an external circuit.

[0043] Although the second transistors included in the pixel PX preferably have the same characteristics, the second transistors may have different characteristics due to process errors and / or degradation conditions, etc. When a deviation in the characteristics of the second transistors occurs, in the pixel circuit of each pixel PX, the pulse width of the drive current output to the emitting element may not be accurately controlled. When the pulse width is not accurately controlled, the gray scale represented by each pixel PX may become inaccurate. According to the present embodiment, the pulse width deviation of the drive current caused by the deviation in the second transistors can be compensated by the pixel circuit in the pixel PX (such as by the pulse width control circuit in the pixel PX) without relying on an external circuit.

[0044] Figure 2 A pixel PX according to an embodiment is shown.

[0045] Referring Figure 2 , the pixel PX includes a pixel circuit 10 and an emitting element 20. The pixel circuit 10 outputs a drive current to the emitting element 20, and the emitting element 20 emits light in response to the drive current. The pixel circuit 10 includes a drive power supply 12, a pulse width control circuit 14, and a constant current control circuit 16. Although the drive power supply 12 and the constant current control circuit 16 are shown separately for ease of description, the drive power supply 12 may be incorporated into the constant current control circuit 16, for example but not limited to.

[0046] The drive power supply 12 includes a first transistor. The first transistor may generate a drive current to be provided to the emitting element 20.

[0047] The pulse width control circuit 14 may receive a data voltage DATA for determining the emission duration of the emitting element 20. The pulse width control circuit 14 may include a second transistor for controlling the pulse width of the drive current according to the data voltage DATA and a second capacitor for storing a second compensation voltage corresponding to the threshold voltage of the second transistor. The second compensation voltage may be a voltage generated by adding the threshold voltage of the second transistor to the voltage corresponding to the data voltage DATA.

[0048] The pulse width control circuit 14 can store the second compensation voltage in the second capacitor and can receive a substantially linearly varying sweep voltage SWP during a preset time period. The pulse width control circuit 14 can apply the voltage generated by adding the second compensation voltage to the sweep voltage SWP to the gate of the second transistor. As the gate voltage of the second transistor gradually increases due to the sweep voltage SWP, when the voltage generated by adding the sweep voltage SWP to the second compensation voltage is greater than the voltage generated by adding the cut-off voltage of the second transistor to the threshold voltage, the second transistor can conduct after the emission duration corresponding to the gray value of the image data DATA2. When the second transistor conducts, the second transistor transfers the cut-off voltage to the gate of the first transistor, and the first transistor cuts off after the emission duration. Therefore, the emission element 20 does not emit light after the emission duration and emits light only during the emission duration.

[0049] The pulse width control circuit 14 can be connected to the data line DL, the reference voltage line RL, the scan line SL_n, the sweep voltage line VL, and the second control line CL2 to the fourth control line CL4. The pulse width control circuit 14 can receive the data voltage DATA through the data line DL and the reference voltage REF through the reference voltage line RL. The pulse width control circuit 14 can receive the scan signal SCAN_n through the scan line SL_n, the sweep voltage SWP through the sweep voltage line VL, and the second control signal CON, the third control signal EM, and the fourth control signal EMB through the second control line CL2 to the fourth control line CL4.

[0050] The constant current control circuit 16 can receive the bias voltage BIAS and the reference voltage REF for setting the value of the drive current. The constant current control circuit 16 can include a first capacitor that stores the first compensation voltage generated by adding the threshold voltage of the first transistor to the difference between the bias voltage BIAS and the reference voltage REF.

[0051] The constant current control circuit 16 can store the first compensation voltage in the first capacitor and connect the first capacitor between the gate and the source of the first transistor. The first transistor controlled by the constant current control circuit 16 can generate a drive current having a preset value.

[0052] The constant current control circuit 16 can be connected to the bias voltage line BL, the reference voltage line RL, and the first control line CL1, the third control line CL3, and the fourth control line CL4. The constant current control circuit 16 can receive the bias voltage BIAS through the bias voltage line BL and receive the reference voltage REF through the reference voltage line RL. The constant current control circuit 16 can receive the first control signal EMP, the third control signal EM, and the fourth control signal EMB through the first control line CL1, the third control line CL3, and the fourth control line CL4, respectively.

[0053] The drive current generated by the drive power supply 12 flows from the first power line PL1 to the second power line PL2. The drive current flows through the emission element 20, and the emission element 20 emits light with a brightness corresponding to the value of the drive current.

[0054] The constant current control circuit 16 can control the drive power supply 12 by compensating for the value deviation of the drive current caused by the deviation of the threshold voltage of the first transistor so that the drive current can have a preset value. Therefore, the emission element 20 can emit light with a preset wavelength at a preset brightness.

[0055] The pulse width control circuit 14 can control the drive power supply 12 by compensating for the pulse width deviation of the drive current caused by the deviation of the threshold voltage of the second transistor so that the drive current can have a pulse width corresponding to the gray value of the image data DATA2. Therefore, the emission element 20 can accurately represent the gray level by emitting light during the emission duration corresponding to the gray value of the image data DATA2.

[0056] Figure 3 An electronic circuit of the pixel PX according to an embodiment is shown.

[0057] Referring to Figure 3 , the pixel PX may include an emission element mLED (20) and a pixel circuit ( Figure 2 10) that outputs a drive current Id to the emission element mLED. The pixel circuit 10 includes a drive power supply 12, a pulse width control circuit 14, and a constant current control circuit 16.

[0058] The drive power supply 12 includes a first transistor T1, the pulse width control circuit 14 includes second transistors T2 to seventh transistors T7, and second capacitors Cst2 and third capacitors Cpr, and the constant current control circuit 16 includes eighth transistors T8 to twelfth transistors T12 and a first capacitor Cst1. Figure 3The circuit diagram of pixel PX is merely an example, and the characteristics of each component and / or the connections between components can be changed without limitation. Although the first transistor T1 to the twelfth transistor T12, the first capacitor Cst1, the second capacitor Cst2, and the third capacitor Cpr are classified herein for the purpose of description as forming the driving power supply 12, the pulse width control circuit 14, and the constant current control circuit 16, this classification can be merely an arbitrary example for convenience of description and is not limited thereto.

[0059] For example, Figure 3 It is shown that the eighth transistor T8 is included in the constant current control circuit 16, but the eighth transistor T8 participates in the driving of the pulse width control circuit 14 through the third capacitor Cpr. Therefore, it can be considered that the eighth transistor T8 is included in the pulse width control circuit 14. In addition, the eighth transistor T8 and the twelfth transistor T12 together with the first transistor T1 form a current path between the first power line PL1 and the second power line PL2, and thus can be included in the driving power supply 12.

[0060] The first transistor T1 to the twelfth transistor T12 can be an n-type MOSFET as shown in Figure 3 , but is not limited thereto. The first transistor T1 to the twelfth transistor T12 can be a thin film transistor, but is not limited thereto. The first transistor T1 to the twelfth transistor T12 can include a semiconductor material of metal oxide, but is not limited thereto. For example, the first transistor T1 to the twelfth transistor T12 can each include an active layer containing metal oxide.

[0061] Hereinafter, as shown in Figure 3 , the first transistor T1 to the twelfth transistor T12 of pixel PX are n-type MOSFETs. However, the first transistor T1 to the twelfth transistor T12 can be p-type MOSFETs, and the interconnections of the pixel circuit 10 can be changed accordingly. The disclosed exemplary embodiments can be similarly applied to pixel PX including one or more p-type MOSFETs and the display panel 100 including pixel PX.

[0062] The emitting element mLED can be a micro LED that uses an inorganic material as the emitting material and has a micron-scale size (for example, a size less than or equal to about 100 microns). The emitting element mLED is connected between the source of the first transistor T1 and the second power line PL2. According to an embodiment, as shown in Figure 3As shown, the anode of the emitting element mLED may be connected to the second connection electrode of the twelfth transistor T12, and the cathode of the emitting element mLED may be connected to the second power line PL2 to which the second driving voltage PVSS is applied. According to another embodiment, the emitting element mLED may be connected between the first power line PL1 to which the first driving voltage PVDD is applied and the drain of the first transistor T1.

[0063] The first transistor T1 may include a gate connected to the first node A, a drain connected to the first power line PL1 to which the first driving voltage PVDD is applied, and a source connected to the anode of the emitting element mLED. The first transistor T1 outputs a driving current Id, and the value of the driving current Id is determined based on the voltage applied between the gate and the source of the first transistor T1 and based on the threshold voltage of the first transistor T1.

[0064] The second transistor T2 includes a control electrode, a first connection electrode, and a second connection electrode. The control electrode, the first connection electrode, and the second connection electrode may be used as a gate electrode, a drain electrode, and a source electrode, and may be referred to as a gate, a drain, and a source, respectively, but are not limited thereto. When the voltage between the control electrode and the second connection electrode is greater than the threshold voltage of the second transistor T2, the second transistor T2 is turned on. When the voltage between the control electrode and the first connection electrode is greater than the threshold voltage of the second transistor T2, the second transistor T2 is also turned on.

[0065] The second capacitor Cst2 includes a second electrode and a first electrode connected to the control electrode of the second transistor T2. The second capacitor Cst2 may store the threshold voltage of the second transistor T2 or a second compensation voltage corresponding to the threshold voltage of the second transistor T2. The second compensation voltage corresponds to the threshold voltage of the second transistor T2. Therefore, the second compensation voltage is determined based on the threshold voltage of the second transistor T2. For example, the second compensation voltage corresponding to the threshold voltage of the second transistor T2 may be a voltage generated by adding an arbitrary voltage to the threshold voltage of the second transistor T2. The second compensation voltage increases in proportion to the increase in the threshold voltage of the second transistor T2, and the second compensation voltage decreases in proportion to the decrease in the threshold voltage of the second transistor T2.

[0066] The third transistor T3 includes a control electrode connected to the scan line SL_n for transmitting the scan signal SCAN_n, a first connection electrode connected to the data line DL for transmitting the data voltage DATA, and a second connection electrode connected to the control electrode of the second transistor T2. The third transistor T3 may apply the data voltage DATA to the control electrode of the second transistor T2 in response to the scan signal SCAN_n.

[0067] The fourth transistor T4 includes a control electrode connected to a second control line CL2 that transmits a second control signal CON, a first connection electrode connected to the gate of the first transistor T1, and a second connection electrode connected to the first connection electrode of the second transistor T2. The fourth transistor T4 can connect the gate of the first transistor T1 and the first connection electrode of the second transistor T2 to each other in response to the second control signal CON.

[0068] The fifth transistor T5 includes a control electrode connected to a fourth control line CL4 that transmits a fourth control signal EMB, a first connection electrode connected to the second electrode of the second capacitor Cst2, and a second connection electrode connected to the second connection electrode of the second transistor T2. The fifth transistor T5 can connect the second capacitor Cst2 between the control electrode and the second connection electrode of the second transistor T2 in response to the fourth control signal EMB.

[0069] The sixth transistor T6 includes a control electrode connected to a third control line CL3 that transmits a third control signal EM, a first connection electrode connected to a sweep voltage line VL that transmits a sweep voltage SWP, and a second connection electrode connected to the second electrode of the second capacitor Cst2. The sixth transistor T6 applies the sweep voltage SWP to the second electrode of the second capacitor Cst2 in response to the third control signal EM.

[0070] The seventh transistor T7 includes a control electrode connected to a third control line CL3 that transmits a third control signal EM, a first connection electrode connected to the second connection electrode of the second transistor T2, and a second connection electrode connected to a reference voltage line RL that transmits a reference voltage REF. The seventh transistor T7 applies the reference voltage REF to the second connection electrode of the second transistor T2 in response to the third control signal EM.

[0071] The third capacitor Cpr can include a first electrode connected to the second connection electrode of the second transistor T2 and a second electrode to which a constant voltage is applied during a preset period. The preset period can at least include the time point from when the voltage corresponding to the data voltage DATA is stored in the second capacitor Cst2 to the time point when the second capacitor Cst2 is separated from the second node B. As Figure 3 shown, the second electrode of the third capacitor Cpr can be connected to a second power line PL2 through which a second driving voltage PVSS is applied. According to another embodiment, the second electrode of the third capacitor Cpr can be connected to one of a bias voltage line BL, a sweep voltage line VL, a reference voltage line RL, or one of the first control line CL1 to the third control line CL3.

[0072] The first capacitor Cst1 includes a first electrode and a second electrode connected to the source of the first transistor T1. The first capacitor Cst1 can store a first compensation voltage corresponding to the threshold voltage of the first transistor T1.

[0073] The eighth transistor T8 includes a control electrode connected to the first control line CL1 that transmits the first control signal EMP, a first connection electrode connected to the first power line PL1 that transmits the first driving voltage PVDD, and a second connection electrode connected to the drain of the first transistor T1. The eighth transistor T8 can apply the first driving voltage PVDD to the drain of the first transistor T1 in response to the first control signal EMP.

[0074] The ninth transistor T9 includes a control electrode connected to the fourth control line CL4 that transmits the fourth control signal EMB, a first connection electrode connected to the reference voltage line RL that transmits the reference voltage REF, and a second connection electrode connected to the gate of the first transistor T1. The ninth transistor T9 can apply the reference voltage REF to the gate of the first transistor T1 in response to the fourth control signal EMB.

[0075] The tenth transistor T10 includes a control electrode connected to the fourth control line CL4 that transmits the fourth control signal EMB, a first connection electrode connected to the bias voltage line BL that transmits the bias voltage BIAS, and a second connection electrode connected to the first electrode of the first capacitor Cst1. The tenth transistor T10 can apply the bias voltage BIAS to the first electrode of the first capacitor Cst1 in response to the fourth control signal EMB.

[0076] The eleventh transistor T11 includes a control electrode connected to the third control line CL3 that transmits the third control signal EM, a first connection electrode connected to the first electrode of the first capacitor Cst1, and a second connection electrode connected to the gate of the first transistor T1. The eleventh transistor T11 can connect the first capacitor Cst1 between the gate and the source of the first transistor T1 in response to the third control signal EM.

[0077] The twelfth transistor T12 includes a control electrode connected to the third control line CL3 that transmits the third control signal EM, a first connection electrode connected to the source of the first transistor T1, and a second connection electrode connected to the emitting element mLED. The twelfth transistor T12 can connect the source of the first transistor T1 and the emitting element mLED to each other in response to the third control signal EM, and transmit the driving current Id generated in the first transistor T1 to the emitting element mLED.

[0078] Hereinafter, reference will be made to Figure 4 Describe the driving of the pixel PX.

[0079] Figure 4shows a timing for one frame period of driving Figure 3 the pixel PX.

[0080] Referring to Figure 3 and Figure 4 , the pixel PX can receive updated data voltage DATA in each frame period of the display image, and can display a gray level corresponding to the received data voltage DATA. One frame 1Frame can include, for example, an initialization and compensation period TP1 for threshold voltage storage, a data addressing and writing period TP2, and an emission period TP3.

[0081] In the initialization and compensation period TP1, a first compensation voltage generated by adding the threshold voltage of the first transistor T1 to the difference between the bias voltage BIAS and the reference voltage REF is stored in the first capacitor Cst1, and the threshold voltage of the second transistor T2 is stored in the second capacitor Cst2. Hereinafter, the threshold voltage of the first transistor T1 is referred to as the first threshold voltage Vth1, and the threshold voltage of the second transistor T2 is referred to as the second threshold voltage Vth2.

[0082] In the data addressing and writing period TP2, the data voltage DATA is received synchronously with the scan signal SCAN_n, and a second compensation voltage generated by adding the second threshold voltage Vth2 to the voltage corresponding to the data voltage DATA is stored in the second capacitor Cst2.

[0083] The emission period TP3 is a period in which the emission element mLED can emit light. In the emission period TP3, the first capacitor Cst1 is connected between the gate and the source of the first transistor T1, and the emission element mLED emits light in response to the drive current Id. In the emission period TP3, a sweep voltage SWP that can increase monotonically and / or substantially linearly is received. A voltage generated by adding the sweep voltage SWP to the second compensation voltage (e.g., DATA plus Vth2) is applied to the gate of the second transistor T2, and after the emission duration corresponding to the gray level value of the image data DATA2 corresponding to the pixel PX, the emission element mLED stops emitting light.

[0084] The initialization and compensation period TP1 can be divided into a first period DP1 to a third period DP3, the data addressing and writing period TP2 can be divided into a fourth period DP4 to an eighth period DP8, and the emission period TP3 can be divided into a ninth period DP9 and a tenth period DP10.

[0085] The first time period DP1 can be a standby time period, the second time period DP2 can be an initialization time period, the third time period DP3 can be a threshold voltage generation time period, the fourth time period DP4 can be a threshold voltage holding time period, the fifth time period DP5 can be a pre-charge time period, the sixth time period DP6 can be a data writing time period, the seventh time period DP7 can be a data holding time period, the eighth time period DP8 can be a transmission preparation time period, the ninth time period DP9 can be a cleaning time period such as for transmission start, and the tenth time period DP10 can be a cleaning time period such as for transmission stop.

[0086] The first driving voltage PVDD can be at a low level PVDD_LO (e.g., -4V) during the first time period DP1 and the second time period DP2, and at a high level PVDD_HI (e.g., 8V) during the third time period DP3 to the tenth time period DP10. The second driving voltage PVSS can be at a low level (e.g., -4V) during the first time period DP1 to the tenth time period DP10.

[0087] The scan signal SCAN_n can be at a high level during the first time period DP1 to the third time period DP3, the fifth time period DP5, and the sixth time period DP6, and at a low level during the fourth time period DP4 and the seventh time period DP7 to the tenth time period DP10. The previous scan signal SCAN_n-1 is at a high level together with the scan signal SCAN_n during the first time period DP1 to the third time period DP3. The third transistor T3 conducts in response to the scan signal SCAN_n being at a high level and cuts off in response to the scan signal SCAN_n being at a low level.

[0088] The first control signal EMP is at a high level during the first time period DP1 to the third time period DP3, the ninth time period DP9, and the tenth time period DP10, and at a low level during the fourth time period DP4 to the eighth time period DP8. The eighth transistor T8 conducts in response to the first control signal EMP being at a high level and cuts off in response to the first control signal EMP being at a low level.

[0089] The second control signal CON is at a high level during the first time period DP1 to the third time period DP3, the ninth time period DP9, and the tenth time period DP10, and at a low level during the fourth time period DP4 to the eighth time period DP8. The fourth transistor T4 conducts in response to the second control signal CON being at a high level and cuts off in response to the second control signal CON being at a low level. During the eighth time period DP8, the second control signal CON can transition to a high level faster or earlier than the first control signal EMP.

[0090] The third control signal EM is at a low level in the first time period DP1 to the seventh time period DP7, and is at a high level in the eighth time period DP8 to the tenth time period DP10. The sixth transistor T6, the seventh transistor T7, the eleventh transistor T11, and the twelfth transistor T12 are turned on in response to the third control signal EM being at a high level, and are turned off in response to the third control signal EM being at a low level.

[0091] Contrary to the third control signal EM, the fourth control signal EMB is at a high level in the first time period DP1 to the seventh time period DP7, and is at a low level in the eighth time period DP8 to the tenth time period DP10. The fifth transistor T5, the ninth transistor T9, and the tenth transistor T10 are turned on in response to the fourth control signal EMB being at a high level, and are turned off in response to the fourth control signal EMB being at a low level.

[0092] In the first time period DP1, first, the third control signal EM can change to a low level, and then the fourth control signal EMB can change to a high level. Therefore, there is no need to have a time period in which both the third control signal EM and the fourth control signal EMB are at a high level. After the fourth control signal EMB changes to a low level in the eighth time period DP8, the third control signal EM can change to a high level.

[0093] The data voltage DATA is at the reference level Vc_data (e.g., -1V) in the first time period DP1 to the third time period DP3, and is at a data level corresponding to the gray value of the image data DATA2 (e.g., -7V to 0V) in the fourth time period DP4 to the sixth time period DP6. The data voltage DATA can be at the data level Vd_n - 1 applied to the pixels of the previous row in the fifth time period DP5, and is at the data level Vd_n applied to the pixels PX of the current row in the sixth time period DP6. In the seventh time period DP7 to the tenth time period DP10, the data voltage DATA can be at the reference level Vc_data.

[0094] In one frame 1Frame of the first time period DP1 to the tenth time period DP10, the bias voltage BIAS can be kept constant at the reference level Vc_bias (e.g., 7V).

[0095] The reference voltage REF is at a low level (e.g., -6V) in the first time period DP1, is at a high level REF_HI (e.g., 0V) in the second time period DP2 to the seventh time period DP7, and is at a low level REF_LO (e.g., -5V) in the ninth time period DP9 and the tenth time period DP10. The reference voltage REF changes from the high level REF_HI to the low level REF_LO in the eighth time period DP8.

[0096] The cleaning voltage SWP can be at a high level (e.g., -1V) during the first time period DP1 to the seventh time period DP7, and transitions to a low level (e.g., -6V) during the eighth time period DP8. That is, the cleaning voltage SWP can transition from a high level to a low level during the eighth time period DP8, and then the reference voltage REF can transition from a high level REF_HI to a low level REF_LO. The cleaning voltage SWP can monotonically or substantially linearly increase from a low level (e.g., -6V) to a high level (e.g., -1V) during the ninth time period DP9 and the tenth time period DP10.

[0097] During the first time period DP1, the first driving voltage PVDD transitions to a low level PVDD_LO (e.g., -4V), and the twelfth transistor T12 is turned off in response to the third control signal EM being at a low level. No current flows between the first power line PL1 and the second power line PL2, and the emitting element mLED does not emit light.

[0098] The ninth transistor T9 and the tenth transistor T10 are turned on in response to the fourth control signal EMB being at a high level. The reference voltage REF at a low level (e.g., -6V) is applied to the gate of the first transistor T1 through the ninth transistor T9, and the first transistor T1 is turned off. The bias voltage BIAS at the reference level Vc_bias (e.g., 7V) is applied to the first electrode of the first capacitor Cst1 through the tenth transistor T10.

[0099] The third transistor T3 is turned on in response to the scan signal SCAN_n being at a high level, the fifth transistor T5 is turned on in response to the fourth control signal EMB being at a high level, and the fourth transistor T4 is turned on in response to the second control signal CON being at a high level.

[0100] The reference voltage REF at a low level (e.g., -6V) is applied to the first connection electrode of the second transistor T2 through the fourth transistor T4. Since the data voltage DATA at the reference level Vc_data (e.g., -1V) is applied to the control electrode of the second transistor T2 through the third transistor T3, the second transistor T2 is turned on. The reference voltage REF at a low level (e.g., -6V) is applied to the second node B and is applied to the second electrode of the second capacitor Cst2 through the fifth transistor T5.

[0101] The sixth transistor T6, the seventh transistor T7, and the eleventh transistor T11 are turned off in response to the third control signal EM being at a low level.

[0102] During a second time period DP2, the reference voltage REF transitions from a low level (e.g., -6V) to a high level REF_HI (e.g., 0V). Since the reference voltage REF at the high level REF_HI (e.g., 0V) is applied to the gate of the first transistor T1 through the ninth transistor T9, the first transistor T1 is turned on.

[0103] The first driving voltage PVDD at a low level PVDD_LO (e.g., -4V) is applied to the second electrode of the first capacitor Cst1 through the first transistor T1. The bias voltage BIAS at a reference level Vc_bias (e.g., 7V) is applied to the source of the first transistor T1.

[0104] The reference voltage REF at a high level REF_HI (e.g., 0V) is applied to the first connection electrode of the second transistor T2 through the fourth transistor T4. The voltage of the second electrode of the second capacitor Cst2 and the second node B can gradually increase. When the voltage of the second node B increases to a voltage Vc_data - Vth2 generated by subtracting the second threshold voltage Vth2 of the second transistor T2 from the data voltage DATA at a reference level Vc_data (e.g., -1V) applied to the gate of the second transistor T2, the second transistor T2 is turned off, and the voltage of the second electrode of the second capacitor Cst2 and the second node B no longer increases. The second threshold voltage Vth2 of the second transistor T2 is stored between the first electrode and the second electrode of the second capacitor Cst2.

[0105] During a third time period DP3, the first driving voltage PVDD transitions from a low level PVDD_LO (e.g., -4V) to a high level PVDD_HI (e.g., 8V). Since the first transistor T1 is turned on, the voltage of the second electrode of the first capacitor Cst1 and the third node C gradually increases. When the voltage of the third node C increases to a voltage REF_HI - Vth1 generated by subtracting the first threshold voltage Vth1 of the first transistor T1 from the reference voltage REF at a high level REF_HI (e.g., 0V) applied to the gate of the first transistor T1, the first transistor T1 is turned off, and the voltage of the second electrode of the first capacitor Cst1 and the third node C no longer increases. The first compensation voltage Vc_bias - REF_HI + Vth1 generated by subtracting the voltage REF_HI - Vth1 from the bias voltage BIAS at a reference level Vc_bias (e.g., 7V) is stored between the first electrode and the second electrode of the first capacitor Cst1.

[0106] In the fourth time period DP4, the scan signal SCAN_n, the first control signal EMP, and the second control signal CON transition to a low level. As a result, the third transistor T3, the eighth transistor T8, and the fourth transistor T4 are turned off. The first compensation voltage Vc_bias-REF_HI+Vth1 is stored in the first capacitor Cst1, and the second threshold voltage Vth2 of the second transistor T2 remains stored in the second capacitor Cst2. A data voltage DATA corresponding to the gray value of the image data DATA2 and at a data level (e.g., -7V to 0V) is applied to the data line DL.

[0107] The previous scan signal SCAN_n-1 transitions to a high level before the fifth time period DP5. In the fifth time period DP5, the scan signal SCAN_n transitions to a high level, and the third transistor T3 is turned on. The data voltage DATA has a data level Vd_n-1 (e.g., -7V to 0V) of the data applied to the pixels of the previous row.

[0108] The data voltage DATA at the data level Vd_n-1 (e.g., -7V to 0V) is applied to the gate of the second transistor T2 and the first electrode of the second capacitor Cst2 through the third transistor T3. Since the potential of the first electrode of the second capacitor Cst2 changes, the potential of the second node B also changes due to the charge sharing between the second capacitor Cst2 and the third capacitor Cpr. The second transistor T2 can be turned on or off according to the data level Vd_n-1 (e.g., -7V to 0V) of the data voltage DATA.

[0109] In the sixth time period DP6, the previous scan signal SCAN_n-1 transitions to a low level, and a data voltage DATA at the data level Vd_n (e.g., -7V to 0V) is applied to the data line DL.

[0110] The data voltage DATA at the data level Vd_n (e.g., -7V to 0V) is applied to the gate of the second transistor T2 and the first electrode of the second capacitor Cst2 through the third transistor T3. Since the potential of the first electrode of the second capacitor Cst2 changes from the data voltage DATA at the reference level Vc_data (e.g., -1V) to the data voltage DATA at the data level Vd_n (e.g., -7V to 0V), the potential of the second node B also changes due to the charge sharing between the second capacitor Cst2 and the third capacitor Cpr.

[0111] Before the fourth time period DP4, the potential of the second node B is already Vc_data - Vth2. Due to charge sharing, the potential of the second node B changes to Vc_data - Vth2 + Cst2 / (Cst2 + Cpr)*(Vd_n - Vc_data). Therefore, the second compensation voltage Vth2 + Cpr / (Cst2 + Cpr)*(Vd_n - Vc_data) generated by subtracting Vc_data - Vth2 + Cst2 / (Cst2 + Cpr)*(Vd_n - Vc_data) from the data voltage DATA at the data level Vd_n (e.g., -7V to 0V) is stored between the first and second electrodes of the second capacitor Cst2. The second compensation voltage Vth2 + Cpr / (Cst2 + Cpr)*(Vd_n - Vc_data) stored in the second capacitor Cst2 will be simply referred to as the second compensation voltage Vth2 + Vcst2. Vcst2 represents Cpr / (Cst2 + Cpr)*(Vd_n - Vc_data).

[0112] The second transistor T2 can be turned on or off according to the data level Vd_n (e.g., -7V to 0V) of the data voltage DATA. When the data level Vd_n is higher than the reference level Vc_data, the second transistor T2 is turned on, and when the data level Vd_n is lower than the reference level Vc_data, the second transistor T2 is turned off.

[0113] In the seventh time period DP7, the scan signal SCAN_n transitions to a low level, and the third transistor T3 is turned off. The data voltage at the reference level Vc_data (e.g., -1V) can be applied to the data line DL.

[0114] The first compensation voltage Vc_bias - REF_HI + Vth1 is stored in the first capacitor Cst1, and the second compensation voltage Vth2 + Vcst2 is stored in the second capacitor Cst2.

[0115] In the eighth time period DP8, the fourth control signal EMB transitions to a low level. Therefore, the fifth transistor T5, the ninth transistor T9, and the tenth transistor T10 are turned off. When the fifth transistor T5 is turned off, the second electrode of the second capacitor Cst2 is insulated from the second node B. When the ninth transistor T9 is turned off, the reference voltage REF is not applied to the gate of the first transistor T1. When the tenth transistor T10 is turned off, the bias voltage BIAS is not applied to the first electrode of the first capacitor Cst1.

[0116] The third control signal EM transitions to a high level, and the sixth transistor T6, seventh transistor T7, eleventh transistor T11, and twelfth transistor T12 turn on. When the sixth transistor T6 turns on, the second electrode of the second capacitor Cst2 is connected to the cleaning voltage line VL. When the seventh transistor T7 turns on, the reference voltage REF is applied to the second node B.

[0117] When the eleventh transistor T11 turns on, the first capacitor Cst1 is connected between the gate and source of the first transistor T1. Since the first compensation voltage Vc_bias - REF_HI + Vth1 stored in the first capacitor Cst1 is applied between the gate and source of the first transistor T1, the first transistor T1 can generate a drive current Id related to the voltage Vc_bias - REF_HI. When the twelfth transistor T12 turns on, the first transistor T1 is connected to the emission element mLED.

[0118] Then, the cleaning voltage SWP transitions from a high level (e.g., -1V) to a low level (e.g., -6V). Since the potential of the second electrode of the second capacitor Cst2 decreases by the difference between the high level (e.g., -1V) and the low level (e.g., -6V) of the cleaning voltage SWP (e.g., 5V), the potential of the first electrode of the second capacitor Cst2 also decreases by the difference between the high level (e.g., -1V) and the low level (e.g., -6V) of the cleaning voltage SWP (e.g., 5V).

[0119] Then, the reference voltage REF transitions from a high level REF_HI (e.g., 0V) to a low level REF_LO (e.g., -5V). The reference voltage REF at the low level REF_LO (e.g., -5V) is applied to the second connection electrode of the second transistor T2 through the seventh transistor T7.

[0120] When the gray value corresponding to the image data DATA2 corresponding to the pixel PX is 0, the pixel PX can receive the data voltage DATA at the highest data level Vd_n (for example, 0V) in the sixth time period DP6. In this case, Vth2 + Cpr / (Cst2 + Cpr)*1 is stored in the second capacitor Cst2. Since the potential of the second electrode of the second capacitor Cst2 is reduced by that difference (for example, 5V) due to the transition of the sweep voltage SWP, the potential of the gate of the second transistor T2 becomes (Vth2 + Cpr / (Cst2 + Cpr)*1) - 5V. Since the reference voltage REF at a low level REF_LO (for example, -5V) is applied to the second connection electrode of the second transistor T2, the second transistor T2 is turned on, and the reference voltage REF at a low level REF_LO (for example, -5V) is applied to the gate of the first transistor T1. Since a voltage higher than the second drive voltage PVSS is applied to the source of the first transistor T1, the first transistor T1 is turned off. That is, when the gray value of the image data DATA2 corresponding to the pixel PX is 0, the first transistor T1 is turned off before the ninth time period DP9. Therefore, the emission element mLED does not emit light.

[0121] Then, the second control signal CON transitions to a high level, and the fourth transistor T4 is turned on. As described above, when the gray value of the image data DATA2 corresponding to the pixel PX is 0, the second transistor T2 is turned on, and the reference voltage REF at a low level REF_LO (for example, -5V) is applied to the gate of the first transistor T1 through the second transistor T2 and the fourth transistor T4.

[0122] In the ninth time period DP9, the first control signal EMP transitions to a high level, so the eighth transistor T8 is turned on. Therefore, a current path is formed between the first power line PL1 and the second power line PL2. Since the first drive voltage PVDD at a high level PVDD_HI (for example, 8V) is applied to the drain of the first transistor T1, the first transistor T1 generates a drive current Id related to the voltage Vc_bias - REF_HI. The drive current Id has a value proportional to (Vc_bias - REF_HI) 2 That is, the drive current Id has a value independent of the value of the first threshold voltage Vth1 of the first transistor T1.

[0123] The emission element mLED emits light with a brightness corresponding to the drive current Id. The drive current Id is determined based on the difference between the bias voltage BIAS at the reference level Vc_bias (e.g., 7V) and the reference voltage REF at the high level REF_HI (e.g., 0V), and is independent of the value of the first threshold voltage Vth1 of the first transistor T1. Therefore, the emission element mLED emits light with a predetermined brightness without being affected by the deviation of the threshold voltage of the first transistor T1.

[0124] When the gray value of the image data DATA2 corresponding to the pixel PX is 0, the reference voltage REF at the low level REF_LO (e.g., -5V) is applied to the gate of the first transistor T1, and the first transistor T1 is turned off. Therefore, no drive current Id is generated, and the emission element mLED does not emit light.

[0125] The cleaning voltage SWP increases substantially linearly at the low level (e.g., -6V). Since the second compensation voltage Vth2 + Vcst2 is stored in the second capacitor Cst2, the voltage of the gate of the second transistor T2 becomes Vth2 + Vcst2 + SWP and increases substantially linearly in the same manner as the cleaning voltage SWP. The difference between the voltage of the gate of the second transistor T2 and the reference voltage REF at the low level REF_LO (e.g., -5V) (i.e., Vth2 + Vcst2 + SWP - REF_LO) also gradually increases. When the voltage between the gate and the source of the second transistor T2 becomes equal to the second threshold voltage Vth2 of the second transistor T2, that is, when Vcst2 + SWP - REF_LO becomes 0, the second transistor T2 is turned on, and the reference voltage REF at the low level REF_LO (e.g., -5V) is applied to the gate of the first transistor T1. When the first transistor T1 is turned off, no drive current Id is generated, and the emission element mLED stops emitting light.

[0126] Assume that the cleaning voltage SWP increases substantially linearly from a low level (SWP_LO) (e.g., -6V) with a gradient (a) according to time (t), e.g., a*t + SWP_LO. The time point (t1) when Vcst2 + SWP - REF_LO becomes 0 is (REF_LO - Vcst2 - SWP_LO) / a. Since Vcst2 is equal to Cpr / (Cst2 + Cpr)*(Vd_n - Vc_data), the time point (t1) when the second transistor T2 turns on is determined according to the data level Vd_n of the data voltage DATA and the reference level Vc_data, and is independent of the value of the second threshold voltage Vth2 of the second transistor T2. Therefore, the time point (t1) when the second transistor T2 turns on, the first transistor T1 turns off due to the reference voltage at the low level REF_LO (e.g., -5V), and the emitting element mLED stops emitting light can be determined according to the data voltage DATA and is not affected by the deviation of the second threshold voltage Vth2 of the second transistor T2, and thus is precisely controlled by the data voltage DATA.

[0127] The ninth time period DP9 and the tenth time period DP10 are distinguished from each other according to the time point (t1) when the emitting element mLED stops emitting light.

[0128] Although the light emission of the emitting element mLED stops in the tenth time period DP10, the cleaning voltage SWP continues to increase monotonically or substantially linearly. Although the voltage of the gate of the second transistor T2 continues to increase, the second transistor T2 has turned on and the emitting element mLED does not emit light. Therefore, no change occurs in the pixel PX.

[0129] While the second transistor T2 is turned on, a reference voltage REF at a low level REF_LO (e.g., -5V) is applied to the first electrode of the second capacitor Cst2 between the ninth time period DP9 and the tenth time period DP10.

[0130] As described above, the pixel PX is driven during one frame 1Frame. Since the emitting element mLED of the pixel PX emits light with a certain brightness, this brightness is not affected by the deviation of the first threshold voltage Vth1, and is determined only by the bias voltage BIAS and the reference voltage REF during the emission duration that is not affected by the deviation of the second threshold voltage Vth2, and is determined by the data voltage DATA, the color and grayscale can be precisely represented.

[0131] According to an exemplary embodiment, a pixel circuit driven in a time-division manner may be provided to drive a light-emitting element such as a micro LED. Since the pixel circuit compensates for the threshold voltage of the internal compensation transistor, the pulse width and value of the driving current output from the pixel circuit to the light-emitting element can be precisely controlled. The light-emitting element may emit light having a certain brightness and color. Therefore, the display quality of the display panel can be optimized.

[0132] According to an exemplary embodiment, a display device includes pixels, each of which includes a first transistor, a second transistor connected to a control electrode of the first transistor, and a light-emitting element connected to a connection electrode of the first transistor. The display device may further include a time-division controller that generates a reference signal and a bias signal. The reference signal and a signal based on the bias signal are alternately connected to the control electrode of the first transistor. The signal based on the bias signal responds to the threshold voltage of the first transistor. The time-division controller may further generate a sweep signal that monotonically increases. The reference signal and the signal based on the bias signal may be alternately connected to the connection electrode of the second transistor. A signal based on the sweep signal may be connected to the control electrode of the second transistor.

[0133] It should be understood that the embodiments described herein should be considered only in a descriptive sense and not for purposes of limitation. The description of features or aspects within each embodiment should generally be considered available for other similar features or aspects in other embodiments. Although one or more embodiments have been described with reference to the accompanying drawings, those of ordinary skill in the relevant art will understand that various changes in form and detail may be made therein without departing from the spirit and scope of the present disclosure as defined by the claims.

Claims

1. A display panel, the display panel comprising: a plurality of sub-pixels, each including an emitting element and a pixel circuit, wherein, the pixel circuit includes: a first transistor configured to generate a driving current for the emitting element; a constant current control circuit configured to receive a reference voltage and a bias voltage for setting a value of the driving current, and including: a first capacitor including a first electrode and a second electrode connected to a source electrode of the first transistor, and configured to store a first compensation voltage generated by adding a threshold voltage of the first transistor to a difference between the bias voltage and the reference voltage; an eighth transistor including a first connection electrode connected to a first power line and a second connection electrode connected to a drain electrode of the first transistor; a ninth transistor including a first connection electrode connected to a reference voltage line and a second connection electrode connected to a gate electrode of the first transistor; a tenth transistor including a first connection electrode connected to a bias voltage line and a second connection electrode connected to the first electrode of the first capacitor; an eleventh transistor including a first connection electrode connected to the first electrode of the first capacitor and a second connection electrode connected to the gate electrode of the first transistor; and a twelfth transistor including a first connection electrode connected to the source electrode of the first transistor and a second connection electrode connected to the emitting element; and a pulse width control circuit configured to receive a data voltage for determining an emission duration of the emitting element, and including: a second transistor including a control electrode, a first connection electrode, and a second connection electrode, and configured to control a pulse width of the driving current according to the data voltage; a second capacitor including a second electrode and a first electrode connected to the control electrode of the second transistor, and configured to store a second compensation voltage corresponding to a threshold voltage of the second transistor; a third transistor including a first connection electrode connected to a data line and a second connection electrode connected to the control electrode of the second transistor; a fourth transistor including a first connection electrode connected to the gate electrode of the first transistor and a second connection electrode connected to the first connection electrode of the second transistor; a fifth transistor including a first connection electrode connected to the second electrode of the second capacitor and a second connection electrode connected to the second connection electrode of the second transistor; a sixth transistor including a first connection electrode connected to a cleaning voltage line and a second connection electrode connected to the second electrode of the second capacitor; a seventh transistor including a first connection electrode connected to the second connection electrode of the second transistor and a second connection electrode connected to the reference voltage line; and a third capacitor including a first electrode connected to the second connection electrode of the second transistor and a second electrode to which a constant voltage is applied during a preset time period.

2. The display panel according to claim 1, wherein: The value deviation of the driving current caused by the deviation of the first transistor included in each of the plurality of sub-pixels is internally compensated by the constant current control circuit of the pixel circuit included in each of the plurality of sub-pixels, and the pulse width deviation of the driving current caused by the deviation of the second transistor included in each of the plurality of sub-pixels is internally compensated by the pulse width control circuit of the pixel circuit included in each of the plurality of sub-pixels.

3. The display panel according to claim 1, wherein, the constant current control circuit is further configured to store the first compensation voltage in the first capacitor, connect the first capacitor between the gate and the source of the first transistor, and the first transistor is configured to generate the driving current having a set value.

4. The display panel according to claim 1, wherein, the pulse width control circuit is configured to: store the second compensation voltage in the second capacitor, the second compensation voltage being generated by adding the threshold voltage of the second transistor and the voltage corresponding to the data voltage; receive a cleaning voltage that monotonically changes during a preset time period; and control the emission duration of the emission element by applying the voltage generated by adding the second compensation voltage and the cleaning voltage to the gate of the second transistor.

5. The display panel according to claim 1, wherein, the value of the driving current is determined based on the difference between the bias voltage and the reference voltage, and is independent of the value of the threshold voltage of the first transistor.

6. The display panel according to claim 1, wherein: the pulse width of the driving current is determined by the data voltage, and is independent of the value of the threshold voltage of the second transistor.

7. The display panel according to claim 1, the display panel further comprises: a second power line for transmitting a second driving voltage to the pixel circuit; a scan line for transmitting a scan signal to the pixel circuit; and a first control line, a second control line, a third control line, and a fourth control line for respectively transmitting a first control signal, a second control signal, a third control signal, and a fourth control signal to the pixel circuit, and wherein the first power line transmits a first driving voltage to the pixel circuit, the data line transmits the data voltage to the pixel circuit synchronously with the scan signal, the bias voltage line transmits the bias voltage to the pixel circuit, the reference voltage line transmits the reference voltage to the pixel circuit, and the cleaning voltage line transmits a cleaning voltage that linearly changes during a preset time period to the pixel circuit.

8. The display panel according to claim 7, the display panel further comprises a driver for driving the plurality of sub-pixels, wherein, The driver is configured to output the first driving voltage and the second driving voltage to the first power line and the second power line respectively, output the scan signal to the scan line, output the data voltage to the data line synchronously with the scan signal, output the bias voltage to the bias voltage line, output the reference voltage to the reference voltage line, output the cleaning voltage to the cleaning voltage line, and output the first control signal, the second control signal, the third control signal, and the fourth control signal to the first control line, the second control line, the third control line, and the fourth control line respectively.

9. The display panel according to claim 7, wherein, the first transistor and the emitting element are connected in series between the first power line and the second power line.

10. The display panel according to claim 7, wherein, the third transistor further includes a control electrode connected to the scan line, the fourth transistor further includes a control electrode connected to the second control line, the fifth transistor further includes a control electrode connected to the fourth control line, the sixth transistor further includes a control electrode connected to the third control line, and the seventh transistor further includes a control electrode connected to the third control line.

11. The display panel according to claim 10, wherein, the second electrode of the third capacitor is connected to the second power line.

12. The display panel according to claim 7, wherein, the eighth transistor further includes a control electrode connected to the first control line, the ninth transistor further includes a control electrode connected to the fourth control line, the tenth transistor further includes a control electrode connected to the fourth control line, the eleventh transistor further includes a control electrode connected to the third control line, and the twelfth transistor further includes a control electrode connected to the third control line.

13. The display panel according to claim 1, the display panel further includes a driver for driving the plurality of sub-pixels, wherein, the driver is configured to drive the plurality of sub-pixels to display an image in each frame period, wherein, the frame period includes: a threshold voltage storage period, in which the first compensation voltage is stored in the first capacitor, and the threshold voltage of the second transistor is stored in the second capacitor; a data writing period, in which the data voltage is received synchronously with the scan signal, and the second compensation voltage is stored in the second capacitor; and Emission period, during which the emission element starts to emit light in response to the drive current by connecting the first capacitor between the gate and the source of the first transistor, and during the emission period, the emission element stops emitting light after the emission duration corresponding to the pulse width by applying a voltage generated by adding the second compensation voltage to a substantially linearly varying sweep voltage to the gate of the second transistor.

14. The display panel according to claim 13, wherein: the first capacitor is separated from the gate of the first transistor during the threshold voltage storage period and the data write period, and is connected between the gate and the source of the first transistor during the emission period, and the second capacitor is connected between the gate and the source of the second transistor during the threshold voltage storage period and the data write period, and is separated from the source of the second transistor during the emission period.

15. The display panel according to claim 13, wherein, during the emission period, when the voltage generated by adding the sweep voltage and the second compensation voltage is greater than the voltage generated by adding the cut-off voltage of the second transistor and the threshold voltage, after the emission period, by applying the cut-off voltage to the gate of the first transistor, the second transistor is turned on and the first transistor is turned off.

16. The display panel according to claim 1, wherein, the emission element includes a micro light-emitting diode having a size less than or equal to 100 microns and using an inorganic material as the emission material.

17. A pixel circuit, the pixel circuit being connected to at least one of a first power line and a second power line that respectively transmit a first drive voltage and a second drive voltage, at least one of a first control line, a second control line, a third control line, and a fourth control line that respectively transmit a first control signal, a second control signal, a third control signal, and a fourth control signal, a scan line that transmits a scan signal, a data line that transmits a data voltage synchronously with the scan signal, a bias voltage line that transmits a bias voltage, a reference voltage line that transmits a reference voltage, a sweep voltage line that transmits a sweep voltage that monotonically changes in a preset period, and an emission element, the pixel circuit comprises: a first transistor connected to the first power line and the emission element; a second transistor including a control electrode, a first connection electrode, and a second connection electrode; a second capacitor including a second electrode and a first electrode connected to the control electrode of the second transistor; a third transistor including a control electrode connected to the scan line, a first connection electrode connected to the data line, and a second connection electrode connected to the control electrode of the second transistor; The fourth transistor includes a control electrode connected to the second control line, a first connection electrode connected to the gate of the first transistor, and a second connection electrode connected to the first connection electrode of the second transistor; The fifth transistor includes a control electrode connected to the fourth control line, a first connection electrode connected to the second electrode of the second capacitor, and a second connection electrode connected to the second connection electrode of the second transistor; The sixth transistor includes a control electrode connected to the third control line, a first connection electrode connected to the cleaning voltage line, and a second connection electrode connected to the second electrode of the second capacitor; The seventh transistor includes a control electrode connected to the third control line, a first connection electrode connected to the second connection electrode of the second transistor, and a second connection electrode connected to the reference voltage line; The third capacitor includes a first electrode connected to the second connection electrode of the second transistor and a second electrode connected to the second power line; The first capacitor includes a first electrode and a second electrode connected to the source of the first transistor; The eighth transistor includes a first connection electrode connected to the first power line and a second connection electrode connected to the drain of the first transistor; The ninth transistor includes a first connection electrode connected to the reference voltage line and a second connection electrode connected to the gate of the first transistor; The tenth transistor includes a first connection electrode connected to the bias voltage line and a second connection electrode connected to the first electrode of the first capacitor; The eleventh transistor includes a first connection electrode connected to the first electrode of the first capacitor and a second connection electrode connected to the gate of the first transistor; and The twelfth transistor includes a first connection electrode connected to the source of the first transistor and a second connection electrode connected to the emitting element.

18. The pixel circuit according to claim 17, wherein, the eighth transistor further includes a control electrode connected to the first control line, the ninth transistor further includes a control electrode connected to the fourth control line, the tenth transistor further includes a control electrode connected to the fourth control line, the eleventh transistor further includes a control electrode connected to the third control line, and the twelfth transistor further includes a control electrode connected to the third control line.

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