Display device

Abstract

This invention relates to a display device. Specifically, a display device according to an exemplary embodiment of the invention includes pixels and a data driver, wherein each pixel includes: a first light-emitting diode aligned in a first direction; a first pixel circuit for driving the first light-emitting diode; a second light-emitting diode aligned in a second direction; and a second pixel circuit for driving the second light-emitting diode, wherein during a frame period, the data driver supplies a first data signal to the first pixel circuit and supplies a second data signal to the second pixel circuit.

Description

[0001] This application claims priority and benefit to Korean Patent Application No. 10-2020-0044130, filed with the Korean Intellectual Property Office on April 10, 2020, the entire contents of which are incorporated herein by reference. Technical Field

[0002] The present invention relates to display devices, and more specifically, to display pixels having light-emitting elements having opposite polarities. Background Technology

[0003] The importance of display devices has increased with the development of multimedia, for example. In response, various types of display devices, such as organic light-emitting diode (OLED) displays and liquid crystal displays, have been used. Furthermore, display devices can include light-emitting diodes, such as organic light-emitting diodes that use organic materials as fluorescent materials, and inorganic light-emitting diodes that use inorganic materials as fluorescent materials. Summary of the Invention

[0004] Compared to organic light-emitting diodes (OLEDs), inorganic OLEDs, such as those using inorganic semiconductors as fluorescent materials, exhibit durability even in high-temperature environments and can achieve high blue light efficiency. In the manufacturing process of such inorganic OLEDs, a transcription method using dielectric electrophoresis (DEP) can be applied. In DEP, when a dielectric is subjected to a non-uniform electric field, a force is applied to the dielectric, the strength of which depends on the electrical properties of the dielectric.

[0005] Embodiments of the present invention provide a display device that minimizes the difference in brightness between frames and substantially prevents flickering during frame changes by driving all light-emitting diodes included in the pixels.

[0006] Embodiments of the present invention provide a display device that minimizes the difference in brightness between pixels arranged on the same horizontal line (or the same pixel row) and improves reliability by driving all light-emitting diodes included in the pixels.

[0007] The embodiments of the present invention are not limited to those mentioned above. Based on the following description, those skilled in the art will clearly understand other technical options not mentioned.

[0008] A display device according to an embodiment of the present invention includes: a pixel connected to a data line; and a data driver supplying data signals to the data line, wherein each of the pixels includes: a first light-emitting diode aligned in a first direction; a first pixel circuit for driving the first light-emitting diode; a second light-emitting diode aligned in a second direction; and a second pixel circuit for driving the second light-emitting diode, wherein during a frame period, the data driver supplies a first data signal to the first pixel circuit and a second data signal to the second pixel circuit.

[0009] In an embodiment, the data driver may supply a first data signal during a first time period in a first frame period, supply a second data signal during a second time period after the first time period in the first frame period, and supply the first data signal during the first time period in the second frame period and the second data signal during the second time period in the second frame period.

[0010] In an embodiment, the first pixel circuit may include: a first transistor, including a first electrode connected to a first power line, a second electrode connected to a first node, and a gate electrode connected to a second node, wherein the first node is connected to the first electrode of a first light-emitting diode and the second electrode of a second light-emitting diode; a second transistor, connected between a data line and the second node, and including a gate electrode connected to a first scan line; and a third transistor, connected between the first node and a sensing line, and including a gate electrode connected to a second scan line.

[0011] In an embodiment, a pixel can be connected to a third scan line and a fourth scan line. The second pixel circuit can include: a fourth transistor, including a first electrode connected to a second power line, a second electrode connected to a third node, and a gate electrode connected to a fourth node, wherein the third node is connected to the second electrode of a first light-emitting diode and the first electrode of a second light-emitting diode; a fifth transistor, connected between a data line and a fourth node, and including a gate electrode connected to the third scan line; and a sixth transistor, connected between the third node and a sensing line, and including a gate electrode connected to the fourth scan line.

[0012] In an embodiment, during the first frame period, a first scan signal at the on level can be supplied to the first scan line during the first time period, a second scan signal at the on level can be supplied to the second scan line during the first time period, and a first data signal can be supplied to the second node and an initialization voltage can be supplied to the sensing line during the first time period.

[0013] In an embodiment, during the first frame period, a third scan signal at the on level can be supplied to the third scan line during a second time period after the first time period, a fourth scan signal at the on level can be supplied to the fourth scan line during the second time period, and during the second time period, a second data signal can be supplied to the fourth node, and an initialization voltage can be supplied to the sensing line.

[0014] In an embodiment, the first data signal may be a signal corresponding to a grayscale value, and the second data signal may be the same as the first data signal or a signal at a level that turns on the fourth transistor and does not correspond to a grayscale value.

[0015] In an embodiment, during a second frame period different from the first frame period, a third scan signal at the on level can be supplied to the third scan line during a first time period, a fourth scan signal at the on level can be supplied to the fourth scan line during the first time period, and a first data signal can be supplied to the fourth node and an initialization voltage can be supplied to the sensing line during the first time period.

[0016] In an embodiment, during the second frame period, a first scan signal at the on level can be supplied to the first scan line during a second time period after the first time period, a second scan signal at the on level can be supplied to the second scan line during the second time period, and during the second time period, a second data signal can be supplied to the second node, and an initialization voltage can be supplied to the sensing line.

[0017] In an embodiment, the first data signal may be a signal corresponding to a grayscale value, and the second data signal may be the same as the first data signal or a signal at a level that turns on the first transistor and does not correspond to a grayscale value.

[0018] In this embodiment, the second scan line and the fourth scan line may be the same, and the second scan signal and the fourth scan signal may be the same.

[0019] In an embodiment, the second scan signal and the fourth scan signal can be supplied during the same time period.

[0020] In an embodiment, the display device may further include a power supply that supplies a first power supply voltage at a first level and a second power supply voltage at a second level lower than the first level during a first frame period, and supplies a first power supply voltage at the second level and a second power supply voltage at the first level during a second frame period.

[0021] In an embodiment, the first pixel circuit may include: a first transistor, including a first electrode connected to a first power line, a second electrode connected to a first node, and a gate electrode connected to a second node, wherein the first node is connected to the first electrode of a first light-emitting diode and the second electrode of a second light-emitting diode; a second transistor, connected between a data line and the second node, and including a gate electrode connected to a first scan line; a third transistor, connected between the first node and a sensing line, and including a gate electrode connected to a second scan line; and a fourth transistor, including a first electrode connected to a second power line, a second electrode connected to a third node, and a gate electrode connected to the second node, wherein the third node is connected to the second electrode of the first light-emitting diode and the first electrode of the second light-emitting diode.

[0022] In an embodiment, a pixel can be connected to a third scan line and a fourth scan line. The second pixel circuit can include: a fifth transistor, including a first electrode connected to a first power line, a second electrode connected to a third node, and a gate electrode connected to a fourth node; a sixth transistor, connected between a data line and a fourth node, and including a gate electrode connected to the third scan line; a seventh transistor, connected between the third node and a sensing line, and including a gate electrode connected to the fourth scan line; and an eighth transistor, including a first electrode connected to a second power line, a second electrode connected to a first node, and a gate electrode connected to the fourth node.

[0023] In one embodiment, during a frame period, a first scan signal at an on level can be supplied to a first scan line during a first time period, a second scan signal at an on level can be supplied to a second scan line during the first time period, and a first data signal can be supplied to a second node and an initialization voltage can be supplied to a sensing line during the first time period.

[0024] In one embodiment, during a frame period, a third scan signal at the on level can be supplied to the third scan line during a second time period after the first time period, a fourth scan signal at the on level can be supplied to the fourth scan line during the second time period, and during the second time period, a second data signal is supplied to the fourth node, and an initialization voltage is supplied to the sensing line.

[0025] In this embodiment, the first data signal and the second data signal may be signals corresponding to grayscale values.

[0026] In this embodiment, the second scan line and the fourth scan line may be the same, and the second scan signal and the fourth scan signal may be the same.

[0027] In an embodiment, the second scan signal and the fourth scan signal may be supplied during the same time period.

[0028] In an embodiment, the display device may further include a power supply that supplies a first power supply voltage to a first power supply line and supplies a second power supply voltage that is lower than the first power supply voltage to a second power supply line.

[0029] In an embodiment, a pixel can be connected to a third scan line and a fourth scan line. The first pixel circuit of the first pixel in the pixel can be connected to the first scan line and the second scan line. The second pixel circuit of the first pixel can be connected to the third scan line and the fourth scan line. The first pixel circuit of the second pixel disposed on the same pixel row as the first pixel can be connected to the second scan line and the third scan line. The second pixel circuit of the second pixel can be connected to the first scan line and the fourth scan line.

[0030] The embodiment of the display panel includes: a data driver connected to a first plurality of data lines; and a first plurality of pixels, each connected to a corresponding data line in the first plurality of data lines and connected to a pair of switchable polarity power lines, wherein each of the first plurality of pixels includes a first light-emitting diode arranged with a first polarity and a second light-emitting diode arranged in parallel with the first light-emitting diode and with a second polarity opposite to the first polarity.

[0031] In the embodiment display panel, each of the plurality of pixels may further include: a first circuit for driving a first light-emitting diode; and a second circuit for driving a second light-emitting diode, wherein, during the same frame period, a data driver supplies a first data signal to the first circuit via a first of the plurality of data lines, and supplies a second data signal to the second circuit via a first of the plurality of data lines.

[0032] The pixel in the embodiment includes: at least one first transistor having a first control terminal connected to a scan line, a first input terminal connected to a data line, and a first output terminal; at least one second transistor having a second control terminal connected to the first output terminal, a second input terminal connected to a first power line, and a second output terminal; a first capacitor connected between the first output terminal and the second output terminal; a first light-emitting diode having a first anode and a first cathode connected to the second output terminal; and a second light-emitting diode having a second anode connected to the first cathode and a second cathode connected to the first anode.

[0033] In the embodiment, the pixel may further include: at least one third transistor having a third control terminal connected to a scan line, a third input terminal connected to a data line, and a third output terminal; and at least one fourth transistor having a fourth control terminal connected to the third output terminal, a fourth input terminal connected to a second power line, and a fourth output terminal; and a second capacitor connected between the third output terminal and the fourth output terminal.

[0034] Embodiments of the present invention can minimize the difference in brightness between frames by driving all light-emitting diodes included in the pixel, and can prevent flickering during frame changes.

[0035] Embodiments of the present invention can minimize the difference in brightness between pixels arranged on the same horizontal line (or the same pixel row) by driving all light-emitting diodes included in the pixel, and can improve the reliability of the display device.

[0036] The effects of the embodiments of the present invention are not limited to those described above. The specificities of other embodiments may be found in the following detailed description and accompanying drawings. Attached Figure Description

[0037] Figure 1 This is a perspective view showing a light-emitting diode according to an embodiment of the present invention.

[0038] Figure 2 yes Figure 1 The image shows a cross-sectional view of a light-emitting diode.

[0039] Figure 3 This is a perspective view showing a light-emitting diode according to an embodiment of the present invention.

[0040] Figure 4 yes Figure 3 The image shows a cross-sectional view of a light-emitting diode.

[0041] Figure 5 This is a perspective view showing a light-emitting diode according to an embodiment of the present invention.

[0042] Figure 6 yes Figure 5 The image shows a cross-sectional view of a light-emitting diode.

[0043] Figure 7 This is a perspective view showing a light-emitting diode according to an embodiment of the present invention.

[0044] Figure 8 This is a block diagram illustrating a display device according to an embodiment of the present invention.

[0045] Figure 9 This is a circuit diagram of a pixel according to an embodiment of the present invention.

[0046] Figure 10A and Figure 10B It is used to show Figure 8 The operation of the power supply shown Figure 9 The timing diagram shows the driving method of the pixel shown.

[0047] Figure 11A and Figure 11BIt is shown Figure 9 The pixels shown are based on Figure 10A and Figure 10B The circuit diagram and schematic diagram show an embodiment of the driving method for emitting light.

[0048] Figure 12A and Figure 12B It is used to show Figure 8 The operation of the power supply shown Figure 9 The timing diagram shows the driving method of the pixel shown.

[0049] Figure 13A and Figure 13B It is shown Figure 9 The pixels shown are based on Figure 12A and Figure 12B The circuit diagram and schematic diagram show an embodiment of the driving method for emitting light.

[0050] Figure 14 It is aimed at Figure 9 The circuit diagram shows a modified embodiment of the pixel shown.

[0051] Figure 15A and Figure 15B It is used to show Figure 8 The operation of the power supply shown Figure 14 The timing diagram shows the driving method of the pixel shown.

[0052] Figure 16A and Figure 16B It is used to show Figure 8 The operation of the power supply shown Figure 14 The timing diagram shows the driving method of the pixel shown.

[0053] Figure 17 This is a circuit diagram of a pixel according to an embodiment of the present invention.

[0054] Figure 18 It is used to show Figure 8 The operation of the power supply shown Figure 17 The timing diagram shows the driving method of the pixel shown.

[0055] Figure 19 and Figure 20 It is shown Figure 17 The pixels shown are based on Figure 18 The diagram shows an embodiment of the driving method for emitting light.

[0056] Figure 21A and Figure 21B It is shown Figure 17 The pixels shown are based on Figure 18 A schematic diagram of an embodiment of the driving method for emitting light is shown.

[0057] Figure 22 It is aimed at Figure 17 A circuit diagram of a modified embodiment of the pixels shown;

[0058] Figure 23 It is used to show Figure 8 The operation of the power supply shown Figure 22 The timing diagram shows the driving method of the pixel shown.

[0059] Figure 24 is with Figure 17 The diagram shows a circuit diagram of pixels arranged on the same pixel row. Detailed Implementation

[0060] Embodiments of the invention (including methods of implementation) will be described by way of example through the following examples described with reference to the accompanying drawings. However, the invention may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Furthermore, the invention is defined only by the scope of the claims.

[0061] In the following description, embodiments of the present disclosure will be described in more detail with reference to the accompanying drawings. The same or similar reference numerals may be used for the same or similar constituent elements in the drawings, and repeated descriptions thereof may be omitted.

[0062] Figure 1 This is a perspective view showing a light-emitting diode according to an embodiment of the present invention. Figure 2 yes Figure 1 The image shows a cross-sectional view of a light-emitting diode.

[0063] Reference Figure 1 and Figure 2 A light-emitting diode (LD) may include a first semiconductor layer 11, a second semiconductor layer 13, and an active layer 12 disposed between the first semiconductor layer 11 and the second semiconductor layer 13. For example, a light-emitting diode (LD) may have a structure in which the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13 are sequentially stacked in one direction.

[0064] According to an embodiment, the light-emitting diode (LD) can be configured as a rod shape extending in one direction. The LD can have one end (first end) and the other end (second end) aligned in substantially one direction.

[0065] According to an embodiment, one of the first semiconductor layer 11 and the second semiconductor layer 13 can be disposed at one end of the light-emitting diode LD, and the other of the first semiconductor layer 11 and the second semiconductor layer 13 can be disposed at the other end of the light-emitting diode LD.

[0066] According to an embodiment, a light-emitting diode (LD) can be manufactured as a bar-shaped LD. Here, the bar shape can include a bar-shaped or strip-shaped (such as a cylinder or polygonal cylinder) shape that is longer in the length direction than in the width direction (i.e., the length-to-width ratio is greater than 1), without specifically limiting the shape of the cross-section of the bar shape. For example, the length L of the LD can be greater than its diameter D (or the width of its cross-section). Figure 1 and Figure 2 A cylindrical rod-shaped light-emitting diode (LD) is shown, but the types and shapes of LDs according to the present invention are not limited thereto.

[0067] According to embodiments, light-emitting diodes (LDs) can have dimensions ranging from nanometers to micrometers, for example, with a diameter D or length L in the range of 100 nm to 10 μm. However, the size of the LD is not limited to this. For example, the size of the LD can vary depending on the design requirements of the display device using the LD.

[0068] The first semiconductor layer 11 may include at least one N-type semiconductor material. For example, the first semiconductor layer 11 may include semiconductor materials such as InAlGaN, GaN, AlGaN, InGaN, AlN, and / or InN, and may include N-type semiconductor materials doped with a first conductive dopant (such as Si, Ge, Sn, etc.). However, the materials constituting the first semiconductor layer 11 are not limited to these, and various other materials may constitute the first semiconductor layer 11.

[0069] The active layer 12 can be disposed on the first semiconductor layer 11 and can be formed as a single quantum well structure or a multi-quantum well structure. In embodiments, a cladding layer doped with a conductive dopant can be formed on and / or under the active layer 12. For example, the cladding layer can be formed of an AlGaN layer or an InAlGaN layer. According to embodiments, materials such as AlGaN, AlInGaN, etc., can be used to form the active layer 12; in addition, various materials can constitute the active layer 12. In other words, the active layer 12 can be disposed between the first semiconductor layer 11 and the second semiconductor layer 13 described below.

[0070] When a voltage equal to or higher than the threshold voltage is applied across the two ends of a light-emitting diode (LD), the LD emits light while electron-hole pairs recombine in the active layer 12. By controlling the light emission of the LD using this principle, the LD can be used as a light source for various light-emitting devices, including pixels in display devices.

[0071] The second semiconductor layer 13 may be disposed on the active layer 12 and may comprise a type of semiconductor material different from that of the first semiconductor layer 11. For example, the second semiconductor layer 13 may comprise at least one P-type semiconductor material. For example, the second semiconductor layer 13 may comprise at least one semiconductor material selected from InAlGaN, GaN, AlGaN, InGaN, AlN, and InN, and may comprise a P-type semiconductor material doped with a second conductive dopant (such as Mg). However, the materials constituting the second semiconductor layer 13 are not limited to these, and various other materials may constitute the second semiconductor layer 13.

[0072] According to an embodiment, the first length L1 of the first semiconductor layer 11 may be longer than the second length L2 of the second semiconductor layer 13.

[0073] According to an embodiment, the light-emitting diode (LD) may further include an insulating film INF disposed on its surface. The insulating film INF may be formed on the surface of the LD to at least surround the outer circumferential surface of the active layer 12, and may also cover portions of the first semiconductor layer 11 and the second semiconductor layer 13.

[0074] However, according to an embodiment, the insulating film INF can expose the two ends of the light-emitting diode LD that have different polarities. For example, the insulating film INF can expose but not cover one end of each of the first semiconductor layer 11 and the second semiconductor layer 13 disposed at the two ends of the light-emitting diode LD in the longitudinal direction (e.g., two planes of a cylinder (e.g., the top surface and the bottom surface)). In an embodiment, the insulating film INF can expose the two ends of the light-emitting diode LD that have different polarities, as well as the sides of the semiconductor layers 11 and 13 adjacent to the two ends.

[0075] According to embodiments, the insulating film INF may include at least one insulating material selected from silicon oxide (SiO2), silicon nitride (Si3N4), aluminum oxide (Al2O3), and titanium dioxide (TiO2), but is not limited thereto. That is, the constituent materials of the insulating film INF are not specifically limited, and the insulating film INF may be made of various insulating materials known in the art.

[0076] In embodiments, the light-emitting diode (LD) may include additional constituent elements in addition to the first semiconductor layer 11, the active layer 12, the second semiconductor layer 13, and / or the insulating film INF. For example, the LD may also include at least one phosphor layer, an active layer, a semiconductor layer, and / or an electrode layer disposed on one side of the first semiconductor layer 11, the active layer 12, and / or the second semiconductor layer 13.

[0077] Figure 3 This is a perspective view showing a light-emitting diode according to an embodiment of the present invention. Figure 4 yes Figure 3 The image shows a cross-sectional view of a light-emitting diode.

[0078] Reference Figure 3 and Figure 4 According to an embodiment, a light-emitting diode (LD) includes a first semiconductor layer 11, a second semiconductor layer 13, and an active layer 12 disposed between the first semiconductor layer 11 and the second semiconductor layer 13. According to an embodiment, the first semiconductor layer 11 may be disposed in the central region of the LD, and the active layer 12 may be disposed on the surface of the first semiconductor layer 11 to cover at least a portion of the first semiconductor layer 11. Furthermore, the second semiconductor layer 13 may be disposed on the surface of the active layer 12 to cover at least a portion of the active layer 12.

[0079] Furthermore, the light-emitting diode (LD) may also include an electrode layer 14 covering at least a portion of the second semiconductor layer 13 and / or an insulating film INF. For example, the LD may further include an electrode layer 14 disposed on the surface of the second semiconductor layer 13 to cover at least a portion of the second semiconductor layer 13, and an insulating film INF disposed on the surface of the electrode layer 14 to cover at least a portion of the electrode layer 14. That is, the LD according to the embodiments described above can be implemented as a core-shell structure including a first semiconductor layer 11, an active layer 12, a second semiconductor layer 13, an electrode layer 14, and an insulating film INF arranged sequentially from the center to the outside. According to embodiments, the electrode layer 14 and / or the insulating film INF may be omitted.

[0080] In this embodiment, the light-emitting diode (LD) can be configured as a pyramidal shape extending in one direction. For example, at least one region of the LD can have a hexagonal pyramidal shape. However, the shape of the LD is not limited to this and can be varied.

[0081] When the extension direction of the light-emitting diode (LD) is named the direction of length L, the LD may have one end (e.g., a first end) and another end (e.g., a second end) along the direction of length L. According to an embodiment, one of the first semiconductor layer 11 and the second semiconductor layer 13 may be disposed at one end of the LD, and the other of the first semiconductor layer 11 and the second semiconductor layer 13 may be disposed at the other end of the LD.

[0082] In embodiments of the present invention, the light-emitting diode (LD) can be an ultra-small light-emitting diode having a core-shell structure composed of a polygonal column shape (e.g., a hexagonal pyramid shape with protruding ends).

[0083] In an embodiment, the two ends of the first semiconductor layer 11 may have protruding shapes along the length L of the light-emitting diode LD. The protruding shapes at the two ends of the first semiconductor layer 11 may differ from each other. For example, one end disposed on the upper side of both ends of the first semiconductor layer 11 may have a pyramidal shape that contacts a vertex as the width of said end narrows upwards. Furthermore, the other end disposed on the lower side of both ends of the first semiconductor layer 11 may be a polygonal prism shape with a constant width. However, the embodiment is not limited to this.

[0084] In an embodiment, the light-emitting diode (LD) may have a cross-section such as a polygonal shape or a stepped shape, the width of which gradually narrows as the first semiconductor layer 11 descends.

[0085] The shapes of the two ends of the first semiconductor layer 11 can be varied based on any embodiment and are not limited to the embodiments described above.

[0086] According to an embodiment, the first semiconductor layer 11 may be disposed in a core (such as the central region or central area of ​​a light-emitting diode LD). Furthermore, the light-emitting diode LD may be configured with a shape corresponding to the shape of the first semiconductor layer 11. For example, when the first semiconductor layer 11 has a hexagonal pyramid shape, the light-emitting diode LD may also have a hexagonal pyramid shape.

[0087] Figure 5 This is a perspective view showing a light-emitting diode according to an embodiment of the present invention. Figure 6 is with Figure 5 The image shows a cross-sectional view of a light-emitting diode similar to the one shown. Figure 5 For better understanding and ease of description, the INF portion of the insulating film has been omitted. (See reference...) Figure 5 According to the embodiments, the light-emitting diode (LD) may include a first semiconductor layer 11, an active layer 12, a second semiconductor layer 13, an electrode layer 14, etc.

[0088] For example, a light-emitting diode (LD) may have a structure in which a first semiconductor layer 11, an active layer 12, a second semiconductor layer 13, and an electrode layer 14 are stacked sequentially in one direction.

[0089] As shown above (refer to the reference) Figure 1 As described, the first semiconductor layer 11 may include at least one N-type semiconductor material (e.g., one of InAlGaN, GaN, AlGaN, InGaN, AlN, and InN), and may include an N-type semiconductor material doped with a first conductive dopant (such as Si, Ge, Sn, etc.).

[0090] The active layer 12 can be disposed on the first semiconductor layer 11, and can be formed as a single quantum well structure or a multiple quantum well structure. The active layer 12 may include nitrogen (N). When the active layer 12 includes nitrogen (N), Figure 5 The light-emitting diode (LD) shown can emit blue or green light.

[0091] As shown above (refer to the reference) Figure 1 As described, the second semiconductor layer 13 may be disposed on the active layer 12 and may include a type of semiconductor material different from that of the first semiconductor layer 11, such as at least one P-type semiconductor material. For example, the second semiconductor layer 13 may include at least one semiconductor material selected from InAlGaN, GaN, AlGaN, InGaN, AlN, and InN, and may include a P-type semiconductor material doped with a second conductive dopant (such as Mg).

[0092] In one embodiment, electrode layer 14 may be an ohmic contact electrode electrically connected to the second semiconductor layer 13. However, the invention is not limited thereto, and electrode layer 14 may be a Schottky contact electrode.

[0093] The electrode layer 14 may include metals or metal oxides, such as Cr, Ti, Al, Au, Ni, ITO, IZO, ITZO and their oxides or alloys, either alone or in combination.

[0094] The electrode layer 14 can be substantially transparent or semi-transparent. Therefore, light generated in the active layer 12 of the light-emitting diode LD can pass through the electrode layer 14 and be emitted to the outside of the light-emitting diode LD.

[0095] The light-emitting diode (LD) may further include an electrode layer disposed on the first semiconductor layer 11, made of the same material as the electrode layer 14, and the two electrode layers may define each end of the light-emitting diode (LD).

[0096] Reference Figure 5 , Figure 5 LEDs and Figure 1 The difference in this embodiment may be that an electrode layer 14 is also provided. Apart from the differences mentioned above, the arrangement and structure of the insulating film INF are similar to... Figure 1 The implementation examples are basically the same. Figure 6 In the middle, some components and Figure 5 The components shown may be the same or similar, but may have optional differences and / or new reference numerals for better understanding and ease of description. Repeated descriptions may be omitted.

[0097] Reference Figure 6In one embodiment, the insulating film INF' may have a curved shape in the edge region adjacent to the electrode layer 14. According to an embodiment, the curved surface can be formed by etching when manufacturing the light-emitting diode (LD).

[0098] In an embodiment of a light-emitting diode (LD) having a structure that also includes an electrode layer disposed on the first semiconductor layer 11 as described above, the insulating film INF' may have a curved shape in the region adjacent to the electrode layer.

[0099] Figure 7 This is a perspective view showing a light-emitting diode according to an embodiment of the present invention.

[0100] exist Figure 7 For better understanding and ease of description, the part about the insulating film INF has been omitted.

[0101] Reference Figure 7 According to the embodiment, the light-emitting diode (LD) may further include a third semiconductor layer 15 disposed between the first semiconductor layer 11 and the active layer 12, a fourth semiconductor layer 16 disposed between the active layer 12 and the second semiconductor layer 13, and a fifth semiconductor layer 17. Figure 7 LEDs and Figure 5 The embodiment differs in that it also includes multiple semiconductor layers 15, 16, and 17, as well as multiple electrode layers 14a and 14b, and the active layer 12 includes another element. Aside from the differences above, the arrangement and structure of the insulating film INF are similar to... Figure 5 The implementation examples are basically the same. Figure 7 In the middle, some components and Figure 5 The components shown are the same or similar, but may have new reference numerals for better understanding and ease of description. Repeated descriptions will be omitted below, and the description will focus primarily on the differences.

[0102] As described above, in Figure 5 In a light-emitting diode (LD), the active layer 12 may include nitrogen (N) and emit blue or green light. On the other hand, in Figure 7 In the light-emitting diode (LD), each of the active layer 12 and / or other semiconductor layers can be a semiconductor comprising at least one other element (such as phosphorus (P)). That is, the LD according to the embodiment can emit red light with a center wavelength of 620 nm to 750 nm. However, it should be understood that the center wavelength of the red light is not limited to the above range and includes all wavelengths that can be identified as red in the art.

[0103] In this embodiment, the light-emitting diode (LD) may include a cladding layer disposed adjacent to the active layer 12. As shown in the accompanying drawings, the third semiconductor layer 15 and the fourth semiconductor layer 16 disposed between the first semiconductor layer 11 and the second semiconductor layer 13 may be cladding layers.

[0104] A third semiconductor layer 15 may be disposed between the first semiconductor layer 11 and the active layer 12. The third semiconductor layer 15 may be an N-type semiconductor, such as the first semiconductor layer 11. For example, the third semiconductor layer 15 may include an N-type semiconductor with In... x Al y Ga 1-x-y A semiconductor material with the chemical formula P (where 0≤x≤1, 0≤y≤1, 0≤x+y≤1). In an embodiment, the first semiconductor layer 11 may be n-AlGaInP, and the third semiconductor layer 15 may be n-AlInP. However, the embodiment is not limited to this.

[0105] A fourth semiconductor layer 16 may be disposed between the active layer 12 and the second semiconductor layer 13. The fourth semiconductor layer 16 may be a P-type semiconductor, such as the second semiconductor layer 13. For example, the fourth semiconductor layer 16 may include a P-type semiconductor with In... x Al y Ga 1-x-y A semiconductor material with the chemical formula P (where 0≤x≤1, 0≤y≤1, 0≤x+y≤1). In an embodiment, the second semiconductor layer 13 may be p-GaP, and the fourth semiconductor layer 16 may be p-AlInP.

[0106] A fifth semiconductor layer 17 may be disposed between the fourth semiconductor layer 16 and the second semiconductor layer 13. The fifth semiconductor layer 17 may be a semiconductor doped with a p-type conductive dopant (such as the second semiconductor layer 13 and the fourth semiconductor layer 16). In embodiments, the fifth semiconductor layer 17 may be used to reduce the difference in lattice constant between the fourth semiconductor layer 16 and the second semiconductor layer 13. That is, the fifth semiconductor layer 17 may be a tensile strain barrier reduction (TSBR) layer. For example, the fifth semiconductor layer 17 may include p-GaInP, p-AlInP, or p-AlGaInP, but is not limited to these.

[0107] The first electrode layer 14a and the second electrode layer 14b may be disposed on the first semiconductor layer 11 and the second semiconductor layer 13, respectively. The first electrode layer 14a may be disposed on the lower surface of the first semiconductor layer 11, and the second electrode layer 14b may be disposed on the upper surface of the second semiconductor layer 13. However, the present invention is not limited thereto, and at least one of the first electrode layer 14a and the second electrode layer 14b may be omitted according to embodiments.

[0108] Each of the first electrode layer 14a and the second electrode layer 14b may include Figure 5 At least one of the materials of the electrode layer 14 shown.

[0109] When Figures 1 to 7 When the light-emitting diode (LD) shown is applied to a display device according to an embodiment of the present invention, Figures 1 to 7 The light-emitting diode (LD) shown can be included in the pixel through an alignment process, in which the alignment process includes... Figures 1 to 7 One or more types of ink are applied to the lines used to align the polarity of the light-emitting diode (LD) as shown (such as by applying conductive ink), but not limited to this.

[0110] In this configuration, the light-emitting diodes (LDs) included in a pixel can be aligned in either a forward direction (or a first direction) or a reverse direction (or a second direction). Typically, since multiple LDs are included in a pixel, a pixel can include LDs aligned in the forward direction (or the first direction) and LDs aligned in the reverse direction (or the second direction).

[0111] Next, the display device according to an embodiment will be described.

[0112] Figure 8 This is a block diagram illustrating a display device according to an embodiment of the present invention.

[0113] Reference Figure 8 According to an embodiment of the present invention, the display device 100 may include a timing controller 110, a data driver 120, a scan driver 130, a sensing unit 140, a compensator 150, a display unit 160, and a power supply 170.

[0114] The timing controller 110 can receive input image data IRGB and timing signals Vsync, Hsync, DE, and CLK from a host system (such as an application processor (AP)) via a predetermined interface. Here, the timing signals Vsync, Hsync, DE, and CLK may include, for example, a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable signal DE, and a clock signal CLK.

[0115] The vertical synchronization signal Vsync can comprise multiple pulses and can indicate the end of the previous frame period and the beginning of the current frame period relative to the time at which each pulse is generated. The interval between adjacent pulses of the vertical synchronization signal Vsync can correspond to one frame period.

[0116] The horizontal synchronization signal Hsync can comprise multiple pulses and can indicate the end of a previous horizontal cycle and the start of a new horizontal cycle relative to the time at which each pulse is generated. The interval between adjacent pulses of the horizontal synchronization signal Hsync can correspond to one horizontal cycle.

[0117] The data enable signal DE can have an enable level for a specific horizontal period. When the data enable signal DE is at the enable level, it can indicate that the input image data IRGB is supplied in the corresponding horizontal period.

[0118] Input image data IRGB can be supplied in pixel rows in each corresponding horizontal cycle.

[0119] In this embodiment, the timing controller 110 can rearrange the input image data IRGB and supply the input image data IRGB to the data driver 120. Specifically, the timing controller 110 can generate image data RGB corresponding to grayscale values ​​based on the input image data IRGB corresponding to the specifications of the display device 100, and can supply the image data RGB to the data driver 120.

[0120] In an embodiment, timing controller 110 may receive compensation values ​​(e.g., the current compensation value COMP as further described below) output by compensator 150, and may supply image data RGB with the compensation value applied to data driver 120.

[0121] The timing controller 110 can generate control signals to be supplied to the data driver 120, the scan driver 130 and the sensing unit 140 based on timing signals Vsync, Hsync, DE and CLK that correspond to the specifications of the display device 100.

[0122] In an embodiment, the timing controller 110 can generate a data drive control signal DCS based on timing signals Vsync, Hsync, DE and CLK, and supply the data drive control signal DCS to the data driver 120.

[0123] In one embodiment, the data driver 120 can convert rearranged image data RGB into a first data signal (or data voltage) in analog format. Specifically, the data driver 120 can generate the first data signal (or data voltage) to be supplied to data lines DL1, DL2 to DLm (where m can be a natural number greater than 2) using image data RGB received from the timing controller 110 and a data drive control signal DCS.

[0124] For example, the data driver 120 can sample grayscale values ​​using a clock signal CLK and can supply a first data signal (or data voltage) to data lines DL1, DL2 to DLm in units of pixel rows (e.g., pixels connected to the same scan line).

[0125] In this embodiment, the first data signal may be a signal corresponding to a grayscale value.

[0126] In an embodiment, the data driver 120 can supply a second data signal at an on level, which can, in pixel rows, via data lines DL1, DL2 to DLm, enable driving transistors (e.g., in pixels PXnm) included in the pixel PXnm. Figure 9 The first transistor Tr1 and the fourth transistor Tr4 shown in the figure are turned on.

[0127] In this embodiment, the second data signal may be the same as the first data signal. That is, the second data signal may be a signal corresponding to a grayscale value.

[0128] In this embodiment, the second data signal may be different from the first data signal. That is, the second data signal at the on level may not correspond to a grayscale value.

[0129] The data driver 120 can supply a first data signal and / or a second data signal to data lines DL1, DL2 to DLm during a frame period. In an embodiment, the first data signal supplied to data lines DL1, DL2 to DLm can be supplied during the time period in which the first scan signal is supplied to the first scan lines SL11 to SL1n and the time period in which the third scan signal is supplied to the third scan lines SL31 to SL3n. In an embodiment, the first data signal supplied to data lines DL1, DL2 to DLm can be supplied during the time period in which the first scan signal is supplied to the first scan lines SL11 to SL1n. Furthermore, in an embodiment, the second data signal supplied to data lines DL1, DL2 to DLm can be supplied during the time period in which the third scan signal is supplied to the third scan lines SL31 to SL3n.

[0130] In this embodiment, the timing controller 110 can supply the gate start pulse GSP and the clock signal CLK to the scan driver 130 based on the timing signals Vsync, Hsync, DE, and CLK. Here, the gate start pulse GSP can be used to control the first timing of the scan signals supplied from the scan driver 130, and the clock signal CLK can be used to shift the gate start pulse GSP.

[0131] The scan driver 130 can receive scan signals CLK, gate start pulses GSP, etc. from the timing controller 110 to generate scan signals supplied to scan lines SL11, SL21, SL31, SL41, ..., SL1n, SL2n, SL3n and SL4n. Here, n can be a natural number greater than 1.

[0132] Scan driver 130 may include multiple sub-scan drivers 131, 132, 133, and 134. For example, scan driver 130 may be configured and operated as a first sub-scan driver 131, a second sub-scan driver 132, a third sub-scan driver 133, and a fourth sub-scan driver 134. In this case, the gate start pulse GSP may include a first gate start pulse GSP1, a second gate start pulse GSP2, a third gate start pulse GSP3, and a fourth gate start pulse GSP4. The pulse widths of the gate start pulses GSP may be different from each other, and the widths of the scan signals corresponding to the pulse widths of the gate start pulses GSP may also be different. The multiple sub-scan drivers 131, 132, 133, and 134 may jointly receive the clock signal CLK.

[0133] The distinction between scan driver 130 and gate start pulse GSP is for better understanding and ease of description.

[0134] In an embodiment, a first sub-scan driver 131 may sequentially supply a first scan signal to first scan lines SL11 to SL1n in response to a first gate start pulse GSP1; a second sub-scan driver 132 may sequentially supply a second scan signal to second scan lines SL21 to SL2n in response to a second gate start pulse GSP2; a third sub-scan driver 133 may sequentially supply a third scan signal to third scan lines SL31 to SL3n in response to a third gate start pulse GSP3; and a fourth sub-scan driver 134 may sequentially supply a fourth scan signal to fourth scan lines SL41 to SL4n in response to a fourth gate start pulse GSP4. Each of the sub-scan drivers 131, 132, 133, and 134 may include multiple scan stages connected in the form of shift registers. For example, a scan signal can be generated by sequentially transmitting the on-level pulses of the gate start pulse GSP supplied to the scan start line to the next scan stage.

[0135] According to an embodiment, the second sub-scan driver 132 and the fourth sub-scan driver 134 can be composed of a single sub-scan driver. In this case, the second scan lines SL21 to SL2n and the fourth scan lines SL41 to SL4n can be connected to the same node, the second gate start pulse GSP2 and the fourth gate start pulse GSP4 can be the same, and the second scan signal and the fourth scan signal can be the same. The sub-scan driver integrating the second sub-scan driver 132 and the fourth sub-scan driver 134 can supply scan signals to scan lines SL21, SL41, ..., SL2n and SL4n.

[0136] In this embodiment, the fourth sub-scan driver 134 may be omitted based on the pixel structure of pixel PXnm.

[0137] The scan signal can be set to a gate on-state voltage (e.g., a pulse at the on-state level) to turn on the transistors included in the pixel PXnm.

[0138] In this embodiment, the scanning signal can be a pulse signal having a first polarity or a second polarity. In this case, the first polarity and the second polarity can be opposite to each other.

[0139] In the following text, polarity may be referred to as the logic level of the pulse. For example, when the pulse is of the first polarity, the pulse may have a high level. When a pulse of the first polarity is supplied to the gate electrode of an N-type transistor, the N-type transistor can conduct. That is, a pulse of the first polarity can be the conduction level for an N-type transistor. Here, it is assumed that a sufficiently low voltage is applied to the source electrode of the N-type transistor compared to the gate electrode. For example, the N-type transistor may be an NMOS transistor.

[0140] Furthermore, when the pulse is of the second polarity, the pulse can have a low level. When a pulse of the second polarity is supplied to the gate electrode of the P-type transistor, the P-type transistor can conduct. That is, the pulse of the second polarity can be the conduction level for the P-type transistor. Here, it is assumed that a sufficiently high voltage is applied to the source electrode of the P-type transistor compared to the gate electrode. For example, the P-type transistor can be a PMOS transistor.

[0141] In an embodiment, the sensing unit 140 may receive a control signal from the timing controller 110 to supply an initialization voltage to the sensing lines including IL1, IL2 to ILk. Here, k can be a natural number greater than 2 and can be the same as m described above, but is not limited thereto. For example, in a system having pixel circuits PXC1 and PXC2 (see example...) Figure 9In an embodiment of the shared sensing line ILk, k can be substantially equal to m. In another embodiment, k can be substantially twice m, where there are separate sensing lines (such as ILk and IL(k+1)) for pixel circuits PXC1 and PXC2.

[0142] An initialization voltage can be supplied to each of the plurality of pixels PXnm electrically connected to sensing lines IL1, IL2 to ILk. In an embodiment, the initialization voltage can be a voltage used to initialize the anode and / or cathode of a light-emitting diode LD included in a pixel PXnm, as can be further described below.

[0143] In this embodiment, the sensing unit 140 may receive control signals from the timing controller 110 to receive sensing signals via each of the sensing lines IL1, IL2 to ILk. For example, the sensing unit 140 may receive sensing signals via sensing lines IL1, IL2 to ILk during at least some time periods of a sensing time period. The sensing unit 140 may be connected to the pixel PXnm via sensing lines IL1, IL2 to ILk.

[0144] The sensing unit 140 can sense the sensing current and output the sensed value of the sensing current to the compensator 150. Here, the sensed value (or sensed data) can be a digital value and can indicate the sensed current value for the sensed current.

[0145] In an embodiment, the sensing unit 140 can sense the sensing current of only some pixels PXnm or all pixels PXnm during a sensing time period according to the control signal supplied from the timing controller 110, thereby outputting the sensing current value (or multiple sensing current values) to the compensator 150.

[0146] The sensing unit 140 may include sensing channels connected to sensing lines IL1, IL2 to ILk. For example, sensing lines IL1, IL2 to ILk and sensing channels may correspond one-to-one.

[0147] like Figure 8 As shown, the data driver 120 and the sensing unit 140 can be formed separately; however, in this embodiment, the data driver 120 and the sensing unit 140 can be formed integrally.

[0148] The compensator 150 can calculate a current compensation value COMP for each pixel PXnm based on the sensed value (e.g., sensed current value) output from the sensing unit 140, and can output the current compensation value COMP to the timing controller 110. For example, the compensator 150 can calculate the current compensation value COMP based on the sensed current value output from the sensing unit 140 and a predetermined reference current value known in advance, and can output the current compensation value COMP to the timing controller 110.

[0149] Here, the reference current value (or reference current data) can be a digital value of the current flowing through the pixel PXnm, and can represent the expected current value when reference grayscale data is input from an external source. The reference current value can be pre-stored in a memory included in the display device 100 before shipment, or can be actively redefined during use of the product. The input grayscale value can be grayscale data input from an external processor, and can represent grayscale data used for image frames.

[0150] Display unit 160 includes a pixel PXnm. For example, pixel PXnm can be connected to its corresponding data line DLm, scan lines SL1n, SL2n, SL3n and SL4n, sensing line ILk, first power line PL1 and second power line PL2. Pixel PXnm can receive a first data signal or both the first data signal and the second data signal from data driver 120, a scan signal from scan driver 130, an initialization voltage from sensing unit 140, and a first power supply voltage (not shown) and a second power supply voltage (not shown) from power supply 170.

[0151] In embodiments of the present invention, the signal lines SL1, SL2, SL3, SL4, DL, IL, PL1 and PL2 connected to the pixel PXnm can be configured differently according to the circuit structure of the pixel PXnm.

[0152] Corresponding to the circuit structure of pixel PXnm, the pixel PXnm disposed on the current horizontal line (or the current pixel row) can also be connected to the scan line disposed on the previous horizontal line (or the previous pixel row) and / or the scan line disposed on the next horizontal line (or the next pixel row). For this purpose, the display unit 160 may also include dummy scan lines and / or dummy light emission control lines.

[0153] The compensator 150 may include a lookup table. The lookup table may exist in data form or in physical form. In one embodiment, the lookup table may pre-store compensation amount data corresponding to sensed values, changes in sensed values, etc., before the display device 100 is shipped. In another embodiment, the lookup table may be updated with compensation amount data corresponding to sensed values, changes in sensed values, etc., after the display device 100 is shipped.

[0154] Power supply 170 can supply power voltage to the power lines. For example, power supply 170 can supply a first power voltage to the first power line PL1 and a second power voltage to the second power line PL2.

[0155] The power supply voltage can be a first level or a second level lower than the first level. In an embodiment, when the first power supply voltage is the first level, the second power supply voltage can be the second level; when the first power supply voltage is the second level, the second power supply voltage can be the first level.

[0156] In an embodiment, power supply 170 may supply a first power supply voltage at a first level and a second power supply voltage at a second level during a first frame period, and may supply a first power supply voltage at a second level and a second power supply voltage at a first level during a second frame period.

[0157] Here, the first frame period can represent, for example, the period corresponding to odd-numbered frames, and the second frame period can represent, for example, the period corresponding to even-numbered frames. However, the embodiments are not limited to this; the first frame period can be the period corresponding to even-numbered frames, and the second frame period can be the period corresponding to odd-numbered frames.

[0158] In other words, power supply 170 can alternately supply the level of a first power supply voltage and the level of a second power supply voltage for each frame.

[0159] In this embodiment, regardless of the frame period, power supply 170 can supply a first power supply voltage at a first level and a second power supply voltage at a second level.

[0160] In an embodiment, regardless of the frame period, power supply 170 can supply a first power supply voltage at the second level and a second power supply voltage at the first level.

[0161] In one embodiment, regardless of the frame period, power supply 170 may supply a first power supply voltage at a first level and a second power supply voltage at a second level, and then supply a first power supply voltage at the second level and a second power supply voltage at the first level. In another embodiment, during the same period and / or regardless of the frame period, one of the first power supply voltage and the second power supply voltage may remain at substantially the same level, while the other of the first power supply voltage and the second power supply voltage switches between a voltage level higher than that voltage level and a voltage level lower than that voltage level.

[0162] The display device 100 may also include a memory.

[0163] In the following text, the pixel PXnm according to an embodiment of the present invention will be described.

[0164] Figure 9 This is a circuit diagram of a pixel according to an embodiment of the present invention.

[0165] exist Figure 9In order to better understand and facilitate description, embodiments of the present invention will be described relative to the pixel PXnm (or the first pixel) connected to the nth horizontal line (e.g., the first scan line SL1n, the second scan line SL2n, the third scan line SL3n, and the fourth scan line SL4n), the mth data line DLm, and the kth sensing line ILk.

[0166] Reference Figure 9 The pixel PXnm may include a first pixel circuit PXC1 and a second pixel circuit PXC2, light-emitting diodes LD1 and LD2, etc.

[0167] The first pixel circuit PXC1 can drive the first light-emitting diode LD1. The first pixel circuit PXC1 can be connected to the first power line PL1, the first scan line SL1n, the second scan line SL2n, the data line DLm, the sensing line ILk, the first electrode (such as the anode of the first light-emitting diode LD1), and the second electrode (such as the cathode of the second light-emitting diode LD2).

[0168] The first pixel circuit PXC1 may include a first transistor Tr1, a second transistor Tr2, a third transistor Tr3, a first storage capacitor Cst1, etc.

[0169] The first transistor Tr1 can control the drive current based on the first data signal during the first frame period. The first transistor Tr1 can be referred to as the drive transistor. The first electrode of the first transistor Tr1 can be connected to the first power supply line PL1, the second electrode of the first transistor Tr1 can be connected to the first node N1, and the gate electrode of the first transistor Tr1 can be connected to the second node N2.

[0170] In an embodiment, when the first power supply voltage applied to the first power supply line PL1 is a first level and the second power supply voltage applied to the second power supply line PL2 is a second level, the first transistor Tr1 can control the amount of drive current flowing through the first power supply line PL1, the first transistor Tr1, the first light-emitting diode LD1, the fourth transistor Tr4, and the second power supply line PL2, corresponding to the voltage of the second node N2 (e.g., the first data signal). For this purpose, as will be discussed later... Figure 10A and Figure 10B As described, the first power supply voltage VS1 can be set to a voltage higher than the second power supply voltage VS2 during the first frame period (e.g., an odd frame period).

[0171] The first transistor Tr1 can be turned on during the second frame period by either the first data signal or the second data signal.

[0172] In an embodiment, when the first power supply voltage applied to the first power supply line PL1 is at a second level and the second power supply voltage applied to the second power supply line PL2 is at a first level, the first transistor Tr1 can be turned on by the voltage of the second node N2 (e.g., the first data signal or the second data signal), and then drive current can flow through the second power supply line PL2, the fourth transistor Tr4, the second light-emitting diode LD2, the first transistor Tr1, and the first power supply line PL1. For this purpose, see reference later. Figure 12A and Figure 12B As described, the first power supply voltage VS1 can be set to a voltage lower than the second power supply voltage VS2 during the second frame period (e.g., an even frame period).

[0173] The second transistor Tr2 can select pixel PXnm to receive a first data signal (or a first data signal and a second data signal) based on a first scan signal supplied to the first scan line SL1n. That is, the second transistor Tr2 can electrically connect data line DLm and the second node N2 based on the first scan signal supplied to the first scan line SL1n. The second transistor Tr2 can be referred to as a scan transistor. The second transistor Tr2 can be connected between data line DLm and the second node N2. Specifically, the first electrode of the second transistor Tr2 can be connected to data line DLm, the second electrode of the second transistor Tr2 can be connected to the second node N2, and the gate electrode of the second transistor Tr2 can be connected to the first scan line SL1n. When a first scan signal with a conduction level pulse is supplied to the first scan line SL1n, the second transistor Tr2 can conduct to electrically connect data line DLm and the second node N2.

[0174] The third transistor Tr3 can be connected between the second electrode (e.g., the first node N1) of the first transistor Tr1 and the sensing line ILk. That is, the first electrode of the third transistor Tr3 can be connected to the first node N1, the second electrode of the third transistor Tr3 can be connected to the sensing line ILk, and the gate electrode of the third transistor Tr3 can be connected to the second scan line SL2n. When a second scan signal with a pulse having a conduction level is supplied to the second scan line SL2n, the third transistor Tr3 can be turned on to electrically connect the sensing line ILk and the first node N1. Simultaneously, when the third transistor Tr3 is turned on, an initialization voltage supplied to the sensing line ILk can be applied to the first node N1. When the initialization voltage is applied to the first node N1, the first electrode (e.g., the anode) of the first light-emitting diode LD1 and the second electrode (e.g., the cathode) of the second light-emitting diode LD2 can be initialized.

[0175] The first storage capacitor Cst1 can be charged with an amount of charge corresponding to the potential difference between the voltage applied to the first node N1 and the voltage applied to the second node N2. The first storage capacitor Cst1 can be connected between the first node N1 and the second node N2. Specifically, the first electrode of the first storage capacitor Cst1 can be connected to the first node N1, and the second electrode of the first storage capacitor Cst1 can be connected to the second node N2.

[0176] The second pixel circuit PXC2 can drive the second light-emitting diode LD2. The second pixel circuit PXC2 can be connected to the second power line PL2, the third scan line SL3n, the fourth scan line SL4n, the data line DLm, the sensing line ILk, the second electrode of the first light-emitting diode LD1, and the first electrode of the second light-emitting diode LD2.

[0177] The second pixel circuit PXC2 may include a fourth transistor Tr4, a fifth transistor Tr5, a sixth transistor Tr6, and a second storage capacitor Cst2.

[0178] The fourth transistor Tr4 can control the drive current based on the first data signal during the second frame cycle. The fourth transistor Tr4 can be referred to as the drive transistor in the same way as the first transistor Tr1. The first electrode of the fourth transistor Tr4 can be connected to the second power line PL2, the second electrode of the fourth transistor Tr4 can be connected to the third node N3, and the gate electrode of the fourth transistor Tr4 can be connected to the fourth node N4.

[0179] In an embodiment, when the first power supply voltage applied to the first power supply line PL1 is at a second level and the second power supply voltage applied to the second power supply line PL2 is at a first level, the fourth transistor Tr4 can control the amount of drive current flowing to the second power supply line PL2, the fourth transistor Tr4, the second light-emitting diode LD2, the first transistor Tr1, and the first power supply line PL1, corresponding to the voltage of the fourth node N4 (e.g., the first data signal). For this purpose, as will be discussed later... Figure 12A and Figure 12B As described, the second power supply voltage VS2 can be set to a voltage higher than the first power supply voltage VS1 during the second frame period (e.g., an even frame period).

[0180] The fourth transistor Tr4 can be turned on during the first frame period by either the first data signal or the second data signal.

[0181] In an embodiment, when the first power supply voltage applied to the first power supply line PL1 is a first level and the second power supply voltage applied to the second power supply line PL2 is a second level, the fourth transistor Tr4 can be turned on by the voltage of the fourth node N4 (e.g., the first data signal or the second data signal), and then drive current can flow to the first power supply line PL1, the first transistor Tr1, the first light-emitting diode LD1, the fourth transistor Tr4, and the second power supply line PL2. For this purpose, see reference later. Figure 10A and Figure 10B As described, the first power supply voltage VS1 can be set to a voltage higher than the second power supply voltage VS2 during the first frame period (e.g., an odd frame period).

[0182] The fifth transistor Tr5 can select pixel PXnm to receive the first data signal (or the first data signal and the second data signal) based on the third scan signal supplied to the third scan line SL3n. That is, the fifth transistor Tr5 can electrically connect the data line DLm and the fourth node N4 based on the third scan signal supplied to the third scan line SL3n. The fifth transistor Tr5 can be referred to as the scan transistor in the same way as the second transistor Tr2. The fifth transistor Tr5 can be connected between the data line DLm and the fourth node N4. Specifically, the first electrode of the fifth transistor Tr5 can be connected to the data line DLm, the second electrode of the fifth transistor Tr5 can be connected to the fourth node N4, and the gate electrode of the fifth transistor Tr5 can be connected to the third scan line SL3n. When a third scan signal with a pulse having an on-level is supplied to the third scan line SL3n, the fifth transistor Tr5 can be turned on to electrically connect the data line DLm and the fourth node N4.

[0183] A sixth transistor Tr6 can be connected between the second electrode (e.g., the third node N3) of the fourth transistor Tr4 and the sensing line ILk. That is, the first electrode of the sixth transistor Tr6 can be connected to the third node N3, the second electrode of the sixth transistor Tr6 can be connected to the sensing line ILk, and the gate electrode of the sixth transistor Tr6 can be connected to the fourth scan line SL4n. When a fourth scan signal with a pulse having a conduction level is supplied to the fourth scan line SL4n, the sixth transistor Tr6 can be turned on to electrically connect the sensing line ILk and the third node N3. On the other hand, when the sixth transistor Tr6 is turned on, an initialization voltage supplied to the sensing line ILk can be applied to the third node N3. When the initialization voltage is applied to the third node N3, the second electrode (e.g., the cathode) of the first light-emitting diode LD1 and the first electrode (e.g., the anode) of the second light-emitting diode LD2 can be initialized.

[0184] In this embodiment, the initialization voltage may be a voltage with a low level, but is not limited to this.

[0185] The second storage capacitor Cst2 can be charged with an amount of charge corresponding to the potential difference between the voltage applied to the third node N3 and the voltage applied to the fourth node N4. The second storage capacitor Cst2 can be connected between the third node N3 and the fourth node N4. Specifically, the first electrode of the second storage capacitor Cst2 can be connected to the third node N3, and the second electrode of the second storage capacitor Cst2 can be connected to the fourth node N4.

[0186] The first electrode of the first light-emitting diode LD1 can be connected to the first pixel circuit PXC1, and the second electrode of the first light-emitting diode LD1 can be connected to the second pixel circuit PXC2. Specifically, the first electrode (e.g., anode) of the first light-emitting diode LD1 can be connected to the first node N1, and the second electrode (e.g., cathode) of the first light-emitting diode LD1 can be connected to the third node N3. The first light-emitting diode LD1 can emit light with a predetermined brightness corresponding to the amount of current supplied from the first transistor Tr1.

[0187] In this embodiment, the first light-emitting diode LD1 can be... Figures 1 to 7 The light-emitting diode (LD) shown is shown in the figure.

[0188] In this embodiment, the number of first light-emitting diodes LD1 may be one, but is not limited thereto. Multiple first light-emitting diodes LD1 may be connected in parallel and / or in series between the first node N1 and the third node N3.

[0189] like Figure 9 As shown, the state in which the first electrode of the first light-emitting diode LD1 is connected to the first node N1 and the second electrode of the first light-emitting diode LD1 is connected to the third node N3 is referred to as the alignment state of the light-emitting diode LD in the forward direction (or the first direction).

[0190] The first electrode of the second light-emitting diode LD2 can be connected to the second pixel circuit PXC2, and the second electrode of the second light-emitting diode LD2 can be connected to the first pixel circuit PXC1. Specifically, the first electrode (e.g., anode) of the second light-emitting diode LD2 can be connected to the third node N3, and the second electrode (e.g., cathode) of the second light-emitting diode LD2 can be connected to the first node N1. The second light-emitting diode LD2 can emit light with a predetermined brightness corresponding to the amount of current supplied from the fourth transistor Tr4.

[0191] In this embodiment, the second light-emitting diode LD2 can be... Figures 1 to 7 The light-emitting diode (LD) shown is shown in the figure.

[0192] In this embodiment, the number of second light-emitting diodes LD2 may be one, but is not limited thereto. Multiple second light-emitting diodes LD2 may be connected in parallel and / or in series between the first node N1 and the third node N3.

[0193] like Figure 9 As shown, the state in which the first electrode of the second light-emitting diode LD2 is connected to the third node N3 and the second electrode of the second light-emitting diode LD2 is connected to the first node N1 is referred to as the alignment state of the light-emitting diode LD in the reverse direction (or the second direction).

[0194] In this embodiment, during the first frame period, the first power supply voltage supplied to the first power line PL1 can be a first level, and the second power supply voltage supplied to the second power line PL2 can be a second level. For example, during odd-numbered frame periods, the first power supply voltage can be higher than the second power supply voltage.

[0195] In this embodiment, during the second frame period, the first power supply voltage supplied to the first power line PL1 can be a second level, and the second power supply voltage supplied to the second power line PL2 can be a first level. For example, during even-numbered frame periods, the first power supply voltage can be lower than the second power supply voltage.

[0196] When an initialization voltage is supplied to the first and second electrodes of LEDs LD1 and LD2, the parasitic capacitors in each of LEDs LD1 and LD2 can discharge. Since the residual voltage charged in the parasitic capacitors is discharged (removed), unintentional fine light emission can be prevented. Therefore, the black level of the pixel PXnm can be improved.

[0197] In this embodiment, transistors Tr1 to Tr6 can be composed of N-type transistors, P-type transistors, or a combination of both. Here, an N-type transistor is one in which the amount of current to be conducted increases when the voltage difference between the gate and source electrodes increases in the positive direction. A P-type transistor is one in which the amount of current to be conducted increases when the voltage difference between the gate and source electrodes increases in the negative direction.

[0198] For example, such as Figure 9 As shown, transistors Tr1 to Tr6 can be N-type transistors. However, the embodiments are not limited to this.

[0199] In the embodiments, the transistor may be an oxide semiconductor transistor, an amorphous semiconductor transistor, and / or a polycrystalline silicon semiconductor transistor.

[0200] When LEDs LD1 and LD2 are Figures 1 to 7 When the light-emitting diode (LD) shown is composed, as in Figure 9As shown, LEDs LD1 and LD2 can be arranged in a forward direction (or a first direction) or a reverse direction (or a second direction). When the first power supply voltage supplied to the first power line PL1 is maintained at a first level and the second power supply voltage supplied to the second power line PL2 is maintained at a second level, only the LED LD1 aligned in a specific direction (e.g., the first LED LD1 aligned in the forward direction or the first direction) emits light, while the LED LD2 aligned in other directions (e.g., the second LED LD2 aligned in the reverse direction or the second direction) does not emit light. In this case, since the second LED LD2 cannot emit light and only the first LED LD1 emits light, the lifespan of the first LED LD1 is shortened, thus increasing the cost of the manufacturing process.

[0201] According to embodiments of the present invention, the pixel PXnm and the display device 100 including the pixel PXnm can use the first transistor Tr1 to the sixth transistor Tr6, and the level of the first power supply voltage and the level of the second power supply voltage can be alternately switched for each frame, thereby causing all light-emitting diodes (LDs) included in the pixel PXnm to emit light regardless of the alignment direction. Therefore, the brightness of the display device 100 can be improved, and the lifespan of the light-emitting diodes (LDs) can be increased.

[0202] The following text will describe this in detail using timing diagrams. Figure 8 The power supply 170 shown and Figure 9 The driving method for pixel PXnm shown.

[0203] Figure 10A and Figure 10B It is used to show Figure 8 The power supply shown Figure 9 The timing diagram of the driving method for the pixels shown is as follows. Figure 11A and Figure 11B It is shown Figure 9 The pixels shown are based on Figure 10A and Figure 10B The diagram shows an embodiment of the driving method for emitting light.

[0204] exist Figure 10A , Figure 10B and Figure 11A In order to better understand and be easier to describe, the driving method of pixel PXnm will be described relative to the pixel PXnm that is set on the nth horizontal line and connected to the mth data line DLm and the kth sensing line ILk.

[0205] In addition, Figure 10A , Figure 10B , Figure 11A and Figure 11BThe driving method for power supply 170 and pixel PXnm in the first frame period (e.g., odd frame period) will be described.

[0206] In this embodiment, the conduction level voltages of the first scan signal SC1, the second scan signal SS1, the third scan signal SC2, and the fourth scan signal SS2 can be defined as voltages with a high level. However, this embodiment is exemplary, and the voltage levels and / or pulse widths of the scan signals SC1, SC2, SS1, and SS2 are not limited thereto and can be varied depending on the pixel structure, transistor type, etc.

[0207] In another embodiment where the first scan signal SC1 is the same as the second scan signal SS1 and the third scan signal SC2 is the same as the fourth scan signal SS2, the second sub-scan driver 132 and the fourth sub-scan driver 134 may be omitted.

[0208] Reference Figure 10A During odd-numbered frame periods, power supply 170 can supply a first power supply voltage VS1 at a first level to the first power supply line PL1, and a second power supply voltage VS2 at a second level to the second power supply line PL2.

[0209] For example, during odd-numbered frame periods, a first power supply voltage VS1 at a high level can be supplied to the first power supply line PL1, and a second power supply voltage VS2 at a low level can be supplied to the second power supply line PL2.

[0210] During the first time period A in a horizontal period 1H, the first sub-scan driver 131 can supply the first scan signal SC1, which is at the on level, to the first scan line SL1n.

[0211] When the first scan signal SC1 is supplied, the second transistor Tr2 is turned on by the first scan signal SC1. When the second transistor Tr2 is turned on, the first data signal DV(n) of the nth row is applied to the second node N2 through the data line DLm.

[0212] During the first time period A in a horizontal period 1H, the second sub-scan driver 132 can supply the second scan signal SS1, which is at the on level, to the second scan line SL2n.

[0213] In this embodiment, when the first scan signal SC1, which is at the on level, is supplied, the second scan signal SS1 can be supplied simultaneously and synchronously.

[0214] When the second scan signal SS1 is supplied, the third transistor Tr3 is turned on by the second scan signal SS1. When the third transistor Tr3 is turned on, the initialization voltage VINT is applied to the first node N1 through the sensing line ILk. When the initialization voltage VINT is applied to the first node N1, the first electrode of the first light-emitting diode LD1 and the second electrode of the second light-emitting diode LD2 are initialized. At this time, the initialization voltage VINT can be, for example, a second level. In an embodiment, the initialization voltage VINT can be a low level.

[0215] During the first time period A, an initialization voltage VINT is applied to the first electrode of the first storage capacitor Cst1, and the nth first data signal DV(n) is applied to the second electrode of the first storage capacitor Cst1. Therefore, a difference voltage corresponding to the difference between the nth first data signal DV(n) and the initialization voltage VINT is charged into the first storage capacitor Cst1.

[0216] During the second time period B in one horizontal period 1H, the third sub-scan driver 133 can supply the third scan signal SC2, which is at the on level, to the third scan line SL3n.

[0217] When the third scan signal SC2 is supplied, the fifth transistor Tr5 is turned on by the third scan signal SC2. When the fifth transistor Tr5 is turned on, the nth first data signal DV(n) is applied to the fourth node N4 through the data line DLm.

[0218] During the second time period B in one horizontal period 1H, the fourth sub-scan driver 134 can supply the fourth scan signal SS2, which is at the on level, to the fourth scan line SL4n.

[0219] In this embodiment, when the third scan signal SC2, which is at the on level, is supplied, the fourth scan signal SS2 can be supplied simultaneously and synchronously.

[0220] When the fourth scan signal SS2 is supplied, the sixth transistor Tr6 is turned on by the fourth scan signal SS2. When the sixth transistor Tr6 is turned on, the initialization voltage VINT is applied to the third node N3 through the sensing line ILk. When the initialization voltage VINT is applied to the third node N3, the second electrode of the first light-emitting diode LD1 and the first electrode of the second light-emitting diode LD2 are initialized. At this time, the initialization voltage VINT can be, for example, a second level. In an embodiment, the initialization voltage VINT can be a low level.

[0221] During the second time period B, an initialization voltage VINT is applied to the first electrode of the second storage capacitor Cst2, and the nth first data signal DV(n) is applied to the second electrode of the second storage capacitor Cst2. Therefore, a difference voltage corresponding to the difference between the nth first data signal DV(n) and the initialization voltage VINT is charged into the second storage capacitor Cst2. In this embodiment, one horizontal period 1H can represent the period from the first time period A to the second time period B.

[0222] In this embodiment, the first time period A and the second time period B may not overlap. Furthermore, the time interval between the first time period A and the second time period B may be... Figure 10A The time interval of the first time period A shown is the same as the time interval of the second time period B, but it is not limited to this. Figure 10A As shown, the sum of the first time period A and the second time period B can maintain one horizontal cycle of 1H, but the time interval of the first time period A can be increased and the time interval of the second time period B can be decreased, or the time interval of the first time period A can be decreased and the time interval of the second time period B can be increased.

[0223] Reference Figure 10A and Figure 11A During odd-numbered frame periods, the first power supply voltage VS1 supplied to the first power line PL1 is set to be higher than the second power supply voltage VS2 supplied to the second power line PL2. Furthermore, the first transistor Tr1 is turned on during the first time period A via the nth first data signal DV(n) stored in the first storage capacitor Cst1, and the fourth transistor Tr4 is turned on during the second time period B via the nth first data signal DV(n) stored in the second storage capacitor Cst2. When the first transistor Tr1 and the fourth transistor Tr4 are turned on and the first power supply voltage VS1 is set to be higher than the second power supply voltage VS2, the drive current Id can flow through the first light-emitting diode LD1 but not through the second light-emitting diode LD2. At this time, after the second time period B, only the first light-emitting diode LD1 emits light.

[0224] Therefore, refer to Figure 11A and Figure 11B In the first frame period (e.g., an odd frame period), at least one light-emitting diode LD (e.g., the first light-emitting diode LD1) aligned in the forward direction among the light-emitting diodes LD included in each of the plurality of pixels PX included in the display unit 160 can emit light.

[0225] Reference Figure 10B , Figure 10B The embodiments shown are the same as those referenced above. Figure 10AThe described embodiments are similar, but refer to the above. Figure 10A The difference in the described embodiment is that, when the third scan signal SC2 is supplied, the nth second data signal BV(n), instead of the nth first data signal DV(n), is applied to the fourth node N4 during the second time period B. Here, the nth second data signal BV(n) can be a voltage used to turn on the driving transistor (e.g., the fourth transistor Tr4), and can represent a voltage that minimizes the equivalent resistance of the turned-on driving transistor (e.g., the fourth transistor Tr4).

[0226] In particular, Figure 10B During the second time period B, the voltage difference between the initialization voltage VINT and the nth second data signal BV(n) is charged into the second storage capacitor Cst2. Here, the nth second data signal BV(n) is set to enable the fourth transistor Tr4 to conduct, so that after the second time period B, the fourth transistor Tr4 can conduct stably.

[0227] Reference Figure 10B , Figure 11A and Figure 11B As shown above Figure 10A , Figure 11A and Figure 11B As described, in the first frame period (e.g., an odd frame period), only the first light-emitting diode LD1 among the first light-emitting diode LD1 and the second light-emitting diode LD2 can emit light, and at least one light-emitting diode LD (e.g., the first light-emitting diode LD1) aligned in the positive direction among the light-emitting diodes LD included in each of the plurality of pixels PX included in the display unit 160 can emit light.

[0228] according to Figure 10B The driving current Id corresponding to the nth first data signal DV(n) flows stably into the pixel PXnm, which makes it possible to display the desired grayscale value, brightness, etc. more accurately.

[0229] Figure 12A and Figure 12B It is used to show Figure 8 The power supply shown Figure 9 The timing diagram of the driving method for the pixels shown is as follows. Figure 13A and Figure 13B It is shown Figure 9 The pixels shown are based on Figure 12A and Figure 12B The diagram shows an embodiment of the driving method for emitting light.

[0230] exist Figure 12A , Figure 12B and Figure 13A In, such as in Figure 10A, Figure 10B and Figure 11A In order to better understand and be easier to describe, the driving method of pixel PXnm will be described with reference to pixel PXnm, which is set on the nth horizontal line and connected to the mth data line DLm and the kth sensing line ILk. The driving method of power supply 170 and pixel PXnm in the second frame period (e.g., even frame period) will also be described.

[0231] Furthermore, in the description Figure 12A , Figure 12B and Figure 13A In the embodiments shown, the terms and conditions will be omitted. Figure 10A , Figure 10B and Figure 11A The same description as shown.

[0232] In this embodiment, the voltages of the first scan signal SC1, the second scan signal SS1, the third scan signal SC2, and the fourth scan signal SS2 at the on level can be defined as voltages with a high level. However, the embodiment is not limited to this.

[0233] Reference Figure 12A During even-numbered frame periods, power supply 170 supplies a first power supply voltage VS1 at the second level to the first power supply line PL1, and supplies a second power supply voltage VS2 at the first level to the second power supply line PL2.

[0234] For example, during even-numbered frame periods, a first power supply voltage VS1 at a low level is supplied to the first power supply line PL1, and a second power supply voltage VS2 at a high level is supplied to the second power supply line PL2.

[0235] During the first time period A within a horizontal period 1H, the third sub-scan driver 133 can supply the third scan signal SC2, which is at the on level, to the third scan line SL3n. When the third scan signal SC2 is supplied, the fifth transistor Tr5 is turned on, and then the nth first data signal DV(n) is applied to the fourth node N4 through the data line DLm.

[0236] During the first time period A within a horizontal period 1H, the fourth sub-scan driver 134 can supply the fourth scan signal SS2, which is at the on level, to the fourth scan line SL4n. When the fourth scan signal SS2 is supplied, the sixth transistor Tr6 is turned on, and then the initialization voltage VINT is applied to the third node N3. When the initialization voltage VINT is applied to the third node N3, the second electrode of the first light-emitting diode LD1 and the first electrode of the second light-emitting diode LD2 are initialized. At this time, the initialization voltage VINT can be, for example, the second level.

[0237] During the first time period A, the initialization voltage VINT is applied to the first electrode of the second storage capacitor Cst2, and the nth first data signal DV(n) is applied to the second electrode of the second storage capacitor Cst2. Therefore, the first storage capacitor Cst1 is charged with a difference voltage corresponding to the difference between the nth first data signal DV(n) and the initialization voltage VINT.

[0238] During the second time period B within one horizontal period 1H, the first sub-scan driver 131 can supply a first scan signal SC1 at the on level to the first scan line SL1n. When the first scan signal SC1 is supplied, the second transistor Tr2 is turned on, and then the nth first data signal DV(n) is applied to the second node N2 through the data line DLm.

[0239] During the second time period B within one horizontal period 1H, the second sub-scan driver 132 can supply a second scan signal SS1 at an on level to the second scan line SL2n. When the second scan signal SS1 is supplied, the third transistor Tr3 is turned on, and then an initialization voltage VINT is applied to the first node N1. When the initialization voltage VINT is applied to the first node N1, the first electrode of the first light-emitting diode LD1 and the second electrode of the second light-emitting diode LD2 are initialized. At this time, the initialization voltage VINT can be, for example, a second level.

[0240] During the second time period B, the initialization voltage VINT is applied to the first electrode of the first storage capacitor Cst1, and the nth first data signal DV(n) is applied to the second electrode of the first storage capacitor Cst1. Therefore, the first storage capacitor Cst1 is charged with a difference voltage corresponding to the difference between the nth first data signal DV(n) and the initialization voltage VINT.

[0241] Reference Figure 12A and Figure 13A During even-numbered frame periods, the first power supply voltage VS1 supplied to the first power line PL1 is set to be lower than the second power supply voltage VS2 supplied to the second power line PL2. Then, the fourth transistor Tr4 is turned on during the first time period A via the nth first data signal DV(n) stored in the second storage capacitor Cst2, and the first transistor Tr1 is turned on during the second time period B via the nth first data signal DV(n) stored in the first storage capacitor Cst1. When the first transistor Tr1 and the fourth transistor Tr4 are turned on and the first power supply voltage VS1 is set to be lower than the second power supply voltage VS2, the drive current Id can flow through the second light-emitting diode LD2 but not through the first light-emitting diode LD1. At this time, after the second time period B, only the second light-emitting diode LD2 emits light.

[0242] Therefore, refer to Figure 13A and Figure 13B In the second frame period (e.g., an even frame period), at least one light-emitting diode LD (e.g., the second light-emitting diode LD2) that is aligned in the opposite direction (or the second direction) among the light-emitting diodes LD included in each of the plurality of pixels PX in the display unit 160 can emit light.

[0243] Reference Figure 12B , Figure 12B The embodiments shown are the same as those referenced above. Figure 12A The described embodiments are similar, but refer to the above. Figure 10A The difference in the described embodiment is that, when the first scan signal SC1 is supplied, the nth second data signal BV(n), instead of the nth first data signal DV(n), is applied to the second node N2 during the second time period B. Here, the nth second data signal BV(n) can be a voltage used to turn on the driving transistor (e.g., the first transistor Tr1), and can represent a voltage that minimizes the equivalent resistance of the turned-on driving transistor (e.g., the first transistor Tr1).

[0244] In particular, Figure 12B During the second time period B, the voltage difference between the initialization voltage VINT and the nth second data signal BV(n) is charged into the first storage capacitor Cst1. Here, the nth second data signal BV(n) is set to enable the first transistor Tr1 to conduct, so that after the second time period B, the first transistor Tr1 can conduct stably. In another embodiment, the nth second data signal BV(n) is set to enable the first transistor Tr1 to be turned off, so that after the second time period B, the first transistor Tr1 can be turned off stably.

[0245] Reference Figure 12B , Figure 13A and Figure 13B As shown above Figure 12A , Figure 13A and Figure 13B As described, during the second frame period (e.g., an even frame period), only the second light-emitting diode LD2 among the first light-emitting diode LD1 and the second light-emitting diode LD2 can substantially emit light, including at least one light-emitting diode LD (e.g., the second light-emitting diode LD2) among the light-emitting diodes LD included in each of the plurality of pixels PX in the display unit 160 that is aligned in the opposite direction (or the second direction) can substantially emit light.

[0246] according to Figure 12BThe driving current Id corresponding to the nth first data signal DV(n) flows stably into the pixel PXnm, which makes it possible to display the desired grayscale value, brightness, etc. more accurately.

[0247] Based on the above, the display device can drive all light-emitting diodes (LDs) included in the pixels by alternately switching the level of the first power supply voltage VS1 and the level of the second power supply voltage VS2 for each frame.

[0248] In addition, the brightness and lifespan of LEDs can be increased by driving all LEDs.

[0249] Figure 14 yes Figure 9 A modified embodiment of the pixels shown.

[0250] In description Figure 14 When the pixel PXnm is shown, the part related to the pixel will be omitted. Figure 9 The construction shown is the same as the description of the construction, and the description will focus on the differences.

[0251] Reference Figure 9 and Figure 14 As shown above Figure 8 As described, since the second sub-scan driver 132 and the fourth sub-scan driver 134 can be composed of a single sub-scan driver, therefore Figure 9 The second scan line SL2n and the fourth scan line SL4n shown can be integrated into a single scan line (e.g., Figure 14 The second scan line SL2n is shown in the diagram. Furthermore, the second scan signal SS1 and the fourth scan signal SS2 can be the same. Based on the above, manufacturing costs can be reduced by not adding scan lines, and power consumption can also be reduced by not adding scan signals.

[0252] In another embodiment, the display panel includes: a data driver connected to a first plurality of data lines; and a first plurality of pixels, each connected to a corresponding one of the first plurality of data lines and connected to a pair of switchable polarity power lines, wherein each of the first plurality of pixels includes a first light-emitting diode arranged with a first polarity, and a second light-emitting diode arranged in parallel with the first light-emitting diode and with a second polarity opposite to the first polarity.

[0253] In another embodiment of the display panel, each of the plurality of pixels may further include: a first circuit for driving a first light-emitting diode; and a second circuit for driving a second light-emitting diode, wherein, during the same frame period, a data driver supplies a first data signal to the first circuit via a first of a plurality of data lines, and supplies a second data signal to the second circuit via a first of a plurality of data lines.

[0254] In the following text, the second scan line SL2n and the second scan signal SS1 will be described. Figure 14 The driving method for pixel PX shown.

[0255] Figure 15A and Figure 15B It is used to show Figure 8 The power supply shown Figure 14 The timing diagram shows the driving method for the pixels shown. Specifically, Figure 15A and Figure 15B It is a timing diagram used to illustrate the driving methods of power supply and pixels during the first frame period (e.g., odd frame period).

[0256] exist Figure 15A and Figure 15B In this context, as described above, the voltage at which the scanning signals SC1, SC2, and SS1 are turned on will be defined as a voltage at which the pixel PXnm is high relative to the pixel connected to the m-th data line DLm and the k-th sensing line ILk.

[0257] Furthermore, in the description Figure 15A and Figure 15B In the embodiments shown, the pairs and Figure 10A and Figure 10B The descriptions shown are identical to those of the content shown, and the descriptions will focus on the differences.

[0258] Reference Figure 15A During odd-numbered frame periods, power supply 170 supplies a first power supply voltage VS1 at a first level (e.g., high level) to the first power supply line PL1, and supplies a second power supply voltage VS2 at a second level (e.g., low level) to the second power supply line PL2.

[0259] During the first time period A in one horizontal period 1H, the first sub-scan driver 131 can supply the first scan signal SC1, which is at the on level, to the first scan line SL1n. When the second transistor Tr2 is turned on by the first scan signal SC1, the nth first data signal DV(n) is applied to the second node N2.

[0260] During one horizontal cycle 1H, the second sub-scan driver 132 can supply a second scan signal SS1 at an on level to the second scan line SL2n. When the third transistor Tr3 and the sixth transistor Tr6 are turned on by the second scan signal SS1, an initialization voltage VINT is applied to the first node N1 and the third node N3. Therefore, the first and second electrodes of each of the first light-emitting diode LD1 and the second light-emitting diode LD2 are initialized. In this case, the initialization voltage VINT can be, for example, a second level (e.g., a low level).

[0261] During the first time period A, an initialization voltage VINT is applied to the first electrode of the first storage capacitor Cst1, and the nth first data signal DV(n) is applied to the second electrode of the first storage capacitor Cst1. Therefore, a difference voltage corresponding to the difference between the nth first data signal DV(n) and the initialization voltage VINT is charged into the first storage capacitor Cst1.

[0262] During the second time period B within one horizontal period 1H, the third sub-scan driver 133 can supply the third scan signal SC2, which is at the on level, to the third scan line SL3n. When the fifth transistor Tr5 is turned on by the third scan signal SC2, the nth first data signal DV(n) is applied to the fourth node N4 through the data line DLm.

[0263] During one horizontal cycle 1H, when the second scan signal SS1, which is at the on level, is supplied to the second scan line SL2n, the third transistor Tr3 and the sixth transistor Tr6 are turned on, and the initialization voltage VINT is applied to the first node N1 and the third node N3.

[0264] During the second time period B, the initialization voltage VINT is applied to the first electrode of the second storage capacitor Cst2, and the nth first data signal DV(n) is applied to the second electrode of the second storage capacitor Cst2. Therefore, the second storage capacitor Cst2 is charged with a difference voltage corresponding to the difference between the nth first data signal DV(n) and the initialization voltage VINT.

[0265] In the driving current Id, as Figure 11A As shown in the flow diagram, after the second time period B, Figure 14 The first light-emitting diode LD1 shown in the figure emits light. Figure 14 The second LED LD2 shown in the diagram does not emit light.

[0266] Reference Figure 15B , Figure 15B The embodiments shown are the same as those referenced above. Figure 15A The described embodiments are similar, but refer to the above. Figure 15A The difference in the described embodiment is that, when the third scan signal SC2 is supplied, the nth second data signal BV(n), instead of the nth first data signal DV(n), is applied to the fourth node N4 during the second time period B. Here, the nth second data signal BV(n) can be a voltage used to turn on the driving transistor (e.g., the fourth transistor Tr4), and can represent a voltage that minimizes the equivalent resistance of the turned-on driving transistor (e.g., the fourth transistor Tr4).

[0267] In particular, Figure 15BDuring the second time period B, the voltage difference between the initialization voltage VINT and the nth second data signal BV(n) is charged into the second storage capacitor Cst2. Here, the nth second data signal BV(n) is set to enable the fourth transistor Tr4 to conduct, so that after the second time period B, the fourth transistor Tr4 can conduct stably. In another embodiment, the nth second data signal BV(n) is set to enable the fourth transistor Tr4 to be turned off, so that after the second time period B, the fourth transistor Tr4 can be turned off stably.

[0268] In addition, such as Figure 11B As shown, at least one light-emitting diode LD (e.g., the first light-emitting diode LD1) aligned in the forward direction (or the first direction) among the light-emitting diodes LD included in each of the plurality of pixels PX included in the display unit 160 can emit light.

[0269] Although the term "direction" as used herein can include physical direction, in another embodiment it is the anode / cathode polarity direction or the direction of current flow, such as when the first and second circuits are not physically located on substantially opposite sides of the first LED LD1 and the second LED LD2, and / or the circuits are arranged differently. That is, the term "direction" should not be limited to the physical direction along which the LEDs LD are arranged in the physical circuit.

[0270] Figure 16A and Figure 16B It is used to show Figure 8 The power supply shown Figure 14 The timing diagram shows the driving method of the pixels shown. Specifically, Figure 16A and Figure 16B It is a timing diagram used to illustrate the driving methods of power supply and pixels during the second frame (e.g., during even-numbered frames).

[0271] exist Figure 16A and Figure 16B In this context, for better understanding and ease of description, the voltages at the conduction level of pixel PXnm and scan signals SC1, SC2, and SS1 are compared with those referenced above. Figure 15A and Figure 15B The described pixel PXnm and the scanning signals SC1, SC2 and SS1 have the same voltage at the on level.

[0272] Furthermore, in the description Figure 16A and Figure 16B In the embodiment shown, the ellipsis and Figure 12A and Figure 12B The content of the embodiments shown is the same, and the description will focus on the differences.

[0273] Reference Figure 16A During even-numbered frame periods, power supply 170 supplies a first power supply voltage VS1 at a second level (e.g., low level) to the first power supply line PL1, and supplies a second power supply voltage VS2 at a first level (e.g., high level) to the second power supply line PL2.

[0274] During the first time period A in one horizontal period 1H, the third sub-scan driver 133 can supply the third scan signal SC2, which is at the on level, to the third scan line SL3n. When the fifth transistor Tr5 is turned on by the third scan signal SC2, the nth first data signal DV(n) is applied to the fourth node N4 through the data line DLm.

[0275] During one horizontal cycle 1H, the second sub-scan driver 132 can supply a second scan signal SS1 at an on level to the second scan line SL2n. In this case, the third transistor Tr3 and the sixth transistor Tr6 are turned on by the second scan signal SS1. When the third transistor Tr3 and the sixth transistor Tr6 are turned on, an initialization voltage VINT is applied to the first node N1 and the third node N3, thus initializing the first and second electrodes of each of the first light-emitting diode LD1 and the second light-emitting diode LD2. In this case, the initialization voltage VINT can be, for example, a second level (e.g., a low level).

[0276] During the first time period A, the initialization voltage VINT is applied to the first electrode of the second storage capacitor Cst2, and the nth first data signal DV(n) is applied to the second electrode of the second storage capacitor Cst2. Therefore, the second storage capacitor Cst2 is charged with a difference voltage corresponding to the difference between the nth first data signal DV(n) and the initialization voltage VINT.

[0277] During the second time period B within a horizontal period 1H, the first sub-scan driver 131 can supply the first scan signal SC1, which is at the on level, to the first scan line SL1n. When the second transistor Tr2 is turned on by the first scan signal SC1, the nth first data signal DV(n) is applied to the second node N2.

[0278] During one horizontal cycle 1H, when the second scan signal SS1, which is at the on level, is supplied to the second scan line SL2n, the third transistor Tr3 and the sixth transistor Tr6 are turned on, and then the initialization voltage VINT is applied to the first node N1 and the third node N3.

[0279] During the second time period B, the initialization voltage VINT is applied to the first electrode of the first storage capacitor Cst1, and the nth first data signal DV(n) is applied to the second electrode of the first storage capacitor Cst1. Therefore, the first storage capacitor Cst1 is charged with a difference voltage corresponding to the difference between the nth first data signal DV(n) and the initialization voltage VINT.

[0280] In the driving current Id, as Figure 13A As shown in the flow diagram, after the second time period B, Figure 14 The first LED LD1 shown does not emit light. Figure 14 The second light-emitting diode LD2 shown in the figure emits light.

[0281] Reference Figure 16B , Figure 16B The embodiments shown are the same as those referenced above. Figure 16A The described embodiments are similar, but refer to the above. Figure 16A The difference in the described embodiment is that during the second time period B, when the first scan signal SC1 is supplied, the nth second data signal BV(n) instead of the nth first data signal DV(n) is applied to the second node N2. Here, the nth second data signal BV(n) can be the voltage used to turn on the driving transistor (e.g., the first transistor Tr1), and can represent the voltage that allows the equivalent resistance of the turned-on driving transistor (e.g., the first transistor Tr1) to have a minimum value.

[0282] In particular, Figure 16B During the second time period B, the voltage difference between the initialization voltage VINT and the nth second data signal BV(n) is charged into the first storage capacitor Cst1. Here, the nth second data signal BV(n) is set to enable the first transistor Tr1 to conduct, so that after the second time period B, the first transistor Tr1 can conduct stably. Furthermore, as... Figure 13B As shown, at least one light-emitting diode LD (e.g., a second light-emitting diode LD2) aligned in the opposite direction (or second direction) among the light-emitting diodes LD included in each of the plurality of pixels PX included in the display unit 160 can emit light.

[0283] Meanwhile, when the number of LEDs (e.g., first LED LD1) aligned in the forward direction (or first direction) among the LEDs included in the pixel PX is the same as the number of LEDs (e.g., second LED LD2) aligned in the reverse direction (or second direction) among the LEDs included in the pixel PX, the difference in brightness between odd-numbered frames and even-numbered frames is very small.

[0284] However, when the number of LEDs (e.g., first LED LD1) aligned in the forward direction (or first direction) among the LEDs included in the pixel PX differs from the number of LEDs (e.g., second LED LD2) aligned in the reverse direction (or second direction) among the LEDs included in the pixel PX, the LEDs emitting light in odd-numbered frames differ from those emitting light in even-numbered frames. Therefore, a difference in brightness may occur between odd and even frames, resulting in flickering.

[0285] Therefore, a pixel structure is provided in which a light-emitting diode (LD) included in a pixel PX can emit light alternately during a frame. Such a pixel PX will be described in detail below.

[0286] Figure 17 This is a circuit diagram of a pixel according to an embodiment of the present invention.

[0287] exist Figure 17 In order to better understand and facilitate description, embodiments of the present invention will be described relative to the pixel PXnm (or the first pixel) that is set on the nth horizontal line and connected to the mth data line DLm and the kth sensing line ILk.

[0288] Reference Figure 17 The pixel PXnm may include a first pixel circuit PXC1, a second pixel circuit PXC2, and light-emitting diodes LD1 and LD2.

[0289] The first pixel circuit PXC1 can drive the first light-emitting diode LD1. The first pixel circuit PXC1 can be connected to the first power line PL1, the second power line PL2, the first scan line SL1n, the second scan line SL2n, the data line DLm, the sensing line ILk, the first light-emitting diode LD1, and the second light-emitting diode LD2.

[0290] The first pixel circuit PXC1 may include a first transistor Tr1, a second transistor Tr2, a third transistor Tr3, a fourth transistor Tr4, and a first storage capacitor Cst1.

[0291] The first electrode of the first transistor Tr1 can be connected to the first power line PL1, the second electrode of the first transistor Tr1 can be connected to the first node N1, and the gate electrode of the first transistor Tr1 can be connected to the second node N2.

[0292] The second transistor Tr2 can be connected between the data line DLm and the second node N2. That is, the first electrode of the second transistor Tr2 can be connected to the data line DLm, the second electrode of the second transistor Tr2 can be connected to the second node N2, and the gate electrode of the second transistor Tr2 can be connected to the first scan line SL1n.

[0293] The third transistor Tr3 can be connected between the second electrode (e.g., the first node N1) of the first transistor Tr1 and the sensing line ILk. That is, the first electrode of the third transistor Tr3 can be connected to the first node N1, the second electrode of the third transistor Tr3 can be connected to the sensing line ILk, and the gate electrode of the third transistor Tr3 can be connected to the second scan line SL2n. When a second scan signal SS1 with a pulse at the on level is supplied to the second scan line SL2n, the third transistor Tr3 is turned on to electrically connect the sensing line ILk and the first node N1. Simultaneously, when the third transistor Tr3 is turned on, an initialization voltage supplied to the sensing line ILk can be applied to the first node N1. When the initialization voltage is applied to the first node N1, the first electrode (e.g., the anode) of the first light-emitting diode LD1 and the second electrode (e.g., the cathode) of the second light-emitting diode LD2 can be initialized.

[0294] The fourth transistor Tr4 can control the drive current based on the data signal. The first electrode of the fourth transistor Tr4 can be connected to the second power line PL2, the second electrode of the fourth transistor Tr4 can be connected to the third node N3, and the gate electrode of the fourth transistor Tr4 can be connected to the second node N2.

[0295] Because the first storage capacitor Cst1 and Figure 9 and Figure 14 The first storage capacitor Cst1 shown is the same, so its description is omitted.

[0296] The second pixel circuit PXC2 can drive the second light-emitting diode LD2. The second pixel circuit PXC2 can be connected to the first power line PL1, the second power line PL2, the third scan line SL3n, the fourth scan line SL4n, the data line DLm, the sensing line ILk, the first light-emitting diode LD1, and the second light-emitting diode LD2.

[0297] The second pixel circuit PXC2 may include a fifth transistor Tr5, a sixth transistor Tr6, a seventh transistor Tr7, an eighth transistor Tr8, and a second storage capacitor Cst2.

[0298] The fifth transistor Tr5 can control the drive current based on the data signal. The first electrode of the fifth transistor Tr5 can be connected to the first power supply line PL1, the second electrode of the fifth transistor Tr5 can be connected to the third node N3, and the gate electrode of the fifth transistor Tr5 can be connected to the fourth node N4.

[0299] The sixth transistor Tr6 can be connected between the data line DLm and the fourth node N4. That is, the first electrode of the sixth transistor Tr6 can be connected to the data line DLm, the second electrode of the sixth transistor Tr6 can be connected to the fourth node N4, and the gate electrode of the sixth transistor Tr6 can be connected to the third scan line SL3n.

[0300] The seventh transistor Tr7 can be connected between the second electrode (e.g., the third node N3) of the fourth transistor Tr4 and the sensing line ILk. That is, the first electrode of the seventh transistor Tr7 can be connected to the third node N3, the second electrode of the seventh transistor Tr7 can be connected to the sensing line ILk, and the gate electrode of the seventh transistor Tr7 can be connected to the fourth scan line SL4n. When a fourth scan signal SS2 with a pulse at the on level is supplied to the fourth scan line SL4n, the seventh transistor Tr7 is turned on, electrically connecting the sensing line ILk and the third node N3. On the other hand, when the seventh transistor Tr7 is turned on, an initialization voltage supplied to the sensing line ILk can be applied to the third node N3. When the initialization voltage is applied to the third node N3, the second electrode (e.g., the cathode) of the first light-emitting diode LD1 and the first electrode (e.g., the anode) of the second light-emitting diode LD2 can be initialized.

[0301] In this embodiment, the initialization voltage may be a voltage with a low level.

[0302] The eighth transistor Tr8 can control the drive current based on the data signal. The first electrode of the eighth transistor Tr8 can be connected to the second power line PL2, the second electrode of the eighth transistor Tr8 can be connected to the first node N1, and the gate electrode of the eighth transistor Tr8 can be connected to the fourth node N4.

[0303] Due to the second storage capacitor Cst2 and Figure 9 and Figure 14 The second storage capacitor Cst2 shown is the same, so its description is omitted.

[0304] In this embodiment, transistors Tr1 to Tr8 can be composed of N-type transistors, P-type transistors, or a combination of N-type and P-type transistors. For example, transistors Tr1 to Tr8 can be as follows: Figure 17 The N-type transistor shown is illustrated. However, the embodiments are not limited to this.

[0305] Because the first light-emitting diode LD1 and the second light-emitting diode LD2 are... Figure 9 and Figure 14 The first LED LD1 and the second LED LD2 shown are the same, so their description is omitted.

[0306] In an embodiment, the first power supply voltage supplied to the first power line PL1 may be higher than the second power supply voltage supplied to the second power line PL2.

[0307] When an initialization voltage is supplied to the first and second electrodes of LEDs LD1 and LD2, the parasitic capacitors in each of LEDs LD1 and LD2 can discharge. When the residual voltage charged in the parasitic capacitors is discharged (removed), unintentional fine light emission can be prevented. Therefore, the black level of the pixel PXnm can be improved.

[0308] The following text will describe it in detail. Figure 8 The power supply shown Figure 17 The driving method for pixel PXnm shown.

[0309] Figure 18 It is used for explanation Figure 8 The power supply shown Figure 17 The timing diagram of the driving method for the pixels shown is as follows. Figure 19 and Figure 20 It is shown Figure 17 The pixels shown are based on Figure 18 The diagram shows an embodiment of the driving method for emitting light. Figure 21A and Figure 21B It is shown Figure 17 The pixels shown are based on Figure 18 The figure shows an embodiment of the driving method for emitting light.

[0310] exist Figures 18 to 20 In order to better understand and be easier to describe, the driving method of pixel PXnm is described relative to pixel PXnm (or the first pixel) which is set on the nth horizontal line and connected to the mth data line DLm and the kth sensing line ILk, and the voltage of the scan signals SC1, SC2, SS1 and SS2 at the on level is defined as the voltage with a high level.

[0311] Reference Figure 18 Power supply 170 supplies a first power supply voltage VS1 at the first level to the first power supply line PL1, and supplies a second power supply voltage VS2 at the second level to the second power supply line PL2.

[0312] For example, a first power supply voltage VS1 at a high level is supplied to the first power supply line PL1, and a second power supply voltage VS2 at a low level is supplied to the second power supply line PL2.

[0313] During the first time period A in a horizontal period 1H, the first sub-scan driver 131 can supply the first scan signal SC1, which is at the on level, to the first scan line SL1n.

[0314] When the first scan signal SC1 is supplied, the second transistor Tr2 is turned on by the first scan signal SC1. When the second transistor Tr2 is turned on, the nth first data signal DV(n) is applied to the second node N2 through the data line DLm. When the nth first data signal DV(n) is applied to the second node N2, the first transistor Tr1 and the fourth transistor Tr4 are turned on.

[0315] During the first time period A in a horizontal period 1H, the second sub-scan driver 132 can supply the second scan signal SS1, which is at the on level, to the second scan line SL2n.

[0316] In this embodiment, when the first scan signal SC1, which is at the on level, is supplied, the second scan signal SS1 can be supplied simultaneously and synchronously.

[0317] When the second scan signal SS1 is supplied, the third transistor Tr3 is turned on by the second scan signal SS1. When the third transistor Tr3 is turned on, the initialization voltage VINT is applied to the first node N1 through the sensing line Ilk. When the initialization voltage VINT is applied to the first node N1, the first electrode of the first light-emitting diode LD1 and the second electrode of the second light-emitting diode LD2 are initialized. At this time, the initialization voltage VINT can be, for example, a second level. In an embodiment, the initialization voltage VINT can be a low level.

[0318] During the first time period A, an initialization voltage VINT is applied to the first electrode of the first storage capacitor Cst1, and the nth first data signal DV(n) is applied to the second electrode of the first storage capacitor Cst1. Therefore, a difference voltage corresponding to the difference between the nth first data signal DV(n) and the initialization voltage VINT is charged into the first storage capacitor Cst1.

[0319] During the second time period B in one horizontal period 1H, the third sub-scan driver 133 can supply the third scan signal SC2, which is at the on level, to the third scan line SL3n.

[0320] When the third scan signal SC2 is supplied, the sixth transistor Tr6 is turned on by the third scan signal SC2. When the sixth transistor Tr6 is turned on, the nth first data signal DV(n) is applied to the fourth node N4 through the data line DLm. When the nth first data signal DV(n) is applied to the fourth node N4, the fifth transistor Tr5 and the eighth transistor Tr8 are turned on.

[0321] During the second time period B in one horizontal period 1H, the fourth sub-scan driver 134 can supply the fourth scan signal SS2, which is at the on level, to the fourth scan line SL4n.

[0322] In this embodiment, when the third scan signal SC2, which is at the on level, is supplied, the fourth scan signal SS2 can be supplied simultaneously and synchronously.

[0323] When the fourth scan signal SS2 is supplied, the seventh transistor Tr7 is turned on by the fourth scan signal SS2. When the seventh transistor Tr7 is turned on, the initialization voltage VINT is applied to the third node N3 through the sensing line ILk. When the initialization voltage VINT is applied to the third node N3, the second electrode of the first light-emitting diode LD1 and the first electrode of the second light-emitting diode LD2 are initialized. At this time, the initialization voltage VINT can be, for example, a second level. In an embodiment, the initialization voltage VINT can be a low level.

[0324] During the second time period B, the initialization voltage VINT is applied to the first electrode of the second storage capacitor Cst2, and the nth first data signal DV(n) is applied to the second electrode of the second storage capacitor Cst2. Therefore, the second storage capacitor Cst2 is charged with a difference voltage corresponding to the difference between the nth first data signal DV(n) and the initialization voltage VINT.

[0325] In an embodiment, a horizontal period 1H can represent the period from the first time period A to the second time period B.

[0326] In this embodiment, the first time period A and the second time period B may not overlap. Furthermore, the time interval between the first time period A and the second time period B may be... Figure 18 The time interval of the first time period A shown is the same as the time interval of the second time period B, but it is not limited to this.

[0327] Reference Figure 19 and Figure 20During the first time period A, when the first data signal stored in the first storage capacitor Cst1 is applied to the second node N2, the first transistor Tr1 and the fourth transistor Tr4 are turned on. Then, during the second time period B, when the first data signal stored in the second storage capacitor Cst2 is applied to the fourth node N4, the fifth transistor Tr5 and the eighth transistor Tr8 are turned on.

[0328] When the first transistor Tr1 and the fourth transistor Tr4 are turned on, the drive current Id flows in the path formed by the first power line PL1, the first transistor Tr1, the first light-emitting diode LD1, the fourth transistor Tr4, and the second power line PL2. Then, when the fifth transistor Tr5 and the eighth transistor Tr8 are turned on, the drive current Id flows in the path formed by the first power line PL1, the fifth transistor Tr5, the second light-emitting diode LD2, the eighth transistor Tr8, and the second power line PL2.

[0329] Therefore, after the second time period B, both the first LED LD1 and the second LED LD2 can emit light.

[0330] Reference Figure 21A and Figure 21B The light-emitting diodes included in each of the plurality of pixels PX in the display unit 160 can emit light during a frame cycle.

[0331] Therefore, when comparing Figure 21A and Figure 21B as well as Figure 11B and Figure 13B At that time, because it was included Figure 17 All the light-emitting diodes LD1 and LD2 in the pixel PXnm shown in the diagram emit light during one frame period, therefore... Figure 9 Compared to the embodiments shown, Figure 17 The embodiments shown can minimize the brightness differences between frames and further improve flicker caused by the brightness differences between frames.

[0332] At the same time, Figure 18 The diagram illustrates a first scan signal SC1 and a second scan signal SS1 supplied at an on level during a first time period A, and a third scan signal SC2 and a fourth scan signal SS2 supplied at an on level during a second time period B following the supply of the first scan signal SC1 and the second scan signal SS1, but is not limited thereto. The third scan signal SC2 and the fourth scan signal SS2 at an on level may be supplied during the first time period A, and the first scan signal SC1 and the second scan signal SS1 at an on level may be supplied during the second time period B.

[0333] Figure 22 yes Figure 17 A modified embodiment of the pixels shown.

[0334] In description Figure 22 In the pixel PXnm shown, the values ​​for those with... Figure 17 The construction shown is the same as the description of the construction, and the description will focus on the differences.

[0335] Reference Figure 17 and Figure 22 As shown above Figure 8 As described, since the second sub-scan driver 132 and the fourth sub-scan driver 134 can be composed of a single sub-scan driver, therefore Figure 17 The second scan line SL2n and the fourth scan line SL4n shown can be integrated into a single scan line (e.g., Figure 22 The second scan line SL2n is shown in the diagram. Furthermore, the second scan signal SS1 and the fourth scan signal SS2 can be the same.

[0336] Based on the above, manufacturing costs can be reduced by not adding scan lines, and power consumption can also be reduced by not adding scan signals.

[0337] In the following text, the description will be relative to the second scan line SL2n and the second scan signal SS1. Figure 23 The driving method for the pixels shown.

[0338] Figure 23 It is used to show Figure 8 The power supply shown is Figure 22 The timing diagram shows the driving method of the pixel shown.

[0339] exist Figure 23 In the middle, as shown above Figures 17 to 20 As described, the voltage of the turn-on level of scan signals SC1, SC2 and SS1 will be defined as a voltage with a high level relative to the pixel PXnm connected to the m-th data line DLm and the k-th sensing line ILk, but is not limited thereto.

[0340] Furthermore, in the description Figure 23 In the embodiment shown, the ellipsis and Figure 18 The embodiments shown are identical in content, and the description will focus on the differences.

[0341] Reference Figure 23 Power supply 170 supplies a first power supply voltage VS1 at a first level (e.g., high level) to the first power supply line PL1, and supplies a second power supply voltage VS2 at a second level (e.g., low level) to the second power supply line PL2.

[0342] During a first time period A within a horizontal period 1H, the first sub-scan driver 131 can supply a first scan signal SC1 at an on level to the first scan line SL1n. When the second transistor Tr2 is turned on by the first scan signal SC1, the nth first data signal DV(n) is applied to the second node N2. Then, during the first time period A, when the nth first data signal DV(n) is applied to the second node N2, the first transistor Tr1 and the fourth transistor Tr4 are turned on.

[0343] During one horizontal cycle 1H, the second sub-scan driver 132 can supply a second scan signal SS1 at an on level to the second scan line SL2n. In this case, the third transistor Tr3 and the seventh transistor Tr7 are turned on by the second scan signal SS1. When the third transistor Tr3 and the seventh transistor Tr7 are turned on, an initialization voltage VINT is applied to the first node N1 and the third node N3, such that the first electrode and the second electrode of each of the first light-emitting diode LD1 and the second light-emitting diode LD2 are initialized. In this case, the initialization voltage VINT can be, for example, a second level (e.g., a low level).

[0344] During the first time period A, an initialization voltage VINT is applied to the first electrode of the first storage capacitor Cst1, and the nth first data signal DV(n) is applied to the second electrode of the first storage capacitor Cst1. Therefore, a difference voltage corresponding to the difference between the nth first data signal DV(n) and the initialization voltage VINT is charged into the first storage capacitor Cst1.

[0345] During the second time period B within one horizontal period 1H, the third sub-scan driver 133 can supply the third scan signal SC2, which is at the on level, to the third scan line SL3n. When the sixth transistor Tr6 is turned on by the third scan signal SC2, the nth first data signal DV(n) is applied to the fourth node N4 through the data line DLm. Then, during the second time period B, when the nth first data signal DV(n) is applied to the fourth node N4, the fifth transistor Tr5 and the eighth transistor Tr8 are turned on.

[0346] During one horizontal cycle 1H, when the second scan signal SS1, which is at the on level, is supplied to the second scan line SL2n, the third transistor Tr3 and the seventh transistor Tr7 are turned on, and then the initialization voltage VINT is applied to the first node N1 and the third node N3.

[0347] During the second time period B, the initialization voltage VINT is applied to the first electrode of the second storage capacitor Cst2, and the nth first data signal DV(n) is applied to the second electrode of the second storage capacitor Cst2. Therefore, the second storage capacitor Cst2 is charged with a difference voltage corresponding to the difference between the nth first data signal DV(n) and the initialization voltage VINT.

[0348] like Figure 19 As shown in the diagram, when the first transistor Tr1 and the fourth transistor Tr4 are turned on, the drive current Id flows through the first light-emitting diode LD1. Figure 20 As shown, when the fifth transistor Tr5 and the eighth transistor Tr8 are turned on, the drive current Id flows through the second light-emitting diode LD2. Therefore, after the second time period B, both the first light-emitting diode LD1 and the second light-emitting diode LD2 can emit light.

[0349] For each of the plurality of pixels PX, the alignment ratio between the number of LEDs (e.g., first LED LD1) aligned in the forward direction (or first direction) and the number of LEDs (e.g., second LED LD2) aligned in the reverse direction (or second direction) among the LEDs included in the pixel PX can be different.

[0350] In this case, the pixels PXnm set on the selected current horizontal line (or current pixel row) are driven simultaneously according to the desired grayscale value, such that when the above alignment ratio for each pixel PXnm set on the current horizontal line (or current pixel row) is different, a difference in brightness will occur between the pixels PXnm set on the current horizontal line (or current pixel row).

[0351] Therefore, with the first pixel and the second pixel set on the current horizontal line (or the current pixel row), the connection structure between the first scan line SL1 and the second scan line SL2 of the first pixel and the second transistor Tr2 and the sixth transistor Tr6 of the second pixel will be described in detail as the opposite of the connection structure between the first scan line SL1 and the second scan line SL2 of the second pixel and the second transistor Tr2 and the sixth transistor Tr6 of the second pixel.

[0352] Figure 24 is with Figure 17 The diagram shows a circuit diagram of pixels arranged on the same pixel row.

[0353] exist Figure 24 In order to better understand and facilitate description, the terms will be used in relation to... Figure 17The pixel PXnm shown is arranged on the same nth horizontal line and connected to the (m+1)th data line DL(m+1) and the (k+1)th sensing line IL(k+1) to describe an embodiment of the present invention.

[0354] Furthermore, in the description Figure 24 In the pixel PXn(m+1) shown, for better understanding and ease of description, Figure 17 The pixel PXnm shown is defined as the first pixel, and... Figure 24 The pixel PXn(m+1) shown is defined as the second pixel. Figure 24 In the pixel PXn(m+1) shown, the values ​​for the corresponding pixels will be omitted. Figure 17 The construction shown is the same as the description of the construction, and the description will focus on the differences.

[0355] Reference Figure 24 Pixel PXn(m+1) may include a first pixel circuit PXC1, a second pixel circuit PXC2, and light-emitting diodes LD1 and LD2.

[0356] The first pixel circuit PXC1 may include a first transistor Tr1, a second transistor Tr2, a third transistor Tr3, a fourth transistor Tr4, and a first storage capacitor Cst1. The second pixel circuit PXC2 may include a fifth transistor Tr5, a seventh transistor Tr7, a sixth transistor Tr6, an eighth transistor Tr8, and a second storage capacitor Cst2.

[0357] Because the first transistor Tr1, the third transistor Tr3 through the fifth transistor Tr5, the seventh transistor Tr7, the eighth transistor Tr8, and the storage capacitors Cst1 and Cst2 are... Figure 17 The first transistor Tr1, the third transistor Tr3 through the fifth transistor Tr5, the seventh transistor Tr7, the eighth transistor Tr8, and the storage capacitors Cst1 and Cst2 shown are the same, so their descriptions will be omitted.

[0358] The first electrode of the second transistor Tr2 can be connected to the data line DL(m+1), the second electrode of the second transistor Tr2 can be connected to the second node N2, and the gate electrode of the second transistor Tr2 can be connected to the third scan line SL3n.

[0359] The first electrode of the sixth transistor Tr6 can be connected to the data line DL(m+1), the second electrode of the sixth transistor Tr6 can be connected to the fourth node N4, and the gate electrode of the sixth transistor Tr6 can be connected to the first scan line SL1n.

[0360] Because LEDs LD1 and LD2 are Figure 17The LEDs LD1 and LD2 shown are identical, so their description will be omitted.

[0361] Figure 24 The driving method for pixel PXn(m+1) shown can be compared with... Figure 18 The driving method for the pixel PXnm shown is the same.

[0362] In the first pixel (e.g., Figure 17 In the pixel PXnm shown, the second transistor Tr2 is connected to the first scan line SL1n, the sixth transistor Tr6 is connected to the third scan line SL3n, and in the second pixel (e.g., Figure 24 In the pixel PXn(m+1) shown, the second transistor Tr2 is connected to the third scan line SL3n, and the sixth transistor Tr6 is connected to the first scan line SL1n. Therefore, the high reliability of the display device 100 can be achieved by minimizing the difference in brightness between pixels PXnm set on the current horizontal line (or the current pixel row).

[0363] As described above, embodiments of the present invention can minimize the difference in brightness between frames by driving all light-emitting diodes included in the pixel, and can prevent flickering during frame changes.

[0364] Furthermore, embodiments of the present invention can minimize the difference in brightness between pixels arranged on the same horizontal line (or the same pixel row) by driving all light-emitting diodes included in the pixel, and can improve the reliability of the display device.

[0365] The effects of the embodiments of the present invention are not limited to those shown above, and many more effects are included in this specification.

[0366] Although embodiments of the invention have been described with reference to the accompanying drawings, it will be understood by those skilled in the art to which this invention pertains that the invention may be made in other specific forms without substantially departing from the spirit or scope defined herein. Therefore, the above embodiments should be considered descriptive only and not for limiting purposes.

Claims

1. A display device, the display device comprising: Pixels are connected to the data cable, the first power cable, and the second power cable. as well as The data driver supplies data signals to the data line. Each of the pixels includes: a first light-emitting diode (LED) aligned in a first direction; a first pixel circuit for driving the first LED, and including a first transistor, the first transistor including a first electrode connected to the first power line, a second electrode connected to a first node, and a gate electrode connected to a second node; a second LED aligned in a second direction; and a second pixel circuit for driving the second LED, and including a fourth transistor, the fourth transistor including a first electrode connected to the second power line, a second electrode connected to a third node, and a gate electrode connected to a fourth node. The first electrode of the first light-emitting diode and the second electrode of the second light-emitting diode are connected to the first node. Wherein, the second electrode of the first light-emitting diode and the first electrode of the second light-emitting diode are connected to the third node, and During a frame period, the data driver supplies a first data signal to the first pixel circuit and a second data signal to the second pixel circuit.

2. The display device according to claim 1, wherein: The data driver supplies the first data signal during a first time period in the first frame period, and supplies the second data signal during a second time period after the first time period in the first frame period, and supplies the first data signal during the first time period in the second frame period, and supplies the second data signal during the second time period in the second frame period.

3. The display device according to claim 1, wherein: The pixel is also connected to a first scan line, a second scan line, and a sensing line. The first pixel circuit also includes: A second transistor, connected between the data line and the second node, and including a gate electrode connected to a corresponding line of the first scan line; and A third transistor is connected between the first node and the sensing line, and includes a gate electrode connected to a corresponding line in the second scan line.

4. The display device according to claim 3, wherein: The pixel is connected to the third scan line and the fourth scan line, and The second pixel circuit also includes: A fifth transistor, connected between the data line and the fourth node, and including a gate electrode connected to a corresponding line of the third scan line; and A sixth transistor is connected between the third node and the sensing line, and includes a gate electrode connected to a corresponding line in the fourth scan line.

5. The display device according to claim 4, wherein: During the first frame period, a first scan signal at the on level is supplied to the corresponding line of the first scan line during a first time period, and a second scan signal at the on level is supplied to the corresponding line of the second scan line during the first time period. During the first time period, the first data signal is supplied to the second node, and an initialization voltage is supplied to the sensing line.

6. The display device according to claim 5, wherein: During the first frame period, a third scan signal at the on level is supplied to the corresponding line of the third scan line during a second time period following the first time period, and a fourth scan signal at the on level is supplied to the corresponding line of the fourth scan line during the second time period. During the second time period, the second data signal is supplied to the fourth node, and the initialization voltage is supplied to the sensing line.

7. The display device according to claim 6, wherein: The first data signal is a signal corresponding to the grayscale value, and The second data signal is the same as the first data signal, or it is a signal at a level that turns on the fourth transistor and does not correspond to the grayscale value.

8. The display device according to claim 4, wherein: In a second frame period different from the first frame period, a third scan signal at the on level is supplied to the corresponding line of the third scan line during a first time period, and a fourth scan signal at the on level is supplied to the corresponding line of the fourth scan line during the first time period. During the first time period, the first data signal is supplied to the fourth node, and an initialization voltage is supplied to the sensing line. During the second frame period, a first scan signal at the on level is supplied to the corresponding line of the first scan line during a second time period following the first time period, and a second scan signal at the on level is supplied to the corresponding line of the second scan line during the second time period. During the second time period, the second data signal is supplied to the second node, and the initialization voltage is supplied to the sensing line.

9. The display device according to claim 8, wherein: The first data signal is a signal corresponding to the grayscale value, and The second data signal is the same as the first data signal, or it is a signal at a level that turns on the first transistor and does not correspond to the grayscale value.

10. The display device according to claim 4, wherein: The corresponding line in the second scan line is the same as the corresponding line in the fourth scan line. The second scan signal and the fourth scan signal are the same, and The second and fourth scan signals are supplied during the same time period.

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