Organic light-emitting display device and pixel circuit

Abstract

This invention relates to an organic light-emitting display device and a pixel circuit. The organic light-emitting display device includes: an organic light-emitting diode (OLED); a driving transistor configured to control the amount of current flowing from a power supply voltage line to the OLED; a compensation transistor configured to diode-connect the driving transistor in response to voltages applied to a first compensation gate electrode and a second compensation gate electrode of the compensation transistor; and a gate insulating layer between the compensation gate electrode and the compensation active region of the compensation transistor. The layer structure of the gate insulating layer between the first compensation gate electrode and the compensation active region is different from the layer structure of the gate insulating layer between the second compensation gate electrode and the compensation active region.

Description

[0001] Cross-reference to related applications

[0002] This application claims the benefit of priority to Korean Patent Application No. 10-2020-0052904, filed on April 29, 2020, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] This disclosure relates to an organic light-emitting display device and a method for manufacturing the same, and more specifically, to an organic light-emitting display device and a method for manufacturing the same capable of displaying high-quality images. Background Technology

[0004] Display devices such as flat panel displays (FPDs) are electronic devices used to view content, such as still / moving images. Compared to traditional cathode ray tube (CRT) devices, FPD devices are much lighter, thinner, and use less power. A display device includes multiple pixels, each comprising a display element and pixel circuitry for controlling the electrical signals transmitted to the display element. Pixel circuitry includes one or more transistors. However, in some cases, compensating transistors contribute to recoil voltages occurring at the gate nodes of the driving transistors, resulting in perceived image retention. Therefore, there is a need to improve the quality of images generated by display devices that include pixel circuitry. Summary of the Invention

[0005] According to an exemplary embodiment of this disclosure, an organic light-emitting display device includes an organic light-emitting diode (OLED), a driving transistor, a compensation transistor, and a gate insulating layer. The driving transistor is configured to control the amount of current flowing from a second node connected to a power supply voltage line to the OLED in response to a voltage applied to a first node connected to a driving gate electrode of the driving transistor. The compensation transistor is connected between the first node and a third node and is configured to diode-connect the driving transistor in response to a voltage applied to a first compensation gate electrode and a second compensation gate electrode of the compensation transistor disposed on the same layer. The third node is located between the driving transistor and the OLED. The gate insulating layer is located between the first and second compensation gate electrodes of the compensation transistor and a compensation active region. The layer structure of the gate insulating layer between the first compensation gate electrode and the compensation active region differs from the layer structure of the gate insulating layer between the second compensation gate electrode and the compensation active region.

[0006] The first compensation portion of the gate insulating layer between the first compensation gate electrode and the compensation active region can have a single-layer structure, and the second compensation portion of the gate insulating layer between the second compensation gate electrode and the compensation active region can have a multi-layer structure.

[0007] The organic light-emitting display device may further include a semiconductor layer, wherein a portion of the semiconductor layer including a compensation active region may be connected to a portion of the semiconductor layer including a driving active region of a driving transistor, and in the semiconductor layer, a portion corresponding to a first compensation gate electrode may be connected to a driving active region corresponding to a driving gate electrode of a driving transistor via a portion corresponding to a second compensation gate electrode.

[0008] The thickness of the first compensation part can be equal to the thickness of the second compensation part.

[0009] The second compensation portion may include a first layer and a second layer, the first layer including the materials included in the first compensation portion, and the second layer including materials different from the materials included in the first compensation portion.

[0010] The dielectric constant of the material included in the second layer can be greater than the dielectric constant of the material included in the first layer.

[0011] The second layer can be closer to the second compensation gate electrode than the first layer.

[0012] The first layer may include silicon oxide, and the second layer may include silicon nitride.

[0013] The first layer and the first compensation section can be integrated into the overall terrain.

[0014] The gate insulating layer can be inserted between the driving gate electrode of the driving transistor and the driving active region of the driving transistor, and the first portion of the gate insulating layer between the driving gate electrode and the driving active region can have a multilayer structure.

[0015] The first part and the second compensation part may each include a first layer and a second layer, the first layer including the materials included in the first compensation part, and the second layer including materials different from the materials included in the first compensation part.

[0016] The dielectric constant of the material included in the second layer can be greater than the dielectric constant of the material included in the first layer.

[0017] The second layer of the second compensation portion can be closer to the second compensation gate electrode than the first layer of the second compensation portion, and the second layer of the first portion can be closer to the driving gate electrode than the first layer of the first portion.

[0018] The first layer may include silicon oxide, and the second layer may include silicon nitride.

[0019] The first layer and the first compensation section can be integrated into the overall terrain.

[0020] The organic light-emitting display device may further include an initialization transistor connected between a first node and an initialization voltage line, the initialization transistor being configured to initialize the voltage at the driving gate electrode of a driving transistor in response to a voltage applied to the initialization gate electrode, wherein a gate insulating layer may be inserted between the initialization gate electrode of the initialization transistor and the initialization active region, and a fourth portion of the gate insulating layer between the initialization gate electrode and the initialization active region may have a multilayer structure.

[0021] The fourth part and the second compensation part may each include a first layer and a second layer, the first layer including the materials included in the first compensation part, and the second layer including materials different from the materials included in the first compensation part.

[0022] The dielectric constant of the material included in the second layer can be greater than the dielectric constant of the material included in the first layer.

[0023] The second layer of the second compensation portion can be closer to the second compensation gate electrode than the first layer of the second compensation portion, and the second layer of the first portion can be closer to the driving gate electrode than the first layer of the first portion.

[0024] The first layer may include silicon oxide, and the second layer may include silicon nitride.

[0025] The first layer and the first compensation section can be integrated into the overall terrain.

[0026] In the compensated active region, the portion overlapping with the first compensated gate electrode may have an area smaller than the area of ​​the portion overlapping with the second compensated gate electrode.

[0027] In the compensated active region, the channel length of the portion overlapping with the first compensated gate electrode can be less than the channel length of the portion overlapping with the second compensated gate electrode.

[0028] According to exemplary embodiments of the present disclosure, the pixel circuit of an organic light-emitting display device includes a driving transistor, a compensation transistor, and a gate insulating layer. The driving transistor is configured to control the amount of current flowing from a power supply voltage line to the organic light-emitting diode, the compensation transistor is configured to diode-connect the driving transistor in response to voltages applied to a first compensation gate electrode and a second compensation gate electrode of the compensation transistor, and the gate insulating layer is located between the first and second compensation gate electrodes of the compensation transistor and a compensation active region. The layer structure of the gate insulating layer between the first compensation gate electrode and the compensation active region differs from the layer structure of the gate insulating layer between the second compensation gate electrode and the compensation active region.

[0029] According to an exemplary embodiment of the present disclosure, an organic light-emitting display device includes an organic light-emitting diode (OLED), a driving transistor, a compensation transistor, and a gate insulating layer. The driving transistor is configured to control the amount of current flowing from a power supply voltage line to the OLED. The compensation transistor is configured to diode-connect the driving transistor in response to voltages applied to a first compensation gate electrode and a second compensation gate electrode of the compensation transistor. The gate insulating layer is located between the first and second compensation gate electrodes of the compensation transistor and a compensation active region. A first compensation portion of the gate insulating layer between the first compensation gate electrode and the compensation active region has a monolayer structure, and a second compensation portion of the gate insulating layer between the second compensation gate electrode and the compensation active region has a multilayer structure. Attached Figure Description

[0030] The above and other aspects, features and elements of certain embodiments of this disclosure will become more apparent from the following description taken in conjunction with the accompanying drawings, in which:

[0031] Figure 1 This is a conceptual diagram illustrating a display device according to an exemplary embodiment of the present disclosure;

[0032] Figure 2 This illustrates exemplary embodiments according to this disclosure. Figure 1 The equivalent circuit diagram of the pixels included in the display device;

[0033] Figure 3 This illustrates exemplary embodiments according to this disclosure. Figure 2 The layout of the positions of thin-film transistors and capacitors in the pixels;

[0034] Figure 4 This illustrates exemplary embodiments according to this disclosure. Figure 3 The layout of the semiconductor layer;

[0035] Figure 5 This illustrates exemplary embodiments according to this disclosure. Figure 3 A partial cross-sectional view;

[0036] Figure 6 This is a cross-sectional view showing a portion of a display device according to an exemplary embodiment of the present disclosure;

[0037] Figure 7 This is a cross-sectional view showing a portion of a display device according to an exemplary embodiment of the present disclosure;

[0038] Figure 8 This is a cross-sectional view showing a portion of a display device according to an exemplary embodiment of the present disclosure;

[0039] Figure 9 This is a cross-sectional view showing a portion of a display device according to an exemplary embodiment of the present disclosure; and

[0040] Figure 10 This is a layout showing the positions of thin-film transistors and capacitors in pixels of a display device according to an exemplary embodiment of the present disclosure. Detailed Implementation

[0041] Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. Throughout the drawings and description, the same reference numerals refer to the same elements. In this respect, the invention may take different forms and is not necessarily to be construed as limited to the description set forth herein. Therefore, several embodiments are described below with reference to the accompanying drawings to illustrate aspects of this description. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. Throughout this disclosure, the expression “at least one of a, b, and c” means only a, only b, only c, both a and b, both a and c, both b and c, all of a, b, and c, or variations thereof.

[0042] Because this disclosure allows for various modifications and numerous embodiments, certain embodiments will be illustrated in the accompanying drawings and described in detail in the written specification. Reference is made to the accompanying drawings, which illustrate one or more embodiments, to aid the reader in understanding this disclosure, its advantages, and the objectives achieved by implementing this disclosure. However, this disclosure may be implemented in many different forms and is not necessarily limited to the exemplary embodiments set forth herein.

[0043] It will be understood that when an element such as a layer, film, region, or substrate is referred to as being placed "on" another element, it may be placed directly on the other element, or an intermediate layer may be present. For ease of illustration, the dimensions of the components in the figures may be exaggerated. In other words, since the dimensions and thicknesses of the components in the figures are shown for ease of illustration, the following embodiments are not necessarily limited thereto.

[0044] The x-axis, y-axis, and z-axis are not limited to the three axes of a rectangular coordinate system, but can be interpreted in a general sense. For example, the x-axis, y-axis, and z-axis can be perpendicular to each other, or they can represent different directions that are not perpendicular to each other.

[0045] Figure 1 This is a conceptual diagram illustrating a display device 1 according to an exemplary embodiment of the present disclosure.

[0046] The display device 1 according to the embodiment can be implemented as an electronic device such as a smartphone, mobile phone, navigation device, game console, television, vehicle head unit, laptop computer, tablet computer, personal media player (PMP), personal digital assistant (PDA), etc. Moreover, the electronic device can be a flexible device.

[0047] like Figure 1As shown, the display device 1 according to an embodiment has a display area DA and a peripheral area PA. The peripheral area PA may surround the display area DA. In an embodiment, the display area DA includes pixels for displaying images, and the peripheral area PA does not include pixels. The display device 1 may include a substrate 101 (see...). Figure 5 Furthermore, the substrate 101 is not limited to, for example, Figure 1 The rectangular shape shown (in the xy plane) can be replaced by various shapes such as a circle. Furthermore, the substrate 101 can have a curved region that is to bend at the curved area. For example, the display device 1 can be flexible.

[0048] The substrate 101 may include glass or metal. Furthermore, the substrate 101 may include various flexible or bendable materials. For example, the substrate 101 may include polymeric resins such as polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, or cellulose acetate propionate.

[0049] In an exemplary embodiment, substrate 101 has a multilayer structure comprising two layers containing a polymer resin and a barrier layer containing an inorganic material between the two layers. For example, the barrier layer may comprise silicon oxide, silicon nitride, and / or silicon oxynitride.

[0050] Multiple display elements can be present in the display area DA. For example, the display elements may include organic light-emitting diodes (OLEDs) (see [link]). Figure 2 It can emit red, green, blue or white light. Figure 1 The sub-pixels in the display area DA of the display device 1 shown include organic light-emitting diodes, and also include thin-film transistors and capacitors for controlling the light intensity of the organic light-emitting diodes.

[0051] Drivers and lines (or wiring) such as power supply voltage lines can be arranged in the peripheral area PA. Furthermore, the peripheral area PA may include pad areas to which various electronic devices, such as driver integrated circuits (ICs) or printed circuit boards, are electrically bonded. The pad areas may include pads (e.g., conductive elements). Various wiring, printed circuit boards, or driver ICs used to transmit electrical signals to the display area DA can be attached to the pads.

[0052] Figure 2 This illustrates exemplary embodiments according to this disclosure. Figure 1 The equivalent circuit diagram of a (sub)pixel in the display area DA of the display device 1. A (sub)pixel can refer to a pixel or a sub-pixel.

[0053] refer to Figure 2The (sub)pixel SPX includes an organic light-emitting diode (OLED) as a display element and a pixel circuit PC (or pixel circuit portion) connected to the OLED. The pixel circuit PC may include multiple thin-film transistors T1 to T7 and a storage capacitor Cst. Depending on the transistor type (p-type or n-type) and / or operating conditions, the first terminal of each of the first thin-film transistors T1 to the seventh thin-film transistor T7 may be a source terminal or a drain terminal, and its second terminal may be different from the first terminal. For example, when the first terminal is a source terminal, the second terminal may be a drain terminal. In embodiments, the first thin-film transistors T1 to the seventh thin-film transistor T7 may be implemented by a P-channel multi-oxide-semiconductor field-effect transistor (MOSFET) or a P-channel metal-oxide-semiconductor (PMOS) transistor.

[0054] The first thin-film transistor T1 can be referred to as a driving transistor or a driving thin-film transistor. The second thin-film transistor T2 can be referred to as a switching transistor or a switching thin-film transistor. The third thin-film transistor T3 can be referred to as a compensation transistor or a compensation thin-film transistor. The fourth thin-film transistor T4 can be referred to as a first initialization transistor or a first initialization thin-film transistor. The fifth thin-film transistor T5 can be referred to as an operation control transistor or an operation control thin-film transistor. The sixth thin-film transistor T6 can be referred to as an emitter control transistor or an emitter control thin-film transistor. The seventh thin-film transistor T7 can be referred to as a second initialization transistor or a second initialization thin-film transistor.

[0055] Thin-film transistors T1 to T7 and storage capacitor Cst can be connected to signal lines SL, SL-1, SL+1, EL and DL, first initialization voltage line VL1, second initialization voltage line VL2 and power supply voltage line PL.

[0056] Signal lines SL, SL-1, SL+1, EL, and DL may include a scan line SL configured to transmit a scan signal Sn, a previous scan line SL-1 configured to transmit a previous scan signal Sn-1 to a first initialization thin-film transistor T4, a next scan line SL+1 configured to transmit a scan signal Sn to a second initialization thin-film transistor T7, an emitter control line EL configured to transmit an emitter control signal En to an operation control thin-film transistor T5 and an emitter control thin-film transistor T6, and a data line DL intersecting (or crossing) the scan line SL and configured to transmit a data signal Dm. A power supply voltage line PL may be configured to transmit a drive voltage ELVDD to a drive thin-film transistor T1. A first initialization voltage line VL1 may be configured to transmit an initialization voltage Vint to a first initialization thin-film transistor T4. A second initialization voltage line VL2 may be configured to transmit an initialization voltage Vint to a second initialization thin-film transistor T7. (The text repeats itself here.) Figure 2 and Figure 3As shown, the first initialization voltage line VL1 and the second initialization voltage line VL2 can be represented by the same wiring, i.e., the initialization voltage line VL. Specifically, Figure 3 The layout of pixels in row n is shown, and the first initialization voltage line VL1 in row n can be the second initialization voltage line VL2 in row n-1.

[0057] The driving gate electrode G1 of the driving thin-film transistor T1 is connected to the lower electrode CE1 of the storage capacitor Cst. The driving source region S1 of the driving thin-film transistor T1 is connected to the power supply voltage line PL via the operation control thin-film transistor T5. The driving drain region D1 of the driving thin-film transistor T1 is electrically connected to the pixel electrode of the organic light-emitting diode (OLED) via the emitter control thin-film transistor T6. That is, in response to the voltage applied to the first node N1 (e.g., the voltage applied to the driving gate electrode G1), the driving thin-film transistor T1 can control the amount of current flowing from the second node N2 connected to the power supply voltage line PL to the OLED. Therefore, the driving thin-film transistor T1 receives the data signal Dm according to the switching operation of the switching thin-film transistor T2 to drive the current I... OLED It is supplied to the organic light-emitting diode (OLED). The operation control thin-film transistor T5 can be inserted between the second node N2 and the power supply voltage line PL.

[0058] The switching gate electrode G2 of the switching thin-film transistor T2 is connected to the scan line SL. The switching source region S2 of the switching thin-film transistor T2 is connected to the data line DL. The switching drain region D2 of the switching thin-film transistor T2 is connected to the second node N2, and thus to the driving source region S1 of the driving thin-film transistor T1, and is also connected to the power supply voltage line PL via the operation control thin-film transistor T5. The switching thin-film transistor T2 is turned on according to the scan signal Sn received through the scan line SL, and performs a switching operation to transmit the data signal Dm transmitted through the data line DL to the driving source region S1 of the driving thin-film transistor T1.

[0059] The compensation thin-film transistor T3 is connected between the third node N3 and the first node N1, and can diode-connect the driving thin-film transistor T1 in response to the voltage applied to the compensation gate electrode G3 of the compensation thin-film transistor T3. The third node N3 is the location between the driving thin-film transistor T1 and the organic light-emitting diode (OLED). That is, the compensation gate electrode G3 of the compensation thin-film transistor T3 is connected to the scan line SL, the compensation drain region D3 of the compensation thin-film transistor T3 is connected to the pixel electrode of the OLED via the emission control thin-film transistor T6, and is also connected to the driving drain region D1 of the driving thin-film transistor T1, and the compensation source region S3 of the compensation thin-film transistor T3 is connected to the lower electrode CE1 of the storage capacitor Cst, the first initialization drain region D4 of the first initialization thin-film transistor T4, and the driving gate electrode G1 of the driving thin-film transistor T1.

[0060] The compensation thin-film transistor T3 is turned on according to the scan signal Sn received through the scan line SL, so as to electrically connect the driving gate electrode G1 and the driving drain region D1 of the driving thin-film transistor T1 to each other and to diode-connect the driving thin-film transistor T1. The compensation thin-film transistor T3 has dual gate electrodes. That is, the compensation gate electrode G3 of the compensation thin-film transistor T3 has a first compensation gate electrode G3-1 (see...). Figure 3 ) and the second compensation gate electrode G3-2 (see Figure 3 ).

[0061] The first initialization thin-film transistor T4 is connected between the first node N1 and the first initialization voltage line VL1 to initialize the voltage at the drive gate electrode G1 in response to the voltage applied to the first initialization gate electrode G4 of the first initialization thin-film transistor T4. Specifically, the first initialization gate electrode G4 of the first initialization thin-film transistor T4 is connected to the previous scan line SL-1, the first initialization source region S4 of the first initialization thin-film transistor T4 is connected to the first initialization voltage line VL1, and the first initialization drain region D4 of the first initialization thin-film transistor T4 is connected to the lower electrode CE1 of the storage capacitor Cst, the compensation source region S3 of the compensation thin-film transistor T3, and the drive gate electrode G1 of the drive thin-film transistor T1. The first initialization thin-film transistor T4 is turned on according to the previous scan signal Sn-1 transmitted through the previous scan line SL-1 to transmit the initialization voltage Vint to the drive gate electrode G1 of the drive thin-film transistor T1 and perform an initialization operation to initialize the voltage at the drive gate electrode G1 of the drive thin-film transistor T1.

[0062] The operation control thin-film transistor T5 is connected between the second node N2 and the power supply voltage line PL, and can be turned on in response to the voltage applied to the operation control gate electrode G5 of the operation control thin-film transistor T5. That is, the operation control gate electrode G5 of the operation control thin-film transistor T5 is connected to the emitter control line EL, the operation source region S5 of the operation control thin-film transistor T5 is connected to the power supply voltage line PL, and the operation control drain region D5 of the operation control thin-film transistor T5 is connected to the drive source region S1 of the driving thin-film transistor T1 and the switch drain region D2 of the switching thin-film transistor T2.

[0063] The emission control thin-film transistor T6 is connected between the third node N3 and the organic light-emitting diode (OLED), and can be turned on in response to the voltage applied from the emission control line EL to the emission control gate electrode G6 of the emission control thin-film transistor T6. That is, the emission control gate electrode G6 of the emission control thin-film transistor T6 is connected to the emission control line EL, the emission control source region S6 of the emission control thin-film transistor T6 is connected to the driving drain region D1 of the driving thin-film transistor T1 and the compensation drain region D3 of the compensation thin-film transistor T3, and the emission control drain region D6 of the emission control thin-film transistor T6 is connected to the second initialization source region S7 of the second initialization thin-film transistor T7 and the pixel electrode of the organic light-emitting diode (OLED).

[0064] The operation control thin-film transistor T5 and the emission control thin-film transistor T6 are simultaneously turned on (or turned on during the same time period) according to the emission control signal En transmitted through the emission control line EL, so as to transmit the driving voltage ELVDD to the organic light-emitting diode OLED and allow the driving current I OLED It flows within an organic light-emitting diode (OLED).

[0065] The second initialization gate electrode G7 of the second initialization thin-film transistor T7 is connected to the next scan line SL+1. The second initialization source region S7 of the second initialization thin-film transistor T7 is connected to the emission control drain region D6 of the emission control thin-film transistor T6 and the pixel electrode of the organic light-emitting diode OLED, and the second initialization drain region D7 of the second initialization thin-film transistor T7 is connected to the second initialization voltage line VL2.

[0066] In an embodiment where scan line SL and the next scan line SL+1 are electrically connected to each other, the same scan signal Sn is applied to both scan line SL and the next scan line SL+1. Therefore, the second initialization thin-film transistor T7 is turned on according to the scan signal Sn transmitted through the next scan line SL+1, and performs the operation of initializing the pixel electrodes of the organic light-emitting diode (OLED). In an exemplary embodiment, the second initialization thin-film transistor T7 is omitted.

[0067] The upper electrode CE2 of the storage capacitor Cst is connected to the power supply voltage line PL, and the common electrode of the organic light-emitting diode (OLED) is connected to the common voltage ELVSS. Therefore, the OLED receives a driving current I from the driving thin-film transistor T1. OLED It emits light to display images.

[0068] although Figure 2 The diagram shows a compensation thin-film transistor T3 with dual gate electrodes and a first initialization thin-film transistor T4, but in other embodiments, the compensation thin-film transistor T3 and the first initialization thin-film transistor T4 may have a single gate electrode.

[0069] Figure 3 This illustrates exemplary embodiments according to this disclosure. Figure 2 A schematic layout diagram showing the positions of multiple thin-film transistors and capacitors in a (sub)pixel. Figure 4 yes Figure 3 A schematic layout diagram of the semiconductor layer 1130 as part of the display device. Figure 5 It is intercepted along lines A-A', B-B', C-C', and D-D'. Figure 3 This is a partial cross-sectional view. For ease of description, the dimensions of each element in the cross-sectional view have been exaggerated and / or reduced. This also applies to the cross-sectional views that will be described later.

[0070] Driving thin-film transistor T1, switching thin-film transistor T2, compensation thin-film transistor T3, first initialization thin-film transistor T4, operation control thin-film transistor T5, emission control thin-film transistor T6, and second initialization thin-film transistor T7 are arranged along semiconductor layer 1130. Some regions in semiconductor layer 1130 correspond to the semiconductor layers of driving thin-film transistor T1, switching thin-film transistor T2, compensation thin-film transistor T3, first initialization thin-film transistor T4, operation control thin-film transistor T5, emission control thin-film transistor T6, and second initialization thin-film transistor T7. That is, some regions of semiconductor layer 1130 may correspond to the active region, source region, or drain region of the thin-film transistor.

[0071] Semiconductor layer 1130 may be on substrate 101. Buffer layer 111 may be on substrate 101, and semiconductor layer 1130 may be on buffer layer 111.

[0072] Buffer layer 111 can reduce or prevent impurities, moisture, or external air from penetrating from beneath substrate 101 and can provide a planarized surface on substrate 101. Buffer layer 111 can comprise inorganic materials, organic materials, or inorganic-organic composite materials such as oxide or nitride materials, and can have a single-layer or multi-layer structure comprising inorganic and organic materials. For example, buffer layer 111 can comprise a stacked structure including a first buffer layer 111a and a second buffer layer 111b, and the first buffer layer 111a and the second buffer layer 111b can comprise materials different from each other. For example, the first buffer layer 111a can comprise silicon nitride, and the second buffer layer 111b can comprise silicon oxide.

[0073] As described above, in embodiments where the first buffer layer 111a comprises silicon nitride, the silicon nitride material includes hydrogen. This improves the carrier mobility of the semiconductor layer 1130 on the buffer layer 111 and enhances the electrical characteristics of the thin-film transistor. Furthermore, the semiconductor layer 1130 may comprise silicon, and in this case, the interfacial bonding characteristics between the silicon-complementing semiconductor layer 1130 and the second buffer layer 111b comprising silicon oxide can be improved, thereby enhancing the electrical characteristics of the thin-film transistor.

[0074] Semiconductor layer 1130 may include low-temperature polycrystalline silicon (LTPS). Polycrystalline silicon material has high electron mobility (100 cm⁻¹). 2 ( / Vs or greater), and therefore has low power consumption and excellent reliability. In another example, semiconductor layer 1130 may include amorphous silicon (a-Si) and / or oxide semiconductor. Alternatively, some of the semiconductor layers in the plurality of thin-film transistors may include LTPS, and some other semiconductor layers may include amorphous silicon (a-Si) and / or oxide semiconductor.

[0075] The source and drain regions of semiconductor layer 1130 may be doped with impurities, and these impurities may include n-type or p-type impurities. The source and drain regions may correspond to the source electrode and drain electrode, respectively. Depending on the nature of the thin-film transistor, the source and drain regions may be interchanged. In the following text, the terms "source region" and "drain region" are used instead of source electrode and drain electrode. Figure 2 In the equivalent circuit diagram, certain portions of the semiconductor layer 1130 are doped with p-type impurities, enabling the thin-film transistor to be implemented as a P-channel multi-oxide-semiconductor field-effect transistor (MOSFET) or a P-channel metal-oxide-semiconductor (PMOS) transistor. Other regions of the semiconductor layer 1130 may also be doped with impurities to serve as wiring for electrically connecting the thin-film transistors and / or capacitors to each other.

[0076] The first gate insulating layer 112 is on the semiconductor layer 1130, and the driving gate electrode G1, scan line SL, previous scan line SL-1, next scan line SL+1, and emitter control line EL can be on the first gate insulating layer 112. The detailed structure of the first gate insulating layer 112 will be described later.

[0077] In scan line SL, the regions overlapping with the second active region A2 (e.g., the switching active region) of the switching thin-film transistor T2 and the third active region A3 (e.g., the compensation active region) of the compensation thin-film transistor T3 can correspond to the switching gate electrode G2 and the compensation gate electrode G3, respectively. In the previous scan line SL-1, the region overlapping with the fourth active region A4 (e.g., the first initialization active region) of the first initialization thin-film transistor T4 can correspond to the first initialization gate electrode G4. In the next scan line SL+1, the region overlapping with the seventh active region A7 (e.g., the second initialization active region) of the second initialization thin-film transistor T7 can correspond to the second initialization gate electrode G7. In the emitter control line EL, the regions overlapping with the fifth active region A5 (e.g., the operation control active region) of the operation control thin-film transistor T5 and the sixth active region A6 (e.g., the emitter control active region) of the emitter control thin-film transistor T6 can correspond to the operation control gate electrode G5 and the emitter control gate electrode G6, respectively. The semiconductor layer 1130 may further include an active region A3a between a pair of third active regions A3 and an active region A4a between a pair of fourth active regions A4.

[0078] The driving gate electrode G1, scan line SL, previous scan line SL-1, next scan line SL+1, and emission control line EL may comprise a conductive material containing molybdenum (Mo), aluminum (Al), copper (Cu), or titanium (Ti), and may have a single-layer or multi-layer structure comprising the aforementioned materials. As an example, the driving gate electrode G1, scan line SL, previous scan line SL-1, next scan line SL+1, and emission control line EL may have a multi-layer structure comprising Mo / Al or Mo / Al / Mo.

[0079] The second gate insulating layer 113 may be located on the driving gate electrode G1, the scan line SL, the previous scan line SL-1, the next scan line SL+1, and the emission control line EL. The second gate insulating layer 113 may include silicon oxide (SiO2) or silicon nitride (SiN). x ), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2) or zinc oxide (ZnO2).

[0080] Electrode voltage line HL, first initialization voltage line VL1, and second initialization voltage line VL2 may be on the second gate insulating layer 113. Electrode voltage line HL covers at least a portion of the drive gate electrode G1 and may form a storage capacitor Cst together with the drive gate electrode G1. In an exemplary embodiment, electrode voltage line HL completely covers the drive gate electrode G1.

[0081] The lower electrode CE1 of the storage capacitor Cst and the driving gate electrode G1 of the driving thin-film transistor T1 can be integrally formed. For example, the driving gate electrode G1 of the driving thin-film transistor T1 can be used as the lower electrode CE1 of the storage capacitor Cst. In the electrode voltage line HL, the region overlapping with the driving gate electrode G1 can be used as the upper electrode CE2 of the storage capacitor Cst. Therefore, the second gate insulating layer 113 can be used as the dielectric layer of the storage capacitor Cst.

[0082] The electrode voltage line HL, the first initialization voltage line VL1, and the second initialization voltage line VL2 may comprise a conductive material containing molybdenum (Mo), aluminum (Al), copper (Cu), or titanium (Ti), and may have a single-layer or multi-layer structure comprising the aforementioned materials. As an example, the electrode voltage line HL, the first initialization voltage line VL1, and the second initialization voltage line VL2 may each have a multi-layer structure comprising Mo / Al or Mo / Al / Mo.

[0083] Interlayer insulating layer 115 is located on electrode voltage line HL, first initialization voltage line VL1, and second initialization voltage line VL2. Interlayer insulating layer 115 may include silicon oxide (SiO2) or silicon nitride (SiN). x ), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2) or zinc oxide (ZnO2).

[0084] The data line DL, power supply line PL, first initialization connection line 1173a, second initialization connection line 1173b, node connection line 1174, and contact metal 1175 may be on the interlayer insulation layer 115. The data line DL, power supply line PL, node connection line 1174, and contact metal 1175 may each comprise a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and may have a single-layer or multi-layer structure comprising the aforementioned materials. As an example, the data line DL, power supply line PL, node connection line 1174, and contact metal 1175 may each have a multi-layer structure comprising Ti / Al / Ti.

[0085] The data line DL can be connected to the switching source region S2 of the switching thin-film transistor T2 via contact hole 1154. A portion of the data line DL can correspond to the switching source region S2.

[0086] The power supply voltage line PL can be connected to the upper electrode CE2 of capacitor Cst via contact hole 1158 in interlayer insulation layer 115. Therefore, the electrode voltage line HL can have the same voltage level (constant voltage) as the power supply voltage line PL. Moreover, the power supply voltage line PL can be connected to the operation control drain area D5 via contact hole 1155.

[0087] The first initialization voltage line VL1 is connected to the first initialization thin-film transistor T4 via the first initialization connection line 1173a, and the second initialization voltage line VL2 can be connected to the second initialization thin-film transistor T7 via the second initialization connection line 1173b and contact holes 1151 and 1152. Furthermore, the first initialization voltage line VL1 and the second initialization voltage line VL2 can have the same contact voltage (e.g., -2V, etc.).

[0088] In an exemplary embodiment, one end of the node connection line 1174 is connected to the compensation source region S3 via the contact hole 1156, and the opposite end of the node connection line 1174 is connected to the drive gate electrode G1 via the contact hole 1157.

[0089] Contact metal 1175 is connected to the emission control drain region D6 of the emission control thin-film transistor T6 via contact hole 1153 passing through interlayer insulating layer 115, second gate insulating layer 113, and first gate insulating layer 112. Contact metal 1175 is connected to the pixel electrode 210 of the organic light-emitting diode OLED via contact hole 1163. Therefore, the emission control thin-film transistor T6 can be electrically connected to the pixel electrode 210 of the organic light-emitting diode OLED.

[0090] The planarization layer 117 is located on the data line DL, the power supply voltage line PL, the first initialization connection line 1173a and the second initialization connection line 1173b, the node connection line 1174, and the contact metal 1175. Organic light-emitting diodes (OLEDs) can be disposed on the planarization layer 117.

[0091] although Figure 2 A pixel circuit PC is shown and Figure 3 The structure of a (sub)pixel SPX is shown, but multiple sub-pixel SPXs with the same pixel circuit PC can be arranged in the first direction (x-axis direction) and the second direction (y-axis direction). Multiple sub-pixel SPXs can share lines. For example, the first initialization voltage line VL1, the previous scan line SL-1, the second initialization voltage line VL2, and the next scan line SL+1 can be shared by two pixel circuit PCs that are adjacent to each other in the second direction (y-axis direction).

[0092] That is, the first initialization voltage line VL1 and the previous scan line SL-1 can be electrically connected in the second direction (y-axis direction) in the attached figure, and in the +y direction... Figure 3 The second initialization thin-film transistor of another pixel circuit PC is located above the pixel circuit PC. Therefore, the previous scan signal applied to the previous scan line SL-1 can be transmitted as the next scan signal to the second initialization thin-film transistor of the other pixel circuit PC. Similarly, the second initialization voltage line VL2 and the next scan line SL+1 can be electrically connected in the second direction (y-axis direction) based on the attached figure, and in the -y direction with... Figure 3 The first initialization thin-film transistor of the pixel circuit PC adjacent to the pixel circuit PC can thus transmit the previous scan signal and initialization voltage to the first initialization thin-film transistor of the other pixel circuit PC.

[0093] Return to reference Figure 5 The planarization layer 117 may have a flat upper surface to planarize the pixel electrode 210. The planarization layer 117 may include organic materials and may have a single-layer or multi-layer structure. The planarization layer 117 may include general-purpose polymers (benzocyclobutene (BCB), polyimide, hexamethyldisiloxane (HMDSO), polymethyl methacrylate (PMMA), or polystyrene (PS)), phenolic polymer derivatives, acrylic polymers, imide polymers, aryl ether polymers, amide polymers, fluoride polymers, p-xylene polymers, vinyl alcohol polymers, or mixtures thereof. In an exemplary embodiment, the planarization layer 117 includes inorganic materials. The planarization layer 117 may include silicon oxide (SiO2), silicon nitride (SiN2), etc. x The materials used may include silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc oxide (ZnO2). When the planarization layer 117 comprises an inorganic material, chemical planarization polishing may be performed in some embodiments. Alternatively, the planarization layer 117 may comprise both organic and inorganic materials.

[0094] An organic light-emitting diode (OLED) may include a pixel electrode 210, a common electrode 230, and an intermediate layer 220 between the pixel electrode 210 and the common electrode 230, which includes an emission layer.

[0095] Pixel electrode 210 can be connected to contact metal 1175 via contact hole 1163, and contact metal 1175 can be connected to emission control drain region D6 via contact hole 1153. Pixel electrode 210 may include a (semi-)transmissive electrode or a reflective electrode. In some embodiments, pixel electrode 210 may include a reflective layer comprising Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr and compounds thereof, and a transparent or semi-transparent electrode layer on the reflective layer. The transparent or semi-transparent electrode layer may include at least one electrode material selected from the group consisting of indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO2), indium oxide (In2O3), indium gallium oxide, and aluminum zinc oxide (AZO). In some embodiments, pixel electrode 210 may include a stacked structure comprising ITO / Ag / ITO.

[0096] A pixel defining layer 119 may be disposed on the planarization layer 117, and the pixel defining layer 119 includes an opening that exposes the central portion of the pixel electrode 210 to define the light-emitting area of ​​the pixel. Furthermore, the pixel defining layer 119 can prevent arcing at the edge of the pixel electrode 210 by increasing the distance between the edge of the pixel electrode 210 and the common electrode 230 on the pixel electrode 210. The pixel defining layer 119 may comprise an organic insulating material, such as polyimide, polyamide, acrylic resin, benzocyclobutene, hexamethyldisiloxane (HMDSO), and phenolic resin, and can be obtained by spin coating.

[0097] Intermediate layer 220 may include an organic light-emitting layer. The organic light-emitting layer may include organic materials, including fluorescent or phosphorescent materials that emit red, green, blue, or white light. The organic light-emitting layer may include low molecular weight organic materials or polymeric organic materials, and functional layers such as hole transport layer (HTL), hole injection layer (HIL), electron transport layer (ETL), and electron injection layer (EIL) may be selectively arranged below and above the organic light-emitting layer. Intermediate layer 220 may correspond to each of the plurality of pixel electrodes 210. However, embodiments of this disclosure are not limited thereto, and the layers such as HTL, HIL, ETL, or EIL included in intermediate layer 220 may be integrally formed on the plurality of pixel electrodes 210.

[0098] The common electrode 230 may include a transmissive electrode or a reflective electrode. In embodiments, the common electrode 230 may include a transparent electrode or a translucent electrode, and may include a metal thin film containing Li, Ca, LiF, Al, Ag, Mg, or compounds thereof, having a low work function. Furthermore, in addition to the metal thin film, a transparent conductive oxide (TCO) layer comprising ITO, IZO, ZnO2, or In2O3 may be further provided. The common electrode 230 may be integrally formed to correspond to a plurality of pixel electrodes 210.

[0099] The encapsulation layer 300 can be on the common electrode 230, wherein the encapsulation layer 300 includes a first inorganic encapsulation layer 310, a second inorganic encapsulation layer 320, and an organic encapsulation layer 330 between the first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 320.

[0100] The first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 320 may each include silicon oxide (SiO2) and silicon nitride (SiN). x The organic encapsulation layer 330 may include polyethylene terephthalate (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc oxide (ZnO2). The organic encapsulation layer 330 may include polyethylene terephthalate, polyethylene naphthalate, polycarbonate, polyimide, polyethylene sulfonate, polyoxymethylene, polyarylate, hexamethyldisiloxane, acrylic resins (e.g., polymethyl methacrylate, polyacrylic acid, etc.), or combinations thereof.

[0101] As described above, the first gate insulating layer 112 is on the semiconductor layer 1130, and the driving gate electrode G1, scan line SL, previous scan line SL-1, next scan line SL+1, and emission control line EL can be on the first gate insulating layer 112. As described above, the scan line SL, previous scan line SL-1, next scan line SL+1, and emission control line EL include a switching gate electrode G2, a compensation gate electrode G3, a first initialization gate electrode G4, an operation control gate electrode G5, an emission control gate electrode G6, and a second initialization gate electrode G7. Therefore, the first gate insulating layer 112 is inserted between the driving gate electrode G1, the switching gate electrode G2, the compensation gate electrode G3, the first initialization gate electrode G4, the operation control gate electrode G5, the emission control gate electrode G6, and the second initialization gate electrode G7 and the semiconductor layer 1130.

[0102] In an organic light-emitting display device according to an exemplary embodiment of the present disclosure, a first gate insulating layer 112 is located between the first compensation gate electrode G3-1 and the second compensation gate electrode G3-2 of the compensation thin-film transistor T3 and the third active region A3 (e.g., the compensation active region). Here, the layer structure of the first gate insulating layer 112 between the first compensation gate electrode G3-1 and the third active region A3 is different from the layer structure of the first gate insulating layer 112 between the second compensation gate electrode G3-2 and the third active region A3.

[0103] As referenced above Figure 2 The driving thin-film transistor T1 receives the data signal Dm according to the switching operation of the switching thin-film transistor T2, and transmits the driving current I... OLED The power supply is provided to the organic light-emitting diode (OLED). Specifically, the voltage between the driving gate electrode G1 and the driving source region S1 in the driving thin-film transistor T1 determines the driving current I flowing in the OLED. OLED Here, when the threshold voltage V of the driving thin-film transistor T1 in multiple pixels... th Even when the same data signal Dm is applied to multiple pixels, the driving current I flowing through the organic light-emitting diode OLED will differ from each other. OLED The sizes are also different. Even when the same data signal Dm is applied to those pixels, the driving current I flowing through the organic light-emitting diode (OLED) is different. OLED When the sizes of the images are different, the display device may not be able to display high-quality images.

[0104] Compensating thin-film transistor T3 can be connected to each of the driving thin-film transistors T1 to prevent the driving thin-film transistors T1 from being subjected to a threshold voltage V. th The effect of this. Therefore, even when the threshold voltage V of the driving thin-film transistor T1 in multiple pixels... th When the same data signal Dm is applied to multiple pixels, the driving current I flowing in the organic light-emitting diode OLED is different from each other. OLED Their sizes can also be almost equal to each other.

[0105] The threshold voltage V is compensated by the voltage difference between the driving gate electrode G1 and the driving source region S1 of the driving thin-film transistor T1. th Afterwards, the compensation thin-film transistor T3 is completely turned off. However, because a parasitic capacitance is generated between the compensation gate electrode G3 and the third active region A3 of the compensation thin-film transistor T3, a voltage change occurs at the driving gate electrode G1 of the driving thin-film transistor T1 due to the change in charge caused by the parasitic capacitance. Therefore, a backlash phenomenon may occur in the display device. The backlash phenomenon refers to the flickering phenomenon of the display screen or the phenomenon of afterimages remaining on the screen.

[0106] To address the aforementioned problems, it is necessary to reduce the parasitic capacitance at the compensation thin-film transistor T3. In an exemplary embodiment of this disclosure, the thickness of the first gate insulating layer 112 is increased to reduce the parasitic capacitance. When the thickness of the first gate insulating layer 112 increases, the distance between the compensation gate electrode G3 and the third active region A3 increases, and thus the parasitic capacitance between them can be reduced. However, when the thickness of the first gate insulating layer 112 increases between the compensation gate electrode G3 and the third active region A3, the sensitivity of the compensation thin-film transistor T3 may decrease. That is, when a preset electrical signal is applied to the compensation gate electrode G3, the on and off states at the compensation thin-film transistor T3 may not be executed at the precise time. Moreover, it may not be easy to finely control the change in current flowing between the compensation source region S3 and the compensation drain region D3 by adjusting the electrical signal applied to the compensation gate electrode G3.

[0107] However, in the organic light-emitting display device according to an exemplary embodiment of the present disclosure, the layer structure of the first gate insulating layer 112 between the first compensation gate electrode G3-1 and the third active region A3 is different from the layer structure of the first gate insulating layer 112 between the second compensation gate electrode G3-2 and the third active region A3. Therefore, the sensitivity of the compensation thin-film transistor T3 can be improved while preventing or reducing backlash.

[0108] In an exemplary embodiment of this disclosure, the first gate insulating layer 112 has a single-layer structure in the first compensation portion between the first compensation gate electrode G3-1 and the third active region A3, and the first gate insulating layer 112 has a multilayer structure in the second gate compensation portion between the second compensation gate electrode G3-2 and the third active region A3. In an exemplary embodiment of this disclosure, the second gate compensation portion includes a first layer 1121 and a second layer 1122. The first layer 1121 includes the same material as the first compensation portion, and the second layer 1122 includes a material different from the material of the first compensation portion. In an exemplary embodiment of this disclosure, the material included in the second layer 1122 has a dielectric constant greater than that of the material included in the first layer 1121. For example, the first layer 1121 may include silicon oxide, and the second layer 1122 may include silicon nitride. Silicon oxide has a dielectric constant of approximately 3.7, and silicon nitride has a dielectric constant of approximately 7.5.

[0109] In the organic light-emitting display device according to an exemplary embodiment, the thickness of the first gate insulating layer 112 between the first compensation gate electrode G3-1 and the third active region A3 is increased, thereby reducing the parasitic capacitance between the first compensation gate electrode G3-1 and the third active region A3 and preventing or reducing the occurrence of backlash. Furthermore, the first gate insulating layer 112 between the second compensation gate electrode G3-2 and the third active region A3 includes a second layer 1122 having a high dielectric constant, and therefore, even when the thickness of the first gate insulating layer 112 increases, the compensation thin-film transistor T3 can respond more quickly to the electrical signal applied to the compensation gate electrode G3.

[0110] like Figure 2 and Figure 3 As shown, the semiconductor layer 1130 including the third active region A3 is connected to the semiconductor layer 1130 including the first active region A1 of the driving thin-film transistor T1. Furthermore, in the semiconductor layer 1130, the portion corresponding to the first compensation gate electrode G3-1 passes through the portion corresponding to the second compensation gate electrode G3-2 and connects to the portion corresponding to the driving gate electrode G1 (e.g., the first active region A1). This improves the parasitic capacitance between the first compensation gate electrode G3-1 and the third active region A3 of the compensation thin-film transistor T3. Parasitic capacitance can directly affect the voltage at the driving gate electrode G1 of the driving thin-film transistor T1.

[0111] The first gate insulating layer 112 can be formed by various methods. For example, the first layer 1121 can be formed using silicon oxide. Then, at least partially, the upper portion of the first layer 1121 is removed from the portion where the second compensation gate electrode G3-2 is to be formed. The removal of the upper portion can be performed by forming a photoresist layer on the first layer 1121, removing the photoresist layer from the portion where the second layer 1122 is to be formed, and performing a dry etching process. Then, a second layer 1122 comprising silicon nitride can be formed at the portion where the first layer 1121 was partially removed. The second layer 1122 can be formed by chemical vapor deposition (CVD) while the portions of the first layer 1121 other than the portion where the second layer 1122 is to be formed are shielded by using a mask. Here, the thickness of the second layer 1122 can be adjusted such that the thickness of the second compensation portion comprising the first layer 1121 and the second layer 1122 is equal to the thickness of the first compensation portion comprising the first layer 1121.

[0112] In the first compensation portion of the first gate insulating layer 112 between the first compensation gate electrode G3-1 and the third active region A3, the first layer 1121 comprising silicon oxide may have approximately To about The thickness. In the second compensation portion of the first gate insulating layer 112 between the second compensation gate electrode G3-2 and the third active region A3, the first layer 1121, including, for example, silicon oxide, may have a thickness of approximately To about The thickness, and the second layer 1122 including silicon nitride can have approximately To about The thickness. In the first layer 1121, the first compensation portion has approximately... The thickness and has approximately in the second compensation part In embodiments with a thickness of [thickness value missing], the second layer 1122 may have approximately [thickness value missing]. The thickness is such that the thickness of the first compensation part is equal to the thickness of the second compensation part, that is... This feature can be applied to other embodiments and variations thereof, which will be described later.

[0113] In the first gate insulating layer 112 formed as described above, the first compensation portion of the first gate insulating layer 112 between the first compensation gate electrode G3-1 and the third active region A3 may have a single-layer structure including a first layer 1121, and the second compensation portion of the first gate insulating layer 112 between the second compensation gate electrode G3-2 and the third active region A3 may have a multi-layer structure including a first layer 1121 and a second layer 1122. In an exemplary embodiment, the second layer 1122 in the second compensation portion is closer to the second compensation gate electrode G3-2 than the first layer 1121. For example, the distance between the second layer 1122 and the second compensation gate electrode G3-2 may be less than the distance between the second compensation gate electrode G3-2 and the first layer 1121. The first layer 1121 in the second compensation portion and the first layer 1121 in the first compensation portion may be integrally formed.

[0114] Furthermore, as the thickness of the first gate insulating layer 112 increases, the distance between the driving gate electrode G1 of the driving thin-film transistor T1 and the first active region A1 also increases. In this case, as described above with reference to the compensated thin-film transistor T3, the sensitivity of the driving thin-film transistor T1 may decrease. That is, when a preset electrical signal is applied to the driving gate electrode G1, it may not be possible to perform the turn-on and turn-off at the driving thin-film transistor T1 at the accurate time. Moreover, it may not be easy to finely control the change in current flowing between the driving source region S1 and the driving drain region D1 by adjusting the electrical signal applied to the driving gate electrode G1.

[0115] Figure 6 This is a cross-sectional view of a portion of a display device according to an exemplary embodiment of the present disclosure, which can be used to solve sensitivity problems. Figure 6In this design, the first portion of the first gate insulating layer 112 between the driving gate electrode G1 and the first active region A1 has a multilayer structure. Therefore, the sensitivity of the driving thin-film transistor T1 can be improved while preventing or reducing backlash.

[0116] In an exemplary embodiment, like the second compensation portion of the first gate insulating layer 112 between the second compensation gate electrode G3-2 and the third active region A3, the first portion of the first gate insulating layer 112 between the driving gate electrode G1 and the first active region A1 has a multilayer structure. In an exemplary embodiment of this disclosure, the first portion includes a first layer 1121 comprising the same material as the first compensation portion, and a second layer 1122 comprising a material different from the material of the first compensation portion. In an exemplary embodiment of this disclosure, the dielectric constant of the material included in the second layer 1122 is greater than the dielectric constant of the material included in the first layer 1121. For example, the first layer 1121 may comprise silicon oxide, and the second layer 1122 may comprise silicon nitride.

[0117] In the organic light-emitting display device according to an exemplary embodiment of the present disclosure, the thickness of the first gate insulating layer 112 between the first compensation gate electrode G3-1 and the third active region A3 is increased, thereby reducing the parasitic capacitance between the first compensation gate electrode G3-1 and the third active region A3 and preventing or reducing the occurrence of backlash. Furthermore, the first gate insulating layer 112 between the driving gate electrode G1 and the first active region A1 includes a second layer 1122 having a large dielectric constant, and therefore, even when the thickness of the first gate insulating layer 112 increases, the driving thin-film transistor T1 can respond more quickly (more sensitively) to the electrical signal applied to the driving gate electrode G1.

[0118] The first gate insulating layer 112 can be formed by various methods. For example, silicon oxide can be used to form the first layer 1121. Then, at least a portion of the upper part of the first layer 1121 is removed from the portion where the first compensation gate electrode G3-2 and the driving gate electrode G1 are to be formed. This can be done by forming a photoresist layer on the first layer 1121, removing the photoresist layer from the portion where the second layer 1122 is to be formed, and performing a dry etching process. Then, a second layer 1122 comprising silicon nitride can be formed at the portion where the first layer 1121 was partially removed. The second layer 1122 can be obtained by a CVD method while using a mask to shield the portions of the first layer 1121 other than the portion where the second layer 1122 is to be formed. In an exemplary embodiment, the thickness of the second layer 1122 is adjusted such that the thickness of the second compensation portion and the thickness of the first portion including the first layer 1121 and the second layer 1122 are equal to the thickness of the first compensation portion including the first layer 1121.

[0119] In the first gate insulating layer 112 formed as described above, the first compensation portion of the first gate insulating layer 112 between the first compensation gate electrode G3-1 and the third active region A3 may have a single-layer structure including a first layer 1121, and the second compensation portion of the first gate insulating layer 112 between the second compensation gate electrode G3-2 and the third active region A3 and the first portion of the first gate insulating layer 112 between the driving gate electrode G1 and the first active region A1 may each have a multilayer structure including a first layer 1121 and a second layer 1122. In an exemplary embodiment of this disclosure, in the second compensation portion, the second layer 1122 is closer to the second compensation gate electrode G3-2 than the first layer 1121. In the first portion, the second layer 1122 is also closer to the driving gate electrode G1 than the first layer 1121. The second compensation portion and the first layer 1121 in the first portion and the first layer 1121 in the first compensation portion may be integrally formed.

[0120] Furthermore, as the thickness of the first gate insulating layer 112 increases, the distance between the first initialization gate electrode G4 and the fourth active region A4 of the first initialization thin-film transistor T4 also increases. In this embodiment, as described above with reference to the compensation thin-film transistor T3, the sensitivity of the first initialization thin-film transistor T4 may decrease. That is, when a preset electrical signal is applied to the first initialization gate electrode G4, it may not be possible to perform the turning on and off of the first initialization thin-film transistor T4 at the accurate time. Moreover, it may not be easy to finely control the change in current flowing between the first initialization source region S4 and the first initialization drain region D4 by adjusting the electrical signal applied to the first initialization gate electrode G4.

[0121] Figure 7 This is a cross-sectional view of a portion of a display device according to an exemplary embodiment of the present disclosure, which can be used to solve sensitivity problems. Figure 7 In this design, the first gate insulating layer 112 has a multilayer structure in the fourth portion between the first initialization gate electrode G4 and the fourth active region A4. Therefore, the sensitivity of the first initialization thin-film transistor T4 can be improved while preventing or reducing backlash.

[0122] In exemplary embodiments of this disclosure, like the second compensation portion of the first gate insulating layer 112 between the second compensation gate electrode G3-2 and the third active region A3, the fourth portion of the first gate insulating layer 112 between the first initialization gate electrode G4 and the fourth active region A4 has a multilayer structure. In an exemplary embodiment, the fourth portion includes a first layer 1121 and a second layer 1122, where the first layer 1121 comprises the same material as the first compensation portion, and the second layer 1122 comprises a material different from the material of the first compensation portion. In an exemplary embodiment, the dielectric constant of the material included in the second layer 1122 is greater than the dielectric constant of the material included in the first layer 1121. For example, the first layer 1121 may comprise silicon oxide, and the second layer 1122 may comprise silicon nitride.

[0123] In the organic light-emitting display device according to an exemplary embodiment of the present disclosure, the thickness of the first gate insulating layer 112 between the first compensation gate electrode G3-1 and the third active region A3 is increased, thereby reducing the parasitic capacitance between the first compensation gate electrode G3-1 and the third active region A3 and preventing or reducing the occurrence of backlash. Furthermore, the first gate insulating layer 112 between the first initialization gate electrode G4 and the fourth active region A4 includes a second layer 1122 having a large dielectric constant, and therefore, even when the thickness of the first gate insulating layer 112 increases, the first initialization thin-film transistor T4 can respond more quickly or more sensitively to the electrical signal applied to the first initialization gate electrode G4.

[0124] The first gate insulating layer 112 can be formed by various methods. For example, the first layer 1121 can be formed using silicon oxide. Then, at least partially, the upper portion of the first layer 1121 is removed from the portion where the second compensation gate electrode G3-2 and the first initialization gate electrode G4 are to be formed. This can be performed by forming a photoresist layer on the first layer 1121, removing the photoresist layer from the portion where the second layer 1122 is to be formed, and performing a dry etching process. Then, a second layer 1122 comprising silicon nitride can be formed at the portion where the first layer 1121 was partially removed. The second layer 1122 can be obtained by a CVD method while using a mask to shield the portions of the first layer 1121 other than the portion where the second layer 1122 is to be formed. In an exemplary embodiment of this disclosure, the thickness of the second layer 1122 is adjusted such that the thickness of the second compensation portion and the thickness of the fourth portion including the first layer 1121 and the second layer 1122 are equal to the thickness of the first compensation portion including the first layer 1121.

[0125] In the first gate insulating layer 112 formed as described above, the first compensation portion of the first gate insulating layer 112 between the first compensation gate electrode G3-1 and the third active region A3 may have a single-layer structure including the first layer 1121, and the second compensation portion of the first gate insulating layer 112 between the second compensation gate electrode G3-2 and the third active region A3 and the fourth portion of the first gate insulating layer 112 between the first initialization gate electrode G4 and the fourth active region A4 may each have a multilayer structure including the first layer 1121 and the second layer 1122. In an exemplary embodiment of this disclosure, in the second compensation portion, the second layer 1122 is closer to the second compensation gate electrode G3-2 than the first layer 1121. In the fourth portion, the second layer 1122 is also closer to the first initialization gate electrode G4 than the first layer 1121. The first layer 1121 in the second compensation portion and the fourth portion, as well as the first layer 1121 in the first compensation portion, may be integrally formed as a single unit.

[0126] exist Figure 7 In this embodiment, because the first initialization thin-film transistor T4 has dual gate electrodes, the fourth portion of the first gate insulating layer 112 between the first initialization gate electrode G4 and the fourth active region A4 is located at two separate positions. However, exemplary embodiments of this disclosure are not limited thereto. For example, as shown in the cross-sectional view illustrating a display device according to an embodiment of this disclosure... Figure 8 As shown, the fourth portion of the first gate insulating layer 112 between the first initial gate electrode G4 and the fourth active region A4 also corresponds to the portion between the two gate electrodes of the first initial thin film transistor T4.

[0127] Can be combined according to reference Figure 8 The organic light-emitting display device described in the embodiments and according to the reference Figure 6 The described embodiment of the organic light-emitting display device is used to form Figure 9 An organic light-emitting display device. That is, like the second compensation portion between the second compensation gate electrode G3-2 and the third active region A3 of the compensation thin-film transistor T3, the first portion of the first gate insulating layer 112 (e.g., the first portion corresponding to the portion between the driving gate electrode G1 of the driving thin-film transistor T1 and the first active region A1) and the fourth portion of the first gate insulating layer 112 (e.g., the fourth portion corresponding to the portion between the first initialization gate electrode G4 and the fourth active region A4 of the first initialization thin-film transistor T4) can have a multilayer structure. For example, along line A-A' Figure 8 The first initialization transistor T4 shown can be used to form Figure 9 The first initialization transistor T4 is located within the line C-C'. Figure 6 The driving transistor T1 shown can be used to form Figure 9 The driving transistor T1 inside.

[0128] Figure 10 This illustrates the layout of the positions of thin-film transistors and capacitors in a pixel of a display device according to an exemplary embodiment of the present disclosure. For example... Figure 10 As shown, in the third active region A3, the portion overlapping with the first compensation gate electrode G3-1 has an area smaller than the area of ​​the portion overlapping with the second compensation gate electrode G3-2. By... Figure 3 and Figure 10 This comparison can be achieved by reducing the size of the first compensation gate electrode G3-1.

[0129] This reduces the parasitic capacitance between the first compensation gate electrode G3-1 and the third active region A3, thus preventing or reducing recoil. Because the size of the second compensation gate electrode G3-2 is not reduced, the compensation thin-film transistor T3 can respond more quickly (or more sensitively) to electrical signals applied to the compensation gate electrode G3. In the above-described organic light-emitting display device according to an exemplary embodiment, the structure of the first gate insulating layer 112 as described above is applied.

[0130] The area of ​​a region in the third active region A3 (e.g., the region overlapping with the first compensation gate electrode G3-1) that is smaller than the area of ​​a region in the third active region A3 (e.g., the region overlapping with the second compensation gate electrode G3-2) indicates that the channel length of the region in the third active region A3 overlapping with the first compensation gate electrode G3-1 is less than the channel length of the region overlapping with the second compensation gate electrode G3-2. The channel length represents the length of the active region on the semiconductor layer 1130 from the source region to the drain region.

[0131] According to at least one exemplary embodiment of the present disclosure, an organic light-emitting display device capable of displaying high-quality images and a method for manufacturing the organic light-emitting display device can be realized. However, the embodiments of the present disclosure are not limited to providing higher quality images, but can provide other benefits.

[0132] It should be understood that the embodiments described herein should be considered in a descriptive sense only and not for limiting purposes. The description of features or aspects within each embodiment should generally be considered applicable to other similar features or aspects in other embodiments. Although one or more embodiments have been described with reference to the accompanying drawings, those skilled in the art will understand that various changes in form and detail may be made without departing from the spirit and scope of this disclosure.

Claims

1. An organic light-emitting display device, comprising: Organic light-emitting diode; A driving transistor is configured to control the amount of current flowing from a second node connected to a power supply voltage line to the organic light-emitting diode in response to a voltage applied to a first node connected to the driving gate electrode of the driving transistor. A compensation transistor, connected between the first node and the third node, is configured to diode-connect the driving transistor in response to a voltage applied to a first compensation gate electrode and a second compensation gate electrode disposed on the same layer, wherein the third node is between the driving transistor and the organic light-emitting diode; and A gate insulating layer is located between the first and second compensation gate electrodes and the compensation active region of the compensation transistor. The layer structure of the gate insulating layer between the first compensated gate electrode and the compensated active region is different from the layer structure of the gate insulating layer between the second compensated gate electrode and the compensated active region. The first compensation portion of the gate insulating layer between the first compensation gate electrode and the compensation active region has a single-layer structure, and the second compensation portion of the gate insulating layer between the second compensation gate electrode and the compensation active region has a multi-layer structure. The second compensation portion includes a first layer and a second layer. The first layer includes the material included in the first compensation portion, and the second layer includes a material different from the material included in the first compensation portion. The dielectric constant of the material included in the second layer is greater than the dielectric constant of the material included in the first layer.

2. The organic light-emitting display device according to claim 1, further comprising a semiconductor layer, wherein, The portion of the semiconductor layer including the compensation active region is connected to the portion of the semiconductor layer including the driving active region of the driving transistor, and In the semiconductor layer, the portion corresponding to the first compensation gate electrode is connected to the driving active region corresponding to the driving gate electrode of the driving transistor via the portion corresponding to the second compensation gate electrode.

3. The organic light-emitting display device according to claim 1, wherein, The thickness of the first compensation portion is equal to the thickness of the second compensation portion.

4. The organic light-emitting display device according to claim 1, wherein, The second layer is closer to the second compensation gate electrode than the first layer.

5. The organic light-emitting display device according to claim 1, wherein, The first layer comprises silicon oxide, and the second layer comprises silicon nitride.

6. The organic light-emitting display device according to claim 1, wherein, The first layer and the first compensation portion form a single, integrated terrain.

7. The organic light-emitting display device according to claim 1, wherein, The gate insulating layer is inserted between the driving gate electrode of the driving transistor and the driving active region of the driving transistor, and the first portion of the gate insulating layer between the driving gate electrode and the driving active region has a multilayer structure.

8. The organic light-emitting display device according to claim 7, wherein, The first part includes a first layer and a second layer, the first layer of the first part including the material included in the first compensation part, and the second layer of the first part including a material different from the material included in the first compensation part.

9. The organic light-emitting display device according to claim 8, wherein, The dielectric constant of the material included in the second layer of the first portion is greater than the dielectric constant of the material included in the first layer of the first portion.

10. The organic light-emitting display device according to claim 8, wherein, The second layer of the second compensation portion is closer to the second compensation gate electrode than the first layer of the second compensation portion, and the second layer of the first portion is closer to the drive gate electrode than the first layer of the first portion.

11. The organic light-emitting display device according to claim 8, wherein, The first layer of the first portion and the second compensation portion comprises silicon oxide, and the second layer of the first portion and the second compensation portion comprises silicon nitride.

12. The organic light-emitting display device according to claim 8, wherein, The first layer of the first part and the second compensation part are integrated with the overall terrain of the first compensation part.

13. The organic light-emitting display device of claim 1, further comprising an initialization transistor connected between the first node and the initialization voltage line, the initialization transistor being configured to initialize the voltage at the driving gate electrode of the driving transistor in response to a voltage applied to the initialization gate electrode of the initialization transistor. in, The gate insulating layer is inserted between the initialization gate electrode and the initialization active region of the initialization transistor, and the fourth portion of the gate insulating layer between the initialization gate electrode and the initialization active region has a multilayer structure.

14. The organic light-emitting display device according to claim 13, wherein, The fourth part includes a first layer and a second layer, wherein the first layer of the fourth part includes the material included in the first compensation part, and the second layer of the fourth part includes a material different from the material included in the first compensation part.

15. The organic light-emitting display device according to claim 14, wherein, The dielectric constant of the material included in the second layer of the fourth part is greater than the dielectric constant of the material included in the first layer of the fourth part.

16. The organic light-emitting display device according to claim 14, wherein, The second layer of the second compensation portion is closer to the second compensation gate electrode than the first layer of the second compensation portion, and the second layer of the fourth portion is closer to the initialization gate electrode than the first layer of the fourth portion.

17. The organic light-emitting display device according to claim 14, wherein, The first layer of the second compensation portion and the fourth portion comprises silicon oxide, and the second layer of the second compensation portion and the fourth portion comprises silicon nitride.

18. The organic light-emitting display device according to claim 14, wherein, The second compensation portion and the first layer of the fourth portion are integrated into the overall terrain.

19. The organic light-emitting display device according to claim 1, wherein, In the compensated active region, the portion overlapping with the first compensated gate electrode has an area smaller than the area of ​​the portion overlapping with the second compensated gate electrode.

20. The organic light-emitting display device according to claim 1, wherein, In the compensated active region, the channel length of the portion overlapping with the first compensated gate electrode is less than the channel length of the portion overlapping with the second compensated gate electrode.

21. A pixel circuit for an organic light-emitting display device, comprising: The driving transistor is configured to control the amount of current flowing from the power supply voltage line to the organic light-emitting diode; The compensation transistor is configured to diode-connect the driving transistor in response to a voltage applied to a first compensation gate electrode and a second compensation gate electrode of the compensation transistor. as well as A gate insulating layer is located between the first and second compensation gate electrodes and the compensation active region of the compensation transistor. The layer structure of the gate insulating layer between the first compensated gate electrode and the compensated active region is different from the layer structure of the gate insulating layer between the second compensated gate electrode and the compensated active region. The first compensation portion of the gate insulating layer between the first compensation gate electrode and the compensation active region has a single-layer structure, and the second compensation portion of the gate insulating layer between the second compensation gate electrode and the compensation active region has a multi-layer structure. The second compensation portion includes a first layer and a second layer. The first layer includes the material included in the first compensation portion, and the second layer includes a material different from the material included in the first compensation portion. The dielectric constant of the material included in the second layer is greater than the dielectric constant of the material included in the first layer.

22. An organic light-emitting display device, comprising: Organic light-emitting diode; A driving transistor is configured to control the amount of current flowing from the power supply voltage line to the organic light-emitting diode; The compensation transistor is configured to diode-connect the driving transistor in response to a voltage applied to a first compensation gate electrode and a second compensation gate electrode of the compensation transistor. as well as A gate insulating layer is located between the first and second compensation gate electrodes and the compensation active region of the compensation transistor. The first compensation portion of the gate insulating layer between the first compensation gate electrode and the compensation active region has a single-layer structure, and the second compensation portion of the gate insulating layer between the second compensation gate electrode and the compensation active region has a multi-layer structure. The first compensation portion of the gate insulating layer between the first compensation gate electrode and the compensation active region has a single-layer structure, and the second compensation portion of the gate insulating layer between the second compensation gate electrode and the compensation active region has a multi-layer structure. The second compensation portion includes a first layer and a second layer. The first layer includes the material included in the first compensation portion, and the second layer includes a material different from the material included in the first compensation portion. The dielectric constant of the material included in the second layer is greater than the dielectric constant of the material included in the first layer.

23. The organic light-emitting display device according to claim 22, wherein, The thickness of the first compensation portion is equal to the thickness of the second compensation portion.

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