Pixel unit, display substrate and display device

Abstract

The present application provides a pixel unit, a display substrate and a display device, which belong to the field of display technology. In the pixel unit, the storage capacitor includes a first electrode, a second electrode and a third electrode stacked in sequence. Since each two adjacent layers of electrodes can form a capacitor, the storage capacitor can be composed of two capacitors in parallel, and accordingly, the capacitance of the storage capacitor is the sum of the capacitances of the two parallel capacitors. Compared with the related art, the capacitance of the storage capacitor in the pixel unit recorded in the present application is larger, and thus, the light-emitting element included in the pixel unit has higher light-emitting accuracy, and the display effect of the display substrate including the pixel unit is better.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a pixel unit, a display substrate, and a display device. Background Art

[0002] Organic light emitting diode (OLED) display substrates are highly favored due to their advantages such as self-luminescence, low power consumption, fast response and low cost.

[0003] In related technologies, an OLED display substrate may include: multiple pixels, each of which may include multiple transistors, storage capacitors, and light-emitting elements. The light-emitting elements can emit light under the drive of each transistor and storage capacitor, and the capacitance of the storage capacitor is proportional to the light-emitting accuracy of the light-emitting element. The storage capacitor may be formed by the gate metal layer and source and drain metal layers, or the active layer and source and drain metal layers, in the display substrate.

[0004] However, since the storage capacitor formed in the related art has a small capacitance, the light emitting element has low light emission accuracy and poor display effect. Summary of the Invention

[0005] The embodiments of the present disclosure provide a pixel unit, a display substrate, and a display device that can solve the problems of low light emission accuracy and poor display effect of light-emitting elements in related technologies. The technical solution is as follows:

[0006] In one aspect, a pixel unit is provided, comprising: a thin film transistor and a storage capacitor located on a substrate; the thin film transistor comprises: an active layer, a gate electrode, and a source and drain electrode; the storage capacitor comprises: a first electrode, a second electrode, and a third electrode stacked in sequence;

[0007] Wherein, the first electrode is located on a side of the active layer close to the base substrate;

[0008] The second electrode is located in the same layer as the active layer or the gate;

[0009] The third electrode and the source and drain are located in the same layer, and the third electrode is electrically connected to the first electrode.

[0010] Optionally, the thin film transistor includes: a driving transistor, and the source and drain electrodes include a source electrode and a drain electrode;

[0011] The second electrode is electrically connected to the first electrode of the driving transistor, and the electrically connected third electrode and the first electrode are electrically connected to the gate of the driving transistor; wherein the first electrode is one of the source and the drain of the driving transistor.

[0012] Optionally, the orthographic projection of the first electrode on the base substrate does not overlap with the orthographic projection of the second electrode of the driving transistor on the base substrate; wherein the second electrode is the other electrode of the source and the drain of the driving transistor.

[0013] Optionally, the thin film transistor includes: a driving transistor, and the source and drain electrodes include a source electrode and a drain electrode;

[0014] The second electrode is electrically connected to the gate of the driving transistor, and the electrically connected third electrode and the first electrode are electrically connected to the first electrode of the driving transistor; wherein the first electrode is one of the source and the drain of the driving transistor.

[0015] Optionally, the orthographic projection of the first electrode on the base substrate overlaps with the orthographic projection of the second electrode of the driving transistor on the base substrate; wherein the second electrode is the other electrode of the source and the drain of the driving transistor.

[0016] Optionally, the second electrode of the driving transistor is used to be electrically connected to a driving power supply terminal.

[0017] Optionally, the third electrode is electrically connected to the first electrode through a via hole.

[0018] Optionally, the pixel unit further includes: a light-emitting element, which is an organic light-emitting diode; wherein the light-emitting element is electrically connected to the first electrode of the driving transistor.

[0019] Optionally, the thin film transistor further includes: a switching transistor;

[0020] The orthographic projection of any one of the first electrode, the second electrode and the third electrode on the substrate does not overlap with the orthographic projection of the active layer of the switching transistor on the substrate, the orthographic projection of the gate of the switching transistor on the substrate, and the orthographic projection of the source and drain of the switching transistor on the substrate.

[0021] Optionally, the thin film transistor further includes: a compensation transistor;

[0022] The orthographic projection of any one of the first electrode, the second electrode and the third electrode on the base substrate does not overlap with the orthographic projection of the active layer of the compensation transistor on the base substrate, the orthographic projection of the gate of the compensation transistor on the base substrate, and the orthographic projection of the source and drain of the compensation transistor on the base substrate.

[0023] Optionally, the storage capacitor further includes: an insulating layer located between every two adjacent electrodes.

[0024] Optionally, the pixel unit is a top-emission pixel unit.

[0025] Optionally, the second electrode of the driving transistor is used to electrically connect to the driving power supply end; the third electrode is electrically connected to the first electrode through a via; the storage capacitor also includes: an insulating layer located between each two adjacent electrodes; the pixel unit is a top-emitting pixel unit.

[0026] On the other hand, a display substrate is provided, comprising: a base substrate, and a plurality of pixel units located on the base substrate and arranged in an array;

[0027] Among them, at least one of the pixel units is the pixel unit described in the above aspect.

[0028] In another aspect, a display device is provided, comprising: a driving circuit, and the display substrate according to the above aspect;

[0029] The driving circuit is connected to the pixel unit in the display substrate, and is used to provide a driving signal for the thin film transistor included in the pixel unit.

[0030] The beneficial effects brought about by the technical solutions provided by the embodiments of the present disclosure may include at least:

[0031] The present disclosure provides a pixel unit, a display substrate, and a display device. In the pixel unit, a storage capacitor includes a first electrode, a second electrode, and a third electrode stacked in sequence. Since each two adjacent layers of electrodes can form a capacitor, the storage capacitor can be composed of two capacitors in parallel. Accordingly, the capacitance of the storage capacitor is the sum of the capacitances of the two capacitors in parallel. Compared with the related art, the capacitance of the storage capacitor in the pixel unit described in this application is larger, and thus, the light-emitting element included in the pixel unit has higher light-emitting accuracy, and the display effect of the display substrate including the pixel unit is better. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0033] Figure 1 is a structural diagram of a pixel unit provided by an embodiment of the present disclosure;

[0034] Figure 2 1 is a schematic diagram of the composition of a storage capacitor provided by an embodiment of the present disclosure;

[0035] Figure 3 is a structural diagram of another pixel unit provided by an embodiment of the present disclosure;

[0036] Figure 4 is an equivalent circuit diagram of a pixel unit provided by an embodiment of the present disclosure;

[0037] Figure 5 is a schematic structural diagram of another storage capacitor provided by an embodiment of the present disclosure;

[0038] Figure 6 is a structural diagram of another pixel unit provided by an embodiment of the present disclosure;

[0039] Figure 7 is a structural diagram of another storage capacitor provided by an embodiment of the present disclosure;

[0040] Figure 8 is a structural diagram of another pixel unit provided by an embodiment of the present disclosure;

[0041] Figure 9 is a schematic structural diagram of a display substrate provided by an embodiment of the present disclosure;

[0042] Figure 10 is a schematic structural diagram of another display substrate provided by an embodiment of the present disclosure;

[0043] Figure 11 It is a structural schematic diagram of a display device provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0044] In order to make the objectives, technical solutions and advantages of the present disclosure more clear, the embodiments of the present disclosure will be further described in detail below with reference to the accompanying drawings.

[0045] Figure 1 Schematic diagram of a pixel unit structure provided by an embodiment of the present disclosure. Figure 1 As shown, the pixel unit may include: a thin film transistor M1 and a storage capacitor Cst located on a substrate 00.

[0046] Among them, reference Figure 1 The thin film transistor M1 may include: an active (ACT) layer 01, a gate (G) 02 and a source & drain (SD) 03, and the active layer 01, the gate 02 and the source & drain 03 may be arranged in sequence in a direction away from the substrate 00.

[0047] Continue to refer Figure 1 The storage capacitor Cst may include: a first electrode 04, a second electrode 05 and a third electrode 06 stacked in sequence.

[0048] The first electrode 04 can be located on a side of the active layer 01 close to the base substrate 00. That is, the first electrode 04 can be located between the active layer 01 and the base substrate 00. Furthermore, to form the storage capacitor Cst, the first electrode 04 can be made of a conductive material, such as a metal material. Accordingly, the first electrode 04 can also be referred to as a metal layer.

[0049] The second electrode 05 can be located in the same layer as the active layer 01 or the gate 02. Figure 1 , which shows that the second electrode 05 is located in the same layer as the active layer 01.

[0050] The third electrode 06 may be located in the same layer as the source and drain electrodes 03 , and the third electrode 06 may be electrically connected to the first electrode 04 .

[0051] In addition, among any two electrodes, the orthographic projection of one electrode on the base substrate 00 overlaps with the orthographic projection of the other electrode on the base substrate 00. Figure 1 The orthographic projection of the second electrode 05 on the substrate 00 may overlap with the orthographic projection of the first electrode 04 on the substrate 00. The orthographic projection of the second electrode 05 on the substrate 00 may also overlap with the orthographic projection of the third electrode 06 on the substrate 00. Furthermore, the orthographic projection of the first electrode 04 on the substrate 00 and the orthographic projection of the third electrode 06 on the substrate 00 may overlap. Accordingly, the second electrode 05 may be located between the first electrode 04 and the third electrode 06. Further, in combination Figure 2 It can be seen that the second electrode 05 and the third electrode 06 can form a capacitor C1, and the second electrode 05 and the first electrode 04 can form another capacitor C2. The storage capacitor Cst can be composed of the two capacitors C1 and C2 in parallel.

[0052] Assuming that the capacitance value of capacitor C1 (hereinafter referred to as "capacitance") is c1 and the capacitance value of capacitor C2 is c2, based on the capacitor parallel formula, the capacitance value cst of storage capacitor Cst is: cst = c1 + c2. Compared with the related art storage capacitor consisting of only two adjacent metal layers, the storage capacitor provided by the embodiment of the present disclosure has a larger capacitance. Of course, in order to form a storage capacitor with a larger capacitance, more layers of electrodes stacked in sequence can be provided (for example, two or more layers of first electrodes 04 can be provided).

[0053] In summary, the embodiments of the present disclosure provide a pixel unit. In the pixel unit, the storage capacitor includes a first electrode, a second electrode, and a third electrode stacked in sequence. Since each two adjacent layers of electrodes can form a capacitor, the storage capacitor can be composed of two capacitors in parallel, and accordingly, the capacitance of the storage capacitor is the sum of the capacitances of the two capacitors in parallel. Compared with the related art, the capacitance of the storage capacitor in the pixel unit described in this application is larger, and thus, the light-emitting element included in the pixel unit has higher light-emitting accuracy, and the display effect of the display substrate including the pixel unit is better.

[0054] Optionally, to avoid increasing manufacturing costs and complexity of the manufacturing process, the same material can be used to form the second electrode 05 and active layer 01 located on the same layer through a single patterning process, or the second electrode 05 and gate 02 located on the same layer can be formed. Similarly, the same material can be used to form the third electrode 06 and source / drain electrodes 03 located on the same layer through a single patterning process. The source / drain electrodes 03 can include a source electrode and a drain electrode.

[0055] That is, assuming that an ACT pattern is formed through a single patterning process, the ACT pattern may include the active layer 01 and the second electrode 05. Assuming that a gate metal (GT) pattern is formed through a single patterning process, the GT pattern may include the gate electrode 02 and the second electrode 05. Assuming that a source / drain electrode SD pattern is formed through a single patterning process, the source / drain electrode SD pattern may include the source / drain electrode 03 and the third electrode 06. In addition, the thin-film transistor M1 may further include a gate insulator (GI) layer located on the side of the gate electrode 02 closest to the substrate 00. That is, a GI pattern is also formed before the GT pattern is formed.

[0056] For example, taking the case where the second electrode 05 and the active layer 01 are located in the same layer, Figure 3 FIG2 shows a schematic diagram of the structure of another pixel unit provided by an embodiment of the present disclosure. Figure 3 It can be seen that the second electrode 05 and the active layer 01 can be an integral structure, and the third electrode 06 and the source and drain electrodes 03 can be an integral structure. The first electrode 04 is a metal layer added to the base substrate 00 using a separate patterning process.

[0057] The following embodiments all take the second electrode 05 and the active layer 01 as an integrated structure, and the third electrode 06 and the source and drain 03 as an integrated structure as an example to introduce the pixel unit described in the embodiments of the present disclosure.

[0058] Optional, Figure 4 : is an equivalent circuit diagram of a pixel unit provided by an embodiment of the present disclosure. Figure 4As shown, the pixel unit may further include a light emitting element L1, which may be an organic light emitting diode OLED. Figure 4 The thin film transistor M1 may include: a driving transistor M11, a switching transistor M12, a compensation transistor M13 and a storage capacitor Cst.

[0059] Among them, the gate of the switching transistor M12 can be connected to a gate line g1, the first electrode can be connected to the node n, and the second electrode can be connected to a data line d1. One end of the storage capacitor Cst can be connected to the node n, and the other end can be connected to one end of the light-emitting element L1. And the other end of the light-emitting element L1 can be connected to the ground terminal. The gate of the driving transistor M11 can be connected to the node n, the first electrode can be connected to one end of the light-emitting element L1, and the second electrode can be connected to the driving power supply terminal OVDD. The gate of the compensation transistor M13 can be connected to another gate line g2, the first electrode can be connected to the reference power supply terminal Vref and the external compensation circuit (not shown), and the second electrode can be connected to one end of the light-emitting element L1.

[0060] It should be noted that the first electrode of the driving transistor M11 can be one of the source and drain of the driving transistor M11, and the second electrode of the driving transistor M11 can be the other of the source and drain of the driving transistor M11, and the same applies to other transistors. Moreover, the second electrode of the driving transistor M11 can refer to an electrode for electrically connecting to the driving power supply terminal OVDD. Accordingly, in combination with the above Figure 4 It can be seen that the first electrode recorded in the embodiment of the present disclosure is the source electrode, and the second electrode is the drain electrode.

[0061] In addition, in addition to the storage capacitor Cst, a parasitic capacitor is formed between the first electrode and the second electrode of each transistor and its gate in the pixel unit. Figure 4 As shown, a parasitic capacitor Cgd1 is formed between the second electrode (i.e., drain) and gate of the driving transistor M11, and a parasitic capacitor Cgs1 is formed between the first electrode (i.e., source) and gate of the driving transistor M11. A parasitic capacitor Cgd2 is formed between the second electrode and gate of the switching transistor M12, and a parasitic capacitor Cgs2 is formed between the first electrode and gate of the switching transistor M12. A parasitic capacitor Cgd3 is formed between the second electrode and gate of the compensation transistor M13, and a parasitic capacitor Cgs3 is formed between the first electrode and gate of the compensation transistor M13. Furthermore, a parasitic capacitor Cl1 is also formed across the two ends of the light-emitting element L1.

[0062] Combine Figure 4The pixel unit shown in FIG. 1 has its operating principle described below: Switching transistor M12 can be turned on when gate line g1 provides a gate drive signal with an effective potential. At this time, data line d1 can write a data signal (also referred to as grayscale data Vgs) to node n via switching transistor M12. Storage capacitor Cst can be used to store and hold the grayscale data Vgs written to node n until the next data signal is written, i.e., to maintain Vgs unchanged within a frame scan time. Driving transistor M11 can generate a driving current in response to a driving power signal provided by driving power supply terminal OVDD and the potential at node n, and output the driving current to light-emitting element L1 to drive light-emitting element L1 to emit light. Compensation transistor M13 can be turned on when gate line g2 provides a gate drive signal with an effective potential. Reference power supply terminal Vref can be used to write a reference power signal to one end of light-emitting element L1 (i.e., the first terminal of driving transistor M11) via compensation transistor M13 to achieve noise reduction for the first terminal of driving transistor M11. Furthermore, the driving current written into the light emitting element L1 by the driving transistor M11 can be collected and output to the external compensation circuit, so that the external compensation circuit can reliably compensate the data signal based on the driving current.

[0063] Combine Figure 4 The following analysis is conducted on the effect of the storage capacitor value on the luminous effect based on the above working principle:

[0064] On the one hand, since the switching transistor M12 may leak, the potential of the node n may change, that is, the grayscale data stored in the storage capacitor Cst may change within one frame time. The change ΔV of the grayscale data stored in the storage capacitor Cst satisfies:

[0065] ΔV=(I off *Δt) / cst formula (1);

[0066] Among them, I off is the leakage current of the switching transistor M12, which is related to the device characteristics of the switching transistor M12 and cannot be avoided. Δt is the scanning time of one frame and is generally fixed. cst is the capacitance of the storage capacitor Cst. Based on formula (1), it can be seen that the larger the capacitance of the storage capacitor Cst, the smaller the change ΔV can be. The smaller ΔV, the better the luminous accuracy.

[0067] On the other hand, when the switch transistor M12 is turned off, the node n is in a floating state, and due to the presence of the parasitic capacitor Cgs2, the potential of the node n is pulled down to a potential ΔVn that satisfies:

[0068]

[0069] Where cgd1 is the capacitance of parasitic capacitor Cgd1, cgd2 is the capacitance of parasitic capacitor Cgd2, cgs1 is the capacitance of parasitic capacitor Cgs1, and ΔVg1 is the potential change of gate line g1. cgd1, cgd2, cgs1, and ΔVg1 are generally not adjustable. Therefore, based on formula (2), it can be seen that the larger the capacitance of storage capacitor Cst, the smaller ΔVn, and the smaller the change in node n potential. Correspondingly, the loss of grayscale data is also reduced, and the luminescence accuracy is improved.

[0070] On the other hand, during the light-emitting phase of driving the light-emitting element L1, the potential of the first electrode (i.e., the source) of the driving transistor M11 gradually rises. Due to the coupling effect of the storage capacitor Cst, the potential of the gate of the driving transistor M11, i.e., the potential of the node n, also rises accordingly. The potential raised to can satisfy:

[0071]

[0072] Among them, cgs2 is the capacitance of the parasitic capacitor Cgs2, and ΔVs is the potential change of the first electrode of the driving transistor M11. As analyzed above, cgs2 and ΔVs are generally not adjustable. Therefore, based on the formula (3), it can be seen that the larger the capacitance of the storage capacitor Cst, the smaller ΔVn1. That is, under the coupling effect of the storage capacitor Cst, the potential of the node n and the potential of the first electrode of the driving transistor M11 are closer. Correspondingly, the smaller the change of Vgs, the smaller the loss of grayscale data, and the better the luminous accuracy.

[0073] above Figure 1 and Figure 3 The thin film transistors M1 shown are all driving transistors M11 .

[0074] Figure 5 Schematic diagram of a film structure of a storage capacitor provided by an embodiment of the present disclosure. As an optional implementation method, combined with Figure 1 、 Figures 3 to 5 It can be seen that the second electrode 05 can be electrically connected to the first electrode of the driving transistor M11, and the electrically connected third electrode 06 and the first electrode 04 can be electrically connected to the gate G of the driving transistor M11. Figure 5 It can be seen that the first electrode of the driving transistor M11 is the source S of the driving transistor M11 .

[0075] Figure 6 Schematic diagram of the film structure of another pixel unit provided by the embodiment of the present disclosure. Figure 6 It can be seen that for Figure 5In the driving transistor M11 of the structure shown, the orthographic projection of the first electrode 04 on the substrate 00 does not overlap with the orthographic projection of the second electrode of the driving transistor M11 on the substrate 00. Based on the above analysis, it can be seen that the second electrode of the driving transistor M11 is the drain of the driving transistor M11.

[0076] This configuration avoids increasing the parasitic capacitance Cgd1 formed between the second electrode and the gate of the driving transistor M11. Combining the above formulas (2) and (3), it can be seen that by avoiding increasing Cgd1, the impact of Cgd1 on luminous accuracy is avoided, further ensuring the display effect.

[0077] Figure 7 This is a schematic diagram of another film structure of a storage capacitor provided by an embodiment of the present disclosure. As another optional implementation method, combined with Figure 1 、 Figure 3 、 Figure 4 and Figure 7 It can be seen that the second electrode 05 can be electrically connected to the gate G of the driving transistor M11 , and the electrically connected third electrode 06 and the first electrode 04 can be electrically connected to the first electrode S of the driving transistor M11 .

[0078] Figure 8 FIG. 1 is a schematic diagram of a film structure of another pixel unit provided in an embodiment of the present disclosure. Figure 8 It can be seen that for Figure 7 The orthographic projection of the first electrode of the storage capacitor shown in FIG. 1 on the substrate 00 may overlap with the orthographic projection of the second electrode of the driving transistor M11 on the substrate 00. Figure 8 The orthographic projection of the first electrode on the base substrate 00 can completely overlap with the orthographic projection of the second electrode of the driving transistor M11 on the base substrate 00 , that is, the storage capacitor Cst can “wrap” the driving transistor M11 .

[0079] By this arrangement, the first electrode 04 included in the storage capacitor Cst can be used to shield the driving transistor M11 from light, that is, the first electrode 04 can be used as a light shielding metal for the driving transistor M11. Figure 6 He Ru Figure 8 , a thin active layer can be avoided, i.e. Figure 8 The second electrode 05 shown crosses the first electrode 04 to ensure the yield. However, this arrangement may use more vias, and the capacitance of the storage capacitor Cst formed is relatively large. Figure 5 The capacitance of the storage capacitor Cst corresponding to the illustrated implementation is approximately 10% smaller.

[0080] Optional, combined with the above Figure 1 、 Figure 3 、 Figures 5 to 8It can be seen that the third electrode 06 included in the storage capacitor Cst can be electrically connected to the first electrode 04 through the via K1 (only Figure 7 Schematically marked K1).

[0081] Optional, combined Figure 6 and Figure 8 It can be seen that the gates of the transistors can be located in the same layer, the source and drain can be located in the same layer, and the active layer can also be located in the same layer.

[0082] Optionally, the orthographic projection of any one of the first electrode 04, the second electrode 05 and the third electrode 06 included in the storage capacitor Cst on the substrate 00 does not overlap with the orthographic projection of the active layer of the switching transistor M12 on the substrate, the orthographic projection of the gate of the switching transistor M12 on the substrate, and the orthographic projection of the source and drain of the switching transistor M12 on the substrate.

[0083] That is, combined Figure 6 and Figure 8 The orthographic projection of the storage capacitor Cst on the substrate 00 does not overlap with the orthographic projection of the switching transistor M12 on the substrate 00. This setting avoids increasing the capacitance of the parasitic capacitance Cgd2 and the capacitance of Cgs2 in the switching transistor M12, thereby avoiding the influence of Cgd2 and Cgs2 on the luminous accuracy, thereby further ensuring the display effect.

[0084] Optionally, the orthographic projection of any one of the first electrode 04, the second electrode 05 and the third electrode 06 included in the storage capacitor Cst on the substrate 00 may not overlap with the orthographic projection of the active layer of the compensation transistor M13 on the substrate, the orthographic projection of the gate of the compensation transistor M13 on the substrate, and the orthographic projection of the source and drain of the compensation transistor M13 on the substrate.

[0085] That is, combined Figure 6 and Figure 8 The orthographic projection of the storage capacitor Cst on the base substrate 00 does not overlap with the orthographic projection of the compensation transistor M13 on the base substrate 00. Similarly, this configuration avoids increasing the capacitance of the parasitic capacitances Cgd3 and Cgs3 in the compensation transistor M13, thereby preventing Cgd3 and Cgs3 from affecting light emission accuracy, further ensuring the display effect.

[0086] Optionally, in order to form a storage capacitor, it can be seen from the above figures that the storage capacitor Cst can also include: an insulating layer located between every two adjacent electrodes. Figure 6 and Figure 8, may include a buffer layer 07 located between the first electrode 04 and the second electrode 05, and an interlayer dielectric (ILD) layer 08 located between the second electrode 05 and the third electrode 06. In the pixel unit protected by the embodiment of the present disclosure, the storage capacitor Cst is small in size, which is conducive to achieving high resolution.

[0087] Continue to combine Figure 6 and Figure 8 The pixel unit may further include: a passivation layer (PVX) 09 located on the side of the third electrode 06 away from the substrate 00; a planar (resin) layer 10 located on the side of the passivation layer 09 away from the substrate 00; an anode 11 located on the side of the planar layer 10 away from the substrate 00, the anode 11 being electrically connected to the source and drain; and a pixel definition layer (PDL) 12 located on the side of the anode 11 away from the substrate 00. In addition, the pixel unit also includes an electroluminescent layer (EL) and a cathode, which are not shown in the figure but are located on the side of the anode layer 11 away from the substrate 00.

[0088] Optionally, the pixel unit can be a top-emitting pixel unit. That is, the light generated by the light-emitting element in the pixel unit can be emitted from the side of the cathode away from the substrate 00. Accordingly, the top-emitting pixel unit is not affected by whether the substrate 00 is light-transmitting, can effectively improve the aperture ratio of the display substrate, and is conducive to achieving high resolution. Alternatively, the pixel unit can also be a bottom-emitting pixel unit. That is, the light generated by the light-emitting element in the pixel unit can be emitted from the side of the anode 11 close to the substrate 00 through the substrate 00. The embodiments of the present disclosure are not limited to this. In addition, the transistors described in the above embodiments can all be N-type switching transistors or P-type switching transistors.

[0089] Because in the related art, in the various hierarchical structures included in the pixel unit, only the gate and source / drain electrodes are made of conductive metal materials, accordingly, the pixel unit in the related art generally can only use the gate and source / drain electrodes as the external signal terminals of the wires, or electrically connect any two ends that need to be conductive. However, compared with the related art, the embodiment of the present disclosure adds a new conductive metal layer (i.e., the first electrode) in addition to the gate and source / drain electrodes to form a storage capacitor. Therefore, the first electrode can be reused as part of the wire, avoiding the problem of relatively dense wires on the same layer and ensuring the yield of the final display substrate.

[0090] In summary, the embodiments of the present disclosure provide a pixel unit. In the pixel unit, the storage capacitor includes a first electrode, a second electrode, and a third electrode stacked in sequence. Since each two adjacent layers of electrodes can form a capacitor, the storage capacitor can be composed of two capacitors in parallel, and accordingly, the capacitance of the storage capacitor is the sum of the capacitances of the two capacitors in parallel. Compared with the related art, the capacitance of the storage capacitor in the pixel unit described in this application is larger, and thus, the light-emitting element included in the pixel unit has higher light-emitting accuracy, and the display effect of the display substrate including the pixel unit is better.

[0091] Figure 9 Schematic diagram of the structure of a display substrate provided by an embodiment of the present disclosure. Figure 9 As shown, the display substrate may include: a base substrate 00, and a plurality of pixel units 001 arranged in an array on the base substrate 00. At least one pixel unit 001 may include: Figure 1 、 Figure 3 、 Figure 6 and Figure 8 Any of the pixel units shown.

[0092] Figure 10 This is a design layout of a display substrate provided by an embodiment of the present disclosure, referring to Figure 10 It can be seen that each pixel unit includes a storage capacitor Cst, which is located at Figure 10 In the area where the first electrode 04 is located, a second electrode 05 and a third electrode 06 are stacked sequentially on the first electrode 04. The device also includes a driving transistor M11, a switching transistor M12, and a compensation transistor M13. The storage capacitor Cst does not overlap with the switching transistor M12 or the compensation transistor M13. Furthermore, the device includes a conductive line L1 made from the first electrode 04, extending along the row arrangement direction. Compared to related technologies that only use gate and source / drain electrodes as conductive lines, this avoids densely packed conductive lines on the same layer, thereby reducing the incidence of defects.

[0093] Figure 11 Schematic diagram of a display device provided by an embodiment of the present disclosure. Figure 11 As shown, the display device may include: a driving circuit 200, and Figure 9 or Figure 10 The display substrate 100 is shown.

[0094] The driving circuit 200 can be connected to the pixel unit in the display substrate 100 ( Figure 11 The driving circuit 200 may be used to provide a driving signal for the thin film transistor included in the pixel unit.

[0095] For example, the driving circuit 200 may include a gate driving circuit and a source driving circuit. Figure 4 In the pixel unit shown, the gate driver circuit can be connected to the gate lines g1 and g2, and can be used to provide gate driver signals at effective potentials to the gate lines g1 and g2 at different stages, thereby controlling the switching transistor M11 connected to the gate line g1 to turn on, and controlling the compensation transistor M13 connected to the gate line g2 to turn on. The source driver circuit can be connected to the data line d1, and can be used to provide a data signal to the data line d1 to which it is connected.

[0096] In addition, combined Figure 9 Multiple pixel units in the same row can be connected to the same gate line g1 and the same gate line g2, and pixel units in different rows can be connected to different gate lines g1 and g2. Multiple pixel units in the same column can be connected to the same data line d1, and pixel units in different rows can be connected to different data lines d1.

[0097] Optionally, the display device may be any product or component with a display function, such as electronic paper, an OLED panel, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, or a navigator.

[0098] It should be noted that in the accompanying drawings, the sizes of layers and regions may be exaggerated for clarity of illustration. It will also be understood that when an element or layer is referred to as being "on" another element or layer, it may be directly on the other element, or there may be an intermediate layer. In addition, it will be understood that when an element or layer is referred to as being "under" another element or layer, it may be directly under the other element, or there may be more than one intermediate layer or element. In addition, it will also be understood that when a layer or element is referred to as being "between" two layers or two elements, it may be the only layer between the two layers or two elements, or there may also be more than one intermediate layer or element. Similar reference numerals throughout the text indicate similar elements. The terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance. The term "plurality" refers to two or more, unless otherwise expressly defined.

[0099] The above description is merely an optional embodiment of the present disclosure and is not intended to limit the present disclosure. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present disclosure shall be included in the scope of protection of the present disclosure.

Claims

1. A pixel unit, characterized in that: The pixel unit includes: a thin film transistor and a storage capacitor located on a substrate; the thin film transistor includes: an active layer, a gate electrode and a source and drain electrode; the storage capacitor includes: a first electrode, a second electrode and a third electrode stacked in sequence; The first electrode is located on a side of the active layer close to the base substrate, the material of the first electrode includes a metal material, and the first electrode, the gate electrode, and the source and drain electrodes are used to form a wire external signal terminal; The second electrode and the active layer are located in the same layer, and the second electrode and the active layer form an integrated structure; The third electrode and the source and drain are located in the same layer, the third electrode and the source and drain are an integrated structure, and the third electrode is electrically connected to the first electrode; Wherein, the thin film transistor includes: a driving transistor, a switching transistor and a compensation transistor; The source-drain electrode includes a source electrode and a drain electrode; the second electrode is electrically connected to the gate electrode of the driving transistor, the electrically connected third electrode and the first electrode are electrically connected to the first electrode of the driving transistor, and the orthographic projection of the first electrode on the substrate overlaps with the orthographic projection of the second electrode of the driving transistor on the substrate; An orthographic projection of any one of the first electrode, the second electrode, and the third electrode on the substrate does not overlap with an orthographic projection of the active layer of the switching transistor on the substrate, an orthographic projection of the gate of the switching transistor on the substrate, and an orthographic projection of the source and drain of the switching transistor on the substrate; The orthographic projection of any one of the first electrode, the second electrode and the third electrode on the base substrate does not overlap with the orthographic projection of the active layer of the compensation transistor on the base substrate, the orthographic projection of the gate of the compensation transistor on the base substrate, and the orthographic projection of the source and drain of the compensation transistor on the base substrate.

2. The pixel unit according to claim 1, wherein: The second electrode of the driving transistor is used to be electrically connected to a driving power supply terminal.

3. The pixel unit according to claim 1, wherein: The third electrode is electrically connected to the first electrode through a via hole.

4. The pixel unit according to any one of claims 1 to 3, characterized in that: The pixel unit further includes: a light emitting element, wherein the light emitting element is an organic light emitting diode; The light emitting element is electrically connected to the first electrode of the driving transistor.

5. The pixel unit according to any one of claims 1 to 3, characterized in that: The storage capacitor further includes an insulating layer located between every two adjacent electrodes.

6. The pixel unit according to any one of claims 1 to 3, characterized in that: The pixel unit is a top emission pixel unit.

7. The pixel unit according to any one of claims 1 to 3, characterized in that: The second electrode of the driving transistor is used to electrically connect to the driving power supply end; the third electrode is electrically connected to the first electrode through a via; the storage capacitor also includes: an insulating layer located between each two adjacent electrodes; the pixel unit is a top emission pixel unit.

8. A display substrate, characterized in that: The display substrate comprises: a base substrate, and a plurality of pixel units located on the base substrate and arranged in an array; Wherein, at least one of the pixel units is a pixel unit according to any one of claims 1 to 7.

9. A display device, characterized in that: The display device comprises: a driving circuit, and the display substrate according to claim 8; The driving circuit is connected to the pixel unit in the display substrate, and is used to provide a driving signal for the thin film transistor included in the pixel unit.

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