Organic light-emitting diode display device

Abstract

An organic light-emitting diode (OLED) display is provided. The OLED display includes: a display area including a plurality of pixel rows configured to emit light in response to a light emission signal; a light emission signal generator located at a periphery of the display area and including a plurality of light emission signal levels connected to the plurality of pixel rows; and a first high-voltage transmission line and a second high-voltage transmission line connected to the light emission signal generator, wherein the first high-voltage transmission line is connected to a plurality of odd-numbered light emission signal levels among the plurality of light emission signal levels, and the second high-voltage transmission line is connected to a plurality of even-numbered light emission signal levels among the plurality of light emission signal levels.

Description

[0001] This application claims priority to and the benefit of Korean Patent Application No. 10-2020-0050863, filed on April 27, 2020, in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0002] Aspects of some example embodiments of the present disclosure relate to an organic light emitting diode (OLED) display. Background Art

[0003] A display device is a device capable of displaying an image (eg, a still image or a video image), and recently, an organic light emitting diode (OLED) display has drawn attention in the consumer market.

[0004] Organic light-emitting diode displays generally have self-luminous properties. Unlike liquid crystal display devices, organic light-emitting diode displays do not use a separate light source (e.g., a backlight). Therefore, organic light-emitting diode displays can be relatively thin and light-weight. Furthermore, organic light-emitting diode displays exhibit high-quality characteristics (e.g., low power consumption, high brightness, and high response speed).

[0005] Because the organic light emitting diode display emits light by itself, the organic light emitting diode of each pixel can emit light individually. To this end, a light emission signal generator can be included, and the light emission signal is transmitted to each pixel so that the organic light emitting diode can emit light.

[0006] In this case, a signal input to or output from a light transmission signal generator may be interfered with by a signal applied to an adjacent light transmission signal generator, thereby causing a signal change.

[0007] The above information disclosed in this Background section is only for enhancement of understanding of the background technology and therefore the information discussed in this Background section does not necessarily constitute prior art. Summary of the Invention

[0008] Aspects of some example embodiments of the present disclosure relate to an organic light emitting diode (OLED) display, for example, to an organic light emitting diode display including a light emission signal generator.

[0009] Aspects of some example embodiments may reduce signal changes due to interference of signals input to and output from adjacent optical transmit signal generators.

[0010] The features of the embodiments according to the present invention are not limited to the above-described features, and various extensions can be made within a range not departing from the spirit and scope of the embodiments according to the present invention.

[0011] An organic light emitting diode (OLED) display according to some example embodiments includes: a display area that emits light by receiving a light emission signal and includes a plurality of pixel rows; a light emission signal generator that is located at the periphery of the display area and includes a plurality of light emission signal levels connected to the plurality of pixel rows; and a first high voltage transmission line and a second high voltage transmission line connected to the light emission signal generator, wherein the first high voltage transmission line can be connected to a plurality of odd-numbered light emission signal levels among the plurality of light emission signal levels, and the second high voltage transmission line can be connected to a plurality of even-numbered light emission signal levels among the plurality of light emission signal levels.

[0012] According to some example embodiments, the first high voltage transmission line and the second high voltage transmission line may be insulated from each other.

[0013] According to some example embodiments, the plurality of light emission signal levels are sequentially arranged and include a first light emission signal level, a second light emission signal level, a third light emission signal level, a fourth light emission signal level, and a fifth light emission signal level to which high voltages are sequentially applied, and the first light emission signal level, the third light emission signal level, and the fifth light emission signal level may receive a first high voltage from a first high voltage transmission line, and the second light emission signal level and the fourth light emission signal level may receive a second high voltage from a second high voltage transmission line.

[0014] According to some example embodiments, the first light emission signal level, the third light emission signal level, and the fifth light emission signal level may sequentially receive the first high voltage at intervals of four horizontal periods, and the second light emission signal level and the fourth light emission signal level may sequentially receive the second high voltage at intervals of four horizontal periods.

[0015] According to some example embodiments, the OLED display may further include a scan signal generator between the display area and the light emission signal generator.

[0016] According to some example embodiments, the previous stage scan signal may be applied during the last two horizontal periods of the four horizontal periods.

[0017] According to some example embodiments, each of the plurality of light emission signal stages may include a first clock input terminal and a second clock input terminal for receiving two clock signals, a control terminal for receiving a light emission signal from a previous light emission signal stage, and an output terminal for outputting a light emission signal. Each of the plurality of light emission signal stages may include a high-level output portion and a low-level output portion. The high-level output portion may output a high voltage to the output terminal, and the low-level output portion may output a low voltage to the output terminal.

[0018] According to some example embodiments, each of the plurality of light emission signal stages may be connected to two pixel rows among the plurality of pixel rows and may apply a light emission signal to the plurality of pixel rows.

[0019] According to some example embodiments, the plurality of pixel rows may include a first pixel row, a second pixel row, a third pixel row, a fourth pixel row, a fifth pixel row, a sixth pixel row, a seventh pixel row, and an eighth pixel row arranged sequentially, and the plurality of light emission signal levels may include a first light emission signal level, a second light emission signal level, a third light emission signal level, and a fourth light emission signal level arranged sequentially. The first light emission signal level may be connected to the first pixel row and the second pixel row, the second light emission signal level may be connected to the third pixel row and the fourth pixel row, the third light emission signal level may be connected to the fifth pixel row and the sixth pixel row, and the fourth light emission signal level may be connected to the seventh pixel row and the eighth pixel row. The first and third light emission signal levels may receive a first high voltage via a first high voltage transmission line, and the second and fourth light emission signal levels may receive a second high voltage via a second high voltage transmission line.

[0020] According to some example embodiments, the first and third light emission signal levels may sequentially receive the first high voltage at intervals of four horizontal periods, and the second and fourth light emission signal levels may sequentially receive the second high voltage at intervals of four horizontal periods.

[0021] An OLED display according to some example embodiments includes: a display area that emits light by receiving a light emission signal and includes a plurality of pixel rows; a first light emission signal generator and a second light emission signal generator that are located on opposite sides of the display area and include a plurality of light emission signal levels connected to the plurality of pixel rows; and two first high voltage transmission lines and two second high voltage transmission lines that are located on opposite sides of the display area and connected to the light emission signal generators, wherein the two first high voltage transmission lines can be connected to a plurality of odd-numbered light emission signal levels among the plurality of light emission signal levels, the two second high voltage transmission lines can be connected to a plurality of even-numbered light emission signal levels among the plurality of light emission signal levels, and the two first high voltage transmission lines can be connected to each other, and the two second high voltage transmission lines can be connected to each other.

[0022] According to some example embodiments, it may be possible to improve the accuracy of a signal of a light transmit signal generator by reducing a signal change due to interference of signals input to and output from adjacent light transmit signal generators.

[0023] The features of the embodiments according to the present invention are not limited to the above-described features, and the embodiments according to the present invention can be variously extended within a range not departing from the spirit and scope of the embodiments according to the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 is a block diagram of an OLED display according to some example embodiments.

[0025] Figure 2 is a block diagram of a portion of an optical transmit signal generator according to some example embodiments.

[0026] Figure 3 is a circuit diagram of one stage in an optical transmit signal generator according to some example embodiments.

[0027] Figure 4 is a waveform diagram of a signal applied to a stage according to some example embodiments.

[0028] Figures 5 to 10 is provided for describing Figure 3 A diagram of the operations at the level .

[0029] Figure 11 is a waveform diagram of an output signal of a light emission signal generator according to some example embodiments.

[0030] Figure 12 are waveform diagrams of some signals of an optical transmit signal generator according to some example embodiments.

[0031] Figure 13 is a block diagram of an organic light emitting diode display according to some example embodiments. DETAILED DESCRIPTION

[0032] Hereinafter, aspects of some example embodiments of the present invention will be described more fully with reference to the accompanying drawings, in which example embodiments of the invention are shown. As will be appreciated by those skilled in the art, the described example embodiments may be modified in various ways without departing from the spirit or scope of embodiments according to the present invention.

[0033] Accordingly, the drawings and description are to be regarded as illustrative in nature and not restrictive, and like reference numerals refer to like elements throughout the specification.

[0034] Because the size and thickness of each structure shown in the drawings are arbitrarily shown for better understanding and ease of description, the embodiments according to the present invention are not limited thereto, and the thickness of parts and regions are exaggerated for clarity. In the drawings, the thickness of layers, films, panels, regions, etc. are exaggerated for clarity. In addition, in the drawings, the thickness of some layers and regions is exaggerated for better understanding and ease of description.

[0035] It will be understood that when an element (such as a layer, film, region, or substrate) is referred to as being "on" another element, the element can be directly on the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly on" another element, there are no intervening elements. Furthermore, throughout this specification, the term "on" a target element will be understood as being above or below the target element, and will not necessarily be understood as being "at the upper side" in the opposite direction based on gravity.

[0036] In addition, unless explicitly described to the contrary, the word “comprise” and variations such as “comprises” and variations thereof, will be understood to imply the inclusion of stated elements but not the exclusion of any other elements.

[0037] Furthermore, throughout the specification, the phrase "on a plane" means viewing a target portion from the top, and the phrase "on a cross section" means viewing a cross section formed by vertically cutting the target portion from the side.

[0038] In addition, throughout the specification, the expression "connected to" does not necessarily mean that two or more constituent elements are directly connected, but that two or more constituent elements may be indirectly connected through other constituent elements, and may be connected not only electrically but also physically, or may be connected differently according to position or function while being integrated.

[0039] First, refer to Figure 1 , an organic light emitting diode (OLED) display (or display device) according to some example embodiments will be described. Figure 1 is a block diagram of an OLED display according to some example embodiments.

[0040] Reference Figure 1 , the OLED display according to some example embodiments includes a display area 300 and a non-display area at the periphery of the display area 300 .

[0041] The display area 300 includes a plurality of pixels PX and signal lines 121 , 123 , and 151 connected to the plurality of pixels PX.

[0042] The non-display area includes a scan signal generator 410 and a light emission signal generator 510 for driving the pixels PX, as well as a first clock signal transmission line CLK1, a third clock signal transmission line CLK3, a first high voltage transmission line VGH1, and a second high voltage transmission line VGH2 connected to the scan signal generator 410 and the light emission signal generator 510. The first high voltage transmission line VGH1 and the second high voltage transmission line VGH2 are electrically insulated and thus can independently transmit high voltages.

[0043] The non-display area may further include another driver such as a data driver in addition to the scan signal generator 410 and the light emission signal generator 510. In addition, according to some example embodiments, the non-display area may further include a low voltage transmission line.

[0044] The plurality of pixels PX of the display area 300 are arranged in row and column directions. However, this is not restrictive, and the alignment of the plurality of pixels PX may vary. According to some example embodiments, each pixel PX includes a pixel circuit portion formed on a substrate and a light emitting element portion formed on the pixel circuit portion. The light emitting element portion includes an organic light emitting diode (OLED), receives current from the pixel circuit portion, and emits light according to the intensity of the current.

[0045] Each pixel PX is connected to signal lines 121, 123, and 151, and the signal lines 121, 123, and 151 include scan lines 121, previous stage scan lines 123, and light emission signal lines 151. According to some example embodiments, the signal lines may further include data lines connected to a data driver.

[0046] The scan line 121 , the previous-stage scan line 123 , and the light emission signal line 151 extend in a first direction, and the data line may extend in a second direction different from the first direction.

[0047] The scan signal generator 410 includes a plurality of scan signal stages GD (e.g., GD[0] to GD

[10] ). Each scan signal stage GD generates and outputs a gate signal, and the output gate signal is transmitted to the pixels PX included in the current pixel row through the scan line 121, and is transmitted to the pixels PX included in the next pixel row through the previous scan line 123. In addition, each scan signal stage GD applies the gate signal as a carry signal to the scan signal stage GD of the next stage. Gate signals having a gate-on voltage and a gate-off voltage are alternately applied, and at least one gate-on voltage is included during one frame.

[0048] The scan signal generator 410 may further include a 0th scan signal stage GD[0] to apply a gate signal to the previous stage scan line 123 connected to the pixels in the first pixel row.

[0049] According to some example embodiments, the light emission signal generator 510 is located outside the scan signal generator 410 .

[0050] The optical transmit signal generator 510 includes a plurality of optical transmit signal stages EM. A single optical transmit signal line 151 is connected to one corresponding optical transmit signal stage EM and thus receives the optical transmit signal from the optical transmit signal stage EM.

[0051] The light emission signal output from one light emission signal stage EM is formed to be applied simultaneously (or concurrently) to the pixels PX connected to two pixel rows. Figure 1 , the light emission signal level represented by EM[1,2] indicates that the emission signal is applied simultaneously (or concurrently) to the first pixel row and the second pixel row. However, according to some example embodiments, the light emission signal may be applied to only one pixel row, or may be applied to three or more pixel rows in common. As described, one light emission signal level EM may be connected to n light emission signal lines 151, and the light emission signal may be applied simultaneously (or concurrently) to the pixels PX included in the n pixel rows. Here, n is a natural number of 1 or greater.

[0052] exist Figure 1 , the first light emission signal level EM[1,2], the second light emission signal level EM[3,4], the third light emission signal level EM[5,6], the fourth light emission signal level EM[7,8] and the fifth light emission signal level EM[9,10] are shown sequentially placed from the top, but they may be only part of the light emission signal generator 510, and the light emission signal generator 510 may include a plurality of light emission signal levels to which high voltages are sequentially applied.

[0053] The first light emission signal level EM[1,2], the second light emission signal level EM[3,4], the third light emission signal level EM[5,6], the fourth light emission signal level EM[7,8] and the fifth light emission signal level EM[9,10] are connected to the first clock signal transmission line CLK1 and the third clock signal transmission line CLK3 and thus receive clock signals.

[0054] Similar to the first light emission signal stage EM[1,2], the third light emission signal stage EM[5,6], and the fifth light emission signal stage EM[9,10], the odd-numbered light emission signal stages are connected to the first high voltage transmission line VGH1 and thus receive a high voltage from the first high voltage transmission line VGH1. Similarly, similar to the second light emission signal stage EM[3,4] and the fourth light emission signal stage EM[7,8], the even-numbered light emission signal stages are connected to the second high voltage transmission line VGH2 and thus receive a high voltage from the second high voltage transmission line VGH2.

[0055] As described, odd-numbered light emission signal stages and even-numbered light emission signal stages are connected to different high voltage transmission lines, so that changes in the magnitude of applied high voltage caused by signal interference between adjacent light emission signal stages can be reduced.

[0056] A light emission signal having a low level voltage (corresponding to the light emitting segment) and a high level voltage (corresponding to the write segment) is applied alternately. One frame includes a high level voltage segment (write segment). In addition, compared with the time period during which a gate turn-on voltage is applied, the light emission signal having a low level voltage and a high level voltage is applied over a longer time period. Due to such a feature, the light emission signal can be applied to multiple light emission signal lines 151 simultaneously (or concurrently). However, the time period during which a gate turn-on voltage is applied is very short, so that the gate signal is applied only to one scan line 121 and one previous scan line 123 of each scan signal level GD.

[0057] Next, refer to Figure 2 , the light emission signal generator will be described in more detail. Figure 2 is a block diagram of a portion of an optical transmit signal generator according to some example embodiments.

[0058] Reference Figure 2 The light emission signal generator 510 includes a plurality of light emission signal stages EM and is connected to the first clock signal transmission line CLK1, the third clock signal transmission line CLK3, the first high voltage transmission line VGH1, and the second high voltage transmission line VGH2.

[0059] Each optical emission signal stage EM of the optical emission signal generator 510 includes a first clock input terminal In1 and a second clock input terminal In2 for receiving two clock signals, a control terminal ACL_FLM for receiving a control signal FLM or an optical emission signal from the optical emission signal stage EM of the previous stage, and an output terminal Out for outputting an optical emission signal.

[0060] The light emission signal stage EM[1,2] (hereinafter referred to as the first light emission stage) that applies the light emission signal to the first light emission signal line EM line 1 and the second light emission signal line EM line 2 applies the light emission signal to the pixels PX connected to the first pixel row and the second pixel row. As a result, the pixels PX connected to the first pixel row and the second pixel row simultaneously (or concurrently) emit light.

[0061] A control signal FLM is externally applied to a control terminal ACL_FLM of the first light emission signal stage EM[1,2], a first clock signal EM_CLK1 is applied to a first clock input terminal In1, and a third clock signal EM_CLK3 is applied to a second clock input terminal In2. The first light emission signal stage EM[1,2] is connected to a first high voltage transmission line VGH1 and thus receives a high voltage from the first high voltage transmission line VGH1.

[0062] The light emission signal is applied to the first light emission signal line EM line 1 and the second light emission signal line EM line 2 through the output terminal Out of the first light emission signal stage EM[1,2].

[0063] The light emission signal output from the first light emission signal stage EM[1,2] is applied to the control terminal ACL_FLM of the next second light emission signal stage EM[3,4] as a carry signal.

[0064] The light emission signal level EM[3,4] (hereinafter referred to as the second light emission signal level) that applies the light emission signal to the third light emission signal line EM line 3 and the fourth light emission signal line EM line 4 applies the light emission signal to the pixels PX connected to the third pixel row and the fourth pixel row. Therefore, all the pixels PX connected to the third pixel row and the fourth pixel row simultaneously (or concurrently) emit light.

[0065] In the second light emission signal stage EM[3,4], the light emission signal is applied as a carry signal from the first light emission signal stage EM[1,2] to the control terminal ACL_FLM, the third clock signal EM_CLK3 is applied to the first clock input terminal In1, and the first clock signal EM_CLK1 is applied to the second clock input terminal In2. At the same time, the second light emission signal stage EM[3,4] is connected to the second high voltage transmission line VGH2 and thus receives a high voltage from the second high voltage transmission line VGH2.

[0066] In addition, the light emission signal is applied to the third light emission signal line EM line 3 and the fourth light emission signal line EM line 4 through the output terminal Out of the second light emission signal stage EM[3,4].

[0067] Meanwhile, the light emission signal output from the second light emission signal stage EM[3,4] serves as a carry signal and is applied to the control terminal ACL_FLM of the third light emission signal stage EM[5,6].

[0068] The light emission signal level EM[5,6] (hereinafter referred to as the third light emission signal level) in which the light emission signal is applied to the fifth light emission signal line EM line 5 and the sixth light emission signal line EM line 6 applies the light emission signal to the pixels PX connected to the fifth pixel row and the sixth pixel row. Therefore, all the pixels PX connected to the fifth pixel row and the sixth pixel row simultaneously (or concurrently) emit light.

[0069] In the third light emission signal stage EM[5,6], the light emission signal is applied as a carry signal from the second light emission signal stage EM[3,4] to the control terminal ACL_FLM, the first clock signal EM_CLK1 is applied to the first clock input terminal In1, and the third clock signal EM_CLK3 is applied to the second clock input terminal In2. The third light emission signal stage EM[5,6] is connected to the first high voltage transmission line VGH1 and is therefore applied with the high voltage from the first high voltage transmission line VGH1.

[0070] In addition, the light emission signal is applied to the fifth light emission signal line EM line 5 and the sixth light emission signal line EM line 6 through the output terminal Out of the third light emission signal stage EM[5,6].

[0071] Meanwhile, the light emission signal output from the third light emission signal stage EM[5,6] serves as a carry signal and is applied to the control terminal ACL_FLM of the fourth light emission signal stage.

[0072] Through such a process, the plurality of light transmit signal stages EM of the light transmit signal generator 510 sequentially apply light transmit signals.

[0073] Similar to the first light emission signal level EM[1,2], the third light emission signal level EM[5,6], and the fifth light emission signal level EM[9,10], the odd-numbered light emission signal levels are connected to the first high voltage transmission line VGH1 and receive a high voltage from the first high voltage transmission line VGH1. Similarly, the even-numbered light emission signal levels, similar to the second light emission signal level EM[3,4] and the fourth light emission signal level EM[7,8], are connected to the second high voltage transmission line VGH2 and thus receive a high voltage from the second high voltage transmission line VGH2.

[0074] As described, the odd-numbered light emission signal stages and the even-numbered light emission signal stages are connected to different high-voltage transmission lines, thereby reducing changes in the magnitude of the applied high voltage due to signal interference between adjacent light emission signal stages. This will be described in more detail later.

[0075] According to some example embodiments, one light emission signal stage EM is connected to two pixel rows and thus applies light emission signals thereto, but according to some example embodiments, one light emission signal stage EM is connected to three or more pixel rows and thus may apply light emission signals thereto.

[0076] Next, refer to Figures 5 to 10 , will be with Figure 3 and Figure 4 The operation of the optical emission signal stage EM is described together. Figure 3is a circuit diagram of a stage in an optical transmit signal generator according to some example embodiments, Figure 4 is a waveform diagram of a signal applied to a stage according to some example embodiments. Figures 5 to 10 is provided for describing Figure 3 A diagram of the operations at the level .

[0077] Each of the optical emission signal stages EM of the optical emission signal generator 510 according to some example embodiments includes a high level output portion 551, a low level output portion 552, a first node first controller 553, a first node second controller 554, a second node first controller 555, a second node second controller 556, and a third node controller 557.

[0078] The high-level output portion 551 is a portion that outputs the high voltage VGH of the light emission signal, and the low-level output portion 552 is a portion that outputs the low voltage VGL of the light emission signal. The high-level output portion 551 and the low-level output portion 552 are connected to the output terminal Out, and when the high voltage VGH is output from the high-level output portion 551, the low-level output portion 552 does not output the low voltage VGL, and when the low-level output portion 552 outputs the low voltage VGL, the high-level output portion 551 does not output the high voltage VGH.

[0079] The high level output part 551 is controlled according to the voltage of the first node N1 , and the voltage of the first node N1 is controlled by the first node first controller 553 and the first node second controller 554 of the first node N1 .

[0080] The low level output portion 552 is controlled according to the voltage of the second node N2, and the voltage of the second node N2 is controlled by the second node first controller 555 and the second node second controller 556. Figure 3 In the embodiment, the second-node first controller 555 is divided into a first sub-second-node first controller 555-1 and a second sub-second-node first controller 555-2.

[0081] The first node second controller 554 is controlled by the voltage of the third node N3 , and the voltage of the third node N3 is controlled by the third node controller 557 .

[0082] and Figure 2 The odd-numbered optical emission signal level EM is similar, Figure 3In the optical emission signal stage EM, the first clock signal line for the clock signal is connected to the first clock input terminal In1 and thus the first clock signal EM_CLK1 is applied, and the second clock signal line for the clock signal is connected to the second clock input terminal In2 and thus the third clock signal EM_CLK3 is applied. Conversely, a clock signal opposite to the clock signal applied to the odd-numbered optical emission signal stage EM may be applied to the even-numbered optical emission signal stage EM.

[0083] Each part will now be described in detail.

[0084] The high-level output portion 551 includes a ninth transistor T9, and a control electrode of the ninth transistor T9 is connected to the first node N1, an input electrode is connected to a terminal of a high voltage VGH, and an output electrode is connected to the output terminal Out. Therefore, when the voltage of the first node N1 is a low voltage, the high voltage VGH is output to the output terminal Out, and when the voltage of the first node N1 is a high voltage, the ninth transistor T9 does not output anything.

[0085] The low-level output portion 552 includes a tenth transistor T10, and a control electrode of the tenth transistor T10 is connected to the second node N2, an input electrode is connected to a terminal of the low voltage VGL, and an output electrode is connected to the output terminal Out. Therefore, when the voltage of the second node N2 is a low voltage, the low voltage VGL is output to the output terminal Out, and when the voltage of the second node N2 is a high voltage, the tenth transistor T10 does not output anything.

[0086] The voltage of the first node N1 is controlled by the first-node first controller 553 and the first-node second controller 554 .

[0087] The first node first controller 553 includes a transistor (i.e., an eighth transistor) T8 and a capacitor (i.e., a first capacitor) C1. The control electrode of the eighth transistor T8 is connected to the second node N2, the input electrode is connected to the high voltage VGH, and the output electrode is connected to the first node N1. At the same time, the two electrodes of the first capacitor C1 are respectively connected to the input electrode and the output electrode of the eighth transistor T8, so that the first capacitor C1 is connected between the first node N1 and the terminal of the high voltage VGH. When the voltage of the second node N2 is a low voltage, the eighth transistor T8 transmits the high voltage VGH to the first node N1, and the first capacitor C1 stores and maintains the voltage of the first node N1. In other words, the first node first controller 553 is used to change the voltage of the first node N1 to the high voltage VGH.

[0088] At the same time, the first node second controller 554 includes two transistors (i.e., a sixth transistor T6 and a seventh transistor T7) and a capacitor (i.e., a second capacitor C2). The control electrode of the sixth transistor T6 is connected to the first clock input terminal In1, the output electrode is connected to the first node N1, and the input electrode is connected to the fourth node N4. The control electrode of the seventh transistor T7 is connected to the third node N3, the output electrode is connected to the fourth node N4, and the input electrode is connected to the first clock input terminal In1. Here, the input electrode and the output electrode can have opposite inputs and outputs depending on the size of the connected voltage. The first node second controller 554 is used to change the voltage of the first node N1 to the low voltage of the clock signal.

[0089] Meanwhile, the second capacitor C2 is connected between the third node N3 and the fourth node N4, and the voltage of the fourth node N4 may be boosted by using the voltage difference between the two nodes.

[0090] The voltage of the second node N2 is controlled by the second-node first controller 555 and the second-node second controller 556 .

[0091] The second-node first controller 555 is formed by a first sub-second-node first controller 555-1 and a second sub-second-node first controller 555-2. The first sub-second-node first controller 555-1 is formed by a transistor (i.e., the first transistor T1), and the second sub-second-node first controller 555-2 is formed by a capacitor (i.e., the third capacitor C3). The control electrode of the first transistor T1 is connected to the second clock input terminal In2, the input electrode is connected to the control terminal ACL_FLM, and the output electrode is connected to the second node N2. One electrode of the third capacitor C3 is connected to the second node N2, and the other electrode is connected to the first clock input terminal In1.

[0092] Due to the structure of the third capacitor C3, the voltage at the second node N2 may also change due to the variable clock signal applied to the first clock input terminal In1. Therefore, to reduce fluctuations in the voltage at the second node N2, the capacitance of the third capacitor C3 can be set high. As a result, although the clock signal applied to one side of the third capacitor C3 changes, the voltage on the other side (i.e., the voltage at the second node N2) does not change significantly. Due to this third capacitor C3, the capacitance of the first clock input terminal In1 has a very high value compared to the capacitance of the second clock input terminal In2.

[0093] When the third clock signal EM_CLK3 applied to the second clock input terminal In2 has a low voltage, the first transistor T1 included in the second node first controller 555 changes the voltage of the second node N2 to the voltage of the control signal FLM or the voltage of the light emission signal of the previous stage, and the third capacitor C3 stores and holds the changed voltage. That is, the second node first controller 555 is used to change the voltage of the second node N2 to a high voltage or a low voltage according to the carry signal (i.e., the control signal FLM or the light emission signal of the previous stage).

[0094] The second node second controller 556 is formed by two transistors (i.e., a second transistor T2 and a third transistor T3). The control electrode of the second transistor T2 is connected to the third node N3, the input electrode is connected to the terminal of the high voltage VGH, and the output electrode is connected to the input electrode of the third transistor T3. The control electrode of the third transistor T3 is connected to the first clock input terminal In1, the input electrode is connected to the output electrode of the second transistor T2, and the output electrode is connected to the second node N2. In other words, the second node second controller 556 can prevent the voltage of the second node N2 from changing to a low voltage by connecting the high voltage VGH to the second node N2.

[0095] The third node controller 557 is formed of two transistors (i.e., a fourth transistor T4 and a fifth transistor T5). The control electrode of the fourth transistor T4 is connected to the second node N2, the input electrode is connected to the second clock input terminal In2, and the output electrode is connected to the third node N3. The control electrode of the fifth transistor T5 is connected to the second clock input terminal In2, the input electrode is connected to the terminal of the low voltage VGL, and the output electrode is connected to the third node N3. The fifth transistor T5 is used to make the voltage of the third node N3 the low voltage VGL, and the fourth transistor T4 is used to make the voltage of the third node N3 the voltage of the second clock input terminal In2, so that the voltage of the third node N3 becomes a high voltage (i.e., the high voltage of the clock signal).

[0096] The light emission signal stage EM having such a configuration operates according to the signal applied to the first clock input terminal In1, the second clock input terminal In2 and the control terminal ACL_FLM, and this will be referred to as Figures 4 to 10 Provide a description.

[0097] Figure 4 is a waveform of a signal applied to the stage according to some example embodiments, and Figures 5 to 10 Provided for description Figure 3 level of operation.

[0098] First, refer to Figure 4Signals applied to the first clock input terminal In1, the second clock input terminal In2, and the control terminal ACL_FLM of the optical emission signal stage EM are described. According to some example embodiments, a first clock signal EM_CLK1 is applied to the first clock input terminal In1, and a third clock signal EM_CLK3 is applied to the second clock input terminal In2. The first clock signal EM_CLK1 and the third clock signal EM_CLK3 are clock signals in which high voltage and low voltage are repeated, and have inversion characteristics relative to each other.

[0099] At the same time, the externally applied control signal FLM is transmitted as a carry signal to the control terminal ACL_FLM of the first light emission signal stage EM[1,2], and the output signal of the previous light emission signal stage is transmitted as a carry signal to the second light emission signal stage EM[3,4]. The control signal FLM and the light emission signal have a high voltage section during one frame, and the control signal FLM and the light emission signal having a low voltage are applied during the remaining sections. The high voltage section is a section during which the data voltage is written to the pixel PX (i.e., a write section), and the pixel PX emits light during the low voltage section (i.e., a light emitting section).

[0100] exist Figure 4 In FIG, the scanning signal GI and the previous scanning signal GW are shown. Figure 4 , the scan signal with a low voltage is applied three times during one frame period, but this is merely an example, and according to some example embodiments, the scan signal with a low voltage may be applied once, or the scan signal with a low voltage may be applied a plurality of times different from one or three times. The current-level scan signal GI and the previous-level scan signal GW applied to one pixel PX should exist during one high-voltage section (i.e., a writing section) of the light emission signal applied to the corresponding pixel PX.

[0101] exist Figure 4 , the voltage applied to the light emission signal level is divided into sections (a), (b), (c), (d), (e) and (f). Figures 5 to 10 Describe the operation of the light transmission signal level for each segment. Figures 5 to 10 In FIG. 1 , when the transistor is off, it is marked with an X, and when the transistor is on and performing the main operation, it is marked with a straight line connecting the input electrode and the output electrode of the transistor. In addition, for ease of viewing, the voltages at the first node N1, the second node N2, the third node N3, and the fourth node N4 are shown in parentheses. H in the parentheses indicates a high voltage, and L indicates a low voltage.

[0102] First, refer to Figure 5 , the operation of the light emission signal level EM at section (a) will be described.

[0103] In section (a), a control signal FLM having a low voltage is applied to the control terminal ACL_FLM, a first clock signal EM_CLK1 having a high voltage is applied to the first clock input terminal In1 , and a third clock signal EM_CLK3 having a low voltage is applied to the second clock input terminal In2 .

[0104] Since the first clock signal EM_CLK1 has a high voltage, the third transistor T3 and the sixth transistor T6 are turned off, and the first transistor T1 and the fifth transistor T5 are turned on by the low-voltage third clock signal EM_CLK3. The low-voltage control signal FLM is applied to the second node N2 via the first transistor T1, causing the low voltage at the second node N2 to be stored in the third capacitor C3. The low voltage at the second node N2 turns on the tenth transistor T10, and the low voltage VGL is output to the output terminal Out. In addition, the low voltage at the second node N2 turns on the eighth transistor T8, causing the first node N1 to reach a high voltage VGH, and the two ends of the first capacitor C1 to reach a high voltage VGH. As a result, the ninth transistor T9 is turned off.

[0105] In addition, the fourth transistor T4 is turned on by the low voltage of the second node N2, so the third clock signal EM_CLK3 with a low voltage is applied, so that the voltage of the third node N3 is applied to a low voltage. In addition, the low voltage VGL is also applied through the fifth transistor T5.

[0106] The seventh transistor T7 is turned on by the low voltage VGL of the third node N3 and the high voltage first clock signal EM_CLK1 is applied to the fourth node N4. Therefore, a high voltage (fourth node N4) and a low voltage (third node N3) are applied to opposite ends of the second capacitor C2.

[0107] In addition, the second transistor T2 is turned on by the low voltage VGL of the third node N3 , but the third transistor T3 is turned off, so the high voltage VGH is not transmitted to the second node N2 but is transmitted only to the input electrode of the third transistor T3 .

[0108] That is, in section (a), the first node N1 is applied with a high voltage H, the second node N2 is applied with a low voltage L, the third node N3 is applied with a low voltage L, and the fourth node N4 is applied with a high voltage H, and as a main operation, the tenth transistor T10 is turned on due to the low voltage L of the second node N2, so the low voltage VGL is applied to the output terminal Out. In this case, the pixel PX receiving the light emission signal is in the light emission section during which the pixel PX emits light.

[0109] Next, refer to Figure 6 , the operation in section (b) of the light emission signal level will be described.

[0110] In section (b), the control signal FLM maintains a low voltage, the first clock signal EM_CLK1 changed to a low voltage is applied to the first clock input terminal In1 , and the third clock signal EM_CLK3 changed to a high voltage is applied to the second clock input terminal In2 .

[0111] The third transistor T3 and the sixth transistor T6 are turned on by the low-voltage first clock signal EM_CLK1, and the first transistor T1 and the fifth transistor T5 are turned off by the high-voltage third clock signal EM_CLK3. Because the first transistor T1 is in the off state, the low voltage stored in the third capacitor C3 is maintained, and the voltage of the second node N2 has a low voltage value. Therefore, the tenth transistor T10 is turned on, and the low voltage VGL is output to the output terminal Out.

[0112] In addition, the eighth transistor T8 is also turned on by the low voltage of the second node N2, so the first node N1 becomes the high voltage VGH, the ninth transistor T9 remains in the off state, and the opposite end of the first capacitor C1 becomes the high voltage VGH.

[0113] In addition, the fourth transistor T4 is also turned on by the low voltage of the second node N2, so the high voltage third clock signal EM_CLK3 is applied to the third node N3, so that the voltage of the third node N3 changes to a high voltage value. In this case, because the fifth transistor T5 is in the off state, the voltage of the third node N3 changes to a high voltage due to the input of the fourth transistor T4.

[0114] The seventh transistor T7 is turned off due to the high voltage of the third node N3, and the sixth transistor T6 is turned on due to the low voltage of the first clock signal EM_CLK1, so that the first node N1 and the fourth node N4 are connected to each other. In this case, the voltage of the third node N3 connected to the second capacitor C2 changes from a low voltage to a high voltage, so the voltage of the fourth node N4 and the voltage of the first node N1 connected to the fourth node N4 increase. Therefore, the voltage of the first node N1 can have a voltage value higher than the high voltage VGH.

[0115] At the same time, the second transistor T2 remains in an off state due to the high voltage at the third node N3, and the third transistor T3 is turned on by the low-voltage first clock signal EM_CLK1. In this case, when the third transistor T3 is turned on in segment (b), the high voltage VGH transmitted to the input electrode of the third transistor T3 via the second transistor T2 in segment (a) can be transmitted to the second node N2. Therefore, an undesirable voltage drop at the second node N2 can be prevented or reduced. That is, the first clock signal EM_CLK1 is applied to one end of the third capacitor C3, but the first clock signal EM_CLK1 changes from a high voltage to a low voltage in segment (b), so the voltage of the second node N2 may drop. However, the voltage of the second node N2 can be maintained by the high voltage VGH applied by the second controller 556 via the second node. In addition, regardless of the swing of the voltage level of the first clock signal EM_CLK1, the capacitance of the third capacitor C3 is increased to maintain the voltage of the second node N2 constant.

[0116] That is, in section (b), the first node N1 and the fourth node N4 are applied with the increased high voltage H, the second node N2 is applied with the low voltage L, and the third node N3 is applied with the high voltage H, and as the main operation, the tenth transistor T10 is turned on by the low voltage of the second node N2, so that the low voltage VGL is continuously applied to the output terminal Out. In this case as well, the pixel PX receiving the light emission signal is in the light emission section, so that the pixel PX emits light.

[0117] Comparing sections (a) and (b), the clock signal is inverted and applied, but the voltage of the first node N1 is maintained at a high voltage, the voltage of the second node N2 is maintained at a low voltage, and the low voltage VGL is continuously output to the output terminal Out.

[0118] Next, refer to Figure 7 , the operation of the light emission signal level in section (c) will be described.

[0119] In section (c), the control signal FLM changes to a high voltage, the first clock signal EM_CLK1 changed to a high voltage is applied to the first clock input terminal In1 , and the third clock signal EM_CLK3 changed to a low voltage is applied to the second clock input terminal In2 .

[0120] The third transistor T3 and the sixth transistor T6 are turned off by the high-voltage first clock signal EM_CLK1, while the first transistor T1 and the fifth transistor T5 are turned on by the low-voltage third clock signal EM_CLK3. A high-voltage control signal FLM is applied to the second node N2 via the first transistor T1, causing the voltage of the second node N2 to change to a high voltage, which is then stored in the third capacitor C3. The high voltage at the second node N2 turns off the tenth transistor T10. Furthermore, the high voltage at the second node N2 turns off the eighth transistor T8.

[0121] At the same time, because the fifth transistor T5 is turned on, the low voltage VGL is applied to the third node N3. In this case, because the second node N2 has a high voltage, the fourth transistor T4 is turned off. Therefore, the voltage of the third node N3 is controlled by the fifth transistor T5 and changes to the low voltage VGL.

[0122] The second transistor T2 and the seventh transistor T7 are turned on due to the low voltage at the third node N3. The seventh transistor T7 is turned on, so the high voltage first clock signal EM_CLK1 is applied to the fourth node N4. Consequently, a high voltage (the fourth node N4) and a low voltage (the third node N3) are applied to the corresponding ends of the second capacitor C2. Furthermore, the second transistor T2 is turned on, but the third transistor T3 is turned off, so that the high voltage VGH is transmitted only to the input electrode of the third transistor T3, and the high voltage VGH is not transmitted to the second node N2.

[0123] Since the sixth transistor T6 and the eighth transistor T8 are turned off, the voltage of the first node N1 in the section (b) is maintained, thereby maintaining a high voltage state.

[0124] That is, in section (c), the first node N1 is applied with a high voltage H, the second node N2 is applied with a high voltage H, the third node N3 is applied with a low voltage L, and the fourth node N4 is applied with a high voltage H, and the tenth transistor T10 and the ninth transistor T9 are both in an off state, so no voltage can be output to the output terminal Out. For example, the low voltage VGL is output until the voltage of the second node N2 becomes the off voltage of the tenth transistor T10, and when the tenth transistor T10 is turned off, the output voltage gradually increases.

[0125] Next, refer to Figure 8 , the operation of the light emission signal level in section (d) will be described.

[0126] In section (d), the control signal FLM is maintained at a high voltage, the first clock signal EM_CLK1 changes to a low voltage and is then applied to the first clock input terminal In1 , and the third clock signal EM_CLK3 changes to a high voltage and is then applied to the second clock input terminal In2 .

[0127] The third transistor T3 and the sixth transistor T6 are turned on by the first clock signal EM_CLK1 of a low voltage, and the first transistor T1 and the fifth transistor T5 are turned off by the third clock signal EM_CLK3 of a high voltage.

[0128] Because the first transistor T1 is in the off state, the high voltage stored in the third capacitor C3 is maintained, so that the voltage at the second node N2 has a high voltage value. Therefore, the tenth transistor T10 remains in the off state. In addition, due to the high voltage at the second node N2, the eighth transistor T8 and the fourth transistor T4 also remain in the off state.

[0129] The fifth transistor T5 is turned off by the high voltage third clock signal EM_CLK3. Since both the fourth transistor T4 and the fifth transistor T5 are turned off, the voltage at the third node N3 does not change and remains at a low voltage, which is the voltage at the third node N3 in section (c).

[0130] The seventh transistor T7 remains in the on state due to the low voltage of the third node N3, and the sixth transistor T6 is turned on by the low voltage first clock signal EM_CLK1, so that the first node N1, the fourth node N4, and the low voltage first clock signal EM_CLK1 are connected to each other. Therefore, the voltage at the first node N1 and the voltage at the fourth node N4 change to a low voltage. The ninth transistor T9 is turned on by the low voltage first node N1, and thus the high voltage VGH is output to the output terminal Out.

[0131] At the same time, the second transistor T2 is turned on by the low voltage of the third node N3, and the third transistor T3 is also turned on by the low voltage first clock signal EM_CLK1, so that the terminal of the high voltage VGH is connected to the second node N2. Therefore, the voltage of the second node N2 remains at the high voltage VGH, so that the tenth transistor T10 cannot be turned on.

[0132] That is, in section (d), the first node N1 and the fourth node N4 are applied with a low voltage L, the second node N2 is applied with a high voltage H, and the third node N3 is applied with a low voltage L, and as a main operation, the ninth transistor T9 is turned on by the low voltage of the first node N1, so that the high voltage VGH is output to the output terminal Out. In this case, the pixel PX receiving the light emission signal is in the writing section, and during this writing section, the data voltage is stored in the capacitor in the pixel PX.

[0133] Next, refer to Figure 9 , the operation of the light emission signal level in section (e) will be described.

[0134] In section (e), the control signal FLM maintains a high voltage, the first clock signal EM_CLK1 changes to a high voltage and is then applied to the first clock input terminal In1 , and the third clock signal EM_CLK3 changes to a low voltage and is then applied to the second clock input terminal In2 .

[0135] The third transistor T3 and the sixth transistor T6 are turned off due to the high voltage first clock signal EM_CLK1 , and the first transistor T1 and the fifth transistor T5 are turned on due to the low voltage third clock signal EM_CLK3 .

[0136] A high voltage control signal FLM is applied to the second node N2 via the first transistor T1, so that the voltage of the second node N2 remains high. The tenth transistor T10 is turned off due to the high voltage of the second node N2. In addition, the eighth transistor T8 and the fourth transistor T4 also remain in the off state due to the high voltage of the second node N2.

[0137] The fifth transistor T5 is turned on, so the low voltage VGL is applied to the third node N3. In this case, since the fourth transistor T4 is turned off, the fourth transistor T4 cannot change the voltage of the third node N3.

[0138] The third node N3 has a low voltage VGL, so the second transistor T2 and the seventh transistor T7 are turned on. The seventh transistor T7 is turned on, so the high voltage first clock signal EM_CLK1 is applied to the fourth node N4. Therefore, opposite ends of the second capacitor C2 are applied with a high voltage (fourth node N4) and a low voltage (third node N3), respectively.

[0139] In addition, the second transistor T2 is turned on but the third transistor T3 is turned off, so the high voltage VGH is transmitted only to the input electrode of the third transistor T3 but not to the second node N2.

[0140] Since the sixth transistor T6 is turned off by the high voltage first clock signal EM_CLK1, the voltage stored in the first capacitor C1 does not change and the voltage of the first node N1 remains low. Therefore, the ninth transistor T9 is turned on and the high voltage VGH is continuously output to the output terminal Out.

[0141] That is, in section (e), the first node N1 is applied with a low voltage L, the second node N2 is also applied with a high voltage H, the third node N3 is applied with a low voltage L, and the fourth node N4 is applied with a high voltage H, and the ninth transistor T9 remains in the on state, so that the high voltage VGH is output to the output terminal Out.

[0142] Comparing sections (d) and (e), the clock signal is inverted and then applied, but the voltage of the first node N1 remains low, so that the high voltage VGH is continuously output to the output terminal Out. In addition, the voltage of the second node N2 remains high, so that the low voltage VGL is not transmitted to the output terminal Out.

[0143] Next, refer to Figure 10 , the operation of the light emission signal level in section (f) will be described.

[0144] In section (f), the control signal FLM changes to a low voltage, the first clock signal EM_CLK1 changes to a high voltage and is applied to the first clock input terminal In1 , and the third clock signal EM_CLK3 changes to a low voltage and is then applied to the second clock input terminal In2 .

[0145] Furthermore, section (f) is applied after the section in the same state as section (d). Therefore, it will be described as the section applied next to section (d).

[0146] The third transistor T3 and the sixth transistor T6 are turned off by the first clock signal EM_CLK1 of a high voltage, and the first transistor T1 and the fifth transistor T5 are turned on by the third clock signal EM_CLK3 of a low voltage.

[0147] A low voltage control signal is applied to the second node N2 via the first transistor T1, causing the voltage of the second node N2 to change to a low voltage, and turning on the tenth transistor T10. Consequently, the low voltage VGL begins to be output to the output terminal Out. Due to the low voltage at the second node N2, the eighth transistor T8 and the fourth transistor T4 are also turned on.

[0148] Because the eighth transistor T8 is turned on, the high voltage VGH is applied to the first node N1 , and the ninth transistor T9 is turned off due to the high voltage of the first node N1 , so that the high voltage VGH is no longer output to the output terminal Out.

[0149] When the fourth transistor T4 is turned on, the third clock signal EM_CLK3 of low voltage is applied to the third node N3. In addition, the low voltage VGL is applied to the third node N3 via the turned-on fifth transistor T5. Therefore, the third node N3 has a low voltage.

[0150] The second transistor T2 and the seventh transistor T7 are turned on due to the low voltage of the third node N3. The seventh transistor T7 is turned on, so the high voltage first clock signal EM_CLK1 is applied to the fourth node N4. Therefore, the high voltage (fourth node N4) and the low voltage (third node N3) are applied to the opposite ends of the second capacitor C2.

[0151] In addition, although the second transistor T2 is turned on, the third transistor T3 is turned off, so the high voltage VGH is transmitted only to the input electrode of the third transistor T3 but not to the second node N2.

[0152] Since the sixth transistor T6 is turned off due to the high voltage first clock signal EM_CLK1, the voltage of the first node N1 is not affected. Therefore, the voltage of the first node N1 is controlled by the eighth transistor T8, and the high voltage VGH is transmitted through the eighth transistor T8 and the voltage of the first node N1 is maintained at a high voltage.

[0153] That is, in section (f), the first node N1 is applied with a high voltage H, the second node N2 is applied with a low voltage L, the third node N3 is applied with a low voltage L, and the fourth node N4 is applied with a high voltage H, the ninth transistor T9 is turned off, and the tenth transistor T10 starts to turn on, so that the voltage of the output terminal Out changes from the high voltage VGH to the low voltage VGL and is then output.

[0154] After the segment (f), the segment corresponding to the segment (b) is positioned, and thereafter the operation is repeated as described above.

[0155] The light emission signal stage outputs a light emission signal delayed by half a clock cycle from the control signal. That is, because the carry signal applied to the light emission signal stage of the next stage is delayed by half a clock cycle, the application timing of the high voltage VGH in the output light emission signal is also sequentially output by delaying half a clock cycle.

[0156] Next, we will refer to Figure 11 An output signal of a light emission signal stage according to some example embodiments is described in detail. Figure 11 is a waveform diagram of an output signal of a light emission signal generator according to some example embodiments.

[0157] Reference Figure 11, the first output signal GC[1,2] of the first light emission signal stage EM[1,2] maintains the high voltage VGH, and then after driving two pixel rows connected to the first light emission signal stage EM[1,2] for two horizontal periods of 2H, the second output signal GC[3,4] of the second light emission signal stage EM[3,4] changes from the low voltage VGL to the high voltage VGH. Subsequently, the third output signal GC[5,6] of the third light emission signal stage EM[5,6] changes from the low voltage VGL to the high voltage VGH (refer to D1). Similarly, after two horizontal periods of 2H, the fourth output signal GC[7,8] of the fourth light emission signal stage EM[7,8] changes from the low voltage VGL to the high voltage VGH (refer to DD1), and then the fifth output signal GC[9,10] of the fifth light emission signal stage EM[9,10] changes from the low voltage VGL to the high voltage VGH (refer to D2). And similarly, thereafter, the output signal GC[n,n+1] changes from the low voltage VGL to the high voltage VGH.

[0158] As described above, the odd-numbered light emission signal levels (such as the first light emission signal level EM[1,2], the third light emission signal level EM[5,6], and the fifth light emission signal level EM[9,10]) are connected to the first high voltage transmission line VGH1 and thus receive a high voltage from the first high voltage transmission line VGH1. In addition, the even-numbered light emission signal levels (such as the second light emission signal level EM[3,4] and the fourth light emission signal level EM[7,8]) are connected to the second high voltage transmission line VGH2 and thus receive a high voltage from the second high voltage transmission line VGH2.

[0159] When a high voltage is applied to the third optical emission signal stage EM[5,6] connected to the first high voltage transmission line VGH1 (D1), the signal resistance of the first output signal GC[1,2] of the first optical emission signal stage EM[1,2] connected to the first high voltage transmission line VGH1 as the same high voltage transmission line and thus receiving the high voltage from the first high voltage transmission line VGH1 may increase, and interference may occur, so that the magnitude of the high voltage VGH of the first output signal GC[1,2] of the first optical emission signal stage EM[1,2] may change. Similarly, when a high voltage is applied to the fifth optical emission signal stage EM[9,10] connected to the first high voltage transmission line VGH1 (D2), the intensity of the first output signal GC[1,2] of the first optical emission signal stage EM[1,2] connected to the first high voltage transmission line VGH1 as the same high voltage transmission line and the intensity of the third output signal GC[5,6] of the third optical emission signal stage EM[5,6] may change.

[0160] In addition, similar to the second light emission signal level EM[3,4] and the fourth light emission signal level EM[7,8] that are connected to the second high voltage transmission line VGH2 and receive a high voltage from the second high voltage transmission line VGH2, the second output signal GC[3,4] and the fourth output signal GC[7,8] of the even-numbered light emission signal levels may experience intensity variations due to the resistance of the second high voltage transmission line VGH2 and signal interference between the second output signal GC[3,4] and the fourth output signal GC[7,8].

[0161] When odd-numbered light emission signal levels (e.g., the first light emission signal level EM[1,2], the third light emission signal level EM[5,6], and the fifth light emission signal level EM[9,10]) and even-numbered light emission signal levels (e.g., the second light emission signal level EM[3,4] and the fourth light emission signal level EM[7,8]) are all connected to the same high voltage transmission line, the high voltage output value of the first light emission signal level EM[1,2] changes when a high voltage is sequentially applied to the light emission signal level of the next stage (e.g., the second output signal GC[3,4] of the second light emission signal level EM[3,4] and the third output signal GC[5,6] of the third light emission signal level EM[5,6]) for every two horizontal periods 2H. In addition, when a high voltage is sequentially applied to the light emission signal level at the next stage for every two horizontal periods 2H, the high voltage value of the second output signal GC[3,4] of the second light emission signal level EM[3,4] is also changed.

[0162] That is, sequentially, whenever a high voltage is applied to the light emission signal stage of the next stage for every two horizontal periods 2H, a high voltage value input to and output from the light emission signal stage of the previous stage changes.

[0163] However, in an organic light emitting diode (OLED) display according to some example embodiments, odd-numbered light emission signal levels (such as the first light emission signal level EM[1,2], the third light emission signal level EM[5,6], and the fifth light emission signal level EM[9,10]) are connected to the first high voltage transmission line VGH1 and thus receive a high voltage from the first high voltage transmission line VGH1, and even-numbered light emission signal levels (such as the second light emission signal level EM[3,4] and the fourth light emission signal level EM[7,8]) are connected to the second high voltage transmission line VGH2 and thus receive a high voltage from the second high voltage transmission line VGH2.

[0164] In this way, the odd-numbered light emission signal stages and the even-numbered light emission signal stages are connected to different high voltage transmission lines, so the magnitude of the high voltage input to the even-numbered light emission signal stages and the magnitude of the high voltage input to the odd-numbered light emission signal stages may not affect each other.

[0165] Therefore, it is possible to reduce the change in the magnitude of the high voltage applied to and output from the light emission signal stage by signal interference between the high voltage input to the odd-numbered light emission signal stage and the high voltage input to the even-numbered light emission signal stage. In addition, whenever a high voltage is applied to the next stage of the light emission signal stage in a period longer than two horizontal periods 2H (for example, every four horizontal periods 4H), the magnitude of the high voltage of the light emission signal stage of the previous stage connected to the same first high voltage transmission line VGH1 can be changed.

[0166] Next, refer to Figure 11 and Figure 12 , a gate signal of an organic light emitting diode display according to another embodiment will be described. Figure 12 are waveform diagrams of some signals of an optical transmit signal generator according to some example embodiments.

[0167] As previously described, in the organic light emitting diode display according to some example embodiments, the odd-numbered light emission signal levels and the even-numbered light emission signal levels are connected to different high voltage transmission lines, so the magnitude of the high voltage input to the even-numbered light emission signal levels and the magnitude of the high voltage input to the odd-numbered light emission signal levels may not be affected by each other.

[0168] Therefore, it is possible to reduce the change in the magnitude of the high voltage applied to and output from the light emission signal stage by signal interference between the high voltage input to the odd-numbered light emission signal stage and the high voltage input to the even-numbered light emission signal stage. In addition, whenever a high voltage is applied to the next stage of the light emission signal stage in a period longer than two horizontal periods 2H (for example, every four horizontal periods 4H), the magnitude of the high voltage of the light emission signal stage of the previous stage connected to the same first high voltage transmission line VGH1 can be changed.

[0169] As in Figure 12 In the first position D1 and the second position D2 shown in FIG, when a high voltage is applied to the light emission signal level of the next stage for every four horizontal periods 4H, the magnitude of the high voltage of the light emission signal level of the previous stage connected to the first high voltage transmission line VGH1 can be changed. In this case, referring to Figure 12In the portion marked by C, the previous-stage scanning signal GW (e.g., GW[1] and GW[2]) may be input during the next (or next) two horizontal periods 2H of the period between the first position D1 and the second position D2 in which the magnitude of the high voltage of the light emission signal level changes. The previous-stage scanning signal GW may be input while the magnitude of the high voltage does not change, thereby preventing the change in the magnitude of the high voltage of the previous-stage light emission signal level from affecting the magnitude of the high voltage of the next-stage light emission signal level by adjusting the input timing of the previous-stage scanning signal GW, thereby not affecting the intensity of light emission of the two pixel rows connected to the next-stage light emission signal level.

[0170] Next, an organic light emitting diode display according to some example embodiments will be described in more detail. Figure 13 is a block diagram of an organic light emitting diode display according to some example embodiments.

[0171] Reference Figure 13 , an organic light emitting diode display according to some example embodiments and an organic light emitting diode display according to Figures 1 to 3 The organic light emitting diode displays of the exemplary embodiments shown and described are similar, and therefore, some detailed descriptions of similar components may be omitted.

[0172] Reference Figure 13 , and about Figures 1 to 3 Unlike the organic light emitting diode display according to some example embodiments shown and described, in the organic light emitting diode display according to some example embodiments, the scan signal generators 410 and 420, the light emission signal generators 510 and 520, the first clock signal transmission line CLK1, the third clock signal transmission line CLK3, the first high voltage transmission line VGH1, and the second high voltage transmission line VGH2 are respectively located at opposite sides of the display area 300. The two first clock signal transmission lines CLK1 located at opposite sides of the display area 300 may be connected to each other, and the two second high voltage transmission lines VGH2 located at opposite sides of the display area 300 may be connected to each other.

[0173] For example, the first scan signal generator 410 and the first light emission signal generator 510 are located at the right side of the display area 300 , and the second scan signal generator 420 and the second light emission signal generator 520 are located at the left side of the display area 300 .

[0174] The first scan signal generator 410 and the second scan signal generator 420 are connected to the same signal line and include a plurality of identical scan signal levels GD. In addition, the first light emission signal generator 510 and the second light emission signal generator 520 are connected to the same signal line and include a plurality of identical light emission signal levels EM.

[0175] As described, the first scan signal generator 410 and the second scan signal generator 420 and the first light emission signal generator 510 and the second light emission signal generator 520 of similar structures are placed at corresponding sides of the display area 300, thereby preventing signal delay of multiple pixels PX located in the same pixel row.

[0176] In addition, as in the organic light emitting diode display of the previously described example embodiments, in the organic light emitting diode display according to some example embodiments, the odd-numbered light emission signal stages are connected to the first high voltage transmission line VGH1 and thus receive a high voltage, and the even-numbered light emission signal stages are connected to the second high voltage transmission line VGH2 and thus receive a high voltage from the second high voltage transmission line VGH2.

[0177] As such, odd-numbered light emission signal levels and even-numbered light emission signal levels are connected to different high voltage transmission lines, thereby reducing a change in the magnitude of an applied high voltage due to signal interference between adjacent light emission signal levels.

[0178] In addition, when the high voltage level does not change, the previous stage scan signal GW may be input, thereby preventing the change in the high voltage level of the light emission signal level in the previous stage from affecting the high voltage level of the next light emission signal level.

[0179] Although the embodiments according to the present disclosure have been described in conjunction with what are presently considered to be practical example embodiments, it will be understood that the embodiments according to the present disclosure are not limited to the disclosed embodiments. On the contrary, the disclosed embodiments are intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims and their equivalents.

[0180] Description of some of the reference numerals

[0181] 300: Display area 410, 420: Scan signal generator

[0182] 510, 520: Light emission signal generator 121: Scan line

[0183] 123: Previous scan line 151: Light emission signal line

[0184] 551: High level output part 552: Low level output part

[0185] 553: First node first controller 554: First node second controller

[0186] 555: Second node first controller

[0187] 555-1: First child, second node, first controller

[0188] 555-2: Second child, second node, first controller

[0189] 556: Second node, second controller

[0190] 557: Third node controller EM: optical transmission signal level

[0191] GD: Scan signal level GI: Scan signal

[0192] GW: previous level scanning signal FLM: control signal

[0193] In1, In2: Clock input terminals Out: Output terminals

[0194] CLK1, CLK3: clock signal transmission lines

[0195] VGH1, VGH2: high voltage transmission lines

Claims

1. An organic light emitting diode display, comprising: a display area including a plurality of pixel rows configured to emit light in response to a light emission signal; a light emission signal generator located at a periphery of the display area and comprising a plurality of light emission signal stages connected to the plurality of pixel rows; as well as A first high voltage transmission line and a second high voltage transmission line are connected to the light emission signal generator, wherein the first high voltage transmission line is connected to a plurality of odd-numbered light emission signal stages among the plurality of light emission signal stages, and the plurality of odd-numbered light emission signal stages are configured to sequentially receive a first high voltage from the first high voltage transmission line at intervals of a period longer than two horizontal periods, and The second high voltage transmission line is connected to a plurality of even-numbered light emission signal stages among the plurality of light emission signal stages, and the plurality of even-numbered light emission signal stages are configured to sequentially receive a second high voltage from the second high voltage transmission line at intervals of a period longer than the two horizontal periods.

2. The organic light emitting diode display according to claim 1, wherein: The first high voltage transmission line and the second high voltage transmission line are insulated from each other.

3. The organic light emitting diode display according to claim 2, wherein: The plurality of light emission signal levels are sequentially arranged and include a first light emission signal level, a second light emission signal level, a third light emission signal level, a fourth light emission signal level, and a fifth light emission signal level to which a high voltage is sequentially applied, The first light transmit signal level, the third light transmit signal level, and the fifth light transmit signal level are configured to receive the first high voltage from the first high voltage transmission line, and The second light transmit signal stage and the fourth light transmit signal stage are configured to receive the second high voltage from the second high voltage transmission line.

4. The organic light emitting diode display according to claim 3, wherein: The first light emission signal level, the third light emission signal level, and the fifth light emission signal level are configured to sequentially receive the first high voltage at intervals of four horizontal periods, and The second light emission signal level and the fourth light emission signal level are configured to sequentially receive the second high voltage at intervals of four horizontal periods. 5 . The organic light emitting diode display of claim 4 , further comprising a scan signal generator located between the display area and the light emission signal generator.

6. The organic light emitting diode display according to claim 5, wherein: The previous stage scan signal is applied during the latter two horizontal periods of the four horizontal periods.

7. The organic light emitting diode display according to claim 6, wherein: Each of the plurality of light emission signal stages includes a first clock input terminal and a second clock input terminal configured to receive two clock signals, a control terminal configured to receive the light emission signal from the light emission signal stage of the previous stage, and an output terminal configured to output the light emission signal. Each of the plurality of light emission signal stages includes a high level output portion and a low level output portion, and The high-level output portion is configured to output a high voltage to the output terminal, and the low-level output portion is configured to output a low voltage to the output terminal.

8. The organic light emitting diode display according to claim 1, wherein: Each of the plurality of light emission signal stages is connected to two pixel rows among the plurality of pixel rows and applies a light emission signal to the plurality of pixel rows.

9. The organic light emitting diode display according to claim 8, wherein: The plurality of pixel rows include a first pixel row, a second pixel row, a third pixel row, a fourth pixel row, a fifth pixel row, a sixth pixel row, a seventh pixel row, and an eighth pixel row that are sequentially arranged. the plurality of light emission signal levels include a first light emission signal level, a second light emission signal level, a third light emission signal level, and a fourth light emission signal level that are sequentially arranged, The first light emission signal stage is connected to the first pixel row and the second pixel row, The second light emission signal stage is connected to the third pixel row and the fourth pixel row, The third light emission signal stage is connected to the fifth pixel row and the sixth pixel row, The fourth light emission signal stage is connected to the seventh pixel row and the eighth pixel row, The first light transmit signal level and the third light transmit signal level are configured to receive the first high voltage through the first high voltage transmission line, and The second light transmit signal stage and the fourth light transmit signal stage are configured to receive the second high voltage through the second high voltage transmission line.

10. The organic light emitting diode display according to claim 9, wherein: The first light emission signal level and the third light emission signal level are configured to sequentially receive the first high voltage at intervals of four horizontal periods, and The second light emission signal level and the fourth light emission signal level are configured to sequentially receive the second high voltage at intervals of four horizontal periods. 11 . The organic light emitting diode display of claim 10 , further comprising a scan signal generator located between the display area and the light emission signal generator.

12. The organic light emitting diode display according to claim 11, wherein: The previous stage scan signal is applied during the latter two horizontal periods of the four horizontal periods.

13. The organic light emitting diode display according to claim 12, wherein: Each of the plurality of light transmit signal stages includes a first clock input terminal and a second clock input terminal configured to receive two clock signals, respectively, a control terminal configured to receive the light transmit signal from the light transmit signal stage, and an output terminal configured to output the light transmit signal. Each of the plurality of light emission signal stages includes a high level output portion and a low level output portion, and The high-level output portion is configured to output a high voltage to the output terminal, and the low-level output portion is configured to output a low voltage to the output terminal.

14. An organic light emitting diode display, comprising: a display area including a plurality of pixel rows configured to emit light in response to a light emission signal; a first light emission signal generator and a second light emission signal generator located on opposite sides of the display area and including a plurality of light emission signal stages connected to the plurality of pixel rows; and two first high voltage transmission lines and two second high voltage transmission lines located on opposite sides of the display area and connected to the light emission signal generator, wherein the two first high voltage transmission lines are connected to a plurality of odd-numbered light emission signal stages among the plurality of light emission signal stages, and the plurality of odd-numbered light emission signal stages are configured to sequentially receive the first high voltage from the first high voltage transmission lines at intervals of a period longer than two horizontal periods, The two second high voltage transmission lines are connected to a plurality of even-numbered light emission signal stages among the plurality of light emission signal stages, and the plurality of even-numbered light emission signal stages are configured to sequentially receive the second high voltage from the second high voltage transmission lines at intervals of a period longer than the two horizontal periods, and The two first high voltage transmission lines are connected to each other, and the two second high voltage transmission lines are connected to each other.

15. The organic light emitting diode display according to claim 14, wherein: The two first high voltage transmission lines and the two second high voltage transmission lines are insulated from each other.

16. The organic light emitting diode display according to claim 15, wherein: the plurality of light emission signal levels include a first light emission signal level, a second light emission signal level, a third light emission signal level, a fourth light emission signal level, and a fifth light emission signal level that are sequentially arranged and configured to sequentially receive a high voltage, The first light transmit signal level, the third light transmit signal level, and the fifth light transmit signal level are configured to receive the first high voltage from the first high voltage transmission line, and The second light transmit signal stage and the fourth light transmit signal stage are configured to receive the second high voltage from the second high voltage transmission line.

17. The organic light emitting diode display according to claim 16, wherein: The first light emission signal level, the third light emission signal level, and the fifth light emission signal level are configured to sequentially receive the first high voltage at intervals of four horizontal periods, and The second light emission signal level and the fourth light emission signal level are configured to sequentially receive the second high voltage at intervals of four horizontal periods.

18. The organic light emitting diode display according to claim 17, further comprising: a first scanning signal generator, located between the display area and the first light emission signal generator; as well as The second scanning signal generator is located between the display area and the second light emission signal generator.

19. The organic light emitting diode display according to claim 18, wherein: The previous stage scan signal is applied during the latter two horizontal periods of the four horizontal periods.

Images