Display panel and display device

Abstract

The present invention provides a display panel and a display device. The display panel includes a plurality of data lines extending from a display area to a fan-out area; a plurality of data fan-out leads disposed in the fan-out area; each data line is electrically connected to a data fan-out lead; the plurality of data fan-out leads converge to a driver chip output binding area; a gate driver circuit disposed in the display area; a plurality of control signal lines electrically connected to the gate driver circuit and configured to transmit control signals to the gate driver circuit; a plurality of control signal lines extending from the display area to the fan-out area; a plurality of control signal line leads disposed in the binding area, each control signal line lead electrically connected to at least one control signal line, and the control signal line leads are connected to at least one of the driver chip output binding area and the peripheral binding area. This reduces the display panel's frame size and increases the display panel's screen-to-body ratio.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] With the development of display technology, organic light-emitting diode (OLED) display devices have become increasingly popular among consumers due to their high screen-to-body ratio and narrow bezel, which have enhanced people's viewing experience.

[0003] Based on this, the signal routing of the gate driver on array (GOA) circuit of the array substrate can be moved from the border area of ​​the display panel to the middle area of ​​the display area, thereby saving the size of the display border, improving the screen-to-body ratio of the display panel, and realizing a full-screen design of the display. Summary of the Invention

[0004] The embodiments of the present invention provide a solution to the problem in the prior art that the screen-to-body ratio of a display panel cannot be improved due to the driving signal lines being located in the border area of ​​the display panel.

[0005] To achieve the above objectives, the embodiments of the present invention adopt the following technical solutions:

[0006] In a first aspect, an embodiment of the present disclosure provides a display panel, comprising a display area, a fan-out area located on one side of the display area, and a binding area located on a side of the fan-out area away from the display area, wherein the binding area comprises a driver chip input binding area, a driver chip output binding area, and a peripheral binding area;

[0007] The display panel includes:

[0008] a plurality of data lines extending from the display area to the fan-out area;

[0009] A plurality of data fan-out leads are provided in the fan-out area; each data line is electrically connected to at least one data fan-out lead; the plurality of data fan-out leads are gathered to the output binding area of ​​the driver chip;

[0010] A gate driving circuit is provided in the display area;

[0011] a plurality of control signal lines electrically connected to the gate drive circuit and configured to transmit control signals to the gate drive circuit; the plurality of control signal lines extending from the display area to the fan-out area;

[0012] A plurality of control signal line leads are provided in the binding area, each control signal line lead is electrically connected to at least one control signal line, and the control signal line leads are connected to at least one of the driver chip output binding area and the peripheral binding area.

[0013] Optionally, the control signal line leads are led out from two ends of the driver chip output binding area and are arranged between the driver chip output binding area and the driver chip input binding area.

[0014] Optionally, the control signal line leads are led out from two ends of the driver chip output binding area and are arranged in the driver chip output binding area.

[0015] Optionally, the control signal line leads are led out from two ends of the driver chip output binding area and are arranged in the driver chip input binding area.

[0016] Optionally, the driver chip output binding area includes a gate layer;

[0017] The control signal line lead and the gate layer are arranged in the same layer.

[0018] Optionally, the driver chip output binding region includes a first source and drain layer;

[0019] The control signal line lead and the first source and drain layer are arranged in the same layer.

[0020] Optionally, the driver chip input binding region includes a second source and drain layer;

[0021] The control signal line lead and the second source and drain layer are arranged in the same layer.

[0022] Optionally, the display panel includes at least two fan-out areas;

[0023] The output binding area of ​​the driver chip includes a wiring pin area;

[0024] The control signal line passes through the area between the two fan-out areas and passes through the connection pin area to be connected to the control signal line lead.

[0025] Optionally, the wiring pin area includes a plurality of wiring pins, the signal control line is introduced from the plurality of wiring pins, and the control signal line lead is led out from the gap between two adjacent wiring pins.

[0026] Optionally, a projection of the connection pin area along a direction perpendicular to the extension direction of the control signal line partially overlaps with the control signal line.

[0027] Optionally, the display panel further includes a first insulating layer;

[0028] The output binding area of ​​the driver chip is covered on the first insulating layer, and a plurality of vias are opened on the first insulating layer. The control signal line lead is laid under the first insulating layer. The control signal line is introduced from the output binding area of ​​the driver chip including a plurality of wiring pins, and is connected to the control signal line lead through the vias.

[0029] Optionally, the display panel further includes a second insulating layer;

[0030] The driver chip input binding area is covered on the second insulating layer, the control signal line lead is laid under the second insulating layer, and the control signal line is introduced from the connection pins included in the driver chip input binding area and connected to the control signal line lead.

[0031] Optionally, the control signal line includes a first control signal line and a second control signal line;

[0032] An input end of the first control signal line and an input end of the second control signal line are respectively connected to some of the plurality of control signal line leads.

[0033] Optionally, the display area includes a third source-drain layer and a fourth source-drain layer located in different planes;

[0034] The first control signal line and the third source / drain layer are provided in the same layer, and the second control signal line and the fourth source / drain layer are provided in the same layer.

[0035] Optionally, the display area includes a scanning drive circuit and a light emitting drive circuit;

[0036] The first control signal lines include a GCK signal line, a GCB signal line, a GSTV signal line, a first VGH signal line and a first VGL signal line;

[0037] The second control signal line includes an ECB signal line, an ESTV signal line, an ECK signal line, a second VGH signal line and a second VGL signal line;

[0038] The GCK signal line, the GCB signal line, the GSTV signal line, the first VGH signal line and the first VGL signal line are electrically connected to the scan driving circuit respectively;

[0039] The ECB signal line, the ESTV signal line, the ECK signal line, the second VGH signal line, and the second VGL signal line are electrically connected to the light emitting driving circuit, respectively.

[0040] Optionally, the plurality of control signal line leads include an ECB signal line lead, an ESTV signal line lead, an ECK signal line lead, a GCK signal line lead, a GCB signal line lead, a GSTV signal line lead, a VGH signal line lead, and a VGL signal line lead;

[0041] The GCK signal line is electrically connected to the GCK signal line lead, the GCB signal line is electrically connected to the GCB signal line lead, the GSTV signal line is electrically connected to the GSTV signal line lead, the first VGH signal line is electrically connected to the VGH signal line, and the first VGL signal line is connected to the VGL signal line lead;

[0042] The ECB signal line is electrically connected to the ECB signal line lead, the ESTV signal line is electrically connected to the ESTV signal line lead, the ECK signal line is electrically connected to the ECK signal line lead, the second VGH signal line is electrically connected to the VGH signal line lead, and the second VGL signal line is electrically connected to the VGL signal line lead.

[0043] Optionally, the VGH signal line lead and the VGL signal line lead are connected to the peripheral bonding area.

[0044] In a second aspect, an embodiment of the present disclosure provides a display device, comprising a display panel as described in any one of the first aspects.

[0045] It can be seen from the above embodiments that since multiple control signal line leads are arranged in the binding area, each control signal line lead is electrically connected to at least one control signal line, and the control signal line lead is connected to at least one of the driver chip output binding area and the peripheral binding area, the control signal line can be set through the binding area including the driver chip input binding area, the driver chip output binding area, or the binding area including the area between the driver chip input binding area and the driver chip output binding area, so that the control signal line can be compatible with the binding area, and the control signal line is set in the middle of the display area, thereby saving the border area of ​​the display panel, and the border of the display panel can be further compressed, which is beneficial to saving the size of the display border and improving the screen-to-body ratio of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0047] Figure 1A schematic diagram of an overall circuit architecture of a display panel provided in the prior art;

[0048] Figure 2 A schematic diagram of an overall circuit architecture of a display panel provided in accordance with an embodiment of the present invention;

[0049] Figure 3 A schematic diagram of the wiring of a control signal line and a driver chip output binding area provided in the disclosed embodiment of the present invention;

[0050] Figure 4 A schematic diagram of a partial circuit architecture of a display panel provided in accordance with an embodiment of the present invention;

[0051] Figure 5 A schematic diagram of the wiring of the control signal line leads in the binding area provided in the disclosed embodiment of the present invention;

[0052] Figure 6 A schematic diagram of the wiring of control signal lines in the display area provided in the disclosed embodiment of the present invention;

[0053] Figure 7 A schematic diagram of the wiring of a scan driving circuit provided in the disclosed embodiment of the present invention;

[0054] Figure 8 A schematic diagram of the driving principle of a scan driving circuit provided in the disclosed embodiment of the present invention;

[0055] Figure 9 A schematic diagram of a light-emitting drive circuit according to an embodiment of the present invention;

[0056] Figure 10 A schematic diagram of the driving principle of the light-emitting driving circuit provided in the disclosed embodiment of the present invention;

[0057] Figure 11 A schematic structural diagram of a display device provided in accordance with an embodiment of the present invention.

[0058] Reference numerals:

[0059] 210: display area; 220: fan-out area; 230: binding area; 240: data line; 250: data fan-out lead; 260: gate drive circuit; 270: control signal line; 280: control signal line lead; 2301: driver chip input binding area; 2302: driver chip output binding area. DETAILED DESCRIPTION

[0060] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the embodiments described are only some embodiments of the present disclosure, not all embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of the present disclosure.

[0061] Unless the context requires otherwise, throughout the specification and claims, the term "comprise" and its other forms, such as the third person singular form "comprises" and the present participle form "comprising", are to be interpreted as open and inclusive, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "example", "specific example" or "some examples" are intended to indicate that the particular features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the particular features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0062] In the following, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0063] When describing some embodiments, the term "electrically connected" and its derivatives may be used. For example, when describing some embodiments, the term "electrically connected" may be used to indicate that two or more components are in direct physical or electrical contact with each other.

[0064] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0065] The use of "configured to" herein is intended to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0066] As used herein, “approximately” includes the stated value and an average value that is within an acceptable range of deviation from the particular value, where the acceptable range of deviation is determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0067] In this article, "same layer" refers to a layer structure formed by using the same film-forming process to form a film layer for forming a specific pattern, and then using the same mask template through a single patterning process. Depending on the specific pattern, a single patterning process may include multiple exposure, development or etching processes, and the specific pattern in the formed layer structure may be continuous or discontinuous. These specific patterns may also be at different heights or have different thicknesses. In contrast, "different layers" refers to a layer structure formed by using corresponding film-forming processes to form film layers for forming specific patterns, and then using corresponding mask templates through a patterning process. For example, "two layer structures are arranged in different layers" means that the two layer structures are formed under corresponding process steps (film-forming process and patterning process).

[0068] Exemplary embodiments are described herein with reference to cross-sectional and / or plan views that are idealized exemplary drawings. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Therefore, the exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include deviations in shape due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0069] In the related art, the display panel adopts the GOA (English full name: Gate Driver on Array, Chinese full name: array substrate row drive) driving method, that is, the gate drive circuit in the display panel is directly integrated into the peripheral area located on at least one side of the display area. In addition, the display panel also includes a plurality of signal lines arranged in the peripheral area, and the plurality of signal lines are electrically connected to the gate drive circuit for transmitting control signals to the gate drive circuit. Among them, the GOA circuit is controlled by a clock signal line, and GOA generally includes Gate GOA and EM GOA. Gate GOA includes GCK control signal line, GCB control signal line, GSTV control signal line, VGH control signal line and VGL control signal line, which are mainly used to improve the Gate signal of the pixel circuit included in the control panel to drive a row of pixels. EM GOA includes ECB control signal line, ESTV control signal line, ECK control signal line, VGH control signal line and VGL control signal line, which are mainly used to provide the control signal required by EM to drive at least one row of pixels.

[0070] Figure 1 is a schematic diagram of the overall circuit architecture of a display panel, such as Figure 1 As shown, 101 represents the overall outer frame line of the display panel; the display panel includes an effective display area (i.e., a pixel array area) 102 and a peripheral area located around the effective display area 102, the effective display area including pixel units 103 arranged in an array; the peripheral area includes a shift register unit 104, and a plurality of cascaded shift register units 104 constitute a gate drive circuit for providing, for example, a gate scan signal shifted row by row to the pixel units 103 arranged in an array in the effective display area 102 of the display panel 101; the peripheral area also includes a light-emitting control unit 105, and a plurality of cascaded light-emitting control units 105 constitute a light-emitting control array for providing, for example, a light-emitting control signal shifted row by row to the pixel units 103 arranged in an array in the effective display area 102 of the display panel 101.

[0071] like Figure 1As shown, data lines D1-DN (N is an integer greater than 1) connected to the data driver chip IC vertically pass through the effective display area 102 to provide data signals to the pixel units 103 arranged in an array; gate lines G1-GM (M is an integer greater than 1) connected to the shift register unit 104 and the light-emitting control unit 105 cross the effective display area 102 to provide gate scanning signals and light-emitting control signals to the pixel units arranged in an array. For example, each pixel unit 103 may include a pixel circuit and a light-emitting element having a circuit structure such as 7T1C, 8T2C, or 4T1C in the art. The pixel circuit operates under the control of the data signal transmitted via the data line and the gate scanning signal and light-emitting control signal transmitted via the gate line to drive the light-emitting element to emit light, thereby realizing display and other operations. The light-emitting element may be an organic light-emitting diode or a quantum dot light-emitting diode.

[0072] It can be seen from the above embodiments that in the related art, since the shift register unit 104 and the light-emitting control unit 105 are located in the border area of ​​the display panel, the data line D1-DN connected to the data driver chip IC needs to be introduced from both ends, occupying the border area of ​​the display panel. Therefore, the display border cannot be further compressed, which is not conducive to saving the size of the display border and improving the screen-to-body ratio of the display panel.

[0073] Based on this, Figure 2 As shown, the embodiment of the present disclosure provides a display panel, including a display area 210, a fan-out area 220 located on one side of the display area 210, and a binding area 230 located on the side of the fan-out area 220 away from the display area 210, wherein the binding area 230 includes a driver chip input binding area 2301, a driver chip output binding area 2302, and a peripheral binding area; the display panel includes: a plurality of data lines 240 extending from the display area 210 to the fan-out area 220; a plurality of data fan-out leads 250, arranged in the fan-out area 220; each data line 240 is electrically connected to a data fan-out lead 250; a plurality of data fan-out leads 250 are gathered to the driver chip output binding area 2302; the gate driver circuit 260 is arranged in the display area 210; multiple control signal lines 270 are electrically connected to the gate driver circuit 260 and are configured to transmit control signals to the gate driver circuit 260; multiple control signal lines 270 extend from the display area 210 to the fan-out area 220; multiple control signal line leads 280 are arranged in the binding area 230, each control signal line lead 280 is electrically connected to at least one control signal line 270, and the control signal line lead 280 is connected to the driver chip output binding area 2302 and at least one of the peripheral binding areas.

[0074] Among them, a plurality of sub-pixels P are provided in the display area 210 of the display panel. For the convenience of explanation, the plurality of sub-pixels P disclosed in the present invention are described as being arranged in a matrix form. At this time, the sub-pixels P arranged in a row along the first direction X are called a row of sub-pixels, and the sub-pixels P arranged in a row along the second direction Y are called a column of sub-pixels. A row of sub-pixels can be connected to a gate line (GL) GL, and a column of sub-pixels can be connected to a data line 240 (DL) DL. A pixel driving circuit for controlling the sub-pixels P to display is provided in the sub-pixels P.

[0075] The display panel includes a gate driver circuit 260 disposed in the display area 210 , that is, the gate driver circuit 260 is directly integrated into the display area 210 of the display panel. The gate driver circuit 260 is a GIA (Gate driver Integrated in Active array) circuit.

[0076] The gate line GL is electrically connected to the gate driving circuit 260 and is configured to receive a gate scanning signal from the gate driving circuit 260 and transmit the gate scanning signal to the pixel driving circuit in the display area 210 . That is, the gate driving circuit 260 is used to drive the gate line GL.

[0077] A plurality of data lines 240 extend from the display area 210 to the fan-out area 220. The data lines 240 are configured to transmit data signals to the pixel driving circuits located on the display. The display panel also includes a plurality of data fan-out leads 250 disposed in the fan-out area 220. Each data line 240 is electrically connected to a data fan-out lead 250. The plurality of data fan-out leads 250 converge into the bonding area 230.

[0078] The display panel further includes a plurality of control signal lines 270 and a plurality of first fan-out leads, wherein the plurality of control signal lines 270 are electrically connected to the gate driving circuit 260 and configured to transmit control signals to the gate driving circuit 260. The plurality of control signal lines 270 extend from the display area 210 to the fan-out area 220.

[0079] In addition, in the embodiment of the present disclosure, a plurality of control signal line leads 280 are arranged in the binding area 230, each control signal line lead 280 is electrically connected to at least one control signal line 270, and the control signal line lead 280 is connected to at least one of the driver chip output binding area 2302 and the peripheral binding area. Therefore, the control signal line lead 280 can be matched through the binding area 230 including the driver chip input binding area 2301, the driver chip output binding area 2302, or the binding area 230 including the driver chip input binding area 2301 and the driver chip output binding area 2302, so that the control signal line 270 can be compatible with the binding area 230, thereby saving the border area of ​​the display panel. Therefore, the border of the display panel can be further compressed, which is beneficial to saving the size of the display border and improving the screen-to-body ratio of the display panel.

[0080] It should be noted that, in the embodiments of the present disclosure, Figure 3 As shown, the control signal line 270 includes a first control signal line and a second control signal line, and the input end of the first control signal line and the input end of the second control signal line are respectively connected to several of the multiple control signal line leads 280. In this way, the first control signal line and the second control signal line can input different control signals to achieve signal transmission of different functions.

[0081] In addition, the display area 210 includes a third source-drain layer and a fourth source-drain layer located in different planes; the first control signal line and the third source-drain layer are arranged in the same layer, and the second control signal line and the fourth source-drain layer are arranged in the same layer.

[0082] It should be noted that the third and fourth source / drain layers are the layers where the data signal lines in the display area reside. Because different data signal lines transmit different drive signals, the data signal lines in the third and fourth source / drain layers, located in different planes, can transmit different drive signals. Furthermore, because the first control signal line is co-located with the third source / drain layer, and the second control signal line is co-located with the fourth source / drain layer, the first and second control signal lines do not interfere with each other when transmitting different signals.

[0083] In addition, the display area 210 includes a scan driving circuit 2701 and a light-emitting driving circuit 2702; the first control signal line includes a GCK signal line, a GCB signal line, a GSTV signal line, a first VGH signal line and a first VGL signal line; the second control signal line includes an ECB signal line, an ESTV signal line, an ECK signal line, a second VGH signal line and a second VGL signal line; the GCK signal line, the GCB signal line, the GSTV signal line, the first VGH signal line and the first VGL signal line are electrically connected to the scan driving circuit respectively; the ECB signal line, the ESTV signal line, the ECK signal line, the second VGH signal line and the second VGL signal line are electrically connected to the light-emitting driving circuit respectively.

[0084] Specifically, the multiple control signal line leads include an ECB signal line lead, an ESTV signal line lead, an ECK signal line lead, a GCK signal line lead, a GCB signal line lead, a GSTV signal line lead, a VGH signal line lead and a VGL signal line lead; the GCK signal line and the GCK signal line lead are electrically connected, the GCB signal line and the GCB signal line lead are electrically connected, the GSTV signal line and the GSTV signal line lead are electrically connected, the first VGH signal line and the VGH signal line are electrically connected, and the first VGL signal line and the VGL signal line lead are connected; the ECB signal line and the ECB signal line lead are electrically connected, the ESTV signal line and the ESTV signal line lead are electrically connected, the ECK signal line and the ECK signal line lead are electrically connected, the second VGH signal line and the VGH signal line lead are electrically connected, and the second VGL signal line and the VGL signal line lead are electrically connected.

[0085] It should be noted that if Figure 6 As shown, the output end of the scan driving circuit 2701 can be connected to the gate line GL of the Gate1 layer through a via, and the output end of the light-emitting driving circuit 2702 can be connected to the light-emitting control line of the Gate 1 layer through a via. In this way, different control signals GH can be transmitted to the control signal line 270 through the control signal lead to realize the input of different signals in the display area 210.

[0086] Furthermore, the VGH signal line lead and the VGL signal line lead are connected to the peripheral bonding area, so that the VGH signal line lead and the VGL signal line lead can be compatible in the peripheral bonding area, making the wiring of the signal line lead 280 and the control signal line 270 simpler and more convenient.

[0087] It should also be noted that, in the embodiment of the present disclosure, the scan driving circuit 2701 may be a Gate GOA, and the light emitting driving circuit 2702 may be an EM GOA. The Gate GOA may be electrically connected to the GCK signal line lead, the GCB signal line lead, the GSTV signal line lead, the VGH signal line lead, and the VGL signal line lead. Figure 7 and Figure 8 , the specific working principle of the Gate GOA is as follows:

[0088] In the input stage t1, the first clock signal provided on the first clock signal line CK is a low-level signal, the second clock signal provided on the second clock signal line CB is a high-level signal, and the input signal Vin provided on the input voltage line STV is a low-level signal. For example, the input signal Vin is equal to the first power supply signal VL. Since the first clock signal is a low-level signal, the second transistor T2 is turned on, and the input signal is transmitted to the third node N3 via the second transistor T2. Since the second transistor T2 has a threshold loss when transmitting a low-level signal, the voltage of the third node N3 is Vin - Vth2, that is, VL - Vth2, where Vth2 represents the threshold voltage of the second transistor T2. Since the gate of the sixth transistor T6 receives the first power supply signal VL, the sixth transistor T6 is in an on state. Thus, the voltage VL - Vth2 is transmitted to the first node N1 via the sixth transistor T6. For example, the threshold voltage of the sixth transistor T6 is denoted as Vth6. Similarly, since the sixth transistor T6 has a threshold loss when transmitting a low-level signal, the voltage of the first node N1 is VL - VthN1, where VthN1 is the smaller one of Vth2 and Vth6. The voltage of the first node N1 can control the eighth transistor T8 to be turned on, and the second clock signal is written to the output terminal GOUT via the eighth transistor T8 as an output signal. That is, in the input stage t1, the output signal is the second clock signal with a high level, that is, the second power supply signal VH.

[0089] In the input stage t1, since the first clock signal is a low-level signal, the first transistor T1 is turned on, and the first power supply signal VL is transmitted to the second node N2 via the first transistor T1. Since the voltage of the third node N3 is VL - Vth2, the seventh transistor T7 is turned on, and the low-level first clock signal is transmitted to the second node N2 via the seventh transistor T7. For example, the threshold voltage of the seventh transistor T7 is denoted as Vth7, and the threshold voltage of the first transistor T1 is denoted as Vth1. When Vth1 < Vth7 + Vth2, the voltage of the second node N2 is VL - Vth7 - Vth2; when Vth1 > Vth7 + Vth2, the voltage of the second node N2 is VL - Vth1. At this time, both the third transistor T3 and the fourth transistor T4 are turned on. Since the second clock signal is a high-level signal, the fifth transistor T5 is turned off.

[0090] During output phase t2, the first clock signal provided on the first clock signal line CK is a high-level signal, the second clock signal provided on the second clock signal line CB is a low-level signal, and the input signal Vin provided on the input voltage line STV is a high-level signal. The eighth transistor T8 is turned on, and the second clock signal is written to the output terminal GOUT via the eighth transistor T8 as the output signal. During input phase t1, the voltage at the end of the second capacitor C2 connected to the output terminal GOUT is the second power supply signal VH, and the voltage at the end of the second capacitor C2 connected to the first node N1 is VL-VthN1. During output phase t2, the voltage at the end of the second capacitor C2 connected to the output terminal GOUT becomes VL. Due to the bootstrap effect of the second capacitor C2, the voltage at the end of the second capacitor C2 connected to the first node N1 becomes 2VL-VthN1-VH, that is, the voltage at the first node N1 becomes 2VL-VthN1-VH. At this time, the sixth transistor T6 is turned off, allowing the eighth transistor T8 to be more effectively turned on, and the output signal is the first power supply signal VL.

[0091] During output phase t2, the first clock signal is a high-level signal, thus turning off both the second transistor T2 and the first transistor T1. The voltage at the third node N3 remains at VL-VthN1, and the seventh transistor T7 is turned on. The high-level first clock signal is transmitted to the second node N2 via the seventh transistor T7, i.e., the voltage at the second node N2 is the second power supply signal VH. Consequently, both the third transistor T3 and the fourth transistor T4 are turned off. Since the second clock signal is a low-level signal, the fifth transistor T5 is turned on.

[0092] During buffering phase t3, the first clock signal provided on the first clock signal line CK and the second clock signal provided on the second clock signal line CB are both high-level signals, and the input signal Vin provided on the input voltage line STV is also high-level. The eighth transistor T8 is turned on, and the second clock signal is written to the output terminal GOUT via the eighth transistor T8 as the output signal. At this point, the output signal is the high-level second clock signal, i.e., the second power supply signal VH. Due to the bootstrap effect of the second capacitor C2, the voltage at the first node N1 reaches VL - VthN1.

[0093] During the buffering phase t3, the first clock signal is high, turning off both the second transistor T2 and the first transistor T1. The voltage at the first node N1 reaches VL - VthN1. At this point, the sixth transistor T6 turns on, and the voltage at the third node N3 also reaches VL - VthN1. The seventh transistor T7 turns on, and the high-level first clock signal is transmitted to the second node N2 via the seventh transistor T7. That is, the voltage at the second node N2 becomes the second power supply signal VH. Consequently, the third transistor T3 and the fourth transistor T4 are both turned off. Because the second clock signal is high, the fifth transistor T5 turns off.

[0094] In the first sub-phase t41 of the stable phase t4, the first clock signal provided on the first clock signal line CK is a low-level signal, the second clock signal provided on the second clock signal line CB is a high-level signal, and the input signal Vin provided on the input voltage line STV is a high-level signal. For example, the input signal Vin is equal to the second power supply signal VH. Because the first clock signal is a low-level signal, the second transistor T2 is turned on, and the input signal Vin is transmitted to the third node N3 via the second transistor T2. Because the second transistor T2 transmits a high-level signal without threshold loss, the voltage at the third node N3 is Vin (i.e., the second power supply signal VH), and the seventh transistor T7 is turned off. Because the sixth transistor T6 is turned on, the voltage at the first node N1 is the same as the third node N3. In other words, the voltage at the first node N1 is VH, and the eighth transistor T8 is turned off. Since the first clock signal is a low-level signal, the first transistor T1 is turned on, the voltage of the second node N2 is VL-Vth1, the third transistor T3 and the fourth transistor T4 are both turned on, and the second power signal VH is transmitted to the output terminal GOUT via the third transistor T3, that is, the output signal is the second power signal VH.

[0095] In the second sub-phase t42 of the stable phase t4, the first clock signal provided on the first clock signal line CK is a high-level signal, the second clock signal provided on the second clock signal line CB is a low-level signal, and the input signal Vin provided on the input voltage line STV is a high-level signal. The voltages at the first node N1 and the third node N3 are Vin (i.e., the second power signal VH), and the eighth transistor T8 and the seventh transistor T7 are both turned off. The first clock signal is a high-level signal, so the second transistor T2 and the first transistor T1 are both turned off. Due to the holding effect of the first capacitor C1, the voltage at the second node N2 remains at VL-Vth1. The third transistor T3 and the fourth transistor T4 are both turned on, and the second power signal VH is transmitted to the output terminal GOUT via the third transistor T3, and the output signal is the second power signal VH.

[0096] In the second sub-phase t42, since the second clock signal is a low-level signal, the fifth transistor T5 is turned on, so that the second power signal VH is transmitted to the third node N3 and the first node N1 via the fourth transistor T4 and the fifth transistor T5, so that the voltage of the first node N1 and the voltage of the third node N3 are maintained at a high level.

[0097] In the third sub-phase t43 of the stable phase t4, the first clock signal provided on the first clock signal line CK and the second clock signal provided on the second clock signal line CB are both high-level signals, and the input signal Vin provided on the input voltage line STV is a high-level signal. The voltages at the first node N1 and the third node N3 are VH, and the eighth transistor T8 and the seventh transistor T7 are turned off. The first clock signal is a high-level signal, so the second transistor T2 and the first transistor T1 are both turned off. The voltage at the second node N2 remains at VL-Vth1, and the third transistor T3 and the fourth transistor T4 are both turned on. The second power supply signal VH is transmitted to the output terminal GOUT via the third transistor T3, and the output signal is the second power supply signal VH.

[0098] The EM GOA can be electrically connected to the ECB signal line lead, the ESTV signal line lead, the ECK signal line lead, the VGH signal line lead, and the VGL signal line lead. Figure 9 and Figure 10 , the specific working principle of EM GOA is as follows:

[0099] In the first phase P1, the first clock signal CK is at a low level, turning on the first transistor M1 and the third transistor M3. The turned-on first transistor M1 transmits the high-level start signal ESTV to the first node N1, thereby changing the level of the first node N1 to a high level. As a result, the second transistor M2, the eighth transistor M8, and the tenth transistor M10 are turned off. Furthermore, the turned-on third transistor M3 transmits the low-level fourth voltage VGL to the second node N2, thereby changing the level of the second node N2 to a low level. This turns on the fifth transistor M5 and the sixth transistor M6. Because the second clock signal CB is at a high level, the seventh transistor M7 is turned off. Furthermore, due to the storage function of the third capacitor C3, the level of the fourth node N4 can remain high, thereby turning off the ninth transistor M9. In the first phase P1, because the ninth transistor M9 and the tenth transistor M10 are both turned off, the light-emission control pulse signal EM output by the light-emission control shift register unit EGOA remains at its previous low level.

[0100] During the second phase P2, the second clock signal CB is at a low level, turning on the fourth transistor M4 and the seventh transistor M7. Since the first clock signal CK is at a high level, the first transistor M1 and the third transistor M3 are turned off. Due to the storage function of the first capacitor C1, the second node N2 can continue to maintain the low level from the previous phase, turning on the fifth transistor M5 and the sixth transistor M6. The high third voltage VGH is transmitted to the first node N1 via the turned-on fifth transistor M5 and fourth transistor M4, causing the level of the first node N1 to continue to maintain the high level from the previous phase. Consequently, the second transistor M2, the eighth transistor M8, and the tenth transistor M10 are turned off. Furthermore, the low second clock signal CB is transmitted to the fourth node N4 via the turned-on sixth transistor M6 and seventh transistor M7, causing the level of the fourth node N4 to go low. This turns on the ninth transistor M9, which outputs the high third voltage VGH. Consequently, the light emission control pulse signal EM output by the light emission control shift register unit EGOA during the second phase P2 is high.

[0101] In the third phase P3, the first clock signal CK is at a low level, so the first transistor M1 and the third transistor M3 are turned on. The second clock signal CB is at a high level, so the fourth transistor M4 and the seventh transistor M7 are turned off. Due to the storage function of the third capacitor C3, the level of the fourth node N4 can remain at the low level of the previous phase, thereby keeping the ninth transistor M9 in the on state. The turned-on ninth transistor M9 outputs the high-level third voltage VGH, so the light-emission control pulse signal EM output by the light-emission control shift register unit EGOA in the third phase P3 remains at a high level.

[0102] In the fourth phase P4, the first clock signal CK is at a high level, so the first transistor M1 and the third transistor M3 are turned off. The second clock signal CB is at a low level, so the fourth transistor M4 and the seventh transistor M7 are turned on. Due to the storage function of the second capacitor C2, the voltage level at the first node N1 remains at the high level from the previous phase, thereby turning off the second transistor M2, the eighth transistor M8, and the tenth transistor M10. Due to the storage function of the first capacitor C1, the second node N2 continues to maintain the low level from the previous phase, thereby turning on the fifth transistor M5 and the sixth transistor M6. In addition, the low-level second clock signal CB is transmitted to the fourth node N4 through the turned-on sixth transistor M6 and seventh transistor M7, causing the voltage level at the fourth node N4 to become low. This turns on the ninth transistor M9, which outputs the high-level third voltage VGH. Therefore, the light-emission control pulse signal EM output by the light-emission control shift register unit EGOA in the second phase P2 remains high.

[0103] In the fifth stage P5, the first clock signal CK is at a low level, so the first transistor M1 and the third transistor M3 are turned on. The second clock signal CB is at a high level, so the fourth transistor M4 and the seventh transistor M7 are turned off. The turned-on first transistor M1 transmits the low-level start signal ESTV to the first node N1, causing the level of the first node N1 to change to a low level, so the second transistor M2, the eighth transistor M8, and the tenth transistor M10 are turned on. The turned-on second transistor M2 transmits the low-level first clock signal CK to the second node N2, thereby further lowering the level of the second node N2. Therefore, the second node N2 continues to maintain the low level of the previous stage, thereby turning on the fifth transistor M5 and the sixth transistor M6. In addition, the turned-on eighth transistor M8 transmits the high-level third voltage VGH to the fourth node N4, causing the level of the fourth node N4 to change to a high level, so the ninth transistor M9 is turned off. The turned-on tenth transistor M10 outputs the fourth voltage VGL of a low level, so the light emitting control pulse signal EM output by the light emitting control shift register unit EGOA in the fifth phase P5 becomes a low level.

[0104] It should be noted that the control signal line lead 280 can be set in any area of ​​the driver chip input binding area 2301, the driver chip output binding area 2302, or the area between the driver chip input binding area 2301 and the driver chip output binding area 2302 in the binding area 230, and the embodiments of the present disclosure do not limit this. In addition, depending on the area connected to the control signal line lead 280, the control signal line is located at a different level in the driver chip. The specific wiring method can be as follows:

[0105] (1) Figure 4 As shown, a plurality of control signal line leads 280 are led out from both ends of the driver chip output binding area 2302 and are arranged between the driver chip output binding area 2302 and the driver chip input binding area 2301 .

[0106] In this wiring method, in a possible implementation, the driver chip output binding area 2302 includes a gate layer, and the control signal line lead 280 and the gate layer are provided in the same layer.

[0107] It should be noted that the output binding area of ​​the driver chip can generally include a top layer, a middle layer and a bottom layer, wherein the top layer is also called the component layer, which is mainly used to place components. The middle layer is mainly used to lay signal lines. The bottom layer is also called the welding layer, which is mainly used for wiring and welding, and can also be used to place components. The gate layer is a metal layer patterned and connected to the gate line, and is located in the middle layer of the driver chip output binding area 2302. In this way, when the control signal line 270 is connected to the control signal line lead 280, the control signal line 270 changes layers in the driver chip output binding area 2302, passes through the driver chip output binding area 2302 and changes to the gate layer, realizing the jumper of the control signal line lead 280, so that the control signal line 270 can pass through the driver chip output binding area 2302.

[0108] In another possible implementation, the display panel includes at least two fan-out areas 220; the driver chip output binding area 2302 includes a wiring pin area, and the control signal line 270 passes through the area between the two fan-out areas 220 and passes through the wiring pin area to connect with the control signal line lead 280.

[0109] It should be noted that if Figure 5 As shown, the pin distribution on the driver chip output binding area 230 and the driver chip output binding area 2302 is that the GOA or DC signal pins are located at both ends, the Data signal is distributed inside the GOA or DC signal pins, and the wiring pins are distributed between the two Data signal pins. That is, the wiring pins are located in the middle of the driver chip output binding area 230 and the driver chip output binding area 2302, which is usually the location of the Dummy Pin, that is, the location of the wiring pin area. On the driver chip output binding area 230 and the driver chip output binding area 2302, the Dummy Pin Dummy in the wiring pin area is mainly used to prevent etching failure caused by excessive or insufficient exposure during the chip manufacturing process, and to avoid the reflection and diffraction of light during the photolithography process from affecting the accuracy of the physical pattern of key components and further affecting the size of the driver chip output binding area 230 and the driver chip output binding area 2302. In this way, when the control signal line 270 passes through the driver chip output binding area 2302, the control signal line 270 can first pass through the area between the two fan-out areas 220, and then pass through the wiring pin area to connect with the control signal line lead 280. In this way, since the GOA signal is connected to the control signal line lead 280 through the connection pin area, interference between the GOA signal and the Data signal can be avoided.

[0110] In addition, the connection pin area includes a plurality of connection pins, the signal control line 270 is introduced from the plurality of connection pins, and the control signal line lead 280 is led out from the gap between two adjacent connection pins.

[0111] It should be noted that the control signal line 270 passes through the wiring pin area and is connected to the control signal line lead 280. The control signal line 270 can be led out from the gap between two adjacent wiring pins, so that the control signal line 270 is led down from both ends of the driver chip output binding area 2302 to the interval area between the driver chip output binding area 2302 and the driver chip input binding area 2301, and then the drive signal line is led out using the original Dummy Pin of the driver chip output binding area 2302. Since the wiring pin area is located in the middle of the driver chip output binding area 2302, the control signal line 270 will not overlap with the Data signal line when it is led out, thereby avoiding mutual interference between the control signal and the Data signal, thereby laying the foundation for the control signal line 270 to be set in the middle of the display area 210. In this way, since the control signal line 270 passes through the wiring pin area and is connected to the control signal line lead 280, the control signal line 270 is led out from the gap between two adjacent wiring pins, and the wiring pin is located in the middle of the driver chip output binding area 2302, and is arranged between the driver chip output binding area 2302 and the driver chip input binding area 2301. Therefore, it can be compatible with the structure of the binding area 230. Without changing the binding area 230, the control signal line 270 can be set in the middle of the display area 210, thereby saving the border area of ​​the display panel, and the border of the display panel can be further compressed, which is beneficial to saving the size of the display border and improving the screen-to-body ratio of the display panel.

[0112] Furthermore, the projection of the connection pin area along a direction perpendicular to the extension direction of the control signal line 270 partially overlaps with the control signal line 270. Thus, the area where the control signal line 270 passes through the driver chip output bonding area 2302 and the area where the connection pin area are located are in a stacked state. Therefore, the control signal line 270 can be led out through the connection pin area within the driver chip output bonding area 2302, making the connection between the control signal line 270 and the control signal line lead 280 fully compatible with the driver chip output bonding area 2302.

[0113] (2) A plurality of control signal line leads 280 are led out from both ends of the driver chip output binding area 2302 and are disposed in the driver chip output binding area 2302 .

[0114] In this wiring mode, the driver chip output bonding area 2302 includes a first source-drain layer, and the control signal line lead 280 and the first source-drain layer are arranged on the same layer.

[0115] It should be noted that the first source and drain layer is the area where the data signal line is located in the driver chip output binding area 2302. Under this wiring method, the signal line lead 280 and the first source and drain layer are located in the same layer, so that the signal line lead 280 can be arranged in the same area as the driver chip output binding area 2302.

[0116] Under the above wiring method, in order to avoid interference between the data signal line and the signal line lead or short circuit of the circuit of the driver chip output binding area 2302, the display panel can also include a first insulating layer; the driver chip output binding area 2302 is covered on the first insulating layer, and a plurality of vias are opened on the first insulating layer. The control signal lead line is laid under the first insulating layer, and the control signal line 270 is introduced from the driver chip output binding area 2302 including a plurality of wiring pins, and is connected to the control signal line lead 280 through the via.

[0117] It should be noted that since multiple Data signal lines are arranged on the back of the driver chip output binding area 2302, in order to avoid mutual interference between the two signal lines, the driver chip output binding area 2302 is covered on the first insulating layer so that the Data signal line and the control signal line lead 280 do not interfere with each other. Then, the control signal line lead 280 passes through the via hole and is led out from the driver chip output binding area 2302 including multiple wiring pins to be connected to the control signal line 270. The control signal line 270 can also be led out from the middle of the driver chip output binding area 2302, thereby achieving the effect of setting the control signal line 270 in the middle of the display area 210, saving the border area of ​​the display panel.

[0118] (3) A plurality of control signal line leads 280 are led out from both ends of the driver chip output binding area 2302 and are arranged in the driver chip input binding area 2301 .

[0119] In this wiring mode, the driver chip input binding area 2301 includes a second source-drain layer; the control signal line lead 280 and the second source-drain layer are arranged in the same layer.

[0120] It should be noted that the second source and drain layer is the area where the data signal line is located in the driver chip input binding area 2301. Under this wiring method, the signal line lead 280 and the second source and drain layer are located in the same layer, so that the signal line lead 280 can be arranged in the same area as the driver chip input binding area 2301.

[0121] Under the above wiring method, in order to avoid interference between the data signal line and the signal line lead or short circuit of the circuit of the driver chip input binding area 2301, the display panel also includes a second insulating layer; the driver chip input binding area 2301 is covered on the second insulating layer, and the control signal line lead 280 is laid under the second insulating layer. The control signal line 270 is introduced from the wiring pin included in the driver chip input binding area 2301 and connected to the control signal line lead 280.

[0122] It should be noted that a plurality of data signal lines are also arranged on the back of the driver chip input binding area 2301. If the signal line leads are to be arranged in the driver chip input binding area 2301, the two signal lines also need to be insulated. The driver chip input binding area 2301 is covered with a second insulating layer, and then the control signal line 270 is introduced from the wiring pins included in the driver chip input binding area 2301 and connected to the control signal line lead 280 in the same manner as described above. That is, the control signal line 270 can be led out from the middle of the driver chip output binding area 2302, thereby achieving the effect of setting the control signal line 270 in the middle of the display area 210, saving the border area of ​​the display panel.

[0123] It should also be noted that regardless of whether the multiple control signal line leads 280 are led out from both ends of the driver chip output binding area 2302 and disposed at the bottom of the driver chip output binding area 2302, or are disposed at the bottom of the driver chip input binding area 2301, an insulating layer must be added within the binding area 230. Considering the processing design and routing costs, a routing method can be chosen in which the multiple control signal line leads 280 are led out from both ends of the driver chip output binding area 2302 and disposed between the driver chip output binding area 2302 and the driver chip input binding area 2301. This can, in turn, reduce the routing costs of the control signal lines 270 to a certain extent.

[0124] It can be seen from the above embodiment that since multiple control signal line leads 280 are arranged in the binding area 230, each control signal line lead 280 is electrically connected to at least one control signal line 270, and the control signal line lead 280 is connected to the driver chip output binding area 2302 and at least one of the surrounding binding areas, the control signal line 270 can be set through the binding area 230 including the driver chip input binding area 2301, the driver chip output binding area 2302, or the binding area 230 including the driver chip input binding area 2301 and the driver chip output binding area 2302, so that the control signal line 270 can be compatible with the binding area 230, and the control signal line 270 is set in the middle of the display area 210, thereby saving the border area of ​​the display panel, and the border of the display panel can be further compressed, which is beneficial to saving the size of the display border and improving the screen-to-body ratio of the display panel.

[0125] Some embodiments of the present disclosure further provide a display device 300, such as Figure 11 As shown, the display device 300 includes the display panel 200 in any of the above embodiments.

[0126] In the above-mentioned embodiment of the present disclosure, the control signal line 270 included in the display panel 200 of the display device 300 can be compatible with the binding area 230, so that the control signal line 270 is set in the middle of the display area 210, thereby saving the border area of ​​the display panel 200, which is conducive to the narrow-border design of the display device 300.

[0127] The display device 300 may be an electroluminescent display device 300 , and the electroluminescent display device 300 may be an OLED display device 300 .

[0128] The display device 300 can be any device that displays an image, whether in motion (e.g., video) or stationary (e.g., still image), and whether textual or graphic. More specifically, it is contemplated that the embodiments described may be implemented in or associated with a variety of electronic devices, such as, but not limited to, mobile phones, wireless devices, personal data assistants (PDAs), handheld or portable computers, GPS receivers / navigators, cameras, MP4 video players, camcorders, game consoles, watches, clocks, calculators, television monitors, flat-panel displays, computer monitors, automotive displays (e.g., speedometer displays, etc.), navigation systems, cockpit controls and / or displays, displays of camera views (e.g., displays of rearview cameras in vehicles), electronic photographs, electronic billboards or signs, projectors, architectural structures, packaging, and aesthetic structures (e.g., displays of images of a piece of jewelry), and the like.

[0129] It should be noted that the various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same and similar parts between the various embodiments can be referenced to each other.

[0130] Although alternative embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they become aware of the basic inventive concept. Therefore, the appended claims are intended to be interpreted as including alternative embodiments and all changes and modifications that fall within the scope of the present invention.

[0131] Finally, it should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity from another, and do not necessarily require or imply any actual relationship or order between these entities. Moreover, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that an article or terminal device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such article or terminal device. In the absence of further limitations, an element defined by the phrase "comprising a..." does not exclude the presence of additional identical elements in the article or terminal device comprising the element.

[0132] The above is a detailed introduction to the technical solution provided by the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. At the same time, for those skilled in the art, according to the principles and implementation methods of the present application, there may be changes in the specific implementation methods and application scope. In summary, the contents of this specification should not be understood as limiting the present application.

Claims

1. A display panel, characterized in that: It includes a display area, a fan-out area located on one side of the display area, and a binding area located on a side of the fan-out area away from the display area, wherein the binding area includes a driver chip input binding area, a driver chip output binding area, and a peripheral binding area; The display panel includes: a plurality of data lines extending from the display area to the fan-out area; A plurality of data fan-out leads are provided in the fan-out area; each data line is electrically connected to at least one data fan-out lead; the plurality of data fan-out leads are gathered to the output binding area of ​​the driver chip; A gate driving circuit is provided in the display area; a plurality of control signal lines electrically connected to the gate drive circuit and configured to transmit control signals to the gate drive circuit; the plurality of control signal lines extending from the display area to the fan-out area; A plurality of control signal line leads are provided in the binding area, each control signal line lead is electrically connected to at least one control signal line, the control signal line leads are led out from both ends of the driver chip output binding area, and are provided between the driver chip output binding area and the driver chip input binding area; A plurality of sub-pixels are arranged in the display area, wherein a pixel driving circuit for controlling the sub-pixels to display is arranged in the sub-pixels; Wherein, the display panel includes at least two fan-out areas; The driver chip output binding area includes a wiring pin area, the wiring pin area includes a plurality of wiring pins, the control signal line is introduced from the plurality of wiring pins, and the control signal line lead is led out from the gap between two adjacent wiring pins; The wiring pin area is arranged in the middle of the output binding area of ​​the driver chip; The control signal line passes through the area between the two fan-out areas and passes through the connection pin area to be connected to the control signal line lead.

2. The display panel according to claim 1, wherein: The driver chip output binding area includes a gate layer; The control signal line lead and the gate layer are arranged in the same layer.

3. The display panel according to claim 1, wherein: The driver chip output bonding area includes a first source and drain layer; The control signal line lead and the first source and drain layer are arranged in the same layer.

4. The display panel according to claim 3, wherein: The driver chip input binding area includes a second source and drain layer; The control signal line lead and the second source and drain layer are arranged in the same layer.

5. The display panel according to claim 1, wherein: A projection of the connection pin area along a direction perpendicular to an extension direction of the control signal line partially overlaps with the control signal line.

6. The display panel according to claim 1, wherein: The control signal line includes a first control signal line and a second control signal line; An input end of the first control signal line and an input end of the second control signal line are respectively connected to some of the plurality of control signal line leads.

7. The display panel according to claim 6, wherein: The display area includes a third source-drain layer and a fourth source-drain layer located in different planes; The first control signal line and the third source-drain layer are provided in the same layer, and the second control signal line and the fourth source-drain layer are provided in the same layer.

8. The display panel according to claim 6, wherein: The display area includes a scanning drive circuit and a light emitting drive circuit; The first control signal lines include a GCK signal line, a GCB signal line, a GSTV signal line, a first VGH signal line and a first VGL signal line; The second control signal line includes an ECB signal line, an ESTV signal line, an ECK signal line, a second VGH signal line and a second VGL signal line; The GCK signal line, the GCB signal line, the GSTV signal line, the first VGH signal line and the first VGL signal line are electrically connected to the scan driving circuit respectively; The ECB signal line, the ESTV signal line, the ECK signal line, the second VGH signal line, and the second VGL signal line are electrically connected to the light emitting driving circuit, respectively.

9. The display panel according to claim 8, wherein: The plurality of control signal line leads include an ECB signal line lead, an ESTV signal line lead, an ECK signal line lead, a GCK signal line lead, a GCB signal line lead, a GSTV signal line lead, a VGH signal line lead, and a VGL signal line lead; The GCK signal line is electrically connected to the GCK signal line lead, the GCB signal line is electrically connected to the GCB signal line lead, the GSTV signal line is electrically connected to the GSTV signal line lead, the first VGH signal line is electrically connected to the VGH signal line, and the first VGL signal line is connected to the VGL signal line lead; The ECB signal line is electrically connected to the ECB signal line lead, the ESTV signal line is electrically connected to the ESTV signal line lead, the ECK signal line is electrically connected to the ECK signal line lead, the second VGH signal line is electrically connected to the VGH signal line lead, and the second VGL signal line is electrically connected to the VGL signal line lead.

10. The display panel according to claim 9, wherein: The VGH signal line lead and the VGL signal line lead are connected to the peripheral bonding area.

11. A display device, characterized in that: The display device comprises the display panel according to any one of claims 1 to 10.

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