Pixel circuit and display device including the same

Abstract

Disclosed are a pixel circuit and a display device including the pixel circuit. The pixel circuit includes first to eighth transistors, a storage capacitor, and a light-emitting element. When the drive time of a panel drive frame is the minimum drive time, the pixel circuit performs a display scan operation. When the drive time of the panel drive frame is not the minimum drive time, the pixel circuit performs a display scan operation and at least one self-scan operation.

Description

Technical Field

[0001] The present invention relates to a display device. More specifically, the present invention relates to a display device (eg, an organic light emitting display device) having a variable driving frequency of a display panel (ie, a variable driving time of a panel driving frame) and a pixel circuit included in the display device. Background Art

[0002] Typically, a display device includes a source device and a sink device. In this case, the source device (e.g., a graphics processing unit (GPU)) transmits image data to the sink device, and the sink device performs a display operation based on the image data transmitted from the source device. Recently, during the display operation, the display device changes the frame rate of the image frames constituting the image data (or the drive time of the image frames) in real time according to the characteristics of the image displayed by the above-mentioned display operation. In this case, without changing the frame rate of the panel drive frame (or the drive time of the panel drive frame) used for the display operation, due to the inconsistency between the frame rate of the image frame (e.g., GPU rendering speed) and the frame rate of the panel drive frame, problems such as tearing (e.g., image cutoff) and stuttering (e.g., image delay) may occur in the image displayed by the sink device. Accordingly, a synchronization (sync) technology is proposed for changing the frame rate of the panel drive frame by increasing the vertical blank interval within the panel drive frame as the frame rate of the image frame is changed. However, if the frame rate of the panel drive frame is reduced, the driving time of the panel drive frame is increased. Therefore, during the panel drive frame, the characteristics of the driving transistor included in the pixel circuit of the display panel are fixed in a predetermined state, and flicker may occur on the display panel due to the hysteresis characteristics. In addition, if the number of control signals applied to the pixel circuit is increased to reduce the above-mentioned flicker, the driver that provides the predetermined control signal (for example, the compensation control signal, etc.) is arranged only on one side of the display panel. Accordingly, uneven brightness may occur between the area close to the driver and the area far from the driver on the display panel. Therefore, when the display panel is operated at a lower driving frequency using the above-mentioned synchronization technology, there is a problem of reduced quality of the image displayed on the display panel. Summary of the Invention

[0003] An object of the present invention is to provide a pixel circuit that can prevent flickering and uneven brightness from occurring on a display panel.

[0004] Another object of the present invention is to provide a display device including the above-mentioned pixel circuit, thereby providing a user with high-quality images even if the display panel operates at a lower driving frequency.

[0005] However, the purpose of the present invention is not limited to the above purpose, and the present invention can be expanded in many ways without departing from the scope of the idea and concept of the present invention.

[0006] To achieve one purpose of the present invention, a pixel circuit according to an embodiment of the present invention may include: a first transistor including a first terminal connected to a first node, a gate terminal connected to a second node, and a second terminal connected to a third node; a second transistor including a first terminal for receiving a data signal, a second terminal connected to the first node, and a gate terminal for receiving a gate control signal; a third transistor including a first terminal connected to the third node, a second terminal connected to the second node, and a gate terminal for receiving a compensation control signal; a fourth transistor including a first terminal connected to the third node, a second terminal for receiving a first initialization voltage, and a gate terminal for receiving a previous gate control signal applied earlier than the gate control signal; a fifth transistor including a first terminal for receiving a first power supply voltage, a second terminal for receiving a first power supply voltage, and a gate terminal for receiving a previous gate control signal applied earlier than the gate control signal. a second terminal connected to the first node and a gate terminal receiving a light-emitting control signal; a sixth transistor including a first terminal connected to the third node, a second terminal connected to the fourth node, and a gate terminal receiving the light-emitting control signal; a seventh transistor including a first terminal connected to the fourth node, a second terminal receiving a second initialization voltage, and a gate terminal receiving a bias control signal; an eighth transistor including a first terminal connected to the first node, a second terminal receiving a bias voltage, and a gate terminal receiving the bias control signal; a storage capacitor including a first terminal receiving the first power supply voltage and a second terminal connected to the second node; and a light-emitting element including a first terminal connected to the fourth node and a second terminal receiving a second power supply voltage lower than the first power supply voltage. At this time, when the driving time of the panel driving frame is the minimum driving time, the pixel circuit can perform one display scanning operation, and when the driving time of the panel driving frame is not the minimum driving time, the pixel circuit can perform one display scanning operation and at least one self-scan operation.

[0007] According to an embodiment, the third transistor may be implemented as an oxide thin film transistor.

[0008] According to an embodiment, the third transistor may be an NMOS transistor.

[0009] According to an embodiment, when the display scan operation is performed, each of the gate control signal, the previous gate control signal, the compensation control signal, the bias control signal, and the light emitting control signal may include a turn-on voltage interval.

[0010] According to one embodiment, the on-voltage interval of the gate control signal, the on-voltage interval of the previous gate control signal, the on-voltage interval of the compensation control signal, and the on-voltage interval of the bias control signal may be within the off-voltage interval of the light emitting control signal.

[0011] According to an embodiment, the conduction voltage interval of the bias control signal may be located before the conduction voltage interval of the compensation control signal.

[0012] According to an embodiment, the turn-on voltage interval of the previous gate control signal and the turn-on voltage interval of the gate control signal may be sequentially located within the turn-on voltage interval of the compensation control signal.

[0013] According to one embodiment, when performing the self-scan operation, each of the bias control signal and the light emitting control signal may include a conduction voltage interval, and each of the gate control signal, the previous gate control signal and the compensation control signal may not include the conduction voltage interval.

[0014] According to an embodiment, the turn-on voltage interval of the bias control signal may be within the turn-off voltage interval of the light emitting control signal.

[0015] To achieve one purpose of the present invention, a pixel circuit according to an embodiment of the present invention may include: a first transistor including a first terminal connected to a first node, a gate terminal connected to a second node, and a second terminal connected to a third node; a second transistor including a first terminal for receiving a data signal, a second terminal connected to the first node, and a gate terminal for receiving a gate control signal; a third transistor including a first terminal connected to the third node, a second terminal connected to the second node, and a gate terminal for receiving a compensation control signal; a fourth transistor including a first terminal connected to the third node, a second terminal for receiving a first initialization voltage, and a gate terminal for receiving a bias control signal; a fifth transistor including a first terminal for receiving a first power supply voltage, a second terminal connected to the first node, and a gate terminal for receiving a bias control signal. a second terminal connected to the third node and a gate terminal receiving a light-emitting control signal; a sixth transistor including a first terminal connected to the third node, a second terminal connected to the fourth node, and a gate terminal receiving the light-emitting control signal; a seventh transistor including a first terminal connected to the fourth node, a second terminal receiving a second initialization voltage, and a gate terminal receiving the bias control signal; an eighth transistor including a first terminal connected to the first node, a second terminal receiving a bias voltage, and a gate terminal receiving the bias control signal; a storage capacitor including a first terminal receiving the first power supply voltage and a second terminal connected to the second node; and a light-emitting element including a first terminal connected to the fourth node and a second terminal receiving a second power supply voltage lower than the first power supply voltage. At this time, when the driving time of the panel driving frame is the minimum driving time, the pixel circuit can perform one display scanning operation, and when the driving time of the panel driving frame is not the minimum driving time, the pixel circuit can perform one display scanning operation and at least one self-scanning operation.

[0016] According to an embodiment, the third transistor may be implemented as an oxide thin film transistor.

[0017] According to an embodiment, the third transistor may be an NMOS transistor.

[0018] According to an embodiment, when the display scanning operation is performed, each of the gate control signal, the compensation control signal, the bias control signal, and the light emitting control signal may include a turn-on voltage interval.

[0019] According to an embodiment, the turn-on voltage interval of the gate control signal, the turn-on voltage interval of the compensation control signal, and the turn-on voltage interval of the bias control signal may be within the turn-off voltage interval of the light emitting control signal.

[0020] According to an embodiment, the turn-on voltage interval of the bias control signal and the turn-on voltage interval of the gate control signal may be sequentially located within the turn-on voltage interval of the compensation control signal.

[0021] According to an embodiment, when the self-scan operation is performed, each of the bias control signal and the light emitting control signal may include a conduction voltage interval, and each of the gate control signal and the compensation control signal may not include the conduction voltage interval.

[0022] According to an embodiment, the turn-on voltage interval of the bias control signal may be within the turn-off voltage interval of the light emitting control signal.

[0023] To achieve another object of the present invention, a display device according to an embodiment of the present invention may include: a display panel including a pixel circuit that performs an initialization operation of initializing a gate terminal of a driving transistor without applying an initialization control signal; a first gate driver and a second gate driver that apply a gate control signal to the pixel circuit via a gate line extending in a first direction and are arranged on both sides of the display panel in the first direction; a first compensation driver and a second compensation driver that apply a compensation control signal to the pixel circuit via a compensation line extending in the first direction and are arranged on both sides of the display panel in the first direction; a bias driver that applies a bias control signal to the pixel circuit via a bias line extending in the first direction and is arranged on one side of the display panel in the first direction; a light emitting driver that applies a light emitting control signal to the pixel circuit via a light emitting line extending in the first direction and is arranged on one side of the display panel in the first direction; a data driver that applies a data signal to the pixel circuit via a data line extending in a second direction intersecting the first direction; and a timing controller that controls the first gate driver, the second gate driver, the first compensation driver, the second compensation driver, the bias driver, the light emitting driver, and the data driver.

[0024] According to one embodiment, the pixel circuit may include: a first transistor corresponding to the driving transistor, including a first terminal connected to the first node, a gate terminal connected to the second node, and a second terminal connected to the third node; a second transistor, including a first terminal receiving the data signal, a second terminal connected to the first node, and a gate terminal receiving the gate control signal; a third transistor, including a first terminal connected to the third node, a second terminal connected to the second node, and a gate terminal receiving the compensation control signal; a fourth transistor, including a first terminal connected to the third node, a second terminal receiving a first initialization voltage, and a gate terminal receiving a previous gate control signal applied earlier than the gate control signal; a fifth transistor, including a first terminal receiving a first power supply voltage, a second terminal connected to the first node, and a gate terminal receiving a compensation control signal. a second terminal connected to the first node and a gate terminal receiving the light-emitting control signal; a sixth transistor including a first terminal connected to the third node, a second terminal connected to the fourth node, and a gate terminal receiving the light-emitting control signal; a seventh transistor including a first terminal connected to the fourth node, a second terminal receiving a second initialization voltage, and a gate terminal receiving the bias control signal; an eighth transistor including a first terminal connected to the first node, a second terminal receiving a bias voltage, and a gate terminal receiving the bias control signal; a storage capacitor including a first terminal receiving the first power supply voltage and a second terminal connected to the second node; and a light-emitting element including a first terminal connected to the fourth node and a second terminal receiving a second power supply voltage lower than the first power supply voltage. At this time, when the driving time of the panel driving frame is the minimum driving time, the pixel circuit can perform one display scanning operation, and when the driving time of the panel driving frame is not the minimum driving time, the pixel circuit can perform one display scanning operation and at least one self-scanning operation.

[0025] According to one embodiment, the pixel circuit may include: a first transistor corresponding to the driving transistor, including a first terminal connected to the first node, a gate terminal connected to the second node, and a second terminal connected to the third node; a second transistor, including a first terminal for receiving the data signal, a second terminal connected to the first node, and a gate terminal for receiving the gate control signal; a third transistor, including a first terminal connected to the third node, a second terminal connected to the second node, and a gate terminal for receiving the compensation control signal; a fourth transistor, including a first terminal connected to the third node, a second terminal for receiving the first initialization voltage, and a gate terminal for receiving the bias control signal; a fifth transistor, including a first terminal for receiving the first power supply voltage, a second terminal connected to the first node, and a gate terminal for receiving the bias control signal. a second terminal connected to the third node and a gate terminal receiving the light-emitting control signal; a sixth transistor including a first terminal connected to the third node, a second terminal connected to the fourth node, and a gate terminal receiving the light-emitting control signal; a seventh transistor including a first terminal connected to the fourth node, a second terminal receiving a second initialization voltage, and a gate terminal receiving the bias control signal; an eighth transistor including a first terminal connected to the first node, a second terminal receiving a bias voltage, and a gate terminal receiving the bias control signal; a storage capacitor including a first terminal receiving the first power supply voltage and a second terminal connected to the second node; and a light-emitting element including a first terminal connected to the fourth node and a second terminal receiving a second power supply voltage lower than the first power supply voltage. At this time, when the driving time of the panel driving frame is the minimum driving time, the pixel circuit can perform one display scanning operation, and when the driving time of the panel driving frame is not the minimum driving time, the pixel circuit can perform one display scanning operation and at least one self-scanning operation.

[0026] According to an embodiment of the present invention, a pixel circuit may include a first transistor including a first terminal connected to a first node, a gate terminal connected to a second node, and a second terminal connected to a third node; a second transistor including a first terminal for receiving a data signal, a second terminal connected to the first node, and a gate terminal for receiving a gate control signal; a third transistor including a first terminal connected to the third node, a second terminal connected to the second node, and a gate terminal for receiving a compensation control signal; a fourth transistor including a first terminal connected to the third node, a second terminal for receiving a first initialization voltage, and a gate terminal for receiving a previous gate control signal or a bias control signal applied earlier than the gate control signal; a fifth transistor including a first terminal for receiving a first power supply voltage, a second terminal connected to the first node, and a gate terminal for receiving a light emitting control signal; a sixth transistor including a first terminal connected to the third node, a second terminal connected to the fourth node, and a gate terminal for receiving the light emitting control signal; a seventh transistor including a first terminal connected to the fourth node, a second terminal for receiving a second initialization voltage, and a gate terminal for receiving a bias control signal; an eighth transistor including a first terminal connected to the first node, a second terminal for receiving a bias voltage, and a gate terminal for receiving a bias control signal; and a storage capacitor including a first terminal connected to the fourth node and a second terminal connected to the second node, and a light-emitting element including a first terminal connected to the fourth node and a second terminal receiving a second power supply voltage lower than the first power supply voltage, and when the driving time of the panel driving frame is the minimum driving time, the pixel circuit can perform a display scanning operation (i.e., an operation of receiving a data signal to make the light-emitting element emit light), and when the driving time of the panel driving frame is not the minimum driving time, the pixel circuit can perform a display scanning operation and at least one self-scanning operation (i.e., an operation of changing the characteristics of the driving transistor), so that the characteristics of the driving transistor are fixed during the panel driving frame. The display panel is fixed in a predetermined state, thereby preventing flickering on the display panel due to the hysteresis characteristic, and performing an initialization operation for initializing the gate terminal of the driving transistor without applying an initialization control signal (that is, since an initialization driver for providing an initialization control signal is not arranged on one side of the display panel, a compensation driver for providing a compensation control signal is additionally arranged in the space where the initialization driver is arranged in the prior art, so that the compensation control signal is applied on both sides of the display panel), thereby preventing the occurrence of uneven brightness due to the fall time and / or rise time of the compensation control signal depending on the deviation of the position of the pixel circuit in the display panel.

[0027] The display device according to the embodiment of the present invention includes the above-described pixel circuit, thereby providing a user with a high-quality image even if the display panel operates at a lower driving frequency.

[0028] However, the effects of the present invention are not limited to the above-mentioned effects, and various extensions can be achieved without departing from the spirit and concept of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 is a block diagram illustrating a display device according to an embodiment of the present invention.

[0030] Figure 2 Is used to illustrate Figure 1 A conceptual diagram of the driving operation of the display device.

[0031] Figure 3 It shows Figure 1 A timing diagram of an example in which a display device operates at a first driving frequency.

[0032] Figure 4 It shows Figure 1 A timing diagram of an example in which a display device operates at a second driving frequency.

[0033] Figure 5 It is shown that Figure 1 A circuit diagram of an example of a pixel circuit of a display device.

[0034] Figure 6 It shows Figure 5 A timing diagram showing an example of a pixel circuit performing a display scanning operation.

[0035] Figure 7 It shows Figure 5 A timing diagram of an example of a pixel circuit performing a self-scanning operation.

[0036] Figure 8 It is shown that Figure 1 A circuit diagram of another example of a pixel circuit of a display device.

[0037] Figure 9 It shows Figure 8 A timing diagram showing an example of a pixel circuit performing a display scanning operation.

[0038] Figure 10 It shows Figure 8 A timing diagram of an example of a pixel circuit performing a self-scanning operation.

[0039] Figure 11 is a block diagram illustrating an electronic device according to an embodiment of the present invention.

[0040] Figure 12 It shows Figure 11 FIG. 1 is a diagram showing an example of an electronic device implemented as a smart phone.

[0041] Description of Reference Numerals

[0042] 100: Display device 110: Display panel

[0043] 111: Pixel circuit 120-1: First gate driver

[0044] 120-2: Second gate driver 130-1: First compensation driver

[0045] 130-2: Second compensation driver 140: Bias driver

[0046] 150: Light emitting driver 160: Data driver

[0047] 170: Timing controller T1-T8: first transistor to eighth transistor

[0048] N1 to N4: first to fourth nodes CST: storage capacitor

[0049] ED: Light-emitting element GW[i]: Gate control signal

[0050] GC[i]: compensation control signal GB[i]: bias control signal

[0051] GW[i-1]: previous gate control signal EM[i]: light emitting control signal

[0052] VINT1: first initialization voltage VINT2: second initialization voltage

[0053] VBIAS: bias voltage 1000: electronic equipment

[0054] 1010: Processor 1020: Memory device

[0055] 1030: Storage device 1040: Input / output device

[0056] 1050: Power supply 1060: Display device DETAILED DESCRIPTION

[0057] Hereinafter, embodiments of the present invention will be described in more detail with reference to the accompanying drawings. The same reference numerals are used for the same components in the drawings, and repeated description of the same components will be omitted.

[0058] Figure 1 is a block diagram showing a display device according to an embodiment of the present invention, Figure 2 Is used to illustrate Figure 1 Conceptual diagram of the driving operation of the display device, Figure 3 It shows Figure 1 A timing diagram of an example of a display device operating at a first driving frequency, Figure 4 It shows Figure 1A timing diagram of an example in which a display device operates at a second driving frequency.

[0059] Reference Figures 1 to 4 , the display device 100 may include a display panel 110, a first gate driver 120-1, a second gate driver 120-2, a first compensation driver 130-1, a second compensation driver 130-2, a bias driver 140, a light emitting driver 150, a data driver 160 and a timing controller 170. At this time, the display device 100 can display images at multiple driving frequencies according to driving conditions. For example, the display device 100 can display images at multiple driving frequencies of 1 Hz to 120 Hz (i.e., the frame rate of the panel drive frame is 1 Hz to 120 Hz). In addition, the display device 100 may be an organic light emitting display device or a quantum dot light emitting display device, but is not limited thereto.

[0060] The display panel 110 may include a plurality of pixel circuits 111. For example, the pixel circuit 111 may include a red pixel circuit, a green pixel circuit, and a blue pixel circuit. At this time, each of the pixel circuits 111 may be connected to a gate line Sj (however, j is a positive integer greater than 1 and less than n) for transmitting a gate control signal, a compensation line Cj for transmitting a compensation control signal, a bias line Bj for transmitting a bias control signal, and an luminous line Ej for transmitting a luminous control signal. When the driving time of the panel driving frame is the minimum driving time, each of the pixel circuits 111 may perform a display scanning operation (i.e., an operation of receiving a data signal to cause the light-emitting element to emit light), and when the driving time of the panel driving frame is not the minimum driving time, each of the pixel circuits 111 may perform a display scanning operation and at least one self-scanning operation (i.e., an operation of changing the characteristics of the driving transistor). In addition, each of the pixel circuits 111 may perform an initialization operation of initializing the gate terminal of the driving transistor without applying an initialization control signal. To this end, each of the pixel circuits 111 may have a so-called 8T-1C structure including eight transistors and one capacitor. As Figure 1 As shown, the first gate driver 120-1 and the second gate driver 120-2 can be arranged on both sides of the display panel 110, the first compensation driver 130-1 and the second compensation driver 130-2 can also be arranged on both sides of the display panel 110, and the bias driver 140 can be arranged on one side of the display panel 110 (for example, on the left). Figure 1 The light emitting driver 150 may also be arranged on one side of the display panel 110 (for example, on the left side of the display panel 110). Figure 1 The middle is the right side of the display panel 110).

[0061] In one embodiment, each of the pixel circuits 111 includes: a first transistor (for example, named a driving transistor), including a first terminal connected to the first node, a gate terminal connected to the second node, and a second terminal connected to the third node; a second transistor (for example, named a switching transistor), including a first terminal receiving a data signal, a second terminal connected to the first node, and a gate terminal receiving a gate control signal; a third transistor (for example, named a compensation transistor), including a first terminal connected to the third node, a second terminal connected to the second node, and a gate terminal receiving a compensation control signal GC; a fourth transistor (for example, named an initialization transistor), including a first terminal connected to the third node, a second terminal receiving a first initialization voltage, and a gate terminal receiving a previous gate control signal applied earlier than the gate control signal; a fifth transistor (for example, named a first light-emitting transistor), including a first terminal connected to the third node, a second terminal receiving a first initialization voltage, and a gate terminal receiving a previous gate control signal applied earlier than the gate control signal A first terminal receiving a first power supply voltage, a second terminal connected to the first node, and a gate terminal receiving a light-emitting control signal; a sixth transistor (for example, named a second light-emitting transistor), including a first terminal connected to the third node, a second terminal connected to the fourth node, and a gate terminal receiving a light-emitting control signal; a seventh transistor (for example, named a reset transistor), including a first terminal connected to the fourth node, a second terminal receiving a second initialization voltage, and a gate terminal receiving a bias control signal; an eighth transistor (for example, named a self-scanning transistor), including a first terminal connected to the first node, a second terminal receiving a bias voltage, and a gate terminal receiving a bias control signal; a storage capacitor including a first terminal receiving the first power supply voltage and a second terminal connected to the second node; and a light-emitting element including a first terminal connected to the fourth node and a second terminal receiving a second power supply voltage smaller than the first power supply voltage. However, reference will be made to this. Figures 5 to 7 To be described later.

[0062] In another embodiment, each of the pixel circuits 111 includes: a first transistor (for example, named a driving transistor), including a first terminal connected to the first node, a gate terminal connected to the second node, and a second terminal connected to the third node; a second transistor (for example, named a switching transistor), including a first terminal for receiving a data signal, a second terminal connected to the first node, and a gate terminal for receiving a gate control signal; a third transistor (for example, named a compensation transistor), including a first terminal connected to the third node, a second terminal connected to the second node, and a gate terminal for receiving a compensation control signal; a fourth transistor (for example, named an initialization transistor), including a first terminal connected to the third node, a second terminal for receiving a first initialization voltage, and a gate terminal for receiving a bias control signal; a fifth transistor (for example, named a first light-emitting transistor), including a first terminal for receiving a first power supply voltage. a first terminal, a second terminal connected to the first node, and a gate terminal receiving a light-emitting control signal; a sixth transistor (for example, named a second light-emitting transistor), including a first terminal connected to the third node, a second terminal connected to the fourth node, and a gate terminal receiving a light-emitting control signal; a seventh transistor (for example, named a reset transistor), including a first terminal connected to the fourth node, a second terminal receiving a second initialization voltage, and a gate terminal receiving a bias control signal; an eighth transistor (for example, named a self-scanning transistor), including a first terminal connected to the first node, a second terminal receiving a bias voltage, and a gate terminal receiving a bias control signal; a storage capacitor including a first terminal receiving a first power supply voltage and a second terminal connected to the second node; and a light-emitting element including a first terminal connected to the fourth node and a second terminal receiving a second power supply voltage smaller than the first power supply voltage. However, reference will be made to this. Figures 8 to 10 This will be described later.

[0063] The first gate driver 120-1 and the second gate driver 120-2 may be connected to the display panel 110 through the gate lines S1 to Sn extending along the first direction. Accordingly, the first gate driver 120-1 and the second gate driver 120-2 may apply gate control signals to the display panel 110 through the gate lines S1 to Sn extending along the first direction. Specifically, Figure 3 and Figure 4As shown, the first gate driver 120-1 and the second gate driver 120-2 can apply a gate control signal having an on-voltage interval and an off-voltage interval to the display panel 110 during a display scan interval DISPLAY SCAN in which the pixel circuit 111 performs a display scan operation, and can apply a gate control signal having only an off-voltage interval to the display panel 110 during a self-scan interval SELFSCAN in which the pixel circuit 111 performs a self-scan operation. In addition, since the first gate driver 120-1 and the second gate driver 120-2 are arranged on both sides of the display panel 110 in the first direction and the first gate driver 120-1 and the second gate driver 120-2 apply the gate control signal on both sides of the display panel 110, deviation in the falling time and / or rising time of the gate control signal according to the position of the pixel circuit 111 in the display panel 110 can be avoided. For example, when the gate driver is disposed on only one side of the display panel 110 and the gate driver applies a gate control signal only on one side of the display panel 110, the fall time and / or rise time of the gate control signal may deviate depending on the position of the pixel circuit 111 within the display panel 110. As a result, uneven brightness may occur between an area close to the gate driver and an area far from the gate driver on the display panel 110. Therefore, since the display device 100 includes the first gate driver 120-1 and the second gate driver 120-2 disposed on both sides of the display panel 110 in the first direction, uneven brightness due to deviations in the fall time and / or rise time of the gate control signal depending on the position of the pixel circuit 111 within the display panel 110 can be prevented.

[0064] The first compensation driver 130-1 and the second compensation driver 130-2 may be connected to the display panel 110 through the compensation lines C1 to Cn extending along the first direction. Accordingly, the first compensation driver 130-1 and the second compensation driver 130-2 may apply compensation control signals to the display panel 110 through the compensation lines C1 to Cn extending along the first direction. Specifically, Figure 3 and Figure 4As shown, the first compensation driver 130-1 and the second compensation driver 130-2 may apply a compensation control signal having an on-voltage interval and an off-voltage interval to the display panel 110 during a display scan interval DISPLAY SCAN in which the pixel circuit 111 performs a display scan operation, and may apply a compensation control signal having only an off-voltage interval to the display panel 110 during a self-scan interval SELFSCAN in which the pixel circuit 111 performs a self-scan operation. In this case, since the first compensation driver 130-1 and the second compensation driver 130-2 are arranged on both sides of the display panel 110 in the first direction and the first compensation driver 130-1 and the second compensation driver 130-2 apply the compensation control signal on both sides of the display panel 110, a deviation in the falling time and / or rising time of the compensation control signal according to the position of the pixel circuit 111 in the display panel 110 may not occur. For example, if the compensation driver is only located on one side of the display panel 110 and applies the compensation control signal only on one side of the display panel 110, the fall time and / or rise time of the compensation control signal may vary depending on the position of the pixel circuit 111 within the display panel 110. This may cause uneven brightness between areas on the display panel 110 that are closer to the compensation driver and areas that are farther away from the compensation driver. Accordingly, since the display device 100 includes the first compensation driver 130-1 and the second compensation driver 130-2 located on both sides of the display panel 110 in a first direction, it is possible to prevent uneven brightness caused by the fall time and / or rise time of the compensation control signal varying depending on the position of the pixel circuit 111 within the display panel 110. In other words, since the pixel circuit 111 performs an initialization operation for initializing the gate terminal of the drive transistor without applying the initialization control signal, the initialization driver that provides the initialization control signal is not located on one side of the display panel 110. As a result, the compensation driver that provides the compensation control signal is additionally located in the space where the initialization driver is located in the conventional display device.

[0065] The bias driver 140 may be connected to the display panel 110 through the bias lines B1 to Bn extending along the first direction. Accordingly, the bias driver 140 may apply the bias control signal to the display panel 110 through the bias lines B1 to Bn extending along the first direction. Specifically, Figure 3 and Figure 4As shown, the bias driver 140 can apply a bias control signal having an on-voltage interval and an off-voltage interval to the display panel 110 in a display scanning interval DISPLAY SCAN in which the pixel circuit 111 performs a display scanning operation, and can also apply a bias control signal having an on-voltage interval and an off-voltage interval to the display panel 110 in a self-scanning interval SELF SCAN in which the pixel circuit 111 performs a self-scanning operation. In this case, the bias driver 140 can be arranged on one side of the display panel 110 in the first direction (i.e., on the left). Figure 1 The left side of the display panel 110 is shown in FIG. 1 ). The light emitting driver 150 may be connected to the display panel 110 through the light emitting lines E1 to En extending along the first direction. Accordingly, the light emitting driver 150 may apply a light emitting control signal to the display panel 110 through the light emitting lines E1 to En extending along the first direction. Specifically, as Figure 3 and Figure 4 As shown, the light emitting driver 150 can apply a light emitting control signal having an on-voltage interval and an off-voltage interval to the display panel 110 in a display scanning interval DISPLAY SCAN in which the pixel circuit 111 performs a display scanning operation, and can also apply a light emitting control signal having an on-voltage interval and an off-voltage interval to the display panel 110 in a self-scanning interval SELF SCAN in which the pixel circuit 111 performs a self-scanning operation. In this case, the light emitting driver 150 can be arranged on one side of the display panel 110 in the first direction (i.e., on the other side). Figure 1 (The figure shows the right side of the display panel 110 in the figure). Generally, the falling time and / or rising time of the gate control signal applied to the gate terminal of the switching transistor in the pixel circuit 111 and the falling time and / or rising time of the compensation control signal applied to the gate terminal of the compensation transistor in the pixel circuit 111 have a relatively large impact on the brightness of the pixel circuit 111. Conversely, the falling time and / or rising time of the bias control signal applied to the gate terminal of the reset transistor in the pixel circuit 111 and the falling time and / or rising time of the light emission control signal applied to the gate terminal of the light emission transistor in the pixel circuit 111 have a relatively small impact on the brightness of the pixel circuit 111. Accordingly, the bias driver 140 and the light emission driver 150 are arranged only on one side of the display panel 110.

[0066] The display panel 110 may be connected to the data driver 160 through the data lines D1 to Dm extending in a second direction intersecting (e.g., perpendicular to) the first direction. The data driver 160 may provide data signals (or data voltages) to the display panel 110 through the data lines D1 to Dm extending in the second direction intersecting the first direction. Specifically, Figure 3 and Figure 4As shown, the data driver 160 may apply a data signal (i.e., DS) to the display panel 110 during a display scan interval DISPLAY SCAN in which the pixel circuit 111 performs a display scan operation, and may not apply a data signal to the display panel 110 during a self-scan interval SELF SCAN in which the pixel circuit 111 performs a self-scan operation. The timing controller 170 may generate a plurality of control signals CTL1, CTL2, CTL3, CTL4, and CTL5 to control the first gate driver 120-1, the second gate driver 120-2, the first compensation driver 130-1, the second compensation driver 130-2, the bias driver 140, the light emitting driver 150, and the data driver 160. The timing controller 170 may receive image data DATA from an external component (e.g., a graphics processing unit (GPU)) through a predetermined interface, and may perform predetermined processing (e.g., brightness compensation, degradation compensation, etc.) on the image data DATA and provide the image data to the data driver 160. For example, Figure 2 As shown, the timing controller 170 can operate at a frequency other than the maximum driving frequency of the display panel 110 (i.e., Figure 2 In the embodiment, the maximum driving frequency of the display panel 110 is assumed to be 240 Hz, and one display scan interval DISPLAY SCAN and at least one self-scan interval SELF SCAN are performed at a driving frequency other than 120 Hz, 80 Hz, 60 Hz, and 48 Hz. Specifically, when the driving frequency of the display panel 110 is 120 Hz, one panel driving frame 1F includes one display scan interval DISPLAY SCAN and one self-scan interval SELF SCAN. When the driving frequency of the display panel 110 is 80 Hz, one panel driving frame 1F includes one display scan interval DISPLAY SCAN and two self-scan intervals SELF SCAN. When the driving frequency of the display panel 110 is 60 Hz, one panel driving frame 1F includes one display scan interval DISPLAY SCAN and three self-scan intervals SELF SCAN. When the driving frequency of the display panel 110 is 48 Hz, one panel driving frame 1F includes one display scan interval DISPLAY SCAN and four self-scan intervals SELF SCAN. In this way, the timing controller 170 can cope with the change of the driving frequency of the display panel 110 (ie, the change of the frame rate of the panel driving frame or the change of the driving time of the panel driving frame) by adjusting the number of the self-scan intervals SELF SCAN.

[0067] Specifically, if Figure 3 and Figure 4As shown, in the display scan interval DISPLAY SCAN in which the pixel circuit 111 performs a display scan operation, the bias control signal applied to the pixel circuit 111 through the bias lines B1 to Bn may include a conduction voltage interval, the gate control signal applied to the pixel circuit 111 through the gate lines S1 to Sn may also include a conduction voltage interval, the compensation control signal applied to the pixel circuit 111 through the compensation lines C1 to Cn may also include a conduction voltage interval, and the light emission control signal applied to the pixel circuit 111 through the light emission lines E1 to En may also include a conduction voltage interval. On the contrary, Figure 3 and Figure 4 As shown, in the self-scan interval SELF SCAN in which the pixel circuit 111 performs a self-scanning operation, the bias control signal applied to the pixel circuit 111 through the bias lines B1 to Bn may include a conduction voltage interval, the gate control signal applied to the pixel circuit 111 through the gate lines S1 to Sn does not include a conduction voltage interval, the compensation control signal applied to the pixel circuit 111 through the compensation lines C1 to Cn also does not include a conduction voltage interval, and the light-emitting control signal applied to the pixel circuit 111 through the light-emitting lines E1 to En may include a conduction voltage interval. In other words, the bias control signal and the light-emitting control signal both include a conduction voltage interval in the display scan interval DISPLAY SCAN and the self-scan interval SELF SCAN, while on the contrary, the gate control signal and the compensation control signal only include a conduction voltage interval in the display scan interval DISPLAY SCAN. In addition, due to Figure 3 and Figure 4 The waveforms shown are simply for the purpose of showing whether the bias control signal, gate control signal, compensation control signal, and light control signal have a conduction voltage range in the display scan interval DISPLAY SCAN and the self-scan interval SELF SCAN, respectively. Therefore, it should be understood that the waveform relationship between the bias control signal, gate control signal, compensation control signal, and light control signal is not accurately shown. Therefore, the accurate waveform relationship between the bias control signal, gate control signal, compensation control signal, and light control signal will be referred to. Figures 5 to 10 This will be described later.

[0068] In addition, the bias control signal including the on-voltage interval in both the display scan interval DISPLAY SCAN and the self-scan interval SELF SCAN can be driven at a first frequency that is higher than the driving frequency of the display panel 110 (i.e., the frame rate of the panel drive frame). In one embodiment, the driving frequency of the display panel 110 can be set to a divisor of the first frequency. For example, the first frequency can be set to twice or four times the maximum driving frequency of the display panel 110. When the maximum driving frequency of the display panel 110 is 120 Hz, the first frequency can be set to 240 Hz or 480 Hz. Accordingly, in one panel drive frame, the scanning operation according to the bias control signal applied to the bias lines B1 to Bn can be repeated multiple times at a predetermined period. For example, the bias driver 140 may perform one scanning operation during the display scan interval DISPLAYSCAN at all driving frequencies of the display panel 110, and may perform at least one scanning operation during the self-scan interval SELF SCAN at a driving frequency other than the maximum driving frequency of the display panel 110 (i.e., there is no self-scan interval SELF SCAN at the maximum driving frequency of the display panel 110). Furthermore, the light emitting control signal including the on-voltage interval in both the display scan interval DISPLAY SCAN and the self-scan interval SELF SCAN may also be driven at a first frequency higher than the driving frequency of the display panel 110 (i.e., the frame rate of the panel driving frame). For example, the first frequency may be set to two or four times the maximum driving frequency of the display panel 110. When the maximum driving frequency of the display panel 110 is 120 Hz, the first frequency may be set to 240 Hz or 480 Hz. Accordingly, in one panel driving frame, the scanning operation according to the light emitting control signal applied to the light emitting lines E1 to En may be repeated multiple times at a predetermined period. For example, the light emitting driver 150 may perform one scanning operation during the display scan interval DISPLAY SCAN at all driving frequencies of the display panel 110, and may perform at least one scanning operation during the self-scan interval SELF SCAN at a driving frequency other than the maximum driving frequency of the display panel 110 (i.e., there is no self-scan interval SELF SCAN at the maximum driving frequency of the display panel 110).

[0069] In contrast, the gate control signals and compensation control signals that include only the on-voltage interval during the display scan interval DISPLAY SCAN can be driven at a second frequency that is the same as the drive frequency of the display panel 110 (i.e., the frame rate of the panel drive frame). Therefore, the second frequency can be set to a submultiple of the first frequency. Accordingly, during one panel drive frame, a scan operation based on the gate control signals applied to the gate lines S1 to Sn can be performed once. For example, the first gate driver 120-1 and the second gate driver 120-2 can perform a scan operation once during the display scan interval DISPLAY SCAN at all drive frequencies of the display panel 110, and may not perform a scan operation during the self-scan interval SELF SCAN. Similarly, during one panel drive frame, a scan operation based on the compensation control signals applied to the compensation lines C1 to Cn can be performed once. For example, the first compensation driver 130-1 and the second compensation driver 130-2 can perform a scan operation once during the display scan interval DISPLAY SCAN at all drive frequencies of the display panel 110, and may not perform a scan operation during the self-scan interval SELFSCAN. As described above, since the pixel circuit 111 performs an initialization operation for initializing the gate terminal of the driving transistor without applying an initialization control signal, the display device 100 can exclude an initialization driver for providing the initialization control signal from one side of the display panel 110. Consequently, the first gate driver 120-1 and the second gate driver 120-2 for providing the gate control signal, and the first compensation driver 130-1 and the second compensation driver 130-2 for providing the compensation control signal, can be arranged on both sides of the display panel 110. Therefore, the gate control signal and the compensation control signal applied to the pixel circuit 111 can be applied from both sides of the display panel 110. This can reduce (or minimize) the variation in the fall time and / or rise time of the gate control signal and the compensation control signal depending on the position of the pixel circuit 111 within the display panel 110. As a result, uneven brightness caused by the aforementioned variation in the position of the pixel circuit 111 within the display panel 110 is prevented, allowing the display device 100 to provide a high-quality image to the user even when the display panel 110 operates at a lower driving frequency.

[0070] Figure 5 It is shown that Figure 1 A circuit diagram of an example of a pixel circuit of a display device, Figure 6 It shows Figure 5 A timing diagram showing an example of a pixel circuit performing a display scanning operation. Figure 7 It shows Figure 5 A timing diagram of an example of a pixel circuit performing a self-scanning operation.

[0071] Reference Figures 5 to 7 The pixel circuit 111 a may include a first transistor T1 , a second transistor T2 , a third transistor T3 , a fourth transistor T4 , a fifth transistor T5 , a sixth transistor T6 , a seventh transistor T7 , an eighth transistor T8 , a storage capacitor CST and a light emitting element ED.

[0072] The first transistor T1 (e.g., a driving transistor) may include a first terminal connected to the first node N1, a gate terminal connected to the second node N2, and a second terminal connected to the third node N3. The first transistor T1 may allow a driving current corresponding to the voltage at the second node N2 (i.e., the data signal stored in the storage capacitor CST) to flow to the light-emitting element ED. The second transistor T2 (e.g., a switching transistor) may include a first terminal connected to the data line Dk (i.e., receiving the data signal), a second terminal connected to the first node N1, and a gate terminal that receives the gate control signal GW[i]. When the second transistor T2 is turned on in response to the gate control signal GW[i] (i.e., in the on-voltage range of the gate control signal GW[i]), the data signal applied via the data line Dk may be transmitted to the first node N1. The third transistor T3 (e.g., a compensation transistor) may include a first terminal connected to the third node N3, a second terminal connected to the second node N2, and a gate terminal that receives the compensation control signal GC[i]. If the third transistor T3 is turned on in response to the compensation control signal GC[i] (i.e., in the on-voltage range of the compensation control signal GC[i]), the second terminal (i.e., the third node N3) and the gate terminal (i.e., the second node N2) of the first transistor T1 can be electrically connected. That is, if the third transistor T3 is turned on, the first transistor T1 can be diode-connected, thereby compensating the threshold voltage of the first transistor T1. The fourth transistor T4 (e.g., designated as the initialization transistor) can include a first terminal connected to the third node N3, a second terminal receiving the first initialization voltage VINT1, and a gate terminal receiving the previous gate control signal GW[i-1] applied earlier than the gate control signal GW[i]. If the fourth transistor T4 is turned on in response to the previous gate control signal GW[i-1] while the third transistor T3 is turned on (i.e., in the on-voltage range of the previous gate control signal GW[i-1]), the first initialization voltage VINT1 can be transmitted to the second node N2. That is, if the fourth transistor T4 is turned on while the third transistor T3 is turned on, the second node N2 (i.e., the gate terminal of the first transistor T1) can be initialized to the first initialization voltage VINT1, accordingly, the first transistor T1 can have an on-bias state (i.e., initialized to an on-bias state). At this time, the first initialization voltage VINT1 can be set to a voltage lower than the data signal applied through the data line Dk. Specifically, when the second transistor T2 is turned on and the data signal is transmitted to the first node N1, the second node N2 is initialized to the first initialization voltage VINT1 lower than the data signal, so that the first transistor T1 is turned on, accordingly, the data signal transmitted to the first node N1 can be transmitted to the second node N2 via the diode-connected first transistor T1.Therefore, a voltage corresponding to the data signal and the threshold voltage of the first transistor T1 may be applied to the second node N2. Accordingly, the storage capacitor CST may store the data signal that compensates for the threshold voltage of the first transistor T1. Furthermore, when the display panel 110 operates at a relatively low driving frequency, if the first initialization voltage VINT1 supplied to the second node N2 is too low, a flicker phenomenon may occur due to a significant hysteresis variation of the first transistor T1. Therefore, the first initialization voltage VINT1 may be set to a voltage higher than the second power supply voltage VSS.

[0073] The fifth transistor T5 (e.g., designated as the first light-emitting transistor) may include a first terminal receiving the first power supply voltage VDD, a second terminal connected to the first node N1, and a gate terminal receiving the light-emitting control signal EM[i]. When the fifth transistor T5 is turned on in response to the light-emitting control signal EM[i] (i.e., in the on-voltage range of the light-emitting control signal EM[i]), the light-emitting element ED may emit light due to the driving current flowing through the first transistor T1 between the first power supply voltage VDD and the second power supply voltage VSS. The sixth transistor T6 (e.g., designated as the second light-emitting transistor) may include a first terminal connected to the third node N3, a second terminal connected to the fourth node N4, and a gate terminal receiving the light-emitting control signal EM[i]. When the sixth transistor T6 is turned on in response to the light-emitting control signal EM[i] (i.e., in the on-voltage range of the light-emitting control signal EM[i]), the light-emitting element ED may emit light due to the current flowing through the first transistor T1 between the first power supply voltage VDD and the second power supply voltage VSS. In addition, in the above content, the fifth transistor T5 and the sixth transistor T6 are described as being simultaneously turned on and off by receiving the light-emitting control signal EM[i]. However, according to an embodiment, the fifth transistor T5 and the sixth transistor T6 may also receive independent light-emitting control signals. The seventh transistor T7 (for example, named as a reset transistor) may include a first terminal connected to the fourth node N4, a second terminal receiving the second initialization voltage VINT2, and a gate terminal receiving the bias control signal GB[i]. If the seventh transistor T7 is turned on in response to the bias control signal GB[i] (i.e., in the on-voltage range of the bias control signal GB[i]), the second initialization voltage VINT2 may be transmitted to the fourth node N4. That is, if the seventh transistor T7 is turned on, the fourth node N4 (i.e., the first terminal of the light-emitting element ED) may be reset to the second initialization voltage VINT2. Specifically, if the second initialization voltage VINT2 is supplied to the first terminal of the light-emitting element ED (e.g., the anode of the organic light-emitting diode), the parasitic capacitor of the light-emitting element ED is discharged, thereby preventing undesirable fine light emission and improving the black rendering capability of the pixel circuit 111a. In addition, the first initialization voltage VINT1 (i.e., the voltage for initializing the second node N2) and the second initialization voltage VINT2 (i.e., the voltage for initializing the fourth node N4) can be set to be different from each other. In addition, when the second initialization voltage VINT2 supplied to the fourth node N4 becomes higher than a predetermined reference, the parasitic capacitor of the light-emitting element ED may not be discharged but may be charged. Therefore, the second initialization voltage VINT2 can be set to a voltage lower than the second power supply voltage VSS. According to an embodiment, the second initialization voltage VINT2 can be changed based on the driving time of the panel drive frame (i.e., the frame rate of the panel drive frame).In this case, since the second initialization voltage VINT2 varies according to the operating frequency of the display panel 110 , the parasitic capacitor of the light emitting element ED may be effectively discharged.

[0074] The eighth transistor T8 may include a first terminal connected to the first node N1, a second terminal receiving a bias voltage VBIAS, and a gate terminal receiving a bias control signal GB[i]. If the eighth transistor T8 is turned on in response to the bias control signal GB[i] (i.e., in the on-voltage interval of the bias control signal GB[i]), the bias voltage VBIAS may be transmitted to the first node N1. That is, as the eighth transistor T8 is turned on, the bias voltage VBIAS is applied to the first node N1, and as the voltage of the first node N1 changes to the bias voltage VBIAS, the characteristic curve of the first transistor T1 may be changed. Accordingly, the brightness variation caused by the hysteresis of the first transistor T1 can be improved. For example, the bias voltage VBIAS can be set to a predetermined voltage (i.e., a DC voltage) within the voltage interval of the data signal or the gate-on voltage VGH of the gate control signal GW, etc. According to an embodiment, the bias voltage VBIAS can be changed based on the driving time of the panel drive frame (i.e., the frame rate of the panel drive frame). In this case, since the bias voltage VBIAS varies according to the operating frequency of the display panel 110, the brightness variation caused by the hysteresis of the first transistor T1 can be effectively improved. The storage capacitor CST may include a first terminal receiving the first power supply voltage VDD and a second terminal connected to the second node N2. As described above, since the data signal transmitted to the first node N1 when the second transistor T2 is turned on is transmitted to the second node N2 via the diode-connected first transistor T1, the storage capacitor CST can store the data signal compensated for the threshold voltage of the first transistor T1. The light-emitting element ED may include a first terminal connected to the fourth node N4 and a second terminal receiving a second power supply voltage VSS lower than the first power supply voltage VDD. As described above, the light-emitting element ED can emit light with a predetermined brightness based on the driving current provided by the first transistor T1. In one embodiment, the light-emitting element ED may be an organic light-emitting diode including an organic light-emitting layer. In another embodiment, the light-emitting element ED may be an inorganic light-emitting element formed using an inorganic substance (e.g., quantum dots). Depending on the embodiment, multiple light-emitting elements ED may also be connected in parallel and / or in series between the second power supply voltage VSS and the fourth node N4. Thus, the pixel circuit 111a may have a so-called 8T-1C structure including eight transistors T1 to T8 and one capacitor CST. In one embodiment, the third transistor T3 may be implemented as an oxide thin film transistor. In this case, compared to the case where the third transistor T3 is implemented as a low temperature polysilicon (LTPS) thin film transistor, the leakage current flowing through the third transistor T3 may be reduced. For example, Figure 5As shown, the third transistor T3 can be an NMOS transistor, and the first transistor T1, the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 can be p-channel metal oxide semiconductor (PMOS) transistors. However, this is merely exemplary, and at least one of the first transistor T1, the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 can also be an NMOS transistor. In addition, according to an embodiment, the pixel circuit 111a may further include a boost capacitor, wherein the boost capacitor includes a first terminal connected to the second node N2 and a second terminal connected to the gate terminal of the third transistor T3. The boost capacitor CB can increase the voltage of the second node N2.

[0075] In addition, when the driving time of the panel driving frame is the minimum driving time (that is, when the driving frequency of the display panel 110 is the maximum driving frequency), the pixel circuit 111a can perform a display scanning operation, and when the driving time of the panel driving frame is not the minimum driving time (that is, when the driving frequency of the display panel 110 is lower than the maximum driving frequency), the pixel circuit 111a can perform a display scanning operation and at least one self-scanning operation. As described above, the display scanning operation is an operation of receiving a data signal to make the light-emitting element ED emit light, and the self-scanning operation is an operation of changing the characteristics of the first transistor T1 (that is, the driving transistor). Figure 6 As shown, when the pixel circuit 111a performs a display scanning operation, each of the gate control signal GW[i], the previous gate control signal GW[i-1], the compensation control signal GC[i], the bias control signal GB[i], and the emission control signal EM[i] may include a conduction voltage interval (e.g., Figure 6In the embodiment of the present invention, the on-voltage interval of the gate control signal GW[i], the previous gate control signal GW[i-1], the bias control signal GB[i] and the light-emitting control signal EM[i] is included in the logic low (logic low) interval and the logic high (logic high) interval of the compensation control signal GC[i]. In addition, the on-voltage interval of the gate control signal GW[i], the on-voltage interval of the previous gate control signal GW[i-1], the on-voltage interval of the compensation control signal GC[i] and the on-voltage interval of the bias control signal GB[i] can be located within the cut-off voltage interval of the light-emitting control signal EM[i]. Moreover, the on-voltage interval of the bias control signal GB[i] can be located before the on-voltage interval of the compensation control signal GC[i]. Furthermore, the on-voltage interval of the previous gate control signal GW[i-1] and the on-voltage interval of the gate control signal GC[i] can be located in sequence within the on-voltage interval of the compensation control signal GC[i]. Specifically, once the off-voltage interval of the emission control signal EM[i] begins, a reset-bias operation BCB can be performed during the on-voltage interval of the bias control signal GB[i]. That is, with the fifth and sixth transistors T5 and T6 turned off and no drive current flowing through the light-emitting element ED, the seventh transistor T7 is turned on, and the second initialization voltage VINT2 can be applied to the fourth node N4. Furthermore, with the eighth transistor T8 turned on, the bias voltage VBIAS can be applied to the first node N1. Subsequently, an initialization operation INIT can be performed during the on-voltage interval of the compensation control signal GC[i] and the on-voltage interval of the previous gate control signal GW[i-1]. That is, since the third transistor T3 is turned on during the on-voltage interval of the compensation control signal GC[i] and the fourth transistor T4 is turned on during the on-voltage interval of the previous gate control signal GW[i-1], the first initialization voltage VINT1 can be applied to the second node N2. Next, a threshold voltage compensation and data write operation COMP / WR can be performed during the on-voltage interval of the compensation control signal GC[i] and the on-voltage interval of the gate control signal GW[i]. Specifically, the third transistor T3 is turned on during the on-voltage interval of the compensation control signal GC[i], the second transistor T2 is turned on during the on-voltage interval of the gate control signal GW[i], and the second node N2 is initialized to a first initialization voltage VINT1 lower than the data signal, turning on the first transistor T1. This allows the storage capacitor CST to store the data signal compensated for the threshold voltage of the first transistor T1. Subsequently, a light-emitting operation EMIT can be performed during the on-voltage interval of the light-emitting control signal EM[i]. Specifically, as the fifth transistor T5 and the sixth transistor T6 are turned on during the on-voltage interval of the light-emitting control signal EM[i], a drive current flows through the light-emitting element ED, causing the light-emitting element ED to emit light.

[0076] like Figure 7As shown, when the pixel circuit 111a performs a self-scanning operation, each of the bias control signal GB[i] and the light emitting control signal EM[i] may include a conduction voltage interval (eg, Figure 7 In other words, when the pixel circuit 111a performs the self-scanning operation, each of the gate control signal GW[i], the previous gate control signal GW[i-1], and the compensation control signal GC[i] only has a cut-off voltage interval (for example, in Figure 7 1] and the previous gate control signal GW[i-1] and the logic high interval of the compensation control signal GC[i]. In addition, the on-voltage interval of the bias control signal GB[i] can be located within the off-voltage interval of the light-emitting control signal EM[i]. Specifically, if the off-voltage interval of the light-emitting control signal EM[i] begins, the reset-bias operation BCB can be performed in the on-voltage interval of the bias control signal GB[i]. That is, in a state where the drive current does not flow through the light-emitting element ED as the fifth transistor T5 and the sixth transistor T6 are turned off, the second initialization voltage VINT2 can be applied to the fourth node N4 as the seventh transistor T7 is turned on, and the bias voltage VBIAS can be applied to the first node N1 as the eighth transistor T8 is turned on. Thereafter, the light-emitting operation EMIT can be performed in the on-voltage interval of the light-emitting control signal EM[i]. That is, as the fifth transistor T5 and the sixth transistor T6 are turned on in the on-voltage interval of the light emitting control signal EM[i], the driving current may flow through the light emitting element ED, so that the light emitting element ED may emit light.

[0077] Thus, the pixel circuit 111a may include a first transistor T1 including a first terminal connected to the first node N1, a gate terminal connected to the second node N2, and a second terminal connected to the third node N3, a second transistor T2 including a first terminal for receiving a data signal, a second terminal connected to the first node N1, and a gate terminal for receiving a gate control signal GW[i], a third transistor T3 including a first terminal connected to the third node N3, a second terminal connected to the second node N2, and a gate terminal for receiving a compensation control signal GC[i], a first terminal connected to the third node N3, a second terminal for receiving a first initialization voltage VINT1, and a gate terminal for receiving a previous gate control signal applied earlier than the gate control signal GW[i] a fourth transistor T4 connected to the gate terminal of GW[i-1], a fifth transistor T5 including a first terminal receiving the first power supply voltage VDD, a second terminal connected to the first node N1 and a gate terminal receiving the light emitting control signal EM[i], a sixth transistor T6 including a first terminal connected to the third node N3, a second terminal connected to the fourth node N4 and a gate terminal receiving the light emitting control signal EM[i], a seventh transistor T7 including a first terminal connected to the fourth node N4, a second terminal receiving the second initialization voltage VINT2 and a gate terminal receiving the bias control signal GB[i], a first terminal connected to the first node N1, a second terminal receiving the bias voltage VBIAS and a gate terminal receiving the bias control signal GB[i] i], an eighth transistor T8 having a gate terminal connected to the second node N2, a storage capacitor CST including a first terminal receiving the first power supply voltage VDD and a second terminal connected to the second node N2, and a light emitting element ED including a first terminal connected to the fourth node N4 and a second terminal receiving a second power supply voltage VSS lower than the first power supply voltage VDD (according to an embodiment, a boosting capacitor including a first terminal connected to the second node N2 and a second terminal connected to the gate terminal of the third transistor T3 may also be included). When the driving time of the panel driving frame is the minimum driving time, a display scanning operation (i.e., an operation of receiving a data signal to make the light emitting element emit light) may be performed once, and when the driving time of the panel driving frame is not the minimum driving time, a display scanning operation (i.e., an operation of receiving a data signal to make the light emitting element emit light) may be performed once. One display scanning operation and at least one self-scanning operation (i.e., an operation of changing the characteristics of the driving transistor) are performed, so that the characteristics of the driving transistor T1 are fixed in a predetermined state during a panel driving frame, thereby preventing a flicker phenomenon on the display panel 110 due to a hysteresis characteristic, and performing an initialization operation INIT for initializing the gate terminal of the driving transistor T1 without applying an initialization control signal (i.e., no initialization driver for providing the initialization control signal is arranged on one side of the display panel 110, so that a compensation driver for providing the compensation control signal GC[i] is additionally arranged in the space where the initialization driver is arranged in the prior art, so that the compensation control signal GC[i] is applied on both sides of the display panel 110).This prevents uneven brightness caused by variations in the falling and / or rising times of the compensation control signal GC[i] depending on the position of the pixel circuit 111a within the display panel 110. Consequently, the display device 100 including the pixel circuit 111a can provide users with high-quality images even when the display panel 110 operates at a lower driving frequency.

[0078] Figure 8 It is shown that Figure 1 A circuit diagram of another example of a pixel circuit of a display device, Figure 9 It shows Figure 8 A timing diagram showing an example of a pixel circuit performing a display scanning operation. Figure 10 It shows Figure 8 A timing diagram of an example of a pixel circuit performing a self-scanning operation.

[0079] Reference Figures 8 to 10 , the pixel circuit 111b may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a storage capacitor CST, and a light emitting element ED. According to an embodiment, the pixel circuit 111b may further include a boost capacitor having a first terminal connected to the second node N2 and a second terminal connected to the gate terminal of the third transistor T3, so as to boost the voltage of the second node N2. In addition, in addition to the signal applied to the gate terminal of the fourth transistor T4, Figure 8 The pixel circuit 111b and Figure 5 The pixel circuits 111a are substantially the same, and thus repeated descriptions therebetween will be omitted.

[0080] The third transistor T3 may include a first terminal connected to the third node N3, a second terminal connected to the second node N2, and a gate terminal receiving the compensation control signal GC[i]. If the third transistor T3 is turned on in response to the compensation control signal GC[i] (i.e., in the on-voltage interval of the compensation control signal GC[i]), the second terminal of the first transistor T1 (i.e., the third node N3) and the gate terminal (i.e., the second node N2) may be electrically connected. That is, if the third transistor T3 is turned on, the first transistor T1 may be diode-connected, thereby compensating for the threshold voltage of the first transistor T1. In one embodiment, the third transistor T3 may be implemented as an oxide thin film transistor. In this case, the leakage current flowing through the third transistor T3 may be reduced compared to the case where the third transistor T3 is implemented as a low-temperature polysilicon thin film transistor. For example, as Figure 8As shown, the third transistor T3 may be an NMOS transistor, and the first transistor T1, the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 may be PMOS transistors. However, this is merely exemplary, and at least one of the first transistor T1, the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 may be an NMOS transistor. The fourth transistor T4 may include a first terminal connected to the third node N3, a second terminal receiving the first initialization voltage VINT1, and a gate terminal receiving the bias control signal GB[i]. If the fourth transistor T4 is turned on in response to the bias control signal GB[i] when the third transistor T3 is turned on (i.e., in the on-voltage interval of the bias control signal GB[i]), the first initialization voltage VINT1 may be transmitted to the second node N2. That is, if the fourth transistor T4 is turned on while the third transistor T3 is turned on, the second node N2 (i.e., the gate terminal of the first transistor T1) is initialized to the first initialization voltage VINT1, thereby allowing the first transistor T1 to have an on-bias state (i.e., be initialized to an on-bias state). At this time, the first initialization voltage VINT1 can be set to a voltage lower than the data signal applied via the data line Dk. Specifically, when the second transistor T2 is turned on and the data signal is transmitted to the first node N1, the second node N2 is initialized to the first initialization voltage VINT1 lower than the data signal, causing the first transistor T1 to be turned on. Accordingly, the data signal transmitted to the first node N1 can be transmitted to the second node N2 via the diode-connected first transistor T1. Therefore, a voltage corresponding to the data signal and the threshold voltage of the first transistor T1 is applied to the second node N2, thereby allowing the storage capacitor CST to store the data signal compensated for the threshold voltage of the first transistor T1. In addition, when the display panel 110 operates at a lower driving frequency, if the first initialization voltage VINT1 supplied to the second node N2 is too low, a flicker phenomenon may occur due to a severe hysteresis variation of the first transistor T1. Therefore, the first initialization voltage VINT1 may be set to a voltage higher than the second power supply voltage VSS.

[0081] In addition, when the driving time of the panel driving frame is the minimum driving time (that is, when the driving frequency of the display panel 110 is the maximum driving frequency), the pixel circuit 111b can perform a display scanning operation, and when the driving time of the panel driving frame is not the minimum driving time (that is, when the driving frequency of the display panel 110 is lower than the maximum driving frequency), the pixel circuit 111b can perform a display scanning operation and at least one self-scanning operation. As described above, the display scanning operation is an operation of receiving a data signal to cause the light-emitting element ED to emit light, and the self-scanning operation is an operation of changing the characteristics of the first transistor T1 (that is, the driving transistor). As Figure 9 As shown, when the pixel circuit 111b performs a display scanning operation, each of the gate control signal GW[i], the compensation control signal GC[i], the bias control signal GB[i], and the emission control signal EM[i] may include a conduction voltage interval (e.g., Figure 9In the embodiment of the present invention, the logic low interval of the gate control signal GW[i], the bias control signal GB[i] and the light emitting control signal EM[i] and the logic high interval of the compensation control signal GC[i] are included. In addition, the on-voltage interval of the gate control signal GW[i], the on-voltage interval of the compensation control signal GC[i] and the on-voltage interval of the bias control signal GB[i] can be located within the cut-off voltage interval of the light emitting control signal EM[i]. Moreover, the on-voltage interval of the bias control signal GB[i] and the on-voltage interval of the gate control signal GW[i] can be located within the on-voltage interval of the compensation control signal GC[i] in sequence. Specifically, if the cut-off voltage interval of the light emitting control signal EM[i] and the on-voltage interval of the compensation control signal GC[i] start, the reset-bias operation BCB and the initialization operation INIT can be performed in the on-voltage interval of the bias control signal GB[i]. That is, when the fifth and sixth transistors T5 and T6 are turned off and the drive current does not flow through the light-emitting element ED, the seventh transistor T7 is turned on, and the second initialization voltage VINT2 can be applied to the fourth node N4. Furthermore, when the eighth transistor T8 is turned on, the bias voltage VBIAS can be applied to the first node N1. Furthermore, when the fifth and sixth transistors T5 and T6 are turned off and the drive current does not flow through the light-emitting element ED, the third and fourth transistors T3 and T4 are turned on, and the first initialization voltage VINT1 can be applied to the second node N2. Subsequently, the threshold voltage compensation and data write operations COMP / WR can be performed during the on-voltage intervals of the compensation control signal GC[i] and the on-voltage intervals of the gate control signal GW[i]. Specifically, the third transistor T3 is turned on during the on-voltage interval of the compensation control signal GC[i], the second transistor T2 is turned on during the on-voltage interval of the gate control signal GW[i], and the second node N2 is initialized to a first initialization voltage VINT1 lower than the data signal, turning on the first transistor T1. As a result, the data signal compensated for the threshold voltage of the first transistor T1 can be stored in the storage capacitor CST. Thereafter, the light-emitting operation EMIT can be performed during the on-voltage interval of the light-emitting control signal EM[i]. Specifically, as the fifth and sixth transistors T5 and T6 are turned on during the on-voltage interval of the light-emitting control signal EM[i], a drive current flows through the light-emitting element ED, thereby causing the light-emitting element ED to emit light.

[0082] like Figure 10 As shown, when the pixel circuit 111b performs the self-scanning operation, each of the bias control signal GB[i] and the light emitting control signal EM[i] may include a conduction voltage interval (eg, Figure 10In other words, when the pixel circuit 111b performs the self-scanning operation, each of the gate control signal GW[i] and the compensation control signal GC[i] only has a cut-off voltage interval (for example, Figure 10 ). Furthermore, the on-voltage interval of the bias control signal GB[i] can be within the off-voltage interval of the light-emitting control signal EM[i]. Specifically, if the off-voltage interval of the light-emitting control signal EM[i] begins, a reset-bias operation BCB can be performed during the on-voltage interval of the bias control signal GB[i]. That is, when the fifth transistor T5 and the sixth transistor T6 are turned off, preventing the drive current from flowing through the light-emitting element ED, the seventh transistor T7 is turned on, and the second initialization voltage VINT2 can be applied to the fourth node N4. Furthermore, when the eighth transistor T8 is turned on, the bias voltage VBIAS can be applied to the first node N1. Thereafter, a light-emitting operation EMIT can be performed during the on-voltage interval of the light-emitting control signal EM[i]. That is, when the fifth transistor T5 and the sixth transistor T6 are turned on during the on-voltage interval of the light-emitting control signal EM[i], a drive current flows through the light-emitting element ED, thereby causing the light-emitting element ED to emit light.

[0083] Thus, the pixel circuit 111b may include a first transistor T1 including a first terminal connected to the first node N1, a gate terminal connected to the second node N2, and a second terminal connected to the third node N3; a second transistor T2 including a first terminal for receiving a data signal, a second terminal connected to the first node N1, and a gate terminal for receiving a gate control signal GW[i]; a third transistor T3 including a first terminal connected to the third node N3, a second terminal connected to the second node N2, and a gate terminal for receiving a compensation control signal GC[i]; and a fourth transistor T4 including a first terminal connected to the third node N3, a second terminal for receiving a first initialization voltage VINT1, and a gate terminal for receiving a bias control signal GB[i]. 4. a fifth transistor T5 including a first terminal receiving the first power supply voltage VDD, a second terminal connected to the first node N1, and a gate terminal receiving the light emitting control signal EM[i]; a sixth transistor T6 including a first terminal connected to the third node N3, a second terminal connected to the fourth node N4, and a gate terminal receiving the light emitting control signal EM[i]; a seventh transistor T7 including a first terminal connected to the fourth node N4, a second terminal receiving the second initialization voltage VINT2, and a gate terminal receiving the bias control signal GB[i]; an eighth transistor T8 including a first terminal connected to the first node N1, a second terminal receiving the bias voltage VBIAS, and a gate terminal receiving the bias control signal GB[i]; A storage capacitor CST including a first terminal receiving a first power supply voltage VDD and a second terminal connected to the second node N2, and a light-emitting element ED including a first terminal connected to the fourth node N4 and a second terminal receiving a second power supply voltage VSS lower than the first power supply voltage VDD (according to an embodiment, the pixel circuit 111b may further include a boost capacitor including a first terminal connected to the second node N2 and a second terminal connected to the gate terminal of the third transistor T3), when the driving time of the panel driving frame is the minimum driving time, performs a display scanning operation (i.e., an operation of receiving a data signal to make the light-emitting element emit light), and when the driving time of the panel driving frame is not the minimum driving time, performs a display scanning operation and at least one self-scanning operation (i.e., an operation of changing the characteristics of the driving transistor), so that the characteristics of the driving transistor T1 are fixed to a predetermined state during a panel driving frame, thereby preventing a flickering phenomenon on the display panel 110 due to the hysteresis characteristic, and performing an initialization operation INIT for initializing the gate terminal of the driving transistor T1 without applying an initialization control signal (i.e., since an initialization driver for providing an initialization control signal is not arranged on one side of the display panel 110, a compensation driver for providing a compensation control signal GC[i] is additionally arranged in the space where the initialization driver is arranged in the prior art, so that the compensation control signal GC[i] is applied on both sides of the display panel 110).This prevents uneven brightness caused by variations in the falling and / or rising times of the compensation control signal GC[i] depending on the position of the pixel circuit 111a within the display panel 110. Consequently, the display device 100 including the pixel circuit 111a can provide users with high-quality images even when the display panel 110 operates at a lower driving frequency.

[0084] Figure 11 is a block diagram showing an electronic device according to an embodiment of the present invention, Figure 12 It shows Figure 11 FIG. 1 is a diagram showing an example of an electronic device implemented as a smart phone.

[0085] Reference Figure 11 and Figure 12 , the electronic device 1000 may include a processor 1010, a memory device 1020, a storage device 1030, an input / output device 1040, a power supply 1050, and a display device 1060. In this case, the display device 1060 may be Figure 1 Furthermore, the electronic device 1000 may further include various ports capable of communicating with a graphics card, a sound card, a memory card, a USB device, etc. or capable of communicating with other systems. In one embodiment, as Figure 12 As shown, electronic device 1000 may be implemented as a smartphone. However, this is merely an illustrative example, and electronic device 1000 is not limited thereto. For example, electronic device 1000 may also be implemented as a portable phone, a video phone, a smart tablet, a smartwatch, a tablet personal computer, a car navigation system, a computer monitor, a notebook computer, a head-mounted display device, etc.

[0086] The processor 1010 can perform specific calculations or tasks. Depending on the embodiment, the processor 1010 can be a microprocessor, a central processing unit, an application processor, etc. The processor 1010 can be connected to other components via an address bus, a control bus, and a data bus. Depending on the embodiment, the processor 1010 can also be connected to an expansion bus such as a peripheral component interconnect (PCI) bus. The memory device 1020 can store data required for the operation of the electronic device 1000. For example, the memory device 1020 may include a nonvolatile memory device such as an Erasable Programmable Read-Only Memory (EPROM) device, an Electrically Erasable Programmable Read-Only Memory (EEPROM) device, a flash memory device, a Phase Change Random Access Memory (PRAM) device, a Resistance Random Access Memory (RRAM) device, a Nano Floating Gate Memory (NFGM) device, a Polymer Random Access Memory (PoRAM) device, a Magnetic Random Access Memory (MRAM) device, a Ferroelectric Random Access Memory (FRAM) device, and / or a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, or the like. The storage device 1030 may include a solid-state drive (SSD), a hard disk drive (HDD), a CD-ROM, or the like.The input / output device 1040 may include input means such as a keyboard, keypad, touchpad, touch screen, mouse, etc., and output means such as a speaker, printer, etc. Depending on the embodiment, the display device 1060 may also be included in the input / output device 1040. The power supply 1050 may provide the power required for the operation of the electronic device 1000. The display device 1060 may be connected to other components via the aforementioned bus or other communication links.

[0087] The display device 1060 can display an image corresponding to the visual information of the electronic device 1000. In this case, the display device 1060 can be an organic light-emitting display device or a quantum dot light-emitting display device, but is not limited thereto. The display device 1060 can include a pixel circuit that performs a display scan operation when the driving time of the panel drive frame is the minimum driving time, and performs a display scan operation and at least one self-scan operation when the driving time of the panel drive frame is not the minimum driving time, and performs an initialization operation to initialize the gate terminal of the drive transistor without applying an initialization control signal, so that the characteristics of the drive transistor are fixed in a predetermined state during the panel drive frame, thereby preventing flickering on the display panel due to hysteresis characteristics, and causes the compensation control signal to be applied on both sides of the display panel, thereby preventing uneven brightness on the display panel. Therefore, even if the display panel operates at a low driving frequency, the display device 1060 can provide a high-quality image to the user. Specifically, the pixel circuit included in the display device 1060 may include a first transistor including a first terminal connected to the first node, a gate terminal connected to the second node and a second terminal connected to the third node, a second transistor including a first terminal for receiving a data signal, a second terminal connected to the first node and a gate terminal for receiving a gate control signal, a third transistor including a first terminal connected to the third node, a second terminal connected to the second node and a gate terminal for receiving a compensation control signal, a fourth transistor including a first terminal connected to the third node, a second terminal for receiving a first initialization voltage and a gate terminal for receiving a previous gate control signal or a bias control signal applied earlier than the gate control signal, and a fifth transistor including a first terminal for receiving a first power supply voltage, a second terminal connected to the first node and a gate terminal for receiving a light emitting control signal. a transistor, a sixth transistor including a first terminal connected to the third node, a second terminal connected to the fourth node, and a gate terminal receiving a light emitting control signal, a seventh transistor including a first terminal connected to the fourth node, a second terminal receiving a second initialization voltage, and a gate terminal receiving a bias control signal, an eighth transistor including a first terminal connected to the first node, a second terminal receiving a bias voltage, and a gate terminal receiving the bias control signal, a storage capacitor including a first terminal receiving a first power supply voltage and a second terminal connected to the second node, and a light emitting element including a first terminal connected to the fourth node and a second terminal receiving a second power supply voltage lower than the first power supply voltage (depending on the embodiment, the pixel circuit may further include a boosting capacitor including a first terminal connected to the second node and a second terminal connected to the gate terminal of the third transistor). However, this has been described above, and thus repeated description thereof is omitted.

[0088] Industrial applicability

[0089] The present invention can be applied to display devices and electronic devices including the same. For example, the present invention can be applied to mobile phones, smartphones, video phones, smart tablets, smart watches, tablet personal computers, vehicle navigation systems, televisions, computer monitors, notebook computers, head-mounted displays, and the like.

[0090] Although the present invention has been described above with reference to exemplary embodiments, those skilled in the art will appreciate that various modifications and variations may be made to the present invention without departing from the spirit and technical scope of the invention as described in the claims.

Claims

1. A pixel circuit, characterized in that: include a first transistor including a first terminal connected to the first node, a gate terminal connected to the second node, and a second terminal connected to the third node; a second transistor comprising a first terminal for receiving a data signal, a second terminal connected to the first node, and a gate terminal for receiving a gate control signal; a third transistor comprising a first terminal connected to the third node, a second terminal connected to the second node, and a gate terminal receiving a compensation control signal; a fourth transistor comprising a first terminal connected to the third node, a second terminal receiving a first initialization voltage, and a gate terminal receiving a previous gate control signal applied earlier than the gate control signal; a fifth transistor comprising a first terminal receiving a first power supply voltage, a second terminal connected to the first node, and a gate terminal receiving a light emitting control signal; a sixth transistor comprising a first terminal connected to the third node, a second terminal connected to the fourth node, and a gate terminal receiving the light emitting control signal; a seventh transistor comprising a first terminal connected to the fourth node, a second terminal receiving a second initialization voltage, and a gate terminal receiving a bias control signal; an eighth transistor comprising a first terminal connected to the first node, a second terminal receiving a bias voltage, and a gate terminal receiving the bias control signal; a storage capacitor comprising a first terminal receiving the first power supply voltage and a second terminal connected to the second node; as well as a light emitting element including a first terminal connected to the fourth node and a second terminal receiving a second power supply voltage lower than the first power supply voltage, Among them, when the driving time of the panel driving frame is the minimum driving time, the pixel circuit performs a display scanning operation; when the driving time of the panel driving frame is not the minimum driving time, the pixel circuit performs the display scanning operation and at least one self-scanning operation.

2. The pixel circuit according to claim 1, wherein: The third transistor is implemented as an oxide thin film transistor.

3. The pixel circuit according to claim 2, wherein: The third transistor is an NMOS transistor.

4. The pixel circuit according to claim 1, wherein: When the display scanning operation is performed, each of the gate control signal, the previous gate control signal, the compensation control signal, the bias control signal, and the light emitting control signal includes a turn-on voltage interval.

5. The pixel circuit according to claim 4, wherein: The on-voltage interval of the gate control signal, the on-voltage interval of the previous gate control signal, the on-voltage interval of the compensation control signal, and the on-voltage interval of the bias control signal are located within the off-voltage interval of the light emitting control signal.

6. The pixel circuit according to claim 5, wherein: The conduction voltage interval of the bias control signal is located before the conduction voltage interval of the compensation control signal.

7. The pixel circuit according to claim 6, wherein: The turn-on voltage interval of the previous gate control signal and the turn-on voltage interval of the gate control signal are sequentially located within the turn-on voltage interval of the compensation control signal.

8. The pixel circuit according to claim 1, wherein: When the self-scan operation is performed, each of the bias control signal and the light emitting control signal includes a conduction voltage interval, and each of the gate control signal, the previous gate control signal, and the compensation control signal does not include the conduction voltage interval.

9. The pixel circuit according to claim 8, wherein: The on-voltage interval of the bias control signal is within the off-voltage interval of the light emitting control signal.

10. A pixel circuit, characterized in that: include: a first transistor including a first terminal connected to the first node, a gate terminal connected to the second node, and a second terminal connected to the third node; a second transistor comprising a first terminal for receiving a data signal, a second terminal connected to the first node, and a gate terminal for receiving a gate control signal; a third transistor comprising a first terminal connected to the third node, a second terminal connected to the second node, and a gate terminal receiving a compensation control signal; a fourth transistor comprising a first terminal connected to the third node, a second terminal receiving a first initialization voltage, and a gate terminal receiving a bias control signal; a fifth transistor comprising a first terminal receiving a first power supply voltage, a second terminal connected to the first node, and a gate terminal receiving a light emitting control signal; a sixth transistor comprising a first terminal connected to the third node, a second terminal connected to the fourth node, and a gate terminal receiving the light emitting control signal; a seventh transistor comprising a first terminal connected to the fourth node, a second terminal receiving a second initialization voltage, and a gate terminal receiving the bias control signal; an eighth transistor comprising a first terminal connected to the first node, a second terminal receiving a bias voltage, and a gate terminal receiving the bias control signal; a storage capacitor comprising a first terminal receiving the first power supply voltage and a second terminal connected to the second node; as well as a light emitting element including a first terminal connected to the fourth node and a second terminal receiving a second power supply voltage lower than the first power supply voltage, Among them, when the driving time of the panel driving frame is the minimum driving time, the pixel circuit performs a display scanning operation; when the driving time of the panel driving frame is not the minimum driving time, the pixel circuit performs the display scanning operation and at least one self-scanning operation.

11. The pixel circuit according to claim 10, wherein: The third transistor is implemented as an oxide thin film transistor.

12. The pixel circuit according to claim 11, wherein: The third transistor is an NMOS transistor.

13. The pixel circuit according to claim 10, wherein: When the display scanning operation is performed, each of the gate control signal, the compensation control signal, the bias control signal, and the light emitting control signal includes a conduction voltage interval.

14. The pixel circuit according to claim 13, wherein: The turn-on voltage interval of the gate control signal, the turn-on voltage interval of the compensation control signal, and the turn-on voltage interval of the bias control signal are located within the turn-off voltage interval of the light emitting control signal.

15. The pixel circuit according to claim 14, wherein: The on-voltage interval of the bias control signal and the on-voltage interval of the gate control signal are sequentially located within the on-voltage interval of the compensation control signal.

16. The pixel circuit according to claim 10, wherein: When the self-scan operation is performed, each of the bias control signal and the light emitting control signal includes a conduction voltage interval, and each of the gate control signal and the compensation control signal does not include the conduction voltage interval.

17. The pixel circuit according to claim 16, wherein: The on-voltage interval of the bias control signal is within the off-voltage interval of the light emitting control signal.

18. A display device comprising: a display panel including a pixel circuit that performs an initialization operation of initializing a gate terminal of a driving transistor without applying an initialization control signal; a first gate driver and a second gate driver, applying gate control signals to the pixel circuits via gate lines extending along a first direction, and arranged on both sides of the display panel in the first direction; a first compensation driver and a second compensation driver, applying compensation control signals to the pixel circuits via compensation lines extending along the first direction, and arranged on both sides of the display panel in the first direction; a bias driver that applies a bias control signal to the pixel circuit through a bias line extending along the first direction and is arranged on one side of the display panel in the first direction; a light emitting driver that applies a light emitting control signal to the pixel circuit via a light emitting line extending along the first direction and is arranged on one side of the display panel in the first direction; a data driver for applying a data signal to the pixel circuit via a data line extending in a second direction intersecting the first direction; as well as a timing controller, controlling the first gate driver, the second gate driver, the first compensation driver, the second compensation driver, the bias driver, the light emitting driver, and the data driver, The pixel circuit is a pixel circuit according to any one of claims 1 to 17.

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