Semiconductor package
By setting dams and trenches on the packaging substrate to separate the bottom filler, the problems of long filling time and void trapping risk are solved, resulting in faster filling and higher packaging reliability.
CN113707619BActive Publication Date: 2026-06-30SAMSUNG ELECTRONICS CO LTD
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SAMSUNG ELECTRONICS CO LTD
- Filing Date
- 2021-03-12
- Publication Date
- 2026-06-30
AI Technical Summary
Technical Problem
In semiconductor packaging, the filling process of filler material is time-consuming and carries a high risk of voids being trapped, which increases the possibility of moisture absorption and short circuits between adjacent solder bumps.
Method used
Dams and trenches are created on the packaging substrate to separate the bottom filler into discontinuous sections, forming air channels to facilitate air discharge and reduce void trapping.
Benefits of technology
Shortening the fill time reduces void trapping, lowers the risk of short circuits caused by moisture absorption, and improves packaging reliability.
✦ Generated by Eureka AI based on patent content.
Smart Images
Figure CN113707619B_ABST
Abstract
This invention provides a semiconductor package including a package substrate, a semiconductor chip on the package substrate, and a plurality of underfill materials between the package substrate and the semiconductor chip. The package substrate includes trenches formed in the package substrate and a plurality of dams on either side of the trenches. In a cross-sectional view of the semiconductor package in which the package substrate provides a basic reference level, the top surfaces of the plurality of dams may be located at a level lower than the bottom surface of the semiconductor chip.
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