High power semiconductor package device and its bonding process

Abstract

This invention discloses a high-power semiconductor packaging device and its bonding process. The packaging device includes pins, a semiconductor chip, and multiple bonding wires. The multiple bonding wires are configured such that: some bonding wires run straight along a reference direction; some bonding wires with their first solder joints located to the left of the straight-running bonding wires are offset to the left relative to the reference direction in an arc shape; and some bonding wires with their first solder joints located to the right of the straight-running bonding wires are offset to the right relative to the reference direction in an arc shape, thereby spreading out in a fan shape in the horizontal direction. With the bonding plane of the pin as a reference, the arc height of each bonding wire increases sequentially. With the second solder joint of one of the bonding wires as the Z-axis reference, the Z-offset of the second solder joints of the remaining bonding wires increases sequentially, and the length of the vertical segments of the multiple bonding wires increases sequentially. The multiple bonding wires are spread out in a three-dimensional fan shape in layers, which solves the interference between lines caused by traditional parallel arrangement, and the dispersed layout reduces the risk of wire misalignment due to thermal stress.

Description

Technical Field

[0001] This invention relates to the field of semiconductor packaging technology, and more specifically to a high-power semiconductor packaging device and its bonding process. Background Technology

[0002] In the field of high-power semiconductor device packaging, especially in the packaging and production of power semiconductor devices such as IGBTs, silicon carbide MOSFETs, and gallium nitride HEMTs, bonding wires, as the core structure for electrical connection between chip pads and pins, have their arrangement, quantity, and process parameters directly determining the device's current carrying capacity, conductivity, heat dissipation effect, and long-term operational reliability.

[0003] In existing technologies, the wire bonding process for TO-247 packages often uses multiple bonding wires connected in parallel to improve current carrying capacity. Traditionally, the source (S) pin typically uses a configuration of four 15mil wires. The conventional approach is to set all four wires to have the same arc height, path, and similar height to simplify the bonding process, connecting the four wires from the pad to the S pin with the same arc height, path, and similar height. However, even if all wires are electrically part of the same network (e.g., as the source), their physical overlap can still lead to serious reliability issues due to reasons including:

[0004] 1. Voltage difference exists during high-frequency switching transients: Due to parasitic inductance (Ls≈1–2 nH / line), when di / dt> 1000 A / μs, a transient voltage difference of 1–2V can be generated between adjacent bonding wires, forming a circulating current at the bonding point, leading to local overheating;

[0005] 2. Unstable contact resistance: The overlap is only a physical contact, not a metallurgical bond, and the resistance is prone to drift due to fretting wear during thermal cycling;

[0006] 3. Inducing secondary short circuits: After the lap solder wires sag, they may come into contact with the gate (G) or drain (D) solder wires, causing permanent failure;

[0007] 4. Molding process disturbance: The flow and impact of epoxy resin (EMC) can easily cause parallel solder lines to bunch together, increasing the probability of overlap.

[0008] Currently, the main methods used to address this are as follows:

[0009] 1. Increase the spacing between solder lines, but this is limited by the package size;

[0010] 2. Reducing the arc height will increase parasitic inductance;

[0011] 3. Use copper clips instead, but the cost is high and the chip needs to be modified. Summary of the Invention

[0012] The technical problem to be solved by the present invention is to provide a high-power semiconductor packaging device and its bonding process to avoid inter-line interference and improve structural reliability.

[0013] The technical solution adopted by the present invention to solve the above-mentioned technical problems is as follows: Firstly, a high-power semiconductor packaging device is provided, including pins, a semiconductor chip and multiple bonding wires; the semiconductor chip includes at least two pads, and the multiple bonding wires are respectively connected to the pads and the pins; the first solder joints of the multiple bonding wires on the same pad are separated from each other, and the second solder joints of each bonding wire on the pin are separated from each other.

[0014] The core improvement lies in using the straight line connecting the center point of the first solder joint to the center point of the second solder joint of each bonding wire as the reference direction. The multiple bonding wires are configured such that: some bonding wires run straight along the reference direction; some bonding wires with the first solder joint located to the left of the bonding wire in the straight direction are offset to the left in an arc relative to the reference direction; and some bonding wires with the first solder joint located to the right of the bonding wire in the straight direction are offset to the right in an arc relative to the reference direction. Thus, each bonding wire spreads out in a fan shape in the horizontal direction. With the bonding plane of the pin as the reference, the arc height of each bonding wire increases sequentially. With the second solder joint of one of the bonding wires as the Z-axis reference, the Z-offset of the second solder joint of the remaining bonding wires increases sequentially. The root of the bonding wire at the second solder joint forms a vertical segment, and the length of the vertical segment of the multiple bonding wires increases sequentially. The multiple bonding wires as a whole spread out in a three-dimensional fan shape in layers, avoiding interference between lines.

[0015] Preferably, a micro-arc transition section is provided between the first arc segment extending from the first solder joint and the vertical segment at the second solder joint in the bonding wire. The length of the micro-arc transition section along the extension direction of the bonding wire is 3 to 5 times the wire diameter, and the radius of curvature of the micro-arc transition section is 2 to 3 times the wire diameter of the bonding wire, so that stress can be released and stress can be avoided from being concentrated again due to the transition being too short.

[0016] Preferably, the multiple bonding wires include two centrally aligned straight bonding wires, which run straight along their respective reference directions. One of the centrally aligned straight bonding wires has one or more left-curved bonding wires offset to the left on its left side, and the other centrally aligned straight bonding wire has one or more right-curved bonding wires offset to the right on its right side. This layout of centrally aligned straight wires and offset bonding wires on both sides achieves a uniform fan-shaped spread in the horizontal direction. The offset angles of the left-side offset bonding wires are fixed or gradually decrease; the offset angles of the right-side offset bonding wires are fixed or gradually increase; this avoids excessively small local spacing caused by multiple offset wires.

[0017] Preferably, the offset angle of the bond line offset to the left in an arc is -10° to 0°, and the offset angle of the bond line offset to the right in an arc is 0° to 10°. This offset angle range can ensure effective dispersion in the horizontal direction without increasing the stress on the bond line due to excessive offset angle.

[0018] Preferably, the arc height of each bonding line increases sequentially along the bonding line arrangement direction, with an increment of 0.1mm to 0.15mm. By setting the gradient of the arc height, the bonding lines are layered in the vertical direction, further increasing the spacing between the lines.

[0019] Preferably, the Z offset of the second solder joint is a virtual height compensation amount set by the bonding machine program. The Z offset range is 20μm to 100μm, which increases sequentially. The spatial layering of the bonding wire root is achieved by stepping up the Z direction, thus avoiding root interference.

[0020] Preferably, the minimum spacing between any two adjacent bonding wires is greater than 1.5 times the bonding wire diameter, which ensures that there is no contact or interference between the wires in terms of spacing value, while reducing the impact of electromagnetic coupling.

[0021] Preferably, the package is a TO-247 package, and the pins are source pins, which are compatible with the mainstream package forms of high-power semiconductor devices.

[0022] Preferably, the semiconductor chip is a silicon carbide MOSFET chip or a gallium nitride HEMT chip, which is suitable for wide bandgap high-power semiconductor devices and improves their packaging performance.

[0023] Secondly, a bonding process for a high-power semiconductor packaged device is provided, comprising the following steps:

[0024] A semiconductor chip is mounted and fixed on a chip holder of a lead frame. The semiconductor chip has at least two pads, and the lead frame has corresponding pins.

[0025] Multiple bond wires are configured independently in the bonder program, as follows:

[0026] Using the straight line connecting the center point of the first solder joint to the center point of the second solder joint corresponding to each bonding wire as the reference direction, the multiple bonding wires are configured such that: some bonding wires run straight along the reference direction, some bonding wires with the first solder joint position on the left side of the bonding wire in the straight direction are offset to the left in an arc relative to the reference direction, and some bonding wires with the first solder joint position on the right side of the bonding wire in the straight direction are offset to the right in an arc relative to the reference direction, so that each bonding wire is fanned out in the horizontal direction;

[0027] Using the bonding plane of the pins as a reference, the arc height of each bonding line is set to increase sequentially;

[0028] Taking the second solder joint of one of the bonding wires as the Z-axis reference, the Z-offset of the second solder joint of the remaining bonding wires increases sequentially, and the root of the bonding wire at the second solder joint forms a vertical line segment, and the length of the vertical line segment of multiple bonding wires increases sequentially.

[0029] The bonding process is performed according to the configured bonding machine program, bonding each bonding wire from the corresponding pad to the pin. The first solder joints on the same pad are separated from each other, and the second solder joints on the pins are separated from each other.

[0030] The beneficial effects of this invention are:

[0031] To avoid inter-line interference and improve structural reliability: By designing the bonding wires as a three-dimensional fan-shaped layered structure with horizontally fan-shaped spread-out, vertically increasing arc height, and Z-shaped stepped elevation at the root, multiple bonding wires can be spatially distributed in all directions. This solves the problems of inter-line interference and contact short circuit caused by traditional parallel arrangement. At the same time, the distributed layout reduces the risk of bonding wire displacement caused by thermal stress and is suitable for complex working conditions of high and low temperature cycles.

[0032] To improve conductivity and heat dissipation performance and match the characteristics of wide bandgap devices: the horizontal fan-shaped spread increases the horizontal spacing of the bonding wires, and the arc height gradient and Z-axis step increase the vertical spatial gap. This not only reduces the electromagnetic coupling between the bonding wires and improves the high-frequency operating performance of the device, but also optimizes the heat dissipation channel inside the device and accelerates heat conduction, perfectly adapting to the high-frequency and high-power operating requirements of wide bandgap high-power semiconductor devices such as silicon carbide MOSFETs and gallium nitride HEMTs.

[0033] Improve solder joint fault tolerance and increase packaging yield: The first solder joints of multiple bonding wires on the same pad are separated from each other, and the second solder joints on the pins are evenly spaced. With the three-dimensional distributed layout of multiple bonding wires, the connection fluctuation of a single solder joint will not directly cause the device electrical connection failure, which greatly improves the fault tolerance of packaging production and increases the effective soldering area.

[0034] Reduce bond line stress and improve high-temperature reliability: The bias angle, arc height increment and Z offset are all designed with a reasonable range of gradient values ​​to avoid bond line stress concentration caused by excessive structural dispersion. At the same time, the three-dimensional layered structure disperses the shear stress caused by the mismatch of thermal expansion coefficients of the packaging materials, so that the device performs well in HTSL high-temperature storage tests without problems such as solder joint cracking and line contact.

[0035] High process adaptability and low modification cost: The bonding process allows for independent parameter configuration of each bonding wire through the bonding machine program, without the need to modify the basic structure such as the TO-247 lead frame and semiconductor chip. It is compatible with existing bonding processes and packaging production lines such as aluminum wire ultrasonic cold pressure bonding and gold wire hot pressure ultrasonic bonding. The process modification cost is low and it is easy to scale up production. Attached Figure Description

[0036] Figure 1 This is a three-dimensional schematic diagram of the pins, pads, and bonding wire connections in the high-power semiconductor package device of the present invention. Figure 1 ;

[0037] Figure 2 This is a front view schematic diagram of the pins, pads, and bonding wire connections in the high-power semiconductor packaging device of the present invention.

[0038] Figure 3 This is a left-side view of the pins, pads, and bonding wire connections in the high-power semiconductor packaging device of the present invention.

[0039] Figure 4 This is a top view schematic diagram of the pins, pads, and bonding wire connections in the high-power semiconductor packaging device of the present invention.

[0040] Figure 5 This is a partially enlarged schematic diagram of the pins, pads, and bonding wires in the high-power semiconductor packaging device of the present invention. The dashed lines in the diagram represent the reference directions of each bonding wire.

[0041] Figure 6 This is a three-dimensional schematic diagram of the pins, pads, and bonding wire connections in the high-power semiconductor package device of the present invention. Figure 2 ;

[0042] Figure 7 This is a three-dimensional schematic diagram of the pins, pads, and bonding wire connections in the high-power semiconductor package device of the present invention. Figure 3 ;

[0043] In the diagram: 1. Pin; 2. Pad. Detailed Implementation

[0044] The present invention will now be described in further detail with reference to the accompanying drawings and preferred embodiments. These embodiments are for illustrative purposes only and are not intended to limit the scope of protection of the present invention. To more clearly show the relationship between the bond lines, Figures 1-7 This is only an illustrative representation of the structural and positional relationships between the bond lines and is not drawn according to the specific dimensional parameters in Example 1.

[0045] Example 1

[0046] like Figures 1-7 As shown,

[0047] A high-power semiconductor packaged device in a TO-247 package includes a pin 1 and two pads 2 (i.e., S-PAD1 and S-PAD2). The pin 1 is connected to the pads 2 by four aluminum bonding wires. The first solder joints of the bonding wires on the same pad 2 are arranged alternately, and the second solder joints on the pins are evenly spaced.

[0048] The bonding wire configuration of this device is as follows:

[0049] like Figure 4 , Figure 5 As shown, the horizontal fan-shaped configuration is as follows: two middle straight bond lines are set, running straight along the reference direction from the first solder point to the second solder point of each; a left-facing arc-shaped offset bond line is set on the left side of one of the straight bond lines, with an offset angle of -5° (to the left), and a right-facing arc-shaped offset bond line is set on the right side of the other straight bond line, with an offset angle of +5° (to the right). All bond lines are fan-shaped in the horizontal direction.

[0050] like Figure 2 As shown, the arc height configuration is as follows: with the bonding plane of the pin as the reference, the arc height of the four bonding wires increases sequentially along the arrangement direction, with an increment of 0.1-0.15mm.

[0051] like Figure 3 , Figure 6 As shown, the Z-axis configuration is as follows: taking the second solder joint of the leftmost bonding wire as the Z-axis reference, the Z-offset of the second solder joint of the other 3 bonding wires increases in a stepwise manner. The Z-offsets of the 4 bonding wires are 0μm, 25μm, 50μm and 75μm respectively, so that the bonding wires are raised in a stepwise manner near the root of the pin.

[0052] At the second solder joint, a vertical segment is formed at the root of the bond wire, and the lengths of the vertical segments of multiple bond wires increase sequentially. A micro-arc transition section is provided between the first arc-shaped segment extending from the first solder joint and the vertical segment at the second solder joint. The length of the micro-arc transition section along the extension direction of the bond wire is 3 to 5 times the wire diameter, and the radius of curvature of the micro-arc transition section is 2 to 3 times the wire diameter of the bond wire. This ensures that there is room for stress release, avoids stress re-concentration caused by an excessively short transition, and prevents microcracks from appearing at the root due to stress concentration.

[0053] Line spacing configuration: The minimum spacing between any two adjacent bonded wires is 1.5-2 times the diameter of the bonded wire to avoid contact between the wires.

[0054] Secondly, a bonding process for a high-power semiconductor packaged device is provided, comprising the following steps:

[0055] Chip mounting: A semiconductor chip is mounted and fixed on a chip holder of a lead frame. The semiconductor chip has at least two pads, and the lead frame has corresponding pins.

[0056] Bonding wire program configuration: Multiple bonding wires are configured independently in the bonding machine program. The specific configuration is as follows:

[0057] Horizontal fan-shaped configuration: Taking the straight line connecting the center point of the first solder joint to the center point of the second solder joint corresponding to each bonding wire as the reference direction, some bonding wires are configured to run straight along the reference direction. The bonding wires with the first solder joint position to the left of the bonding wire in the straight direction are offset to the left in an arc relative to the reference direction, and the bonding wires with the first solder joint position to the right of the bonding wire in the straight direction are offset to the right in an arc relative to the reference direction, so that each bonding wire is spread out in a fan shape in the horizontal direction.

[0058] Arc height gradient configuration: Based on the bonding plane of the pin, the arc height of each bonding line is set to increase sequentially;

[0059] Z-axis stepped configuration: Taking the second solder joint of one of the bonding wires as the Z-axis reference, the Z offset of the second solder joint of the remaining bonding wires is set to increase in a stepwise manner, so that the bonding wires are raised from low to high near the root of the pin.

[0060] In the Die Bonder bonding machine, the bonding parameters are set as shown in Table 1 below. The bonding wire numbers from left to right are wire 1, wire 2, wire 3, and wire 4.

[0061] Table 1:

[0062]

[0063] Bonding execution: Execute the bonding according to the configured bonding machine program, bonding each bonding wire from the corresponding pad to the pin, ensuring that the first solder joint on the same pad is separated from each other, and the second solder joint on the pin is separated from each other.

[0064] Arc height: refers to the vertical height of the highest point of the arc formed by the wire bonding relative to the bonding plane of the pin. The arc height of the four wires increases in a step-like manner, with the highest point of the arc height of wire 1 to wire 4 being raised sequentially to ensure that the wires do not overlap in the vertical direction.

[0065] Second solder joint Z offset: This is a virtual Z-axis height compensation amount set by the bonding machine program. Taking the plane where the second solder joint of line 1 is located as the Z-axis reference plane, the virtual Z-axis reference planes of the second solder joints of the remaining bonding wires are raised in a stepped manner, so that the bonding wires form vertical segments near the root of the pin. The length of the vertical segments of multiple bonding wires increases sequentially, thus forming a stepped raised shape at the root, avoiding bonding wire overlap from the root.

[0066] Arc offset angle: refers to the left and right offset angle of the arc of the welding wire relative to the straight line connecting the center point of the first welding point to the center point of the second welding point. Line 1 is offset to the left by -5°, line 4 is offset to the right by +5°, and lines 2 and 3 are straight along their respective straight connection directions, forming a "left offset + double straight line + right offset" layout, so that the four welding wires are naturally fanned out in the horizontal direction, increasing the horizontal spacing.

[0067] Verification method

[0068] I. C-SAM Ultrasound Scan (Satellite Acoustic Microscopy)

[0069] The net spacing of aluminum wires in 24 samples of the present invention (72 measurement points in total) was measured in detail, and the specific data are shown in Table 2 below.

[0070] Table 2:

[0071]

[0072] Initial state: The minimum net spacing is 70μm and the average is 79.7μm, which is much higher than the lower limit of the design specification (50μm). After 1000 hours of high temperature storage at 150°C (HTS), the minimum net spacing slightly decreased to 68μm (change rate < 3%), indicating that the wire structure is stable and no significant injection molding offset (Wire Sweep) or thermal creep collapse occurred.

[0073] II. RDSON Test

[0074] A comprehensive RDSON test and statistical analysis were conducted on 3,000 finished products manufactured using the bonding process of this invention. The results showed robust performance, with the overall process under control under four key operating conditions. Specific statistical data are shown in Table 3.

[0075] Table 3:

[0076]

[0077] III. HTS Storage Testing

[0078] Forty samples were randomly selected and subjected to a high-temperature storage test (HTS) at 150°C for 1000 hours to verify the RDSON drift characteristics of the new bonding process under extreme high-temperature conditions. The average drift rate was about 2%, which proved that the bonding process was stable. The specific data are shown in Table 4.

[0079] Table 4:

[0080]

[0081] The three-dimensional layout synergy effect of the present invention: through the composite design of "horizontal fan-shaped expansion + root stepped elevation + arc height stepped increase", the four welding wires form a three-dimensional fan-shaped layered structure, eliminating the possibility of overlap from a physical level.

[0082] Those skilled in the art should understand that the above embodiments are merely illustrative of the technical concept and features of the present invention, and are intended to enable those skilled in the art to understand the content of the present invention and implement it accordingly, and are not intended to limit the scope of protection of the present invention. All equivalent changes or modifications made according to the spirit and essence of the present invention should be covered within the scope of protection of the present invention.

Claims

1. A high-power semiconductor package device, comprising pins, a semiconductor chip, and multiple bonding wires; said semiconductor chip comprising at least two pads; The multiple bonding wires are respectively connected to the pads and the pins; The first solder joints of multiple bonding wires on the same pad are separated from each other, and the second solder joints of each bonding wire on the pin are separated from each other. Its features are: Using the straight line connecting the center point of the first solder joint to the center point of the second solder joint corresponding to each bonding wire as the reference direction, the multiple bonding wires are configured such that: some bonding wires run straight along the reference direction, some bonding wires with the first solder joint position on the left side of the bonding wire in the straight direction are offset to the left in an arc relative to the reference direction, and some bonding wires with the first solder joint position on the right side of the bonding wire in the straight direction are offset to the right in an arc relative to the reference direction, so that each bonding wire is fanned out in the horizontal direction; With the bonding plane of the pin as a reference, the arc height of each bonding line increases sequentially; Taking the second solder joint of one of the bonding wires as the Z-axis reference, the Z-offset of the second solder joint of the remaining bonding wires increases sequentially. The root of the bonding wire at the second solder joint forms a vertical line segment. The length of the vertical line segments of multiple bonding wires increases sequentially, and the multiple bonding wires as a whole spread out in a three-dimensional fan shape.

2. The high power semiconductor package device of claim 1, wherein: A micro-arc transition section is provided between the first arc segment extending from the first solder joint and the vertical line segment at the second solder joint in the bonding wire. The length of the micro-arc transition section along the extension direction of the bonding wire is 3 to 5 times the wire diameter, and the radius of curvature of the micro-arc transition section is 2 to 3 times the wire diameter of the bonding wire, so that stress can be released.

3. The high-power semiconductor packaged device according to claim 1, characterized in that: The multiple bonding wires include two intermediate straight bonding wires, which run straight along their respective reference directions; One or more left-curved bonding wires are provided on the left side of one of the middle straight bonding wires; One or more bonding wires offset to the right in an arc shape are provided on the right side of the other middle straight bonding wire; The bias angles of the multiple bias bonding lines on the left are fixed or decreasing gradually; the bias angles of the multiple bias bonding lines on the right are fixed or increasing gradually.

4. The high-power semiconductor packaged device according to claim 1, characterized in that: The offset angle of the bond line, which is offset to the left in an arc, is -10° to 0°. The offset angle of the bond line, which is offset to the right in an arc, is 0° to 10°.

5. The high-power semiconductor packaged device according to claim 1, characterized in that: The arc height of each bond line increases sequentially along the bond line arrangement direction, with an increment of 0.10 mm to 0.15 mm.

6. The high-power semiconductor packaged device according to claim 1, characterized in that: The second solder joint Z offset is a virtual height compensation amount set by the bonding machine program, and the Z offset range that increases sequentially is 20μm to 100μm.

7. The high power semiconductor package device of claim 1, wherein: The minimum spacing between any two adjacent bond wires is greater than 1.5 times the bond wire diameter.

8. The high power semiconductor package device of claim 1, wherein: The package is a TO-247 package, and the pin is the source pin.

9. The high-power semiconductor packaged device according to claim 1, characterized in that: The semiconductor chip is a silicon carbide MOSFET chip or a gallium nitride HEMT chip.

10. A bonding process of a high power semiconductor package device, characterized by: Includes the following steps: A semiconductor chip is mounted and fixed on a chip holder of a lead frame. The semiconductor chip has at least two pads, and the lead frame has corresponding pins. Multiple bond wires are configured independently in the bonder program, as follows: Using the straight line connecting the center point of the first solder joint to the center point of the second solder joint corresponding to each bonding wire as the reference direction, the multiple bonding wires are configured such that: some bonding wires run straight along the reference direction, some bonding wires with the first solder joint position on the left side of the bonding wire in the straight direction are offset to the left in an arc relative to the reference direction, and some bonding wires with the first solder joint position on the right side of the bonding wire in the straight direction are offset to the right in an arc relative to the reference direction, so that each bonding wire is fanned out in the horizontal direction; Using the bonding plane of the pins as a reference, the arc height of each bonding line is set to increase sequentially; Taking the second solder joint of one of the bonding wires as the Z-axis reference, the Z-offset of the second solder joint of the remaining bonding wires increases sequentially, and the root of the bonding wire at the second solder joint forms a vertical line segment, and the length of the vertical line segment of multiple bonding wires increases sequentially. The bonding process is performed according to the configured bonding machine program, bonding each bonding wire from the corresponding pad to the pin. The first solder joints on the same pad are separated from each other, and the second solder joints on the pins are separated from each other.

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