A voltage vector regulation method, device, motor controller and storage medium

Abstract

The present application is applicable to the field of motor technology and provides a voltage vector regulation method, device, motor controller and storage medium. The method obtains an original comparison value based on the amplitude and phase angle of the target voltage vector; determines the sub-sector in which the target voltage vector is located based on the original comparison value, and the sub-sector is a sub-sector in a sector of a spatial voltage vector plane; when the sub-sector is located in a sampling blind area, a pulse width regulation method corresponding to the sub-sector is used to obtain a new comparison value, so that the duration of the two effective vectors constituting the target voltage vector within half a carrier cycle is greater than the minimum sampling time, which can effectively reduce the deviation of the target voltage vector before and after regulation, thereby reducing the current harmonics introduced by the voltage vector deviation.

Description

Technical Field

[0001] The present application belongs to the field of motor technology, and in particular relates to a voltage vector regulation method, device, motor controller and storage medium. Background Art

[0002] High-performance motor control algorithms, such as vector control, direct torque control, and model predictive control, typically rely on accurately detecting the motor's phase currents and performing closed-loop control based on these values. To detect phase currents, at least two current sensors are required in a three-phase motor system. However, current sensors are expensive, significantly increasing the overall cost of the motor controller. Furthermore, if multiple current sensors are used, individual variability, such as errors in gain and zero position, can reduce the effectiveness of motor current control.

[0003] Single-bus current sensing technology reduces the cost of current sensors. This technology simply measures the bus current on the DC bus in the motor controller. Based on the switching states of the inverter's three-phase bridge arms, it determines the correlation between the bus current and the motor's phase current, thereby estimating the motor's phase current. Requiring only a single current sensor, this method significantly reduces costs, leading to its widespread use in cost-sensitive industries such as air conditioner compressors, fans, and washing machine motors.

[0004] The single-bus current detection method has an inherent defect, that is, the current on the bus can only be matched with the phase current of the motor when the voltage vector applied to the motor is an effective voltage vector. Taking into account the disturbance introduced by the inverter switching action and the inherent delay of the analog-to-digital converter during the current detection process, the single-bus current detection method has a minimum requirement for the pulse width of the inverter output effective voltage vector. In addition, during the reconstruction of the motor phase current, the bus current needs to be collected twice continuously to convert it into two-phase current and infer the third-phase current. However, when the output voltage is low or the output voltage is close to the spatial coordinate vector, there is a problem that the bus current cannot be effectively sampled due to the short duration of the effective spatial voltage vector, resulting in the failure of current reconstruction, which is the current sampling blind spot.

[0005] The existing technology solves the sampling blind zone problem by performing pulse width modulation on the effective space voltage vector. However, the existing voltage vector pulse width modulation method ignores the current harmonic problem introduced by the voltage vector deviation between the effective space voltage vectors before and after the modulation. Summary of the Invention

[0006] The embodiments of the present application provide a voltage vector regulation method, device, motor controller and storage medium, which aim to solve the current harmonic problem introduced by the voltage vector pulse width regulation method in the prior art, which ignores the voltage vector deviation between the effective spatial voltage vectors before and after regulation.

[0007] A first aspect of an embodiment of the present application provides a voltage vector regulation method, including:

[0008] Obtaining an original comparison value according to the magnitude and phase angle of the target voltage vector;

[0009] determining, according to the original comparison value, a sub-sector in which the target voltage vector is located, the sub-sector being a sub-region in a sector of a spatial voltage vector plane;

[0010] When the sub-sector is located in a sampling blind area, a pulse width modulation method corresponding to the sub-sector is used to obtain a new comparison value, so that the duration of the two effective vectors constituting the target voltage vector within a half carrier cycle is greater than the minimum sampling time.

[0011] A second aspect of an embodiment of the present application provides a voltage vector regulation device, including:

[0012] an original value acquisition unit, configured to obtain an original comparison value according to the amplitude and phase angle of the target voltage vector;

[0013] a sub-sector determining unit, configured to determine, based on the original comparison value, a sub-sector in which the target voltage vector is located, the sub-sector being a sub-sector in a sector of a spatial voltage vector plane;

[0014] The new value acquisition unit is used to obtain a new comparison value by adopting a pulse width modulation method corresponding to the sub-sector when the sub-sector is located in a sampling blind area, so that the duration of the two effective vectors constituting the target voltage vector within the half carrier cycle is greater than the minimum sampling time.

[0015] A third aspect of an embodiment of the present application provides a motor controller, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, the steps of the voltage vector regulation method described in the first aspect of the embodiment of the present application are implemented.

[0016] A fourth aspect of the embodiments of the present application provides a computer-readable storage medium, which stores a computer program. When the computer program is executed by a processor, it implements the steps of the voltage vector regulation method as described in the first aspect of the embodiments of the present application.

[0017] The first aspect of the embodiment of the present application provides a voltage vector regulation method, which obtains an original comparison value based on the amplitude and phase angle of the target voltage vector; determines the sub-sector in which the target voltage vector is located based on the original comparison value, and the sub-sector is a sub-sector in a sector of the spatial voltage vector plane; when the sub-sector is located in a sampling blind area, a pulse width regulation method corresponding to the sub-sector is used to obtain a new comparison value, so that the duration of the two effective vectors constituting the target voltage vector within half a carrier cycle is greater than the minimum sampling time, which can effectively reduce the deviation of the target voltage vector before and after regulation, thereby reducing the current harmonics introduced by the voltage vector deviation.

[0018] It can be understood that the beneficial effects of the second to fourth aspects mentioned above can be found in the relevant description of the first aspect mentioned above, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the embodiments or descriptions of the prior art. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0020] Figure 1 is a schematic structural diagram of a motor controller provided in an embodiment of the present application;

[0021] Figure 2 This is a first flow chart of the voltage vector regulation method provided in an embodiment of the present application;

[0022] Figure 3 This is a table of calculation formulas for the three-phase comparison values ​​of the target voltage vector in the six sectors of the space vector plane provided by the embodiment of the present application;

[0023] Figure 4 It is the PWM waveform of the switch tube within the carrier period when the target voltage vector provided in the embodiment of the present application is located in the first sector of the space vector plane;

[0024] Figure 5 It is the PWM waveform of the switch tube within the adjusted carrier period when the target voltage vector provided in the embodiment of the present application is located in the first sector of the space vector plane;

[0025] Figure 6 This is a second flow chart of the voltage vector regulation method provided in an embodiment of the present application;

[0026] Figure 7 Schematic diagram of the area division of the first sector of the space vector plane provided in an embodiment of the present application;

[0027] Figure 8 This is a third flow chart of the voltage vector regulation method provided in an embodiment of the present application;

[0028] Figure 9 This is a fourth flow chart of the voltage vector regulation method provided in an embodiment of the present application;

[0029] Figure 10 This is a fifth flow chart of the voltage vector regulation method provided in an embodiment of the present application;

[0030] Figure 11 1 is a schematic diagram of the adjustment principle of the sampling voltage vector when the target voltage vector provided by the embodiment of the present application is located in the first sub-area of ​​a sampling blind area;

[0031] Figure 12 1 is a schematic diagram of the adjustment principle of the sampling voltage vector when the target voltage vector is located in the second sub-area of ​​a sampling blind area provided by an embodiment of the present application;

[0032] Figure 13 1 is a schematic diagram of the adjustment principle of the sampling voltage vector when the target voltage vector provided by the embodiment of the present application is located in the first sub-area of ​​the second type of sampling blind area;

[0033] Figure 14 1 is a schematic diagram of the adjustment principle of the sampling voltage vector when the target voltage vector provided by an embodiment of the present application is located in the second sub-area of ​​the second type of sampling blind area;

[0034] Figure 15 1 is a schematic diagram of the adjustment principle of the sampling voltage vector when the target voltage vector provided by the embodiment of the present application is located in the third sub-area of ​​the second type sampling blind area;

[0035] Figure 16 1 is a schematic diagram of the adjustment principle of the sampling voltage vector when the target voltage vector provided by an embodiment of the present application is located in the first sub-area of ​​the non-equivalent sampling blind area;

[0036] Figure 17 1 is a schematic diagram of the adjustment principle of the sampling voltage vector when the target voltage vector provided by an embodiment of the present application is located in the second sub-area of ​​the non-equivalent sampling blind area;

[0037] Figure 18 Schematic diagram of the structure of the voltage vector regulation device provided in an embodiment of the present application;

[0038] Figure 19 It is a structural diagram of the motor controller provided in an embodiment of the present application. DETAILED DESCRIPTION

[0039] In the following description, specific details such as specific system structures and techniques are provided for purposes of illustration rather than limitation to facilitate a thorough understanding of the embodiments of the present application. However, it will be apparent to those skilled in the art that the present application may be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, circuits, and methods are omitted to avoid obscuring the description of the present application with unnecessary detail.

[0040] It should be understood that when used in the present specification and the appended claims, the term "comprising" indicates the presence of described features, integers, steps, operations, elements and / or components, but does not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or collections thereof.

[0041] It will also be understood that the term "and / or" used in this specification and the appended claims refers to and includes any and all possible combinations of one or more of the associated listed items.

[0042] As used in this specification and the appended claims, the term "if" can be interpreted as "when" or "upon" or "in response to determining" or "in response to detecting," depending on the context. Similarly, the phrase "if it is determined" or "if [described condition or event] is detected" can be interpreted as meaning "upon determination" or "in response to determining" or "upon detection of [described condition or event]" or "in response to detecting [described condition or event]," depending on the context.

[0043] In addition, in the description of the present application specification and the appended claims, the terms "first", "second", "third", etc. are only used to distinguish the descriptions and cannot be understood as indicating or implying relative importance.

[0044] References to "one embodiment" or "some embodiments" in this specification mean that a particular feature, structure, or characteristic described in conjunction with that embodiment is included in one or more embodiments of the present application. Thus, phrases such as "in one embodiment," "in some embodiments," "in other embodiments," and "in other embodiments" appearing in various places in this specification do not necessarily refer to the same embodiment, but rather mean "one or more but not all embodiments," unless otherwise specifically emphasized. The terms "including," "comprising," "having," and variations thereof all mean "including but not limited to," unless otherwise specifically emphasized.

[0045] An embodiment of the present application provides a voltage vector regulation method, which can be executed by a processor of a motor controller when running a corresponding computer program. The method is used to determine the sub-sector in which a target voltage vector is located in a sector of a space vector plane when performing single-bus current detection, and when the sub-sector in which the target voltage vector is located is located in a sampling blind spot, adopt a pulse width regulation method corresponding to the sub-sector in which the target voltage vector is located to adjust the original comparison value to obtain a new comparison value. Based on the new comparison value, the pulse width of two effective vectors constituting the target voltage vector within the carrier period is adjusted so that the duration of the two effective vectors within half the carrier period is greater than the minimum sampling time. This can effectively reduce the deviation of the target voltage vector before and after adjustment, reduce the current harmonics introduced by the voltage vector deviation, and thus eliminate the single-bus current sampling blind spot while reducing the current harmonics.

[0046] In application, the motor controller can be used in air conditioners, fans and washing machines to drive and control the motors of air conditioners, fans and washing machines. The motor controller can specifically be a frequency converter.

[0047] like Figure 1 , which exemplarily shows a schematic structural diagram of a motor controller;

[0048] Among them, the motor controller includes a processor, a current sensor and an inverter;

[0049] The current sensor is electrically connected to the negative pole of the DC bus and is used to detect the bus current on the DC bus. Figure 1 In the example shown, the current sensor is realized by a sampling resistor connected in series to the negative pole of the DC bus;

[0050] The first input terminal of the inverter is electrically connected to the positive pole of the DC bus, the second input terminal of the inverter is electrically connected to the negative pole of the DC bus, the six controlled terminals of the inverter are electrically connected to the processor, and the three output terminals of the inverter are electrically connected to the three phase current and phase voltage input terminals of the motor respectively. Figure 1 The inverter is exemplarily shown to include three-phase bridge arms (a-phase bridge arm, b-phase bridge arm, and c-phase bridge arm), each phase bridge arm includes two switching tubes (an upper switching tube and a lower switching tube), the input ends of the upper switching tubes of the three-phase bridge arms are connected together to form a first input end of the inverter, the output ends of the lower switching tubes of the three-phase bridge arms are connected together to form a second input end of the inverter 3, the controlled end of each switching tube constitutes a controlled end of the inverter, and the output end of the upper switching tube and the input end of the lower switching tube of each phase bridge arm are connected together to form an output end of the inverter;

[0051] The processor is used to:

[0052] According to the target rotor speed that the motor needs to achieve, the target phase voltages (phase A voltage, phase B voltage, and phase C voltage) that need to be applied to the stator are obtained to generate corresponding target phase currents (phase A current ia, phase B current ib, and phase C current ic) in the stator;

[0053] The space vector pulse width modulation (SVPWM) method is adopted to determine the target voltage vector according to the rotor angle and the target phase voltage. According to the target voltage vector amplitude and phase angle, the three-phase comparison value is obtained by the comparison value calculation method based on the SVPWM method. Then, a triangular carrier is used to compare the calculated three-phase comparison value to generate a pulse width modulation (PWM) signal for driving the switch tube of the corresponding phase, controlling the on and off states of the six switch tubes of the three-phase bridge arm of the inverter, thereby outputting the three-phase voltage to the motor.

[0054] The on / off states of the six switches in the three-phase bridge arm of the inverter are controlled according to the PWM signal, so that the actual voltage applied by the bus voltage to the stator is equivalent to the target phase voltage. Correspondingly, the actual current applied by the bus current to the stator is equivalent to the target phase current, thereby causing the stator to generate a corresponding magnetic field to drive the rotor to rotate at the target rotor speed. To improve the motor control accuracy, it is necessary to collect the bus current on the DC bus through a current sensor to obtain the magnitude of the bus current on the DC bus. Based on the magnitude of the bus current, the magnitude of the actual phase current applied to the stator can be estimated. By comparing the actual phase current with the target phase current, the target phase current can be adjusted according to the deviation between the actual phase current and the target phase current. Based on the adjusted target phase current, the adjusted target phase voltage can be obtained. Combined with the space vector pulse width modulation method, the adjusted target voltage vector can be determined. Then, an adjusted pulse width modulation signal is generated based on the adjusted target voltage vector. The on / off states of the six switches in the three-phase bridge arm of the inverter are controlled based on the adjusted pulse width modulation signal, ultimately achieving feedback control of the motor.

[0055] In applications, the switching tube has the function of turning on or off when triggered by an electrical signal (PWM signal), and is used to act as an electronic switch. Specifically, it can be an insulated gate bipolar transistor (IGBT), or a bipolar junction transistor (BJT), a field effect transistor (FET), a thyristor, etc. The insulated gate bipolar transistor is a composite fully controlled voltage-driven power semiconductor device composed of a bipolar transistor and an insulated gate field effect transistor. It has the advantages of both the high input impedance of the insulated gate field effect transistor and the low conduction voltage drop of the bipolar transistor. The field effect transistor can specifically be a metal oxide semiconductor field effect transistor (MOS-FET).

[0056] like Figure 2 As shown, the voltage vector regulation method provided in the embodiment of the present application includes the following steps S201 to S203:

[0057] Step S201: Obtain an original comparison value according to the amplitude and phase angle of the target voltage vector.

[0058] In the application, the original comparison value can be obtained according to the amplitude and phase angle of the target voltage vector through the comparison value calculation method based on the SVPWM method. The following is a detailed introduction to an SVPWM comparison value calculation method:

[0059] If the target voltage vector has an amplitude of Vr and a phase angle of θ1, the modulation coefficient m1 is calculated as:

[0060]

[0061] Wherein, Vdc is the bus voltage;

[0062] If θ1>0 and θ1≤1 / 3*π, the target voltage vector is located in the first sector of the space vector plane, and the angle θm relative to the first sector is = θ1;

[0063] If θ1>1 / 3*π and θ1≤2 / 3*π, then the target voltage vector is located in the second sector of the space vector plane, and the angle θm relative to the second sector is θ1-1 / 3*π;

[0064] If θ1>2 / 3*π and θ1≤3 / 3*π, the target voltage vector is located in the third sector of the space vector plane, and the angle θm relative to the third sector is θ1-2 / 3*π;

[0065] If θ1>3 / 3*π and θ1≤4 / 3*π, the target voltage vector is located in the fourth sector of the space vector plane, and the angle θm relative to the fourth sector is θ1-3 / 3*π;

[0066] If θ1>4 / 3*π and θ1≤5 / 3*π, the target voltage vector is located in the fifth sector of the space vector plane, and the angle θm relative to the fifth sector is θ1-4 / 3*π;

[0067] If θ1>5 / 3*π and θ1≤2*π, the target voltage vector is located in the sixth sector of the space vector plane, and the angle θm relative to the sixth sector is θ1-5 / 3*π;

[0068] Based on m1 and θm, the duration proportions Tm1 and Tm2 of the two effective vectors in the carrier period are calculated:

[0069]

[0070]

[0071] Where Tm is the maximum value of the carrier counter, that is, the maximum carrier cycle count value;

[0072] The calculation method of the duration ratio Tm0 of the zero vector is:

[0073] Tm0=0.5*(1-Tm1-Tm2)*Tm

[0074] like Figure 3 As shown in the figure, the calculation formula table of the three-phase comparison values ​​(i.e., original comparison values) of the target voltage vector in six sectors of the space vector plane is shown as an example; among them, the comparison value of phase A at the falling edge of the carrier is DDA0, and the comparison value at the rising edge of the carrier is DUA0; the comparison value of phase B at the falling edge of the carrier is DDB0, and the comparison value at the rising edge of the carrier is DUB0; the comparison value of phase C at the falling edge of the carrier is DDC0, and the comparison value at the rising edge of the carrier is DUC0. In the symmetrical sampling mode, the comparison value at the falling edge of the carrier is the same as the comparison value at the rising edge of the carrier, that is, DDA0 = DUA0, DDB0 = DUB0, and DDC0 = DUC0.

[0075] In applications, a triangular carrier wave is compared with the calculated three-phase comparison values ​​to generate the PWM waveforms used to drive the corresponding phase switches. For ease of presentation, the carrier period is defined as Ts, half the carrier period as Tsh, and the maximum carrier period as DT. The SVPWM sampling method uses asymmetric sampling, meaning that the comparison values ​​corresponding to the falling and rising edges of the carrier wave can differ. The carrier comparison operation generates the PWM waveforms for the three-phase switches, forming a traditional 7-segment PWM waveform. The vector action sequence for the falling carrier edge is: zero vector → active vector 1 → active vector 2 → zero vector; the vector action sequence for the rising carrier edge is: zero vector → active vector 2 → active vector 1 → zero vector.

[0076] like Figure 4 As shown, the PWM waveform of the switch tube within the SVPWM carrier period is exemplarily shown when the target voltage vector is located in the first sector of the space vector plane; wherein, the effective vector 1 is the space voltage vector 100, and the duration is T1; the effective vector 2 is the space voltage vector 110, and the duration is T2, Tmin represents the minimum sampling time, Tsh represents half the carrier period, and Ts represents the carrier period.

[0077] In the application, based on the single bus current detection method, the bus current within the duration of two adjacent effective vectors (i.e., effective vector 1 and effective vector 2) is detected respectively, and the corresponding motor phase current is estimated. The relationship between the bus current detection, the phase current, and the space voltage vector is:

[0078] If the voltage at the moment of bus current detection is the space voltage vector 100, then the bus current is equal to the phase A current;

[0079] If the voltage at the moment of bus current detection is a space voltage vector 110, then the bus current is equal to the negative C-phase current;

[0080] If the voltage at the moment of bus current detection is a space voltage vector 101, then the bus current is equal to the negative B-phase current;

[0081] If the voltage at the moment of bus current detection is the space voltage vector 010, then the bus current is equal to the B phase current;

[0082] If the voltage at the moment of bus current detection is the space voltage vector 011, then the bus current is equal to the negative A phase current;

[0083] If the voltage at the moment of bus current detection is a space voltage vector 001, the bus current is equal to the C-phase current.

[0084] To reconstruct the motor phase currents using the single-bus current detection method, the durations of both valid vectors must satisfy a condition related to the minimum sampling time Tmin required for sampling: that is, both T1 and T2 must be greater than or equal to Tmin. However, in actual motor operation, there are cases where either T1 or T2 is less than Tmin. In these cases, the motor phase current reconstruction based on the single-bus current detection method fails, resulting in a sampling blind zone.

[0085] In applications, to address the issue of motor phase current reconstruction failure within the sampling blind zone, it is necessary to adjust the pulse width of the PWM waveforms of the switches corresponding to the two active vectors so that the durations T1 and T2 of both active vectors are greater than or equal to Tmin. One approach to addressing the sampling blind zone is to adjust the three-phase comparison value so that the durations of both active vectors are greater than Tmin.

[0086] like Figure 5 As shown, the PWM waveform of the switching tube within the adjusted SVPWM carrier period is exemplarily shown when the target voltage vector is located in the first sector of the space vector plane; wherein, the comparison value of the adjusted A phase at the falling edge of the carrier is DDA, and the comparison value of the carrier rising edge is DUA; the comparison value of the adjusted B phase at the falling edge of the carrier is DDB, and the comparison value of the carrier rising edge is DUB; the comparison value of the adjusted C phase at the falling edge of the carrier is DDC, and the comparison value of the carrier rising edge is DUC.

[0087] In the application, if T1 is less than Tmin, the comparison value of phase A is increased at the falling edge of the carrier to meet the requirement that T1 is greater than or equal to Tmin. The adjusted comparison value DDA of phase A at the falling edge of the carrier is:

[0088] DDA=DDB0+Dmin

[0089] Among them, Dmin represents the change in Tmin reflected on the carrier. At the same time, in order to keep the output voltage of phase A unchanged, the adjustment amount of the comparison value of phase A on the falling edge of the carrier needs to be reduced, that is:

[0090] DUA=DUA0-(DDA-DDA0)

[0091] It is understandable that the comparison value of phase A within the carrier period can also be adjusted by increasing the comparison value of phase A on the falling edge of the carrier and reducing the comparison value of phase A on the rising edge of the carrier, that is, DUA=DUB0+Dmin, DDA=DDA0-(DUA-DUA0).

[0092] Step S202: determining the sub-sector where the target voltage vector is located based on the original comparison value, where the sub-sector is a sub-region in a sector of the spatial voltage vector plane;

[0093] Step S203: When the sub-sector is located in the sampling blind area, a pulse width modulation method corresponding to the sub-sector is used to obtain a new comparison value so that the duration of the two effective vectors constituting the target voltage vector within the half carrier cycle is greater than the minimum sampling time.

[0094] In the application, Figure 5 The blind zone processing method shown ignores the current harmonic problem introduced by the voltage vector deviation between the effective space voltage vectors before and after adjustment. Therefore, each sector of the space vector plane is further partitioned, and the corresponding pulse width adjustment method is used for different partitions to adjust the original comparison value to obtain a new comparison value. The pulse width of the effective vector within the carrier period is adjusted according to the new comparison value to reduce the deviation of the target voltage vector before and after adjustment, thereby reducing the current harmonics introduced by the voltage vector deviation. The triangular carrier is compared with the new three-phase comparison value to generate a PWM signal for controlling the inverter, thereby controlling the inverter to output the three-phase voltage to the motor.

[0095] like Figure 6 As shown, in one embodiment, step S202 includes the following steps S601 and S602:

[0096] Step S601: Determine the duration of two effective vectors constituting the target voltage vector within a half carrier cycle according to the original comparison value;

[0097] Step S602: Determine the sub-sector where the target voltage vector is located according to the duration of the two effective vectors.

[0098] In applications, the durations of the two active vectors are determined based on their duration ratios within the carrier period, Tm1 and Tm2, ​​and the carrier period. Different durations of the two active vectors result in different current sampling effects. Each sector of the space vector plane is further divided into multiple sub-sectors based on these different current sampling effects. When the durations of the two active vectors satisfy different relationships, their corresponding target voltage vectors are located in different sub-sectors.

[0099] like Figure 7 As shown, a schematic diagram of the area division of the first sector of the space vector plane is exemplarily shown; wherein, the first sector is divided into 8 sub-sectors R1 to R8, R5 is a sampleable area, R2 is the first sub-area in a type of sampling blind area, R8 is the second sub-area in a type of sampling blind area, R1 is the first sub-area in a type of sampling blind area, R4 is the second sub-area in a type of sampling blind area, R6 is the third sub-area in a type of sampling blind area, R3 is the first sub-area in a non-equivalent sampling blind area, and R7 is the second sub-area in a non-equivalent sampling blind area.

[0100] It should be understood that the area division rules of other sectors of the space vector plane are the same as the area division rule of the first sector and can be derived based on the area division rule of the first sector, which will not be repeated here.

[0101] like Figure 8 As shown, in one embodiment, the two valid vectors include a first valid vector (i.e., valid vector 1) and a second valid vector (i.e., valid vector 2), and step S602 includes the following steps S801 to S808:

[0102] S801 : When the durations of the two valid vectors are both greater than the minimum sampling time, determine that the target voltage vector is in a sampleable region.

[0103] In the application, Figure 7 The R5 region shown in the figure is the sampleable region. If the target voltage vector is located at Figure 7 In the R5 region shown in , the durations T1 and T2 of the two effective vectors constituting the target voltage vector within the half carrier period are both greater than the minimum sampling time Tmin, and the current sampling action can be performed directly without the need for voltage vector regulation.

[0104] S802: When the duration of the first valid vector is less than the minimum sampling time and the two valid vectors satisfy a first relationship, determine that the target voltage vector is in a first sub-area of ​​a first sampling blind area;

[0105] S803 : When the duration of the second effective vector is less than the minimum sampling time and the two effective vectors satisfy a second relationship, determine that the target voltage vector is in a second sub-area of ​​a first-type sampling blind area.

[0106] In applications, one type of sampling blind area includes Figure 7 The first sub-region R2 and the second sub-region R8 shown in FIG;

[0107] If the target voltage vector is located at Figure 7 If the R2 region shown in , the duration T2 of the first effective vector constituting the target voltage vector is less than the minimum sampling time Tmin, and T1 and T2 satisfy the following first relationship:

[0108] 3*Tmin≤T1+2*T2≤2*Tsh-Tmin

[0109] If the target voltage vector is located at Figure 7 In the R8 region shown in , the duration T2 of the second effective vector constituting the target voltage vector is less than the minimum sampling time Tmin, and T1 and T2 satisfy the following second relationship:

[0110] 3*Tmin≤T2+2*T1≤2*Tsh-Tmin.

[0111] S804: When the two valid vectors satisfy the third relationship, determine that the target voltage vector is in the first sub-area of ​​the second sampling blind area;

[0112] S805: When the duration of the first valid vector is less than the minimum sampling time, the duration of the second valid vector is less than half the carrier period minus 0.5 times the minimum sampling time, and the two valid vectors satisfy the fourth relationship, determine that the target voltage vector is in the second sub-area of ​​the second sampling blind area;

[0113] S806: When the duration of the second effective vector is less than the minimum sampling time, the duration of the first effective vector is less than half the carrier period minus 0.5 times the minimum sampling time, and the two effective vectors satisfy the fifth relationship, determine that the target voltage vector is in the third sub-area of ​​the second-category sampling blind area.

[0114] In application, the second type of sampling blind area includes Figure 7 The first sub-area R1, the second sub-area R4 and the third to the sector R6 shown in FIG;

[0115] If the target voltage vector is located at Figure 7 In the R1 region shown in , the durations T1 and T2 of the two effective vectors constituting the target voltage vector within a half carrier cycle satisfy the following third relationship:

[0116] T1+2*T2≤3*Tmin

[0117] If the target voltage vector is located at Figure 7 In the R4 region shown in , the duration T1 of the first effective vector constituting the target voltage vector is less than the minimum sampling time Tmin, the duration T2 of the second effective vector constituting the target voltage vector is less than half the carrier period Tsh minus 0.5 times the minimum sampling time Tmin, and T1 and T2 satisfy the following fourth relationship:

[0118] T1+2*T2≥2*Tsh-Tmin

[0119] If the target voltage vector is located at Figure 7 In the R6 region shown in , the duration T2 of the second effective vector constituting the voltage vector is less than the minimum sampling time Tmin, the duration T1 of the first effective vector constituting the target voltage vector is less than half the carrier period Tsh minus 0.5 times the minimum sampling time Tmin, and T1 and T2 satisfy the following fifth relationship:

[0120] T2+2*T1≥2*Tsh-Tmin.

[0121] S807: When the duration of the first effective vector is less than 0.5 times the minimum sampling time and the duration of the second effective vector is greater than half the carrier period minus 0.5 times the minimum sampling time, determine that the target voltage vector is in the first sub-area of ​​the non-equivalent sampling blind area;

[0122] S808 : When the duration of the second effective vector is less than 0.5 times the minimum sampling time and the duration of the first effective vector is greater than half the carrier period minus 0.5 times the minimum sampling time, determine that the target voltage vector is in the second sub-area of ​​the non-equivalent sampling blind area.

[0123] In applications, the non-equivalent sampling blind area includes Figure 7 The first sub-region R3 and the second sub-region R7 shown in FIG;

[0124] If the target voltage vector is located at Figure 7 In the R3 region shown in , the duration T1 of the first effective vector constituting the target voltage vector is less than 0.5 times the minimum sampling time Tmin, and the duration T2 of the second effective vector constituting the target voltage vector is greater than half the carrier period Tsh minus 0.5 times the minimum sampling time Tmin;

[0125] If the target voltage vector is located at Figure 7 In the R7 region shown in , the duration T2 of the second effective vector constituting the target voltage vector is less than 0.5 times the minimum sampling time Tmin, and the duration T1 of the first effective vector constituting the target voltage vector is greater than half the carrier period Tsh minus 0.5 times the minimum sampling time Tmin.

[0126] like Figure 9 As shown, in one embodiment, step S203 includes the following steps S901 to S904:

[0127] Step S901: When a sub-sector is located in a sampling blind area, a pulse width modulation method corresponding to the sub-sector is used to obtain a sampled voltage vector within the first half carrier cycle;

[0128] Step S902: Obtain a new comparison value within the first half carrier cycle according to the sub-sector, the original comparison value within the first half carrier cycle, and the sampled voltage vector;

[0129] Step S903: Obtain a compensation voltage vector in the second half carrier cycle according to the sampled voltage vector, so that the deviation between the composite vector of the sampled voltage vector and the compensation voltage vector and the target voltage vector is minimized;

[0130] Step S904: Obtain a new comparison value within the second half carrier cycle according to the sub-sector, the original comparison value within the second half carrier cycle, and the compensation voltage vector.

[0131] In the application, when the target voltage vector Vr is calculated by the SVPWM method, an asymmetric sampling method is used to output two voltage vectors within the carrier period Ts for the target voltage vector located in the sampling blind zone. One of the two voltage vectors is defined as the sampled voltage vector Vs, which is used to ensure that the durations T1 and T2 of the two effective voltage vectors that constitute the target voltage vector are both greater than the minimum sampling time Tmin; the other voltage vector is defined as the compensation voltage vector Vc, which is used to synthesize the target space vector Vr with the sampled voltage vector Vs. The purpose is to make the actual voltage vector output within the carrier period equivalent to the target voltage vector Vr.

[0132] In applications, if the target voltage vector Vr falls within any sampling blind zone, pulse width modulation (PWM) is required for the effective vector at the rising or falling edge of the carrier. The first half of the carrier cycle and the second half of the carrier cycle are either the rising or falling edge of the carrier, respectively. This means that the sampled voltage vector Vs can fall within the falling edge of the carrier, and the compensation voltage vector Vc falls within the rising edge of the same carrier cycle. Alternatively, the sampled voltage vector Vs can fall within the rising edge of the carrier, and the compensation voltage vector Vc falls within the falling edge of the same carrier cycle.

[0133] In applications, different pulse width modulation methods are used depending on the region where the target voltage vector Vr is located to obtain the sampled voltage vector Vs. Based on the sampled voltage vector Vs, the compensation voltage vector Vc is derived. This minimizes the deviation between the resulting vector and the target voltage vector Vr, ensuring that the actual voltage vector output within a carrier cycle is as close to the target voltage vector Vr as possible. New comparison values ​​are then calculated for the regions where the compensation voltage vector Vc and the target voltage vector Vr are located, respectively, based on the sampled voltage vector Vs.

[0134] like Figure 10 As shown, in one embodiment, step S901 includes the following steps S1001 to S1003:

[0135] Step S1001: When a sub-sector is located in a type of sampling blind area, in a space vector plane, a first perpendicular line is drawn through the end point of a target voltage vector to a first boundary line adjacent to the target voltage vector in a sampleable area, and the intersection of the first perpendicular line and the first boundary line is taken as the end point of the sampled voltage vector.

[0136] like Figure 11As shown, a schematic diagram of the adjustment principle of the sampling voltage vector when the target voltage vector is located in the first sub-area of ​​a type of sampling blind area is exemplified; wherein, the target voltage vector Vr is located in the first sub-area R2 of the type of sampling blind area. In the space vector plane, a first perpendicular line is drawn through the end point of the target voltage vector Vr to the first boundary line O1O2 adjacent to the target voltage vector Vr in the sampleable area R5, and the intersection of the first perpendicular line and the first boundary line O1O2 is taken as the end point of the sampling voltage vector Vs.

[0137] like Figure 12 As shown, a schematic diagram of the adjustment principle of the sampling voltage vector when the target voltage vector is located in the second sub-area of ​​a type of sampling blind area is exemplified; wherein, the target voltage vector Vr is located in the second sub-area R8 of the type of sampling blind area. In the space vector plane, a first perpendicular line is drawn through the end point of the target voltage vector Vr to the first boundary line O1O3 adjacent to the target voltage vector Vr in the sampleable area R5, and the intersection of the first perpendicular line and the first boundary line O1O3 is taken as the end point of the sampling voltage vector Vs.

[0138] Step S1002: When the sub-sector is located in the second-category sampling blind area, in the space vector plane, the endpoint closest to the end point of the target voltage vector in the sampleable area is used as the end point of the sampled voltage vector.

[0139] like Figure 13 As shown, a schematic diagram of the adjustment principle of the sampling voltage vector when the target voltage vector is located in the first sub-area of ​​the second sampling blind area is exemplified; wherein, the target voltage vector Vr is located in the first sub-area R1 of the second sampling blind area, and in the space vector plane, the endpoint O1 closest to the end point of the target voltage vector Vr in the sampleable area R5 is used as the end point of the sampling voltage vector Vs.

[0140] like Figure 14 As shown, a schematic diagram of the adjustment principle of the sampling voltage vector when the target voltage vector is located in the second sub-area of ​​the second sampling blind area is exemplified; wherein, the target voltage vector Vr is located in the second sub-area R4 of the second sampling blind area, and in the space vector plane, the endpoint O2 closest to the end point of the target voltage vector Vr in the sampleable area R5 is used as the end point of the sampling voltage vector Vs.

[0141] like Figure 15 As shown, a schematic diagram of the adjustment principle of the sampling voltage vector when the target voltage vector is located in the third sub-area of ​​the second-category sampling blind zone is exemplified; wherein, the target voltage vector Vr is located in the third sub-area R6 of the second-category sampling blind zone, and in the space vector plane, the endpoint O3 closest to the end point of the target voltage vector Vr in the sampleable area R5 is used as the end point of the sampling voltage vector Vs.

[0142] Step S1003: When the sub-sector is located in a non-equivalent sampling blind area, in the space vector plane, a second perpendicular line is drawn through the end point of the target voltage vector to a second boundary line adjacent to the target voltage vector in the second type of sampling blind area. The intersection of the second perpendicular line and the second boundary line is used as the end point of the corrected target voltage vector. The endpoint in the sampleable area that is closest to the end point of the corrected target voltage vector is used as the end point of the sampled voltage vector.

[0143] like Figure 16 As shown, a schematic diagram of the adjustment principle of the sampling voltage vector when the target voltage vector is located in the first sub-area of ​​the non-equivalent sampling blind area is exemplarily shown; wherein, the target voltage vector Vr is located in the first sub-area R3 of the non-equivalent sampling blind area, and in the space vector plane, a second perpendicular line is drawn through the end point of the target voltage vector Vr to the second boundary line O4O5 adjacent to the target voltage vector Vr in the first sub-area R3 of the second type of sampling blind area, and the intersection of the second perpendicular line and the second boundary line O4O5 is taken as the end point of the corrected target voltage vector Vr1, and the endpoint O2 in the sampleable area R5 that is closest to the end point of the corrected target voltage vector Vr1 is taken as the end point Vs of the sampling voltage vector.

[0144] like Figure 17 As shown, a schematic diagram of the adjustment principle of the sampling voltage vector when the target voltage vector is located in the second sub-area of ​​the non-equivalent sampling blind zone is exemplarily shown; wherein, the target voltage vector Vr is located in the second sub-area R7 of the non-equivalent sampling blind zone, and in the space vector plane, a second perpendicular line is drawn through the end point of the target voltage vector Vr to the second boundary line O6O7 adjacent to the target voltage vector Vr in the second sub-area R7 of the second type of sampling blind zone, and the intersection of the second perpendicular line and the second boundary line O6O7 is taken as the end point of the corrected target voltage vector Vr1, and the endpoint O3 in the sampleable area R5 that is closest to the end point of the corrected target voltage vector Vr1 is taken as the end point Vs of the sampling voltage vector.

[0145] In one embodiment, when the sub-sector is located in a first-class sampling blind area or a second-class sampling blind area, the calculation formula of the compensation voltage vector is:

[0146] Vc=2*Vr-Vs

[0147] When the sub-sector is located in the non-equivalent sampling blind area, the calculation formula of the compensation voltage vector is:

[0148] Vc=2*Vr1-Vs

[0149] Wherein, Vc represents the compensation voltage vector, Vr represents the target voltage vector, Vr1 represents the corrected target voltage vector, and Vs represents the sampled voltage vector.

[0150] In applications, in order to make the actual voltage vector output within the carrier period equivalent to the target voltage vector, the compensation voltage vector can be obtained by vector subtraction.

[0151] In one embodiment, when the sub-sector is located in the first sub-area of ​​a sampling blind area, the calculation formula of the new comparison value in the first half carrier cycle is:

[0152] DDA=DDA1-DDS, DDB=DDB1-DDS, DDC=DDC1-DDS

[0153] DDA1=DDB0+Dmin, DDB1=DDB0, DDC1=DDC0+0.5*(Dmin-DDA1)

[0154] DDS=0.5*DT-0.5(DDMAX-DDMIN)

[0155] When the sub-sector is located in the second sub-area of ​​a sampling blind area, the calculation formula of the new comparison value in the first half carrier cycle is:

[0156] DDA=DDA1-DDS, DDB=DDB1-DDS, DDC=DDC1-DDS

[0157] DDA1=DDB0-0.5*(Dmin-DDC0), DDB1=DDB0, DDC1=DDB0-Dmin

[0158] DDS=0.5*DT-0.5(DDMAX-DDMIN)

[0159] Among them, DDA, DDB and DDC represent the new three-phase comparison values ​​in the first half of the carrier cycle, DDA0, DDB0 and DDC0 represent the original three-phase comparison values ​​in the first half of the carrier cycle, DDA1, DDB1 and DDC1 represent the three-phase comparison values ​​to be adjusted in the first half of the carrier cycle, DDS represents the offset of the three-phase comparison values ​​to be adjusted in the first half of the carrier cycle, Dmin represents the size of the minimum sampling time Tmin reflected on the carrier, DT represents the maximum value of the carrier, DDMAX and DDMIN represent the maximum and minimum values ​​of DDA1, DDB1 and DDC1, respectively.

[0160] In an application, when the sub-sector where the target voltage vector Vr is located is in the first sub-region R2 of a type of sampling blind area, the three-phase comparison value corresponding to the sampled voltage vector Vs (i.e., the three-phase comparison value to be adjusted within the first half carrier cycle) is calculated as follows:

[0161] DDA1=DDB0+Dmin, DDB1=DDB0, DDC1=DDC0+0.5*(Dmin-DDA1)

[0162] Since the adjusted comparison value has the risk of exceeding the carrier maximum value DT and falling below zero, the three-phase comparison values ​​corresponding to the sampled voltage vector Vs need to be centered, and the offset DDS of the sampled voltage vector Vs is defined. Its calculation method is:

[0163] DDS=0.5*DT-0.5(DDMAX-DDMIN)

[0164] Then the three-phase comparison value corresponding to the centered sampled voltage vector is adjusted to:

[0165] DDA=DDA1-DDS, DDB=DDB1-DDS, DDC=DDC1-DDS;

[0166] Similarly, when the sub-sector where the target voltage vector Vr is located is in the second sub-area R8 in the first-class sampling blind area, the calculation method of the three-phase comparison value corresponding to the sampled voltage vector Vs is:

[0167] DDA1=DDB0-0.5*(Dmin-DDC0), DDB1=DDB0, DDC1=DDB0-Dmin

[0168] Since the adjusted comparison value has the risk of exceeding the carrier maximum value DT and falling below zero, the three-phase comparison values ​​corresponding to the sampled voltage vector Vs need to be centered, and the offset DDS of the sampled voltage vector Vs is defined. Its calculation method is:

[0169] DDS=0.5*DT-0.5(DDMAX-DDMIN)

[0170] Then the three-phase comparison values ​​corresponding to the centered sampled voltage vector Vs are adjusted to:

[0171] DDA=DDA1-DDS, DDB=DDB1-DDS, DDC=DDC1-DDS.

[0172] In one embodiment, when the sub-sector is located in a type of sampling blind area, the calculation formula for the new comparison value in the second half carrier cycle is:

[0173] DUA=DUA1+DUS, DUB=DUB1+DUS, DUC=DUC1+DUS

[0174] DUA1=DUA0-(DDA1-DDA0), DUB1=DUB0-(DDB1-DDB0), DUC1=DUC0-(DDC1-DDC0)

[0175] DUS=0.5*DT-0.5(DUMAX-DUMIN)

[0176] Among them, DUA, DUB and DUC represent the new three-phase comparison values ​​in the second half carrier cycle, DUA0, DUB0 and DUC0 represent the original three-phase comparison values ​​in the second half carrier cycle, DUA1, DUB1 and DUC1 represent the three-phase comparison values ​​to be adjusted in the second half carrier cycle, DUS represents the offset of the three-phase comparison values ​​to be adjusted in the second half carrier cycle, DUMAX and DUMIN represent the maximum and minimum values ​​of DUA1, DUB1 and DUC1, respectively.

[0177] In an application, when the sub-sector where the target voltage vector Vr is located is located in the first sub-area R2 and the second sub-area R8 in a type of sampling blind area, the calculation method of the compensation voltage vector Vc is the same. The calculation method of the three-phase comparison value corresponding to the compensation voltage vector Vc (that is, the three-phase comparison value to be adjusted in the second half carrier cycle) is:

[0178] DUA1=DUA0-(DDA1-DDA0), DUB1=DUB0-(DDB1-DDB0), DUC1=DUC0-(DDC1-DDC0)

[0179] Since the adjusted comparison value has the risk of exceeding the carrier maximum value DT and falling below zero, the three-phase comparison values ​​corresponding to the compensation voltage vector Vc need to be centered, and the offset DUS of the compensation voltage vector Vc is defined. Its calculation method is:

[0180] DUS=0.5*DT-0.5(DUMAX-DUMIN)

[0181] Then the three-phase comparison value corresponding to the centered compensation voltage vector Vc is adjusted to:

[0182] DUA=DUA1+DUS, DUB=DUB1+DUS, DUC=DUC1+DUS.

[0183] In one embodiment, when the sub-sector is located in the first sub-area of ​​the second type of sampling blind area, the calculation formula of the new comparison value in the first half carrier cycle is:

[0184] DDA=DDB0+Dmin, DDB=DDB0, DDC=DDB0-Dmin

[0185] When the sub-sector is located in the second sub-area of ​​the second type of sampling blind area, the calculation formula of the new comparison value in the first half carrier cycle is:

[0186] DDA=DT, DDB=DT-Dmin, DDC=0

[0187] When the sub-sector is located in the third sub-area of ​​the second-type sampling blind area, the calculation formula of the new comparison value in the first half carrier cycle is:

[0188] DDA=DT, DDB=Dmin, DDC=0

[0189] Among them, DDA, DDB and DDC represent the new comparison values ​​of the three phases in the first half of the carrier cycle, DDA0, DDB0 and DDC0 represent the original comparison values ​​of the three phases in the first half of the carrier cycle, Dmin represents the size of the minimum sampling time reflected on the carrier, and DT represents the maximum value of the carrier.

[0190] In one embodiment, when the sub-sector is located in the second type of sampling blind area, the calculation formula of the new comparison value in the second half carrier cycle is:

[0191] DUA=DUA1+DUS, DUB=DUB1+DUS, DUC=DUC1+DUS

[0192] DUA1=DUA0-(DDA1-DDA0), DUB1=DUB0-(DDB1-DDB0), DUC1=DUC0-(DDC1-DDC0)

[0193] DUS=0.5*DT-0.5(DUMAX-DUMIN)

[0194] Among them, DUA, DUB and DUC represent the new three-phase comparison values ​​in the second half carrier cycle, DUA0, DUB0 and DUC0 represent the original three-phase comparison values ​​in the second half carrier cycle, DUA1, DUB1 and DUC1 represent the three-phase comparison values ​​to be adjusted in the second half carrier cycle, DUS represents the offset of the three-phase comparison values ​​to be adjusted in the second half carrier cycle, DUMAX and DUMIN represent the maximum and minimum values ​​of DUA1, DUB1 and DUC1, respectively.

[0195] In an application, when the sub-sector where the target voltage vector Vr is located is located in the first sub-area R2, the second sub-area R4, and the third sub-area R6 in the second type of sampling blind area, the calculation method of the compensation voltage vector Vc is the same. The calculation method of the three-phase comparison value corresponding to the compensation voltage vector Vc (that is, the three-phase comparison value to be adjusted in the second half carrier cycle) is:

[0196] DUA1=DUA0-(DDA1-DDA0), DUB1=DUB0-(DDB1-DDB0), DUC1=DUC0-(DDC1-DDC0)

[0197] Since the adjusted comparison value has the risk of exceeding the carrier maximum value DT and falling below zero, the three-phase comparison values ​​corresponding to the compensation voltage vector Vc need to be centered, and the offset DUS of the compensation voltage vector Vc is defined. Its calculation method is:

[0198] DUS=0.5*DT-0.5(DUMAX-DUMIN)

[0199] Then the three-phase comparison value corresponding to the centered compensation voltage vector Vc is adjusted to:

[0200] DUA=DUA1+DUS, DUB=DUB1+DUS, DUC=DUC1+DUS.

[0201] In one embodiment, when the sub-sector is located in the first sub-area of ​​the non-equivalent sampling blind area, the calculation formula of the new comparison value in the first half carrier cycle is:

[0202] DDA=DT, DDB=DT-Dmin, DDC=0

[0203] When the sub-sector is located in the second sub-area of ​​the non-equivalent sampling blind area, the calculation formula of the new comparison value in the first half carrier cycle is:

[0204] DDA=DT, DDB=Dmin, DDC=0

[0205] Among them, DDA, DDB and DDC represent the new comparison values ​​of the three phases in the first half carrier cycle, Dmin represents the size of the minimum sampling time reflected on the carrier, and DT represents the maximum value of the carrier.

[0206] In one embodiment, when the sub-sector is located in a non-equivalent sampling blind area, the calculation formula for the new comparison value in the second half carrier cycle is:

[0207] DUA=DUA1+DUS, DUB=DUB1+DUS, DUC=DUC1+DUS

[0208] DUA1=DUA0-(DDA1-DDA0), DUB1=DUB0-(DDB1-DDB0), DUC1=DUC0-(DDC1-DDC0)

[0209] DUS=0.5*DT-0.5(DUMAX-DUMIN)

[0210] Among them, DUA, DUB and DUC represent the new three-phase comparison values ​​in the second half of the carrier cycle, DDA0, DDB0 and DDC0 represent the original three-phase comparison values ​​in the first half of the carrier cycle obtained according to the corrected target voltage vector, DUA0, DUB0 and DUC0 represent the original three-phase comparison values ​​in the second half of the carrier cycle obtained according to the corrected target voltage vector, DUA1, DUB1 and DUC1 represent the three-phase comparison values ​​to be adjusted in the second half of the carrier cycle, DUS represents the offset of the three-phase comparison values ​​to be adjusted in the second half of the carrier cycle, DUMAX and DUMIN represent the maximum and minimum values ​​of DUA1, DUB1 and DUC1, respectively.

[0211] In an application, when the sub-sector where the target voltage vector Vr is located is located in the first sub-region R3 and the second sub-region R7 in the non-equivalent sampling blind area, the calculation method of the compensation voltage vector Vc is the same. The calculation method of the three-phase comparison value corresponding to the compensation voltage vector Vc (that is, the three-phase comparison value to be adjusted in the second half carrier cycle) is:

[0212] DUA1=DUA0-(DDA1-DDA0), DUB1=DUB0-(DDB1-DDB0), DUC1=DUC0-(DDC1-DDC0)

[0213] Since the adjusted comparison value has the risk of exceeding the carrier maximum value DT and falling below zero, the three-phase comparison values ​​corresponding to the compensation voltage vector Vc need to be centered, and the offset DUS of the compensation voltage vector Vc is defined. Its calculation method is:

[0214] DUS=0.5*DT-0.5(DUMAX-DUMIN)

[0215] Then the three-phase comparison value corresponding to the centered compensation voltage vector Vc is adjusted to:

[0216] DUA=DUA1+DUS, DUB=DUB1+DUS, DUC=DUC1+DUS.

[0217] It should be understood that the size of the serial numbers of the steps in the above embodiments does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0218] In the above embodiment, only the voltage vector adjustment method when the target voltage vector is located in the first sector of the space vector plane is introduced by way of example. The voltage vector adjustment method when the target voltage vector is located in other sectors can be derived according to the same principle. In addition, in the above embodiment, only the new comparison value calculation method when the first half carrier cycle is the carrier falling edge cycle and the second half carrier cycle is the carrier rising edge cycle is introduced by way of example. The new comparison value calculation method when the first half carrier cycle is the carrier rising edge cycle and the second half carrier cycle is the carrier falling edge cycle can be derived according to the same principle and will not be repeated in the embodiments of this application.

[0219] The present application also provides a voltage vector control device for use in a motor controller to perform the steps of the above method embodiments. The device can be a virtual appliance in the motor controller, run by a processor of the motor controller, or the motor controller itself.

[0220] like Figure 18 As shown, the voltage vector regulation device 100 provided in the embodiment of the present application includes:

[0221] The original value acquisition unit 101 is used to obtain an original comparison value according to the amplitude and phase angle of the target voltage vector;

[0222] A sub-sector determining unit 102 is configured to determine a sub-sector in which the target voltage vector is located based on the original comparison value, where the sub-sector is a sub-region in a sector of the spatial voltage vector plane;

[0223] The new value acquisition unit 103 is used to obtain a new comparison value by adopting a pulse width modulation method corresponding to the sub-sector when the sub-sector is located in a sampling blind area, so that the duration of the two effective vectors constituting the target voltage vector within the half carrier cycle is greater than the minimum sampling time.

[0224] In application, each component in the above device may be a software program unit, or may be implemented by different logic circuits integrated in a processor or independent physical components connected to a processor, or may be implemented by multiple distributed processors.

[0225] like Figure 19 As shown, the embodiment of the present application further provides a motor controller 200, comprising: at least one processor 201 ( Figure 19 Only one processor is shown in the figure), a memory 202, and a computer program 203 stored in the memory 202 and executable on at least one processor 201. When the processor 201 executes the computer program 203, the steps in the above-mentioned various method embodiments are implemented.

[0226] In applications, the motor controller may include, but is not limited to, a processor and a memory, and may also include Figure 1 The current sensor and inverter shown, and / or, may also include a filter, a PWM driver, an analog-to-digital converter, etc. It will be understood by those skilled in the art that Figure 19 This is merely an example of a motor controller and does not limit the scope of the present invention. The motor controller may include more or fewer components than shown, or a combination of certain components or different components. For example, the motor controller may also include input / output devices, network access devices, etc. The input / output devices may include the aforementioned human-computer interaction devices, and may also include a display screen for displaying the operating parameters of the motor controller. The network access device may include a communication module for communication between the motor controller and a client.

[0227] In applications, the processor may be a central processing unit (CPU), other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA), other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or any conventional processor, etc.

[0228] In applications, in some embodiments, the memory can be an internal storage unit of the motor controller, such as a hard disk or memory of the motor controller. In other embodiments, the memory can also be an external storage device of the motor controller, such as a plug-in hard disk equipped on the motor controller, a smart media card (SMC), a secure digital (SD) card, a flash card, etc. The memory can also include both the internal storage unit of the motor controller and an external storage device. The memory is used to store an operating system, application programs, a boot loader, data, and other programs, such as the program code of a computer program. The memory can also be used to temporarily store data that has been output or is about to be output.

[0229] In applications, the display can be a thin film transistor liquid crystal display (TFT-LCD), a liquid crystal display (LCD), an organic electroluminesence display (OLED), a quantum dot light emitting diode (QLED) display, a seven-segment or eight-segment digital tube, etc.

[0230] In applications, the communication module can be configured as any device capable of direct or indirect long-distance wired or wireless communication with a client, allowing the user to control the operating state of the motor by operating the client and utilizing the motor controller, thereby controlling the operating state of the equipment used by the motor, such as the air conditioner, fan, and washing machine. The communication module can provide communication solutions for network devices, including wireless local area networks (WLAN) (such as Wi-Fi networks), Bluetooth, Zigbee, mobile communication networks, global navigation satellite systems (GNSS), frequency modulation (FM), near field communication (NFC), infrared (IR), and other communication technologies. The communication module can include an antenna, which can have a single element or an antenna array including multiple elements. The communication module can receive electromagnetic waves through the antenna, frequency-modulate and filter the electromagnetic wave signals, and then transmit the processed signals to the processor. The communication module can also receive signals to be transmitted from the processor, frequency-modulate and amplify them, and then convert them into electromagnetic waves for radiation via the antenna.

[0231] It should be noted that the information interaction, execution process, etc. between the above-mentioned devices / modules are based on the same concept as the method embodiment of this application. Their specific functions and technical effects can be found in the method embodiment section and will not be repeated here.

[0232] Those skilled in the art can clearly understand that, for the convenience and brevity of description, only the division of the above-mentioned functional modules is used as an example for illustration. In actual applications, the above-mentioned functions can be distributed and completed by different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above. The functional modules in the embodiment can be integrated into a processing module, or each module can exist physically alone, or two or more modules can be integrated into one module. The above-mentioned integrated modules can be implemented in the form of hardware or in the form of software functional modules. In addition, the specific names of the functional modules are only for the convenience of distinguishing each other and are not used to limit the scope of protection of this application. The specific working process of the modules in the above-mentioned system can refer to the corresponding process in the aforementioned method embodiment, which will not be repeated here.

[0233] An embodiment of the present application further provides a computer-readable storage medium, in which a computer program is stored. When the computer program is executed by a processor, the steps in the above-mentioned method embodiments can be implemented.

[0234] An embodiment of the present application provides a computer program product. When the computer program product is run on a motor controller, the motor controller can implement the steps in the above-mentioned various method embodiments.

[0235] If the integrated module is implemented in the form of a software function module and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the present application implements all or part of the process in the above-mentioned embodiment method, which can be completed by instructing the relevant hardware through a computer program. The computer program can be stored in a computer-readable storage medium, and the computer program, when executed by the processor, can implement the steps of the above-mentioned various method embodiments. Wherein, the computer program includes computer program code, and the computer program code can be in source code form, object code form, executable file or some intermediate form, etc. The computer-readable medium may at least include: any entity or device that can carry the computer program code to the motor controller, a recording medium, a computer memory, a read-only memory (ROM, Read-Only Memory), a random access memory (RAM, Random Access Memory), an electric carrier signal, a telecommunication signal and a software distribution medium. For example, a USB flash drive, a mobile hard disk, a magnetic disk or an optical disk, etc.

[0236] In the above embodiments, the description of each embodiment has its own focus. For parts that are not described or recorded in detail in a certain embodiment, reference can be made to the relevant description of other embodiments.

[0237] Those skilled in the art will appreciate that the modules and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0238] In the embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are merely schematic. For example, the division of the modules is merely a logical function division. In actual implementation, there may be other division methods, such as multiple modules or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or modules, which can be electrical, mechanical or other forms.

[0239] The modules described as separate components may or may not be physically separate, and the components shown as modules may or may not be physical modules, that is, they may be located in one place or distributed across multiple network modules. Some or all of the modules may be selected to achieve the purpose of the present embodiment according to actual needs.

[0240] The above-described embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present application, and should all be included in the scope of protection of the present application.

Claims

1. A voltage vector regulation method, characterized in that: include: Obtaining an original comparison value according to the magnitude and phase angle of the target voltage vector; determining, according to the original comparison value, a sub-sector in which the target voltage vector is located, the sub-sector being a sub-region in a sector of a spatial voltage vector plane; When the sub-sector is located in a sampling blind area, a pulse width modulation method corresponding to the sub-sector is used to obtain a new comparison value, so that the duration of the two effective vectors constituting the target voltage vector within a half carrier cycle is greater than the minimum sampling time; When the sub-sector is located in a sampling blind area, a pulse width modulation method corresponding to the sub-sector is used to obtain a new comparison value, including: When the sub-sector is located in a sampling blind area, a pulse width modulation method corresponding to the sub-sector is used to obtain a sampled voltage vector within a first half carrier cycle; Obtaining a new comparison value within the first half carrier cycle according to the sub-sector, the original comparison value within the first half carrier cycle, and the sampled voltage vector; Obtaining a compensation voltage vector within a second half carrier cycle according to the sampled voltage vector, so that a deviation between a composite vector of the sampled voltage vector and the compensation voltage vector and the target voltage vector is minimized; A new comparison value in the second half carrier cycle is obtained according to the sub-sector, the original comparison value in the second half carrier cycle, and the compensation voltage vector.

2. The voltage vector regulation method according to claim 1, wherein: When the sub-sector is located in a sampling blind area, a pulse width modulation method corresponding to the sub-sector is used to obtain a sampled voltage vector, including: When the sub-sector is located in a type of sampling blind area, in a space vector plane, a first perpendicular line is drawn through the end point of the target voltage vector to a first boundary line adjacent to the target voltage vector in the sampleable area, and the intersection of the first perpendicular line and the first boundary line is taken as the end point of the sampled voltage vector; When the sub-sector is located in a second-class sampling blind area, in the space vector plane, the endpoint closest to the end point of the target voltage vector in the sampleable area is used as the end point of the sampled voltage vector; When the sub-sector is located in a non-equivalent sampling blind area, in a space vector plane, a second perpendicular line is drawn through the end point of the target voltage vector to a second boundary line adjacent to the target voltage vector in the second type of sampling blind area. The intersection of the second perpendicular line and the second boundary line is used as the end point of the revised target voltage vector. The endpoint in the sampleable area that is closest to the end point of the revised target voltage vector is used as the end point of the sampled voltage vector.

3. The voltage vector regulation method according to claim 2, wherein: When the sub-sector is located in a first-class sampling blind area or a second-class sampling blind area, the calculation formula of the compensation voltage vector is: Vc=2*Vr-Vs When the sub-sector is located in a non-equivalent sampling blind area, the calculation formula of the compensation voltage vector is: Vc=2*Vr1-Vs Wherein, Vc represents the compensation voltage vector, Vr represents the target voltage vector, Vr1 represents the corrected target voltage vector, and Vs represents the sampled voltage vector.

4. The voltage vector regulation method according to claim 2, wherein: When the sub-sector is located in the first sub-area of ​​a sampling blind area, the calculation formula of the new comparison value in the first half carrier cycle is: DDA=DDA1-DDS, DDB=DDB1-DDS, DDC=DDC1-DDS DDA1=DDB0+Dmin, DDB1=DDB0, DDC1=DDC0+0.5*(Dmin-DDA1) DDS=0.5*DT-0.5(DDMAX-DDMIN) When the sub-sector is located in the second sub-area of ​​a type of sampling blind area, the calculation formula of the new comparison value in the first half carrier cycle is: DDA=DDA1-DDS, DDB=DDB1-DDS, DDC=DDC1-DDS DDA1=DDB0-0.5*(Dmin-DDC0), DDB1=DDB0, DDC1=DDB0-Dmin DDS=0.5*DT-0.5(DDMAX-DDMIN) Wherein, DDA, DDB and DDC represent the new three-phase comparison values ​​within the first half carrier cycle, DDA0, DDB0 and DDC0 represent the original three-phase comparison values ​​within the first half carrier cycle, DDA1, DDB1 and DDC1 represent the three-phase comparison values ​​to be adjusted within the first half carrier cycle, DDS represents the offset of the three-phase comparison values ​​to be adjusted within the first half carrier cycle, Dmin represents the size of the minimum sampling time Tmin reflected on the carrier, DT represents the maximum value of the carrier, DDMAX and DDMIN represent the maximum and minimum values ​​of DDA1, DDB1 and DDC1 respectively; When the sub-sector is located in a type-one sampling blind area, the calculation formula for the new comparison value in the second half carrier cycle is: DUA=DUA1+DUS, DUB=DUB1+DUS, DUC=DUC1+DUS DUA1=DUA0-(DDA1-DDA0), DUB1=DUB0-(DDB1-DDB0), DUC1=DUC0-(DDC1-DDC0) DUS=0.5*DT-0.5(DUMAX-DUMIN) Among them, DUA, DUB and DUC represent the new three-phase comparison values ​​in the second half carrier cycle, DUA0, DUB0 and DUC0 represent the original three-phase comparison values ​​in the second half carrier cycle, DUA1, DUB1 and DUC1 represent the three-phase comparison values ​​to be adjusted in the second half carrier cycle, DUS represents the offset of the three-phase comparison values ​​to be adjusted in the second half carrier cycle, and DUMAX and DUMIN represent the maximum and minimum values ​​of DUA1, DUB1 and DUC1, respectively.

5. The voltage vector regulation method according to claim 2, wherein: When the sub-sector is located in the first sub-area of ​​the second type of sampling blind area, the calculation formula of the new comparison value in the first half carrier cycle is: DDA=DDB0+Dmin, DDB=DDB0, DDC=DDB0-Dmin When the sub-sector is located in the second sub-area of ​​the second type of sampling blind area, the calculation formula of the new comparison value in the first half carrier cycle is: DDA=DT, DDB=DT-Dmin, DDC=0 When the sub-sector is located in the third sub-area of ​​the second type of sampling blind area, the calculation formula of the new comparison value in the first half carrier cycle is: DDA=DT, DDB=Dmin, DDC=0 Wherein, DDA, DDB and DDC represent the new three-phase comparison values ​​within the first half carrier cycle, DDA0, DDB0 and DDC0 represent the original three-phase comparison values ​​within the first half carrier cycle, Dmin represents the size of the minimum sampling time reflected on the carrier, and DT represents the maximum value of the carrier; When the sub-sector is located in the second type of sampling blind area, the calculation formula of the new comparison value in the second half carrier cycle is: DUA=DUA1+DUS, DUB=DUB1+DUS, DUC=DUC1+DUS DUA1=DUA0-(DDA1-DDA0), DUB1=DUB0-(DDB1-DDB0), DUC1=DUC0-(DDC1-DDC0) DUS=0.5*DT-0.5(DUMAX-DUMIN) Among them, DUA, DUB and DUC represent the new three-phase comparison values ​​in the second half carrier cycle, DUA0, DUB0 and DUC0 represent the original three-phase comparison values ​​in the second half carrier cycle, DUA1, DUB1 and DUC1 represent the three-phase comparison values ​​to be adjusted in the second half carrier cycle, DUS represents the offset of the three-phase comparison values ​​to be adjusted in the second half carrier cycle, and DUMAX and DUMIN represent the maximum and minimum values ​​of DUA1, DUB1 and DUC1, respectively.

6. The voltage vector regulation method according to claim 2, wherein: When the sub-sector is located in the first sub-area of ​​the non-equivalent sampling blind area, the calculation formula of the new comparison value in the first half carrier cycle is: DDA=DT, DDB=DT-Dmin, DDC=0 When the sub-sector is located in the second sub-area of ​​the non-equivalent sampling blind area, the calculation formula of the new comparison value in the first half carrier cycle is: DDA=DT, DDB=Dmin, DDC=0 Wherein, DDA, DDB and DDC represent the new three-phase comparison values ​​within the first half carrier cycle, Dmin represents the size of the minimum sampling time reflected on the carrier, and DT represents the maximum value of the carrier; When the sub-sector is located in a non-equivalent sampling blind area, a calculation formula for a new comparison value in the second half carrier cycle is: DUA=DUA1+DUS, DUB=DUB1+DUS, DUC=DUC1+DUS DUA1=DUA0-(DDA1-DDA0), DUB1=DUB0-(DDB1-DDB0), DUC1=DUC0-(DDC1-DDC0) DUS=0.5*DT-0.5(DUMAX-DUMIN) Among them, DUA, DUB and DUC represent new three-phase comparison values ​​in the second half carrier cycle, DDA0, DDB0 and DDC0 represent original three-phase comparison values ​​in the first half carrier cycle obtained according to the corrected target voltage vector, DUA0, DUB0 and DUC0 represent original three-phase comparison values ​​in the second half carrier cycle obtained according to the corrected target voltage vector, DUA1, DUB1 and DUC1 represent three-phase comparison values ​​to be adjusted in the second half carrier cycle, DUS represents the offset of the three-phase comparison values ​​to be adjusted in the second half carrier cycle, and DUMAX and DUMIN represent the maximum and minimum values ​​of DUA1, DUB1 and DUC1, respectively.

7. The voltage vector regulation method according to any one of claims 1 to 6, characterized in that: Determining the sub-sector in which the target voltage vector is located according to the original comparison value includes: determining, according to the original comparison value, the duration of two effective vectors constituting the target voltage vector within a half carrier cycle; The sub-sector where the target voltage vector is located is determined according to the durations of the two effective vectors.

8. The voltage vector regulation method according to claim 7, wherein: The two valid vectors include a first valid vector and a second valid vector; Determining the sub-sector in which the target voltage vector is located according to the durations of the two effective vectors includes: When the durations of the two valid vectors are both greater than the minimum sampling time, determining that the target voltage vector is in the sampleable region; When the duration of the first effective vector is less than the minimum sampling time and the two effective vectors satisfy a first relationship, determining that the target voltage vector is in a first sub-area of ​​a sampling blind area, wherein the first relationship is: 3*Tmin≤T1+2*T2≤2*Tsh-Tmin; When the duration of the second effective vector is less than the minimum sampling time and the two effective vectors satisfy a second relationship, determining that the target voltage vector is in a second sub-area of ​​a first-class sampling blind area, the second relationship being: 3*Tmin≤T2+2*T1≤2*Tsh-Tmin; When the two valid vectors satisfy a third relationship, it is determined that the target voltage vector is in the first sub-area of ​​the second type of sampling blind area, and the third relationship is: T1+2*T2≤3*Tmin; When the duration of the first effective vector is less than the minimum sampling time, the duration of the second effective vector is less than half the carrier period minus 0.5 times the minimum sampling time, and the two effective vectors satisfy a fourth relationship, it is determined that the target voltage vector is in the second sub-area of ​​the second type of sampling blind area, and the fourth relationship is: T1+2*T2≥2*Tsh-Tmin; When the duration of the second effective vector is less than the minimum sampling time, the duration of the first effective vector is less than half the carrier period minus 0.5 times the minimum sampling time, and the two effective vectors satisfy a fifth relationship, it is determined that the target voltage vector is in the third sub-area of ​​the second type of sampling blind area, and the fifth relationship is: T2+2*T1≥2*Tsh-Tmin; When the duration of the first effective vector is less than 0.5 times the minimum sampling time and the duration of the second effective vector is greater than half the carrier period minus 0.5 times the minimum sampling time, determining that the target voltage vector is in the first sub-area of ​​the non-equivalent sampling blind area; When the duration of the second effective vector is less than 0.5 times the minimum sampling time and the duration of the first effective vector is greater than half the carrier period minus 0.5 times the minimum sampling time, determining that the target voltage vector is in the second sub-area of ​​the non-equivalent sampling blind area; Wherein, T1 represents the duration of the first effective vector, T2 represents the duration of the second effective vector, Tmin represents the minimum sampling time, and Tsh represents the half carrier period.

9. A voltage vector regulation device, characterized in that: include: an original value acquisition unit, configured to obtain an original comparison value according to the amplitude and phase angle of the target voltage vector; a sub-sector determining unit, configured to determine, based on the original comparison value, a sub-sector in which the target voltage vector is located, the sub-sector being a sub-sector in a sector of a spatial voltage vector plane; a new value acquisition unit, configured to, when the sub-sector is located in a sampling blind area, obtain a new comparison value by using a pulse width modulation method corresponding to the sub-sector, so that the durations of the two effective vectors constituting the target voltage vector within a half carrier cycle are both greater than a minimum sampling time; When the sub-sector is located in a sampling blind area, a pulse width modulation method corresponding to the sub-sector is used to obtain a new comparison value, including: When the sub-sector is located in a sampling blind area, a pulse width modulation method corresponding to the sub-sector is used to obtain a sampled voltage vector within a first half carrier cycle; Obtaining a new comparison value within the first half carrier cycle according to the sub-sector, the original comparison value within the first half carrier cycle, and the sampled voltage vector; Obtaining a compensation voltage vector within a second half carrier cycle according to the sampled voltage vector, so that a deviation between a composite vector of the sampled voltage vector and the compensation voltage vector and the target voltage vector is minimized; A new comparison value in the second half carrier cycle is obtained according to the sub-sector, the original comparison value in the second half carrier cycle, and the compensation voltage vector.

10. A motor controller, characterized in that: The method comprises a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the steps of the voltage vector regulation method according to any one of claims 1 to 8 when executing the computer program.

11. A computer-readable storage medium storing a computer program, wherein the computer program is executed by a processor to implement the steps of the voltage vector regulation method according to any one of claims 1 to 8.

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