LDPC rate matching method and communication device

Abstract

The present application provides a method and communication device for LDPC rate matching. During retransmission, the transmitter repeatedly transmits the information bits of an LDPC codeword based on their repetition priority order in rate matching, thereby achieving performance gains at the receiver. Because the order of information bit repetition priority is determined based on the sensitivity of the LDPC codeword, information bits with higher sensitivity are assigned a lower repetition priority, while information bits with lower sensitivity are assigned an upper repetition priority. Consequently, when the transmitter repeats information bits of an LDPC codeword, information bits with lower sensitivity are assigned a higher repetition priority, thereby improving decoding performance at the receiver.

Description

Technical Field

[0001] This application relates to the field of channel coding, and more specifically, to a method and communication apparatus for rate matching of LDPC. Background Technology

[0002] In the field of channel coding, low-density parity check (LDPC) is one of the most mature and widely used channel coding schemes. LDPC has performance approaching the Shannon limit and offers numerous advantages. Therefore, IEEE protocols such as 802.11n, 802.11ac, and 802.11ax have proposed LDPC as the standard channel coding scheme for wireless local area networks (WLANs). The 802.11ac / ax standard currently adopts 12 parity check matrices for LDPC, supporting three code lengths, each supporting four code rates. The transmitting device selects the appropriate parity check matrix from the 12 parity check matrices for LDPC coding based on the target code length and code rate.

[0003] To further improve the throughput of communication systems, the next-generation WLAN standard 802.11be was proposed, introducing an incremental redundancy-hybrid automatic repeat request (IR-HARQ) mechanism based on 802.11ax. The IR-HARQ mechanism aims to increase redundant bits through retransmissions, thereby reducing the channel coding rate and improving the decoding performance at the receiver.

[0004] However, the LDPC coding scheme currently used in WLAN standards cannot meet the performance gain requirement of continuously adding redundant bits through retransmission in the IR-HARQ mechanism, resulting in low decoding performance. Summary of the Invention

[0005] This application provides a method and communication apparatus for rate matching of LDPC, which can improve decoding performance.

[0006] In a first aspect, this application provides a method for rate matching of LDPC, the method comprising: a transmitter performing rate matching on a first LDPC codeword of a first code rate according to the order of the repetition priority of the K information bits of the LDPC mother code in rate matching, to obtain a second LDPC codeword of a second code rate, wherein K is a positive integer; and the transmitter transmitting the second LDPC codeword.

[0007] In various embodiments of this application, the priority at which an information bit is repeated during rate matching is called the repetition priority of that information bit.

[0008] In the technical solution of this application, the transmitting end repeats the information bits of the LDPC codeword according to the repetition priority order of the information bits during the rate matching process, thereby obtaining a performance gain at the receiving end. Since the repetition priority order of the information bits is determined based on the sensitivity of the LDPC codeword, information bits with higher sensitivity have a lower repetition priority, while information bits with lower sensitivity have a higher repetition priority. Therefore, when the transmitting end repeats the information bits of the LDPC codeword, information bits with lower sensitivity are repeated first, which can improve the decoding performance at the receiving end.

[0009] In conjunction with the first aspect, in certain implementations of the first aspect, the transmitting end performs rate matching on the first LDPC codeword of the first code rate according to the repetition priority order of the K information bits, including:

[0010] The transmitting end, based on the required number of repeating bits L and the sorting of the repeating priorities of the K information bits, repeatedly transmits L information bits from the first information bit set in the first LDPC codeword in descending order of repeating priority. The repeating priority of the information bit with the lowest repeating priority among the L information bits in the first information bit set is higher than or equal to the repeating priority of the remaining information bits in the first LDPC codeword excluding the information bits in the first information bit set, where L ≤ K and L is an integer.

[0011] It should be understood that the first set of information bits refers to the L information bits with the highest repetition priority among all the information bits of the first LDPC codeword, sorted from high to low repetition priority.

[0012] In conjunction with the first aspect, in some implementations of the first aspect, the repetition priority of the K information bits is ordered as follows:

[0013] The parity-check matrix of an LDPC with K information bits, N mother code length, and R code rate is sorted by the repetition priority of the columns corresponding to the information bits in the parent matrix. Each column in the parent matrix corresponds to z codeword bits of the LDPC, where z = N / n, and n is the total number of columns in the parent matrix. The parity-check matrix of the LDPC is obtained by extending the parent matrix. Each element i in the parent matrix represents a z×z cyclic shift matrix, where i represents the cyclic shift value, i ≥ 0, and i is an integer. N ≥ K, where N is an integer, and R = K / N.

[0014] In conjunction with the first aspect, in some implementations of the first aspect, the mother code length is 1944, the code rate is 1 / 2, and the repetition priority of the columns corresponding to the information bits in the mother matrix is ​​ordered as follows according to the repetition priority from high to low: 10, 6, 8, 11, 4, 3, 12, 7, 2, 5, 9, 1, where each element 'a' in the order represents the 'a'th column of the mother matrix.

[0015] In conjunction with the first aspect, in some implementations of the first aspect, the mother code length is 1296, the code rate is 1 / 2, and the repetition priority of the columns corresponding to the information bits in the mother matrix is ​​ordered as follows according to the repetition priority from high to low: 8, 12, 7, 3, 11, 10, 4, 6, 2, 5, 9, 1, where each element 'a' in the order represents the 'a'th column of the mother matrix.

[0016] In conjunction with the first aspect, in some implementations of the first aspect, the mother code length is 648, the code rate is 1 / 2, and the repetition priority of the columns corresponding to the information bits in the mother matrix is ​​ordered as follows according to the repetition priority from high to low: 8, 6, 12, 11, 2, 3, 10, 7, 4, 1, 5, 9, where each element 'a' in the order represents the 'a'th column of the mother matrix.

[0017] In conjunction with the first aspect, in some implementations of the first aspect, the mother code length is 1944, the code rate is 2 / 3, and the repetition priority of the columns corresponding to the information bits in the mother matrix is ​​ordered as follows according to the repetition priority from high to low: 16,8,15,12,9,10,14,6,13,11,7,5,1,2,3,4, where each element 'a' in the order represents the 'a'th column of the mother matrix.

[0018] In conjunction with the first aspect, in some implementations of the first aspect, the mother code length is 1296, the code rate is 2 / 3, and the repetition priority of the columns corresponding to the information bits in the mother matrix is ​​ordered as follows according to the repetition priority from high to low: 16,9,12,7,10,8,11,14,13,15,6,4,5,1,2,3, where each element 'a' in the order represents the 'a'th column of the mother matrix.

[0019] In conjunction with the first aspect, in some implementations of the first aspect, the mother code length is 648, the code rate is 2 / 3, and the repetition priority of the columns corresponding to the information bits in the mother matrix is ​​ordered as follows according to the repetition priority from high to low: 16,9,12,7,10,8,11,14,13,15,6,4,5,1,2,3, where each element 'a' in the order represents the 'a'th column of the mother matrix.

[0020] In conjunction with the first aspect, in some implementations of the first aspect, the mother code length is 1944, the code rate is 3 / 4, and the repetition priority of the columns corresponding to the information bits in the mother matrix is ​​ordered as follows according to the repetition priority from high to low: 12, 16, 11, 10, 14, 17, 15, 8, 13, 18, 7, 9, 1, 2, 3, 4, 5, 6, where each element 'a' in the order represents the 'a'th column of the mother matrix.

[0021] In conjunction with the first aspect, in some implementations of the first aspect, the mother code length is 1296, the code rate is 3 / 4, and the repetition priority of the columns corresponding to the information bits in the mother matrix is ​​ordered as follows according to the repetition priority from high to low: 9, 11, 13, 15, 17, 8, 10, 12, 14, 16, 18, 1, 2, 3, 4, 5, 6, 7, where each element 'a' in the order represents the 'a'th column of the mother matrix.

[0022] In conjunction with the first aspect, in some implementations of the first aspect, the mother code length is 648, the code rate is 3 / 4, and the repetition priority of the columns corresponding to the information bits in the mother matrix is ​​ordered as follows according to the repetition priority from high to low: 18, 13, 15, 16, 12, 14, 17, 10, 6, 7, 8, 11, 9, 1, 2, 3, 4, 5, where each element 'a' in the order represents the 'a'th column of the mother matrix.

[0023] In conjunction with the first aspect, in some implementations of the first aspect, the mother code length is 1944, the code rate is 5 / 6, and the repetition priority of the columns corresponding to the information bits in the mother matrix is ​​ordered as follows according to the repetition priority from high to low: 12, 14, 15, 17, 19, 13, 20, 11, 16, 18, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, where each element 'a' in the order represents the 'a'th column of the mother matrix.

[0024] In conjunction with the first aspect, in some implementations of the first aspect, the mother code length is 1296, the code rate is 5 / 6, and the repetition priority of the columns corresponding to the information bits in the mother matrix is ​​ordered as follows according to the repetition priority from high to low: 17,20,19,18,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16, where each element 'a' in the order represents the 'a'th column of the mother matrix.

[0025] In combination with the first aspect, in certain implementations of the first aspect, the length of the mother code is 648 and the code rate is 5 / 6. In the order of decreasing repetition priority, the sorting of the repetition priorities of the columns corresponding to the information bits in the mother matrix is as follows: 13, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 14, 15, 16, 17, 18, 19, 20, where each element a in the sorting represents the a-th column of the mother matrix.

[0026] In combination with the first aspect, in certain implementations of the first aspect, the transmitter repeats the information bits with the top L repetition priorities among the first LDPC codewords according to the number L of bits to be repeated and the sorting of the repetition priorities of the K information bits, in the order of decreasing repetition priority, including:

[0027] If L < z, the transmitter selects L information bits from the z information bits corresponding to the column with the highest repetition priority in the mother matrix in the parity-check matrix for repetition;

[0028] If L = m × z, the transmitter repeats the mz information bits corresponding to the first m columns with the highest repetition priorities selected from the mother matrix in the parity-check matrix in the order of decreasing repetition priority, where m is a positive integer;

[0029] If (m - 1) × z < L < m × z, the transmitter repeats the (m - 1) × z information bits corresponding to the first (m - 1) columns with the highest repetition priorities selected from the mother matrix in the parity-check matrix in the order of decreasing repetition priority, and p information bits from the z information bits corresponding to the m-th column in the parity-check matrix, where L = (m - 1) × z + p, p ≥ 1 and p is an integer, m > 1, and m is an integer.

[0030] In combination with the first aspect, in certain implementations of the first aspect, before the transmitter repeats and sends the L information bits included in the first information bit set in the first LDPC codeword according to the number L of bits to be repeated and the sorting of the repetition priorities of the K information bits, in the order of decreasing repetition priority, the method further includes:

[0031] The transmitter sends the first LDPC codeword;

[0032] And, the transmitter repeats and sends the L information bits included in the first information bit set in the first LDPC codeword according to the number L of bits to be repeated and the sorting of the repetition priorities of the K information bits, in the order of decreasing repetition priority, including:

[0033] If the first LDPC codeword is not successfully decoded by the receiving end, the sending end shall repeatedly transmit the L information bits contained in the first information bit set in the first LDPC codeword in descending order of the repetition priority, according to the number L of repetition bits required and the repetition priority of the K information bits.

[0034] Furthermore, the method further includes:

[0035] If all information bits contained in the first LDPC codeword have been repeatedly transmitted, and the receiving end still fails to successfully decode the information bits, the method further includes:

[0036] The transmitting end sends the parity bits that have been punctured in the first LDPC codeword according to the puncturing priority of the parity bits. The parity bits with lower puncturing priority are sent first. The puncturing priority is used to indicate the priority of puncturing (NK) parity bits in rate matching. N is the length of the LDPC mother code, N≥K, and N is an integer.

[0037] In conjunction with the first aspect, in some implementations of the first aspect, before the transmitting end repeatedly transmits the L information bits contained in the first information bit set of the first LDPC codeword in descending order of repetition priority, based on the required number of repeated bits L and the repetition priority of the K information bits, the method further includes:

[0038] The transmitting end sends the first LDPC codeword;

[0039] If the first LDPC codeword is not successfully decoded by the receiving end, the transmitting end sends the parity bits that have been punctured in the first LDPC codeword according to the priority of the parity bits. The parity bits with lower puncturing priority are sent first. The puncturing priority is used to indicate the priority of puncturing (NK) parity bits in rate matching. N is the length of the LDPC mother code, N≥K, and N is an integer.

[0040] Furthermore, the transmitting end, based on the required number of repeated bits L and the sorting of the repetition priorities of the K information bits, repeatedly transmits the L information bits contained in the first information bit set of the first LDPC codeword in descending order of repetition priority, including:

[0041] If all the punctured parity bits of the first LDPC codeword have been sent and the receiver has still not successfully decoded it, the sender sends the information bits of the first LDPC codeword according to the repetition priority of the K information bits.

[0042] Secondly, this application provides a communication device that has the function of implementing the method in the first aspect or any possible implementation thereof. The function can be implemented by hardware or by hardware executing corresponding software. The hardware or software includes one or more units corresponding to the above-described function.

[0043] Thirdly, this application provides a communication device, including an interface circuit and a processor. The interface circuit is used to receive computer code or instructions and transmit them to the processor. The processor executes the computer code or instructions, and the method in the first aspect or any implementation thereof is implemented.

[0044] Fourthly, this application provides a communication device including at least one processor coupled to at least one memory for storing computer programs or instructions, and the at least one processor for calling and running the computer program or instructions from the at least one memory, causing the communication device to perform the method in the first aspect or any possible implementation thereof.

[0045] In one example, the communication device may be an encoder.

[0046] Fifthly, this application provides a computer-readable storage medium storing computer instructions that, when executed on a computer, implement the method of the first aspect or any possible implementation thereof.

[0047] Sixthly, this application provides a computer program product comprising computer program code, wherein when the computer program code is run on a computer, the method in the first aspect or any possible implementation thereof is implemented.

[0048] In a seventh aspect, this application provides a wireless communication system, including the communication device as described in the fourth aspect. Attached Figure Description

[0049] Figure 1 H is the parity check matrix of the LDPC code.

[0050] Figure 2 The Tanner plot of the parity-check matrix H for the LDPC code.

[0051] Figure 3 (a) and (b) are system architecture diagrams applicable to embodiments of this application.

[0052] Figure 4 A flowchart for establishing a sensitivity sorting table for bit positions provided in this application.

[0053] Figure 5 The function is shown The image.

[0054] Figure 6 A schematic flowchart of the LDPC rate matching method provided in this application.

[0055] Figure 7 An example of the application of the replication scheme provided in this application in IR-HARQ.

[0056] Figure 8 An example of the application of the combination of the information bit repetition scheme and the parity bit punching scheme provided in this application in IR-HARQ.

[0057] Figures 9-19 The FER curves and throughput curves of the system under various IR-HARQ transmission strategies are shown.

[0058] Figure 20 A schematic block diagram of the communication device 1000 provided in this application. Detailed Implementation

[0059] The technical solutions in this application will now be described with reference to the accompanying drawings.

[0060] The evolution of IEEE 802.11n / ac / ax / be and other wireless local area network (WLAN) transmission standards primarily focuses on improving user experience in high-bandwidth scenarios such as 60GHz. This includes increasing average throughput and energy efficiency for battery-powered devices, requiring high-speed and reliable transmission of data, time-frequency, and other services within limited frequency and power resources. Therefore, highly reliable and efficient channel coding and decoding schemes are needed. Currently, low-density parity check (LDPC) is one of the most mature and widely used channel coding schemes in the field of channel coding, and it has been widely applied in communications. LDPC exhibits performance close to the Shannon limit and offers numerous advantages, such as good error rate performance without deep interleaving, good frame error rate performance, significantly reduced error planes, network-independent decoding, support for parallel decoding, and low decoding latency. Therefore, LDPC has become the standard channel coding scheme for low-frequency short-range WLAN communication systems such as IEEE 802.11n / ac / ax. At the same time, it has become the mandatory channel coding scheme when the bandwidth of IEEE 802.11ax is greater than or equal to 40MHz.

[0061] The next-generation WLAN standard 802.11be, following the new 802.11ax, introduces Hybrid Automatic Repeat Request (HARQ) to further improve system throughput. HARQ mainly involves storage, retransmission requests, and merging demodulation. When the receiver fails to decode data, it saves the received data and requests the sender to retransmit it. The receiver then merges the retransmitted data with the previously received and saved data before decoding, achieving diversity gain, reducing the number of retransmissions and latency, and increasing the probability of successful data decoding.

[0062] HARQ can be broadly categorized into two types: chase combine (CC) and incremental redundancy (IR), which can be referred to as CC HARQ and IR HARQ, respectively.

[0063] HARQ mechanisms can be categorized into two types: chase-comb (CC) and incremental redundancy (IR-HARQ). In a simple HARQ mechanism, the receiver discards incorrectly received data packets. However, while these incorrectly received packets cannot be decoded independently, they still contain some useful information. In CC-HARQ, the CC process utilizes this information, storing the incorrectly received packets in memory and combining them with retransmitted packets for decoding, thus improving transmission efficiency. The IR-HARQ mechanism involves the sender initially transmitting information bits and a portion of redundant bits, and then transmitting additional redundant bits in retransmissions. If the initial transmission fails to decode, the sender reduces the channel code rate by retransmitting more redundant bits, thereby improving the decoding success rate. If the receiver still cannot decode successfully even with the added redundant bits, the sender retransmits again. As the number of retransmissions increases, the redundant bits increase, the coding rate decreases, and better decoding results are achieved.

[0064] If the next-generation WLAN standard introduces the IR HARQ mechanism, it will require a rate-compatible LDPC (RC-LDPC) coding scheme to support it in order to introduce new incremental redundant bits during retransmission.

[0065] To facilitate understanding of the scheme in this application, the relevant concepts of LDPC will be introduced first.

[0066] LDPC is a linear block code whose parity check matrix is ​​a sparse matrix, meaning that the number of zero elements in the parity check matrix is ​​much greater than the number of non-zero elements. In other words, the row weight and column weight of the parity check matrix are very small compared to the code length of LDPC.

[0067] In 1981, Tanner represented the LDPC codewords graphically, a method now known as the Tanner diagram. The Tanner diagram corresponds one-to-one with the parity-check matrix and consists of two types of nodes: variable nodes (representing codeword symbols) and check nodes (representing check constraints). Each check node represents a check constraint. The following section will discuss this further. Figure 1 and Figure 2 Please provide an explanation.

[0068] See Figure 1 , Figure 1 H is the parity check matrix of LDPC. Figure 1 In the middle, {V i} represents the set of variable nodes, {C i} represents the set of check nodes. Each row of the check matrix H represents a check equation, and each column represents a codeword bit. Figure 1 In the diagram, there are 8 variable nodes and 4 check nodes. If a codeword bit is included in the corresponding check equation, a line is used to connect the involved variable nodes and check nodes to obtain the Tanner diagram.

[0069] See Figure 2 , Figure 2 This is a Tanner plot of the parity-check matrix H of the LDPC. (Example:) Figure 2 As shown, the Tanner diagram represents the parity-check matrix of the LDPC. For example, for a parity-check matrix H of size m rows and n columns, the Tanner diagram contains two types of nodes: n variable nodes and m parity nodes. The n variable nodes correspond to the n columns of the parity-check matrix H, and the m parity nodes correspond to the m rows of the parity-check matrix H. A cycle in the Tanner diagram consists of interconnected nodes. The cycle uses one node in the group of nodes as both the start and end point, and visits each node only once. The length of the cycle is defined as the number of connections it contains, while the circumference of the graph, also known as the size of the graph, is defined as the minimum cycle length in the graph, such as... Figure 2 In the middle, the circumference is 6, such as Figure 2The diagram shows the black lines connecting the variable nodes in the Tanner graph. In the Tanner graph, each variable node corresponds to a column of the parity-check matrix H, which is equivalent to a bit in the LDPC codeword. Each parity-check node in the Tanner graph corresponds to a row of the parity-check matrix H, which is equivalent to a parity-check bit in the LDPC codeword. The connection between the two types of nodes corresponds to the value of an element in the H matrix. If there is a connection between the i-th parity-check node and the j-th variable node, the element (i,j) in the H matrix has a value of 1; otherwise, the corresponding element is 0. Furthermore, in the Tanner graph, a cycle is a closed loop formed by connecting variable nodes, parity-check nodes, and edges end-to-end.

[0070] As mentioned above, LDPC is a linear block code. A linear block code divides the information sequence to be encoded into groups of k bits each. The encoder then performs linear operations on these k information bits to obtain m parity bits. These k information bits are then combined with the m parity bits to obtain a code group of length n = k + m. The mapping from k information bits to an n-bit code group is typically represented by a corresponding parity check matrix H. The encoding sequence is generated based on the parity check matrix H, completing the encoding process. After the encoded codewords are transmitted through the channel, the receiving end decodes the received signal to determine the original information bits.

[0071] When the code length is long, the parity check matrix H of LDPC becomes very large. Therefore, the parity check matrix H is usually represented in blocks: the parity check matrix H (specifically the original parity check matrix) is regarded as generated by multiple z×z submatrices. Thus, the parity check matrix H can be represented by a parent matrix, where each element corresponds to a z×z submatrix, and each submatrix can be represented by a cyclically shifted number of bits. This greatly reduces the storage space required for the parity check matrix H. Each parity check matrix corresponds to a code rate and a code length.

[0072] This application uses the parity-check matrix from the 802.11ac standard, supporting code lengths of 1944, 1296, and 648. All three code lengths support code rates of 1 / 2, 2 / 3, 3 / 4, and 5 / 6. Based on the parent matrix and expansion factor z given by the 802.11ac standard, the original parity-check matrix H can be obtained.

[0073] The LDPC codes used in the IEEE 802.11ac and 802.11ax standards are quasi-cyclic low-density parity check (QC-LDPC) codes. QC-LDPC codes are a type of structured LDPC code. Due to the unique structure of their parity-check matrix, encoding can be achieved using a simple feedback shift register, reducing the encoding complexity of LDPC codes.

[0074] IEEE 802.11ac and 802.11ax adopt a total of 12 parity-check matrices, supporting three code lengths: 648, 1296, and 1944. Each code length supports four different code rates: 1 / 2, 2 / 3, 3 / 4, and 5 / 6. The parity bits of these 12 parity-check matrices all have the same structure.

[0075] For example, the parent matrix of the parity-check matrix H of an LDPC with a code length of 1944 and a code rate of 5 / 6 in 802.11ac is shown below:

[0076]

[0077] As can be seen, the parent matrix has a size of 4 rows and 24 columns. Each element in the parent matrix represents a square matrix of order z = N / 24. The "-" in the parent matrix indicates a square matrix of size z × z containing all zeros. The element i in the parent matrix represents the cyclic shift value, where 0 ≤ i ≤ z - 1, and i is an integer. For example, i = 0 represents an identity matrix of size 81 × 81, while i = 1 represents the following cyclic shift matrix:

[0078]

[0079] In traditional WLANs, when performing LDPC encoding, the transmitting end selects the appropriate parity check matrix from the aforementioned 12 parity check matrices based on the target code length and target code rate. These 12 parity check matrices are all distinct.

[0080] If the IR-HARQ mechanism is introduced in the next-generation WLAN standard, a rate-compatible LDPC coding scheme also needs to be introduced to obtain new incremental redundant bits during retransmission.

[0081] The following section describes the technical solution provided in this application.

[0082] The technical solution of this application is mainly applicable to wireless communication systems, which can comply with the wireless communication standards of the third generation partnership project (3GPP) or other wireless communication standards, such as the IEEE 802 series (e.g., 802.11, 802.15, or 802.20) wireless communication standards.

[0083] See Figure 3 , Figure 3 Figures (a) and (b) are system architecture diagrams applicable to embodiments of this application. The wireless communication system includes at least one network device and one or more terminal devices. The at least one network device and the one or more terminal devices communicate using wireless communication technology. For example, Figure 3 (a) illustrates communication between a network device and a single terminal device. Figure 3 (b) illustrates a network device communicating with multiple terminal devices. Optionally, the communication between the network device and the terminal devices may include downlink transmission of signals from the network device to the terminal devices and uplink transmission of signals from the terminal devices to the network device, which is not limited herein.

[0084] The technical solution of this application can be applied to scenarios involving uplink and downlink data transmission. For example, in uplink transmission, the sending end in each embodiment is a terminal device, and the receiving end is a network device. In downlink transmission, the sending end is a network device, and the receiving end is a terminal device.

[0085] The terminal devices involved in the embodiments of this application can be user equipment (UE), terminals, mobile phones, tablet computers, laptop computers, wearable devices (e.g., smartwatches, smart bracelets, smart helmets, smart glasses, etc.), and other devices with wireless access capabilities, such as smart cars, various Internet of Things (IoT) devices, including various smart home devices (e.g., smart meters and smart appliances) and smart city devices (e.g., security or monitoring equipment, smart road traffic facilities), terminal devices in 5G systems or future communication systems, etc.

[0086] The network equipment involved in the embodiments of this application can be a base station, which is sometimes also called a wireless access point (AP), a transmission reception point (TRP), or a transmission point (TP). Optionally, the base station can be a generation Node B (gNB) in a 5th generation (5G) system or an evolutionary Node B (eNB) in a long term evolution (LTE) system. Furthermore, depending on the physical form or transmission power of the base station, it can be classified as a macro base station or a micro base station. Micro base stations are sometimes also called small base stations or small cells. In addition, the network equipment can also be network nodes constituting a gNB or TRP, such as a building baseband unit (BBU), a centralized unit (CU), or a distributed unit (DU).

[0087] This application provides a repetition scheme based on LDPC. By repeating the information bits in the LDPC codeword bits, some repeated information bits can be obtained during retransmission, so that these repeated information bits can be combined with the corresponding information bits of the first transmission at the receiving end.

[0088] Furthermore, the LDPC repetition scheme provided in this application can be combined with a puncturing (or punching) scheme, thereby repeating the information bits in the LDPC codeword bits while punching the parity bits. This allows for the retransmission of the information bits and the remaining parity bits after puncturing, ultimately resulting in a more flexible HARQ retransmission mechanism. The receiving end can simultaneously combine the initially transmitted bits, the retransmitted portion of the information bits, and the incremental redundant bits to achieve performance gains.

[0089] The basic idea of ​​the LDPC repetition scheme based on confidence criteria proposed in this application is to determine the position of the sensitive information bits to be repeated based on statistical confidence characteristics, such as the absolute value of the contrastive likelihood ratio (LLR) of iterative decoding. IR-HARQ requires that the LDPC code rates at the receiving end be compatible, that is, bits transmitted at high code rates are included in bits transmitted at low code rates, and the retransmitted information bits need to meet this condition. In the IR-HARQ mechanism, system bits with low confidence are preferentially repeated because lower confidence is more prone to errors, and only system bits carry valid information.

[0090] To illustrate the basic principles of the confidence criterion, we first define the sensitivity of codeword bits.

[0091] First, the source is fixed as a source of all "0"s. Under noise-free conditions, a certain number of iterations are performed on the LDPC codeword that has not yet undergone rate matching. After the iterative decoding converges, the absolute value of the LLR (Local Level Ratio) of the iterative decoding, |LLR|, is used as a confidence feature to determine the sensitivity of the bit position. The smaller the |LLR|, the more sensitive the bit position corresponding to that |LLR|.

[0092] It should be noted that, since LDPC codes are linear codes, and the positions of the check bits determined by different information sources have similar sensitivity orders, the ring and degree distribution characteristics of different information bits are consistent, and the puncturing performance is basically the same. Therefore, in the technical solution of this application, the fixed information source is an all-"0" information source.

[0093] For repeated LDPC information bits, sort them in order of confidence from smallest to largest (or from largest to smallest), and store the sorting relationship in table T. Table T is the sensitivity sorting table of bit position.

[0094] Alternatively, as an example, table T can be represented by the following equation (1):

[0095]

[0096] Next, let's combine... Figure 4 Explain the process of establishing a sensitivity sorting table for bit positions.

[0097] See Figure 4 , Figure 4 A flowchart illustrating the establishment of a sensitivity sorting table for bit positions provided in this application. (For example...) Figure 4In a noise-free environment, a fixed source of all "0"s is encoded using LDPC with the appropriate code rate and code length, and then modulated, for example, by binary phase shift keying (BPSK). The initial decoding information is set to a fixed value ±x, and then fed into an iterative decoder for decoding. After a certain number of iterations (e.g., n times), the LLR of the parity bits is output, and the absolute values ​​of the LLRs are sorted, for example, in ascending order.

[0098] Optionally, the iterative decoder can specifically be a log-SPA iterative decoder. SPA stands for sum-product algorithm, a type of LDPC decoding algorithm based on iterative decoding, and belongs to the soft-decision algorithm category. When using log-SPA decoding, the initial decoding information for the additive white Gaussian noise (AWGN) channel is y / σ. 2 y represents channel information, σ 2 Let be the noise variance. When the noise variance is 0, the initial decoding information should be ±∞. Considering that setting it this way directly in the computer program would lead to data overflow, the function shown in equation (2) is used when solving for the verification information:

[0099]

[0100] in, The functional properties are as follows Figure 5 , Figure 5 The function is shown The image.

[0101] Optionally, in actual decoding, the initial decoding value x can be set to 3, 4, 5, etc.

[0102] Based on the above principles, this application proposes a repetition priority sorting of LDPC with code rates of 1 / 2, 2 / 3, 3 / 4 and 5 / 6 for next-generation WLAN systems based on the IR-HARQ mechanism.

[0103] During the initial transmission, the IR-HARQ mechanism can either directly transmit the original LDPC codeword, or punch the parity bits of the original LDPC codeword before transmitting the punched codeword.

[0104] During the i-th transmission, some information bits are retransmitted in descending priority (or ascending confidence level), or, simultaneously, the punctured parity bits are retransmitted. The number of retransmitted bits is determined based on the new code rate required for retransmission or the number of channel resources allocated for retransmission.

[0105] See Figure 6 , Figure 6 This is a schematic flowchart illustrating the LDPC rate matching method provided in this application. The methods in the various embodiments of this application can be executed by a transmitting end, or by devices or modules such as chips, processors, and processing circuits disposed in the transmitting end. The following embodiments use the transmitting end as the execution subject for example.

[0106] 410. The transmitting end performs rate matching on the first LDPC codeword of the first code rate according to the repetition priority of the K information bits of the LDPC mother code during the rate matching process, and obtains the second LDPC codeword of the second code rate.

[0107] In this application, the priority at which information bits in an LDPC codeword are repeated (or, in other words, repeatedly transmitted) during rate matching is called the repetition priority.

[0108] The order of the repetition priority of the K information bits reflects the reliability (or confidence) of the K information bits.

[0109] For example, the higher the repetition priority of an information bit, the higher its reliability, and therefore, it will be repeated preferentially in rate matching. Conversely, the lower the repetition priority of an information bit, the lower its reliability, and therefore, it will be repeated later in the K information bits during rate matching.

[0110] Optionally, the repetition priority of the K information bits can be sorted from high to low priority, in which case the information bits that appear earlier have a higher repetition priority. Alternatively, they can be sorted from low to high priority, in which case the information bits that appear later have a higher repetition priority.

[0111] It should be understood that in traditional WLANs, a parity check matrix corresponding to the target code rate and target code length is used to perform LDPC encoding on K information bits to obtain an LDPC master code of length N. In this master code, K codeword bits correspond to the K information bits, and the remaining (NK) codeword bits correspond to (NK) parity bits, where N and M are both positive integers, and N > K. The target code rate can be 1 / 2, 2 / 3, 3 / 4, and 5 / 6 as mentioned above, and the target code length can be 1944, 1296, and 648.

[0112] Since different parity check matrices correspond to different bitrates, changing the bitrate from a high bitrate to a low bitrate, or from a low bitrate to a high bitrate, requires selecting different parity check matrices.

[0113] In this embodiment, since the IR-HARQ mechanism requires compatibility between high and low bitrates, it is also possible to switch from a high bitrate to a low bitrate, or from a low bitrate to a high bitrate, based on the same parity check matrix. This process of switching from a high bitrate to a low bitrate, or from a low bitrate to a high bitrate, is called rate matching.

[0114] In one embodiment, the first LDPC codeword in step 410 can be the parent codeword. In this case, the first code rate of the first LDPC codeword is also the code rate of the parent codeword. That is, by using a parity check matrix with a target code length and a target code rate, LDPC encoding is performed on K information bits to obtain the first LDPC codeword. Here, the code length of the first LDPC is the target code length, and the first code rate of the first LDPC codeword is the target code rate. For example, taking the parity check matrix of the LDPC with a code length of 1944 and a code rate of 5 / 6 mentioned above as an example, using this parity check matrix to perform LDPC encoding on K information bits yields a first LDPC codeword with a code length of 1944 and a code rate of 5 / 6.

[0115] Based on this, the rate matching scheme provided in this application can be used to perform rate matching on the first LDPC codeword of the first code rate to obtain the second LDPC codeword of the second code rate.

[0116] For example, if the first LDPC codeword at the first code rate is successfully transmitted for the first time, the sender can try a higher code rate. At this time, by performing rate matching on the first LDPC codeword at the first code rate, a second LDPC codeword at a higher code rate can be obtained, that is, the second code rate is higher than the first code rate.

[0117] For example, if the first transmission of the first LDPC codeword at the first code rate fails, the transmitter can try to reduce the code rate to increase the probability of successful decoding by the receiver. In this case, the transmitter can perform rate matching on the first LDPC codeword at the first code rate to obtain a second LDPC codeword at a lower code rate, i.e., the second code rate is lower than the first code rate.

[0118] Specifically, if the repetition priority of the information bits provided in the embodiments of this application is used to rate match the first LDPC codeword to obtain the second LDPC codeword, then the code rate (i.e., the second code rate) of the second LDPC codeword is lower than the first code rate of the first LDPC codeword.

[0119] In this application, rate matching is performed based on the repetition priority of the information bits. Alternatively, in other examples, the repetition priority of the information bits and the puncturing priority of the parity bits can be combined.

[0120] It should be noted that the above describes the process of obtaining the repetition priority of information bits based on the sensitivity of codeword bits. Based on the same principle, the reliability (i.e., confidence) of check bits can also be ranked based on the sensitivity of check bits to obtain the punching priority of check bits.

[0121] Unlike the repetition priority of information bits, if a parity bit is more sensitive, it indicates lower reliability. Therefore, in rate matching, this parity bit is preferentially punctured, and thus has a higher puncturing priority. Conversely, if a parity bit is less sensitive, it indicates higher reliability, and thus has a lower puncturing priority in rate matching.

[0122] Since retransmission is intended to improve the decoding success rate at the receiving end, the higher the puncturing priority of the parity bit, the lower its reliability, and the lowest its retransmission priority during the retransmission process. Conversely, the lower the puncturing priority of the parity bit, the higher its retransmission priority during the retransmission process.

[0123] In another embodiment, the first LDPC codeword can be a rate-matched LDPC codeword. For example, the first LDPC codeword can be an LDPC codeword obtained by puncturing the master code. Alternatively, the first LDPC codeword can be an LDPC codeword obtained by repeating some information bits of the master code. Based on this, the transmitting end can perform rate matching on the first LDPC codeword of the first code rate based on the repetition priority of the information bits, or based on the repetition priority of the information bits and the puncturing priority of the parity bits, to obtain the desired second code rate.

[0124] 420. The transmitting end sends the LDPC codeword of the second code rate.

[0125] Therefore, the information bit repetition priority ordering provided in this application is used for rate matching of LDPC codewords. Specifically, the transmitter obtains a lower-rate LDPC codeword by repeating the information bits with higher repetition priority of a high-rate LDPC codeword. Alternatively, the transmitter obtains a desired code rate by repeating the information bits with higher repetition priority of a high-rate LDPC codeword and simultaneously punching punctures in some of the high-priority parity bits of that LDPC codeword. In this application, high and low code rates are compatible.

[0126] Since each code rate (four code rates in total: 1 / 2, 2 / 3, 3 / 4, and 5 / 6) in WLAN currently has three code lengths for LDPC, namely 648, 1296, and 1944, this application provides a ranking of the confidence levels of the corresponding information bits for each of the four code rates and three code lengths.

[0127] (1) Code rate R = 1 / 2, code length L = 1944.

[0128] First, the parent matrix (denoted as matrix 1) of the parity-check matrix of an LDPC code with a code rate of 1 / 2 and a code length of 1944 is given below:

[0129]

[0130] As shown above, matrix 1 has a size of 12×24, and each element in matrix 1 represents a square matrix of order z = 1944 / 24 = 81. Here, "-" indicates an 81×81 matrix of all zeros. Each element i in matrix 1 represents an 81×81 cyclic permutation matrix, where i represents the cyclic shift value. For example, i = 0 represents an 81×81 identity matrix.

[0131] Optionally, the LLR| of the parity bits and their reliability order in the parent matrix of the parity check matrix corresponding to an LDPC with a code rate of 1 / 2 and a code length of 1944 can be shown in Table 1.

[0132] Table 1

[0133] Reliability ranking 19(2) 20(2) 18(2) 21(2) 17(2) 22(2) LLR 26.9747 27.1948 27.3161 27.9524 28.1107 29.1414 Reliability ranking 16(2) 23(2) 15(2) 24(2) 14(2) 13(3) LLR 29.2333 30.6309 30.6696 32.3636 32.5114 32.5925

[0134] In Table 1, a(b) represents the a-th column of the parent matrix, and the column weight of the a-th column is b (that is, the column contains b ones).

[0135] As shown in Table 1, because lower confidence levels are more prone to errors and provide less effective information to other system variable nodes, parity bits with lower confidence levels are preferentially punctured. Furthermore, punctured parity bits can ensure the recoverability of system variable nodes, especially when the number of punctured bits is large.

[0136] It should be understood that, in the various embodiments of this application, the order of reliability of the columns corresponding to information bits in the parent matrix is ​​consistent with the order of repetition priority levels in the rate matching process. That is, the order of reliability from high to low is the same as the order of repetition priority from high to low.

[0137] Table 2 shows the order of repetition priorities of information bits given in this application.

[0138] Table 2

[0139] Reliability ranking 10(3) 6(3) 8(3) 11(3) 4(3) 3(3) LLR 35.1049 35.3955 35.3983 35.4292 35.4818 35.5749 Reliability ranking 12(3) 7(3) 2(4) 5(11) 9(11) 1(11) LLR 35.6812 35.8946 47.0243 126.4571 126.7682 126.7955

[0140] In Table 2, a(b) represents the a-th column in the parent matrix, with a column weight of b. As shown in Table 2, information bits with lower confidence levels have higher repetition priority.

[0141] Since this application only provides the order of repetition priority of information bits, Table 2 shows the order of columns 1 to 12 of matrix 1, because columns 1 to 12 correspond to the information (or system) part of the parity check matrix. The codeword bits corresponding to these columns are all original information bits.

[0142] Based on the correspondence between the original parity-check matrix and the parent matrix described above, for a parent matrix of size p×q, each element of the parent matrix corresponds to a square matrix of order z = N / q, and each column of the parent matrix corresponds to the z codeword bits of the original parity-check matrix. Since the repetition priority of the information bits is given by the columns of the parent matrix, the repetition priority of the z codeword bits corresponding to each column of the parent matrix in the original parity-check matrix is ​​the same.

[0143] For example, the parent matrix for an LDPC with a code rate R = 1 / 2 and a code length N = 1944 is 12 × 24, and each element in the parent matrix corresponds to a square matrix of order z = 1944 / 24 = 81. Therefore, any column of the parent matrix corresponds to 81 codeword bits in the original parity-check matrix. Taking the 10th column in Table 2, which has the highest reliability ranking, as an example, the 81 codeword bits in the original parity-check matrix in the 10th column have the same repetition priority.

[0144] As shown in Table 2, for an LDPC parity check matrix with a code rate of 1 / 2 and a code length of 1944, the repetition priority of the columns corresponding to the information bits in the parent matrix during rate matching, in descending order, can be sorted as follows:

[0145] Sorting 1: 10, 6, 8, 11, 4, 3, 12, 7, 2, 5, 9, 1.

[0146] In this sequence, each element 'a' in sorting 1 represents the 'a'th column of the parent matrix of the parity check matrix. Furthermore, the column indices in the parent matrix start from 1. For example, for a parent matrix of size 12×24, the column indices range from [1, 24].

[0147] Optionally, in various embodiments of this application, the column indices of the parent matrix may also start from 0, without limitation. Whether the index starts from 0 or from 1, the repetition priority of the columns corresponding to the information bits in the parent matrix is ​​essentially the same.

[0148] In addition, it should be understood that the columns of the mother matrix include two parts, one part corresponding to information bits and the other part corresponding to parity bits. For example, for an LDPC with a code rate R = 1 / 2 and a code length N = 1944, the size of the mother matrix is 12 × 24. The 1st to 12th columns of the 24 columns correspond to information bits, and the 13th to 24th columns correspond to parity bits. Therefore, since this application mainly relates to the sorting of repetition priorities of information bits, the "columns in the mother matrix corresponding to information bits" described in each embodiment refers to all columns excluding the parity section of the mother matrix. For example, for the mother matrix corresponding to an LDPC with a code rate R = 1 / 2 and a code length N = 1944, the "columns corresponding to information bits" refers to the 1st to 12th columns of the mother matrix. The following embodiments are similar and will not be elaborated further.

[0149] If each column of the mother matrix corresponds to z codeword bits of the original parity-check matrix, during the rate matching process, according to the number L of information bits to be repeated, the information bits can be selected to perform the repetition operation according to the following rules.

[0150] In one possible case, if L < z, the transmitting end selects L information bits from the z information bits corresponding to the column with the highest repetition priority in the mother matrix to perform the repetition operation.

[0151] Specifically, since the repetition priorities of the z information bits corresponding to each column in the mother matrix in the original parity-check matrix are the same, the transmitting end can arbitrarily select L information bits from the z information bits corresponding to the column with the highest repetition priority to perform the repetition operation. For example, the transmitting end selects L information bits in the order from back to front, or from front to back, or randomly.

[0152] Taking Table 2 as an example, if the number L of information bits to be repeated is 50 and L < z = 81, the transmitting end can arbitrarily select 50 information bits from the 81 information bits corresponding to the 10th column of the mother matrix in the original matrix.

[0153] In another possible case, if L = m × z, where m is a positive integer, the transmitting end selects the mz information bits corresponding to the m columns with the highest repetition priority in the mother matrix in the original parity-check matrix to perform the repetition operation.

[0154] Since the number of information bits to be repeated is exactly equal to the number of information bits corresponding to m columns in the mother matrix in the original parity-check matrix, the transmitting end selects the m × z information bits corresponding to the m columns with higher repetition priority in the order from the highest to the lowest repetition priority to perform the repetition operation.

[0155] Taking Table 2 as an example, if the number L of information bits to be repeated is 81, L = z, the sender performs a repetition operation on the 81 information bits corresponding to the 10th column of the mother matrix in the original matrix. If the number L of information bits to be repeated is 162, L = 2×z, the sender performs a repetition operation on the 81 information bits corresponding to the 10th column of the mother matrix in the original matrix and the 81 information bits corresponding to the 6th column of the original parity-check matrix. If the number L of information bits to be repeated is 4×z, the sender performs a repetition operation on a total of 4×81 information bits corresponding to the 10th, 6th, 8th, and 11th columns of the mother matrix in the original matrix, and details are not repeated here.

[0156] In another possible case, if (m - 1)×z < L < m×z, L is an integer, m > 1, and m is an integer, the sender selects the (m - 1)×z information bits corresponding to the first (m - 1) columns with higher repetition priority in the original parity-check matrix from the mother matrix, and p information bits from the z information bits corresponding to the mth column in the original parity-check matrix for repetition operation, where L = (m - 1)×z + p, p ≥ 1 and p is an integer.

[0157] Taking Table 2 as an example, for instance, if the number L of information bits to be repeated is 100, z < L < 2×z, that is, 81 < L < 162, the sender selects the 81 information bits corresponding to the 10th column of the mother matrix in the original parity-check matrix and (100 - 81) information bits from the 81 information bits corresponding to the 6th column of the mother matrix in the original parity-check matrix for repetition operation. Among the 81 information bits corresponding to the 6th column of the mother matrix in the original parity-check matrix, 19 information bits can be randomly selected because the repetition priorities of the 81 information bits corresponding to the 6th column of the mother matrix in the original parity-check matrix are the same.

[0158] For another example, if the number L of information bits to be repeated is 170, 2×z < L < 3×z, that is, 2×81 < L < 3×81, the sender selects the 81 information bits corresponding to the 10th column of the mother matrix in the original parity-check matrix, the 81 information bits corresponding to the 6th column of the mother matrix in the original parity-check matrix, and arbitrarily selects (170 - 2×81) information bits from the 81 information bits corresponding to the 8th column of the mother matrix in the original parity-check matrix for repetition operation. Similarly, since the repetition priorities of the z information bits corresponding to each column of the mother matrix in the original parity-check matrix are the same, the sender can arbitrarily select 8 information bits from the 81 information bits corresponding to the 8th column of the mother matrix in the original parity-check matrix.

[0159] Alternatively, in all the above cases, the set of repeated information bits at the transmitting end can be called the first information bit set. In other words, the transmitting end repeats the information bits in the first information bit set of the LDPC codeword according to the required number of repeated bits L. The first information bit set contains L information bits, and the repetition priority of the information bit with the lowest repetition priority among these L information bits is higher than or equal to the repetition priority of the remaining information bits in the entire LDPC codeword excluding the L information bits in the first information bit set.

[0160] Taking Table 2 as an example, if L = 50, then 50 information bits are randomly selected from the 81 information bits corresponding to the 10th column of the parent matrix in the original matrix to form the first information bit set. If L = 81, then the 81 information bits corresponding to the 10th column of the parent matrix in the original matrix form the first information bit set. If L = 162, then the 81 information bits corresponding to the 10th column of the parent matrix in the original matrix, and the 81 information bits corresponding to the 6th column of the parent matrix in the original parity check matrix, form the first information bit set. If L = 170, then any 8 information bits from the 81 information bits corresponding to the 10th column of the parent matrix in the original parity check matrix, the 81 information bits corresponding to the 6th column of the parent matrix in the original parity check matrix, and the 81 information bits corresponding to the 81 information bits in the 8th column of the parent matrix in the original parity check matrix, form the first information bit set.

[0161] Table 3 shows a comparison between the replication scheme based on the confidence criterion provided in this application and the replication scheme of the 802.11ac standard.

[0162] Table 3

[0163]

[0164] As shown in Table 3, taking the number of information bits to be repeated as 2×81, 5×81, 8×81, and 10×81 as examples, Table 3 lists the column indices of the columns corresponding to the information bits with priority for repetition in the parent matrix. For comparison, the repetition priority of 802.11ac is from front to back.

[0165] Furthermore, as can be seen from Table 3, in the technical solution of this application, for LDPC codes of a specific code length, the repetition scheme of low-rate LDPC is compatible with the repetition scheme of high-rate LDPC. In other words, the repetition positions of the information bits in low-rate LDPC include the repetition positions of the information bits in high-rate LDPC.

[0166] For example, when the number of repetitions is 2×81 (i.e., 2 columns of the parent matrix), the repetition positions of the information bits in LDPC correspond to the index set of the columns of the parent matrix as {12,14}.

[0167] With a repetition count of 5×81 (i.e., 5 columns of the parent matrix), the repetition positions of the LDPC information bits correspond to the index set of the columns of the parent matrix as {12,14,15,17,19}, where the index set includes the 12th and 14th columns of the parent matrix.

[0168] When the number of repetitions is 8×81 (i.e., 8 columns of the parent matrix), the repetition positions of the LDPC information bits correspond to the index set of columns in the parent matrix as {12,14,15,17,19,13,20,11}. This index set includes not only the 12th and 14th columns of the parent matrix (i.e., the case of 2-column repetition), but also the 12th, 14th, 15th, 17th, and 19th columns of the parent matrix (i.e., the case of 5-column repetition).

[0169] According to the principle of rate matching, the more information bits are repeated, the higher the code rate of the LDPC code. Therefore, in the repetition scheme of this application, high code rates and low code rates are compatible. That is, by adding new repetition positions to the repetition positions of a low-code-rate LDPC codeword, a higher-code-rate LDPC codeword can be obtained.

[0170] (2) Code rate R = 1 / 2, code length L = 1296.

[0171] The parent matrix (denoted as matrix 2) of the parity-check matrix of an LDPC code with a code rate of 1 / 2 and a code length of 1296 is shown below:

[0172]

[0173] As shown above, matrix 2 has a size of 12×24, and each element in matrix 2 represents a square matrix of order z = 1296 / 24 = 54. Here, "-" indicates a 54×54 matrix of all zeros. Each element i in matrix 2 represents a 54×54 cyclic permutation matrix, where i represents the cyclic shift value. For example, i = 0 represents a 54×54 identity matrix.

[0174] Table 4 shows the repetition priority of the information bits in the LDPC with a code rate of 1 / 2 and a code length of 1296, as given in this application.

[0175] Table 4

[0176] Reliability ranking 8(3) 12(3) 7(3) 3(3) 11(3) 10(3) LLR 39.2121 39.3214 39.7775 39.7809 40.3593 40.5239 Reliability ranking 4(3) 6(3) 2(4) 5(11) 9(11) 1(11) LLR 40.9689 41.0671 52.9074 143.0869 144.3379 144.4487

[0177] In Table 4, a(b) represents the a-th column of the parent matrix, with a column weight of b.

[0178] Since this application only provides the order of repetition priority of information bits, Table 4 shows the order of columns 1 to 12 of matrix 2, because columns 1 to 12 correspond to the information (or system) part of the matrix. The codeword bits corresponding to these columns are all original information bits.

[0179] Since matrix 2 is the parent matrix, each column corresponds to 54 codeword bits of the original parity-check matrix. Each column in the parent matrix corresponds to z information bits of the original parity-check matrix, and the z codeword bits have the same repetition priority. Taking the 8th column, which has the highest repetition priority in Table 4, as an example, the 54 information bits corresponding to the 8th column of the parent matrix have the same repetition priority in the original parity-check matrix.

[0180] As shown in Table 4, the parity check matrix of an LDPC with a code rate of 1 / 2 and a code length of 1296 has the following sorting 2: The repetition priority of the columns corresponding to the information bits in the parent matrix during rate matching is arranged from high to low.

[0181] Sorting 2: 8, 12, 7, 3, 11, 10, 4, 6, 2, 5, 9, 1.

[0182] In this sequence, each element 'a' in sorting 2 represents the 'a'-th column of the parent matrix of the check matrix. Furthermore, the column indices in the parent matrix start from 1.

[0183] (3) Code rate R = 1 / 2, code length L = 648.

[0184] The parent matrix (denoted as matrix 3) of the parity-check matrix of an LDPC code with a code rate of 1 / 2 and a code length of 648 is shown below:

[0185]

[0186] As shown above, matrix 3 has a size of 12×24, and each element in matrix 3 represents a square matrix of order z = 648 / 24 = 27. Here, "-" indicates a 27×27 matrix of all zeros. Each element i in matrix 3 represents a 27×27 cyclic permutation matrix, where i represents the cyclic shift value. For example, i = 0 represents an identity matrix of size 27×27.

[0187] Table 5 shows the repetition priority of the information bits in the LDPC with a code rate of 1 / 2 and a code length of 648, as given in this application.

[0188] Table 5

[0189] Reliability ranking 8(3) 6(3) 12(3) 11(3) 2(3) 3(3) LLR 46.8189 48.0339 49.6489 50.3947 50.6030 50.0061 Reliability ranking 10(3) 7(3) 4(3) 1(12) 5(12) 9(12) LLR 51.5432 52.8294 53.0404 199.0153 199.0153 199.0153

[0190] In Table 5, a(b) represents column a of the parent matrix, with a column weight of b. Additionally, Table 5 shows the order of columns 1 through 12 of matrix 3, as these columns correspond to the information (or system) portion of the matrix. The codeword bits corresponding to these columns are all original information bits.

[0191] Since matrix 3 is the parent matrix, each column corresponds to 27 codeword bits of the original parity-check matrix. Each column in the parent matrix corresponds to z information bits of the original parity-check matrix, and the z codeword bits have the same repetition priority. Taking the 8th column, which has the highest repetition priority in Table 5, as an example, the 27 information bits corresponding to the 8th column of the parent matrix have the same repetition priority in the original parity-check matrix.

[0192] As shown in Table 5, the parity check matrix of an LDPC with a code rate of 1 / 2 and a code length of 648, the columns corresponding to information bits in the parent matrix, in descending order of repetition priority during rate matching, can be sorted as follows:

[0193] Sorting 3: 8, 6, 12, 11, 2, 3, 10, 7, 4, 1, 5, 9.

[0194] In this sequence, each element 'a' in sorting 3 represents the 'a'-th column of the parent matrix of the check matrix. Furthermore, the column indices in the parent matrix start from 1.

[0195] (4) Code rate R = 2 / 3, code length L = 1944. The parent matrix (denoted as matrix 4) of the parity check matrix of LDPC with a code rate of 1 / 2 and a code length of 648 is shown below:

[0196]

[0197] As shown above, matrix 4 has a size of 8×24, and each element in matrix 4 represents a square matrix of order z = 1944 / 24 = 81. Here, "-" indicates an 81×81 matrix of all zeros. Each element i in matrix 4 represents an 81×81 cyclic permutation matrix, where i represents the cyclic shift value. For example, i = 0 represents an 81×81 identity matrix.

[0198] Table 6 shows the repetition priority of the information bits in the LDPC with a code rate of 2 / 3 and a code length of 1944, as given in this application.

[0199] Table 6

[0200]

[0201] In Table 6, a(b) represents the a-th column of the parent matrix, with a column weight of b. As shown in Table 6, information bits with lower confidence levels have higher repetition priority.

[0202] In addition, Table 6 shows the order of columns 1 to 16 of matrix 4, because columns 1 to 16 correspond to the information (or system) part of the matrix. The codeword bits corresponding to these columns are all original information bits.

[0203] Since matrix 4 is the parent matrix, each column corresponds to 81 codeword bits of the original parity-check matrix. Each column in the parent matrix corresponds to z information bits of the original parity-check matrix, and the z codeword bits have the same repetition priority. Taking the 16th column, which has the highest repetition priority in Table 6, as an example, the 81 information bits corresponding to the 16th column of the parent matrix have the same repetition priority in the original parity-check matrix.

[0204] As shown in Table 6, the parity check matrix of an LDPC with a code rate of 2 / 3 and a code length of 1944, the columns corresponding to information bits in the parent matrix, in descending order of repetition priority during rate matching, can be sorted as follows:

[0205] Sorting 4: 16,8,15,12,9,10,14,6,13,11,7,5,1,2,3,4.

[0206] In this sequence, each element 'a' in sorting 4 represents the 'a'-th column of the parent matrix of the check matrix. Furthermore, the column indices in the parent matrix start from 1.

[0207] (5) Code rate R = 2 / 3, code length L = 1296.

[0208] The parent matrix (denoted as matrix 5) of the parity-check matrix of an LDPC code with a code rate of 2 / 3 and a code length of 1296 is shown below:

[0209]

[0210] As shown above, matrix 5 has a size of 8×24, and each element in matrix 5 represents a square matrix of order z = 1296 / 24 = 54. Here, "-" indicates a 54×54 matrix of all zeros. Each element i in matrix 5 represents a 54×54 cyclic permutation matrix, where i represents the cyclic shift value. For example, i = 0 represents an identity matrix of size 54×54.

[0211] Table 7 shows the repetition priority of the information bits in the LDPC with a code rate of 2 / 3 and a code length of 1296, as given in this application.

[0212] Table 7

[0213]

[0214] In Table 7, a(b) represents column a of the parent matrix, with a column weight of b. Table 7 also shows the order of columns 1 to 16 of matrix 5, because columns 1 to 16 correspond to the information (or system) portion of the parity check matrix. The codeword bits corresponding to these columns are all original information bits.

[0215] Since matrix 5 is the parent matrix, each column corresponds to 54 codeword bits of the original parity-check matrix. Each column in the parent matrix corresponds to z information bits of the original parity-check matrix, and these z codeword bits have the same repetition priority. Taking the 16th column in Table 7, which has the highest repetition priority, as an example, it means that the 54 information bits corresponding to the 16th column of the parent matrix have the same repetition priority in the original parity-check matrix.

[0216] As shown in Table 7, the parity check matrix of an LDPC with a code rate of 2 / 3 and a code length of 1296 has the following sorting 5: The repetition priority of the columns corresponding to the information bits in the parent matrix during rate matching is arranged from high to low:

[0217] Sorting 5: 16,9,12,7,10,8,11,14,13,15,6,4,5,1,2,3.

[0218] In this sequence, each element 'a' in sort 5 represents the 'a'-th column of the parent matrix of the check matrix. Furthermore, the column indices in the parent matrix start from 1.

[0219] (6) Code rate R = 2 / 3, code length L = 648.

[0220] The parent matrix (denoted as matrix 6) of the parity-check matrix of an LDPC code with a code rate of 2 / 3 and a code length of 648 is shown below:

[0221]

[0222] As shown above, matrix 6 has a size of 8×24. Each element in matrix 6 represents a square matrix of order z = 648 / 24 = 27. Here, "-" indicates a 27×27 matrix of all zeros. Each element i in matrix 6 represents a 27×27 cyclic permutation matrix, where i represents the cyclic shift value. For example, i = 0 represents an identity matrix of size 27×27.

[0223] Table 8 shows the repetition priority of the information bits in the LDPC with a code rate of 2 / 3 and a code length of 648, as given in this application.

[0224] Table 8

[0225]

[0226] In Table 8, a(b) represents the a-th column of the parent matrix, with a column weight of b.

[0227] Furthermore, each column in the parent matrix corresponds to z information bits of the original parity-check matrix, and these z codeword bits have the same repetition priority. Since matrix 6 gives the parent matrix, each column corresponds to 27 codeword bits of the original parity-check matrix. Taking the 16th column in Table 7, which has the highest repetition priority, as an example, it means that the 27 information bits corresponding to the 16th column of the parent matrix have the same repetition priority in the original parity-check matrix.

[0228] As shown in Table 8, the parity check matrix of an LDPC with a code rate of 2 / 3 and a code length of 648, the columns corresponding to the information bits in the parent matrix, in descending order of repetition priority during rate matching, can be sorted as follows:

[0229] Sorting 6: 16,9,12,7,10,8,11,14,13,15,6,4,5,1,2,3.

[0230] In this sequence, each element 'a' in sorting 6 represents the 'a'-th column of the parent matrix of the parity check matrix. Furthermore, the column indices in the parent matrix start from 1.

[0231] (7) Code rate R = 3 / 4, code length L = 1944.

[0232] The parent matrix (denoted as matrix 7) of the parity-check matrix of an LDPC code with a code rate of 3 / 4 and a code length of 1944 is shown below:

[0233]

[0234] As shown above, matrix 7 has a size of 12×24, and each element in matrix 7 represents a square matrix of order z = 1944 / 24 = 81. Here, "-" indicates an 81×81 matrix of all zeros. Each element i in matrix 7 represents an 81×81 cyclic permutation matrix, where i represents the cyclic shift value. For example, i = 0 represents an 81×81 identity matrix.

[0235] Table 9 shows the repetition priority of the information bits in the LDPC with a code rate of 3 / 4 and a code length of 1944, as given in this application.

[0236] Table 9

[0237]

[0238] In Table 9, a(b) represents the a-th column of the parent matrix, with a column weight of b.

[0239] Additionally, Table 9 shows the order of columns 1 through 18 of matrix 7, because columns 1 through 18 correspond to the information (or system) part of the matrix. The codeword bits corresponding to these columns are all original information bits.

[0240] Each column in the parent matrix corresponds to z information bits of the original parity-check matrix, and these z codeword bits have the same repetition priority. Since matrix 7 gives the parent matrix, each column corresponds to 81 codeword bits of the original parity-check matrix. Taking the 18th column in Table 9, which has the highest repetition priority, as an example, it means that the 81 information bits corresponding to the 18th column of the parent matrix have the same repetition priority in the original parity-check matrix.

[0241] As shown in Table 9, the parity check matrix of an LDPC with a code rate of 3 / 4 and a code length of 1944, the repetition priority of the columns corresponding to the information bits in the parent matrix during rate matching, in descending order, can be sorted as follows:

[0242] Sorting 7: 12, 16, 11, 10, 14, 17, 15, 8, 13, 18, 7, 9, 6, 1, 2, 3, 4, 5, 6.

[0243] In this sequence, each element 'a' in sort 7 represents the 'a'-th column of the parent matrix of the parity check matrix. Furthermore, the column indices in the parent matrix start from 1.

[0244] (8) Code rate R = 3 / 4, code length L = 1296.

[0245] The parent matrix (denoted as matrix 8) of the parity-check matrix of an LDPC code with a code rate of 3 / 4 and a code length of 1296 is shown below:

[0246]

[0247] As shown above, matrix 8 has a size of 12×24. Each element in matrix 8 represents a square matrix of order z = 1296 / 24 = 54. Here, "-" indicates a 54×54 matrix of all zeros. Each element i in matrix 8 represents a 54×54 cyclic permutation matrix, where i represents the cyclic shift value. For example, i = 0 represents a 54×54 identity matrix.

[0248] Table 10 shows the repetition priority of information bits in an LDPC with a code rate of 3 / 4 and a code length of 1296.

[0249] Table 10

[0250]

[0251] In Table 10, a(b) represents the a-th column of the parent matrix, with a column weight of b.

[0252] Additionally, Table 10 shows the order of columns 1 through 18 of matrix 8, because columns 1 through 18 correspond to the information (or system) part of the matrix. The codeword bits corresponding to these columns are all original information bits.

[0253] Each column in the parent matrix corresponds to z information bits of the original parity-check matrix, and the z codeword bits have the same repetition priority. Since matrix 7 gives the parent matrix, each column corresponds to 54 codeword bits of the original parity-check matrix. Taking the 9th column with the highest repetition priority in Table 10 as an example, it means that the 54 information bits corresponding to the 9th column of the parent matrix have the same repetition priority in the original parity-check matrix.

[0254] As shown in Table 10, the parity check matrix of an LDPC with a code rate of 3 / 4 and a code length of 1296 has the following order of repetition priority in rate matching for the columns corresponding to information bits in the parent matrix, from high to low:

[0255] Sorting 8: 9, 11, 13, 15, 17, 8, 10, 12, 14, 16, 18, 1, 2, 3, 4, 5, 6, 7.

[0256] In this sequence, each element 'a' in sort 8 represents the 'a'-th column of the parent matrix of the parity check matrix. Furthermore, the column indices in the parent matrix start from 1.

[0257] (9) Code rate R = 3 / 4, code length L = 648.

[0258] The parent matrix (denoted as matrix 9) of the parity-check matrix of an LDPC code with a code rate of 3 / 4 and a code length of 648 is shown below:

[0259]

[0260] As shown above, matrix 9 has a size of 12×24, and each element in matrix 9 represents a square matrix of order z = 648 / 24 = 27. Here, "-" indicates a 27×27 matrix of all zeros. Each element i in matrix 9 represents a 27×27 cyclic permutation matrix, where i represents the cyclic shift value. For example, i = 0 represents an identity matrix of size 27×27.

[0261] Table 11 shows the repetition priority of the information bits in the LDPC with a code rate of 3 / 4 and a code length of 648, as given in this application.

[0262] Table 11

[0263]

[0264]

[0265] In Table 11, a(b) represents the a-th column of the parent matrix, with a column weight of b.

[0266] Additionally, Table 11 shows the order of columns 1 through 18 of matrix 9, as these columns correspond to the information (or system) portion of the matrix. The codeword bits corresponding to these columns are all original information bits.

[0267] Each column in the parent matrix corresponds to z information bits of the original parity-check matrix, and these z codeword bits have the same repetition priority. Since matrix 9 represents the parent matrix, each column corresponds to 27 codeword bits of the original parity-check matrix. Taking the 18th column in Table 10, which has the highest repetition priority, as an example, it means that the 27 information bits corresponding to the 18th column of the parent matrix have the same repetition priority.

[0268] As shown in Table 11, the parity check matrix of an LDPC with a code rate of 3 / 4 and a code length of 648, the columns corresponding to information bits in the parent matrix, in descending order of repetition priority during rate matching, can be sorted as follows: 9

[0269] Sorting 9: 18, 13, 15, 16, 12, 14, 17, 10, 6, 7, 8, 11, 9, 1, 2, 3, 4, 5.

[0270] In this sequence, each element 'a' in sorting 9 represents the 'a'th column of the parent matrix of the parity check matrix. Furthermore, the column indices in the parent matrix start from 1.

[0271] (10) Code rate R = 5 / 6, code length L = 1944.

[0272] The parent matrix (denoted as matrix 10) of the parity-check matrix for an LDPC code with a code rate of 5 / 6 and a code length of 1944 is shown below:

[0273]

[0274] As shown above, matrix 10 has a size of 8×24, and each element in matrix 10 represents a square matrix of order z = 1944 / 24 = 81. Here, "-" indicates an 81×81 matrix of all zeros. Each element i in matrix 10 represents an 81×81 cyclic permutation matrix, where i represents the cyclic shift value. For example, i = 0 represents an 81×81 identity matrix.

[0275] Table 12 shows the repetition priority of the information bits in the LDPC with a code rate of 5 / 6 and a code length of 1944, as given in this application.

[0276] Table 12

[0277]

[0278] In Table 12, a(b) represents the a-th column of the parent matrix, with a column weight of b.

[0279] Additionally, Table 12 shows the order of columns 1 through 20 of matrix 10, as these columns correspond to the information (or system) portion of the matrix. The codeword bits corresponding to these columns are all original information bits.

[0280] Each column in the parent matrix corresponds to z information bits of the original parity-check matrix, and the z codeword bits have the same repetition priority. Since matrix 10 gives the parent matrix, each column corresponds to 81 codeword bits of the original parity-check matrix. Taking the 12th column with the highest repetition priority in Table 12 as an example, it means that the 81 information bits corresponding to the 12th column of the parent matrix have the same repetition priority in the original parity-check matrix.

[0281] As shown in Table 12, the parity check matrix of an LDPC with a code rate of 5 / 6 and a code length of 1944, the columns corresponding to information bits in the parent matrix, in descending order of repetition priority during rate matching, can be sorted as follows: 10

[0282] Sorting 10: 12, 14, 15, 17, 19, 13, 20, 11, 16, 18, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10.

[0283] In this sequence, each element 'a' in sort 10 represents the 'a'th column of the parent matrix of the parity check matrix. Furthermore, the column indices in the parent matrix start from 1.

[0284] (11) Code rate R = 5 / 6, code length L = 1296.

[0285] The parent matrix (denoted as matrix 11) of the parity-check matrix of an LDPC code with a code rate of 5 / 6 and a code length of 1296 is shown below:

[0286]

[0287] As shown above, matrix 11 has a size of 8×24, and each element in matrix 11 represents a square matrix of order z = 1296 / 24 = 54. Here, "-" indicates a 54×54 matrix of all zeros. Each element i in matrix 11 represents a 54×54 cyclic permutation matrix, where i represents the cyclic shift value. For example, i = 0 represents a 54×54 identity matrix.

[0288] Table 13 shows the repetition priority of the information bits in the LDPC with a code rate of 5 / 6 and a code length of 1296, as given in this application.

[0289] Table 13

[0290]

[0291] In Table 13, a(b) represents the a-th column of the parent matrix, with a column weight of b.

[0292] Additionally, Table 13 shows the order of columns 1 through 20 of matrix 11, because columns 1 through 20 correspond to the information (or system) part of the matrix. The codeword bits corresponding to these columns are all original information bits.

[0293] Each column in the parent matrix corresponds to z information bits of the original parity-check matrix, and the z codeword bits have the same repetition priority. Since matrix 11 gives the parent matrix, each column corresponds to 54 codeword bits of the original parity-check matrix. Taking the 17th column with the highest repetition priority in Table 13 as an example, it means that the 54 information bits corresponding to the 17th column of the parent matrix have the same repetition priority in the original parity-check matrix.

[0294] As shown in Table 13, the parity check matrix of an LDPC with a code rate of 5 / 6 and a code length of 1296 has the following order of repetition priority in rate matching for the columns corresponding to information bits: 11.

[0295] Sorting 11: 17,20,19,17,19,13,20,11,16,18,1,2,3,4,5,6,7,8,9,10.

[0296] In this sequence, each element 'a' in sort 11 represents the 'a'th column of the parent matrix of the parity check matrix. Furthermore, the column indices in the parent matrix start from 1.

[0297] (12) Code rate R = 5 / 6, code length L = 648.

[0298] The parent matrix (denoted as matrix 12) of the parity-check matrix of an LDPC code with a code rate of 5 / 6 and a code length of 648 is shown below:

[0299]

[0300] As shown above, matrix 12 has a size of 8×24, and each element in matrix 12 represents a square matrix of order z = 648 / 24 = 27. Here, "-" indicates a 27×27 matrix of all zeros. Each element i in matrix 12 represents a 27×27 cyclic permutation matrix, where i represents the cyclic shift value. For example, i = 0 represents an identity matrix of size 27×27.

[0301] Table 14 shows the repetition priority of information bits in an LDPC with a code rate of 5 / 6 and a code length of 648, as given in this application.

[0302] Table 14

[0303]

[0304] In Table 14, a(b) represents the a-th column of the parent matrix, with a column weight of b.

[0305] Additionally, Table 14 shows the order of columns 1 through 20 of matrix 12, as these columns correspond to the information (or system) portion of the matrix. The codeword bits corresponding to these columns are all original information bits.

[0306] Each column in the parent matrix corresponds to z information bits of the original parity-check matrix, and the z codeword bits have the same repetition priority. Since matrix 12 gives the parent matrix, each column corresponds to 27 codeword bits of the original parity-check matrix. Taking the 13th column with the highest repetition priority in Table 14 as an example, it means that the 27 information bits corresponding to the 13th column of the parent matrix have the same repetition priority in the original parity-check matrix.

[0307] As shown in Table 14, the parity check matrix of an LDPC with a code rate of 5 / 6 and a code length of 648 has the following sorting 12: The repetition priority of the columns corresponding to the information bits in the parent matrix during rate matching is arranged from high to low.

[0308] Sorting 12: 13,1,2,3,4,5,6,7,8,9,10,11,12,14,15,16,17,18,19,20.

[0309] In this sequence, each element 'a' in sort 12 represents the 'a'-th column of the parent matrix of the parity check matrix. Furthermore, the column indices in the parent matrix start from 1.

[0310] The above describes the repetition priority order of information bits under the three code lengths and four code rates provided in this application. The following example illustrates the application of this repetition priority in IR-HARQ.

[0311] See Figure 7 , Figure 7 An example of the application of the replication scheme provided in this application in IR-HARQ.

[0312] 510. The transmitting end generates an LDPC codeword suitable for channel transmission, for example, the codeword has a code rate of 1 / 2.

[0313] 520. The sending end sends the LDPC codeword.

[0314] This transmission will be defined as the initial transmission.

[0315] If the receiving end can correctly decode all the information bits (i.e., system bits), the transmission of this data packet ends. If the receiving end cannot decode correctly, it requests the sending end to retransmit. The retransmission process can proceed as described in step 530 and subsequent steps.

[0316] 530. Sorting the repetition priority of information bits acquired by the sending end.

[0317] 540. Based on the repetition priority, the sending end retransmits the t1 information bits with the highest repetition priority.

[0318] The receiving end receives the t1 information bits retransmitted by the sending end, combines the t1 information bits with the corresponding information bits of the previously received sequence, and then decodes them. If the receiving end still cannot decode correctly, and the preset maximum number of retransmissions has not been reached, the receiving end continues to request the sending end to retransmit.

[0319] 550. Based on the repetition priority, the sending end retransmits the t2 information bits with the second highest repetition priority.

[0320] The receiving end receives the t2 information bits retransmitted by the sending end, combines the t2 information bits with the previously received t1 information bits and the corresponding information bits of the sequence received in the initial transmission, and then decodes them.

[0321] This process continues until the sending end has retransmitted all the information bits. If the receiving end still cannot correctly recover the information bits, it indicates that the transmission of the data packet has failed and the transmission ends, proceeding to the transmission of the next data packet.

[0322] In the above transmission process, the code rate of the l-th transmission can satisfy the following equation (3):

[0323]

[0324] In equation (3), R c The code rate of the LDPC codeword transmitted by the transmitter for the first time (e.g., 1 / 2 as listed in step 510 above), k represents the number of system bits, and n represents the length of the LDPC master codeword. The redundancy added in the first transmission is t0 = 0.

[0325] Furthermore, the information bit repetition scheme provided in this application can be used in conjunction with the parity bit puncturing scheme, as described below. Figure 8 For example.

[0326] See Figure 8 , Figure 8 An example of the application of the combination of the information bit repetition scheme and the parity bit punching scheme provided in this application in IR-HARQ.

[0327] 611. The transmitting end generates a raw LDPC codeword suitable for channel transmission, for example, the code rate of the raw LDPC codeword is 1 / 2.

[0328] Assume that the code length of the LDPC mother code is N, the number of information bits is K, and the number of parity bits is (NK), where N and K are both positive integers.

[0329] 612. The sending end obtains the sorting of the repetition priority of K information bits and the sorting of the puncturing priority of the (NK) check bits.

[0330] It should be understood that the higher the repetition priority of an information bit, the higher its reliability, and therefore, the higher its retransmission priority. Conversely, the higher the puncturing priority of a parity bit, the lower its reliability, and the higher its priority during rate matching, but the lower its retransmission priority.

[0331] 613. The transmitting end punctures the original LDPC codeword based on the puncturing priority of the (NK) parity bits (assuming only the parity bits are punctured) to obtain the LDPC codeword with the expected target code rate for the initial transmission (hereinafter referred to as the first LDPC codeword). For example, by puncturing the original LDPC codeword, the code rate of the first LDPC codeword obtained is 5 / 6.

[0332] 614. Send the first LDPC codeword.

[0333] If the receiving end can correctly decode all the information bits, the transmission of this data packet ends. If the receiving end cannot decode correctly, it requests the sending end to retransmit. The retransmission process can proceed as described in step 615 and subsequent steps.

[0334] 615. The sending end prioritizes sending the t1 punctured parity bits with the highest reliability.

[0335] The t1 punched check bits with the highest reliability are the first t1 check bits sorted from low to high punching priority.

[0336] In this embodiment, the punched parity bit refers to the parity bit that is punched during the rate matching process of the initial transmission.

[0337] The receiving end receives the t1 puncture check bits, merges the t1 puncture check bits with the sequence received in the initial transmission into a single sequence, and then decodes it.

[0338] If the receiver still cannot decode correctly, it will continue to request the sender to retransmit before the preset maximum number of retransmissions is reached.

[0339] 616. The sending end then sends t2 punched check bits with the second highest reliability.

[0340] The t2 punch check bits with the highest reliability are, that is, the first t2 punch check bits that are ranked first among all punch check bits except for the t1 punch check bits, in order of punch priority from low to high.

[0341] The receiving end receives the t2 puncture check bits, combines the t2 puncture check bits with the sequence received in the initial transmission and the t1 puncture check bits into a single sequence, and then decodes it.

[0342] This process continues until the sending end has sent all the puncture check bits. If the receiving end still cannot decode correctly, the sending end will then consider sending information bits.

[0343] 617. The sending end sends the s1 information bits with the highest repetition priority.

[0344] The receiving end receives the s1 information bits and merges them with the previous decoding sequence, then re-decodes the merged sequence. If the receiving end still cannot decode correctly, it continues to request the sending end to retransmit before reaching the preset maximum number of retransmissions.

[0345] 618. The sending end sends s2 information bits with the second highest repetition priority.

[0346] The receiving end receives the s2 information bits and combines them with the previous decoding sequence, then decodes the combined sequence again. This process is repeated until the sending end has retransmitted all the information bits. If the receiving end still cannot correctly decode the information bits at this point, it indicates that the transmission of this data packet has failed and the transmission ends, proceeding to the transmission of the next data packet.

[0347] exist Figure 8 In the example, the sending end sends the first LDPC codeword. If the receiving end fails to decode, the sending end first sends the punctured parity bits according to the puncturing priority of the parity bits until all the parity bits are sent. If the receiving end still fails to decode, the sending end then retransmits the information bits in the first LDPC codeword according to the repetition priority of the information bits.

[0348] In another example, if the receiver fails to decode the first LDPC codeword sent by the sender, the sender can first retransmit the information bits in the first LDPC codeword according to the repetition priority of the information bits until all information bits have been retransmitted. If the receiver still fails to decode successfully, the sender then retransmits the punctured parity bits according to the puncturing priority of the parity bits.

[0349] In other words, the embodiments of this application do not limit the order in which the puncturing scheme and the repetition scheme are combined. That is, if the LDCP codeword sent by the transmitter is not successfully decoded by the receiver, the transmitter can execute the repetition scheme first and then the puncturing scheme, or it can execute the repetition scheme first and then the puncturing scheme.

[0350] In the above transmission process, the code rate of the l-th transmission can satisfy the following equation (4):

[0351]

[0352] In equation (4), R c =k / n, n represents the length of the LDPC mother codeword.

[0353] Compared to rate-compatible puncture latitude HARQ (RCPL-HARQ) and rate-compatible repeat latitude HARQ (RCRL-HARQ), rate-compatible latitude HARQ (RCL-HARQ) can achieve more flexible bitrates.

[0354] The above combination Figures 1-8 This application provides a detailed description of the LDPC repetition scheme and the combination of the repetition scheme and the drilling scheme. The simulation results of BER and FER of the LDPC repetition scheme provided in this application are compared with those of the traditional repetition scheme below.

[0355] Figures 9-19 The FER curves and throughput curves of the system under various IR-HARQ transmission strategies are shown.

[0356] in, Figures 9-19 The simulation parameters are set as follows: AWGAN channel; BPSK modulation; log-SPA decoding, with a maximum number of iterations of decoding of 10; a stop-and-wait retransmission request strategy is adopted; the maximum number of transmissions to recover each frame of data is 4.

[0357] in addition, Figures 9-19 The performance evaluation parameters considered are mainly frame error rate (FER) and throughput. Throughput is calculated as (number of correctly received frames × k) / total number of bits transmitted, where k is the number of information bits in each frame. Furthermore, E in each figure... s / N0 represents the symbol signal-to-noise ratio.

[0358] The LDPC code in the traditional method is the QC-LDPC code with a code length of 1944 or 972 in the 802.11ac standard.

[0359] Specifically, Figure 9 Comparison of BER performance between the repetition scheme of this application and the traditional repetition scheme under different numbers of information bit repetitions, when the code length N = 1944 and the code rate R = 1 / 2.

[0360] Figure 10 Comparison of BER performance between the repetition scheme of this application and the traditional repetition scheme under different numbers of information bit repetitions, when the mother code length N = 1944 and the code rate R = 5 / 6.

[0361] Figure 11 Comparison of BER performance between the repetition scheme of this application and the traditional repetition scheme under different numbers of information bit repetitions, when the mother code length N = 1920 and the code rate R = 1 / 2.

[0362] Figure 12 Comparison of BER performance between the repetition scheme of this application and the traditional repetition scheme under different numbers of information bit repetitions, when the mother code length N = 1920 and the code rate R = 5 / 6.

[0363] Figure 13 Comparison of BER performance between the repetition scheme of this application and the traditional repetition scheme under different numbers of information bit repetitions, when the mother code length N = 648 and the code rate R = 1 / 2.

[0364] Figure 14 Comparison of BER performance between the repetition scheme of this application and the traditional repetition scheme under different numbers of information bit repetitions, when the mother code length N = 648 and the code rate R = 5 / 6.

[0365] Figure 15 Simulation results of QC-LDPC with a code rate of 5 / 6 (1944,1620) for IR-HARQ technology.

[0366] Figure 16 Simulation results of QC-LDPC with a code rate of 5 / 6 (1944,1620) for IR-HARQ technology.

[0367] Figure 17 Simulation results of QC-LDPC with a code rate of 1 / 2 (1944,972) for IR-HARQ technology.

[0368] Figure 18 Simulation results of QC-LDPC with a code rate of 1 / 2 (1944,972) for IR-HARQ technology.

[0369] Figure 19 The simulation results of QC-LDPC with a code rate of 1 / 2 (1944,972) for IR-HARQ technology are shown in Figure 5.

[0370] in, Figures 9-14 In the text, the curve corresponding to "the reliability based repetition" represents the performance curve of the repetition scheme of this application, while "the standard based puncturing" represents the performance curve of the traditional repetition scheme. The number in parentheses after "repetition" indicates the number of repetitions of information bits, in columns. For example, repetition(2) indicates a repetition of 2 columns, and repetition(5) indicates a repetition of 5 columns.

[0371] in, Figures 9-19 In the illustrations, "proposed scheme" refers to the scheme proposed in this application, and "standard scheme" refers to the standard (i.e., the 802.11ac standard mentioned above), which is the traditional scheme.

[0372] from Figures 15-19 It can be seen that the same E s Under / N0 conditions, the repetition scheme of this application has a lower FER and higher throughput, indicating that the repetition scheme of this application is superior to the traditional repetition scheme.

[0373] The communication device provided in this application is described below.

[0374] See Figure 20 , Figure 20 A schematic block diagram of the communication device 1000 provided in this application. Figure 20 The communication device 1000 includes a processing unit 1100 and a transceiver unit 1200.

[0375] Alternatively, the transceiver unit 1200 can be replaced by a transmitting unit or a receiving unit. For example, when performing the transmitting action, the transceiver unit 1200 can be replaced by a transmitting unit. When performing the receiving action, the transceiver unit 1200 can be replaced by a receiving unit.

[0376] Processing unit 1100 is used to perform rate matching on the first LDPC codeword of the first code rate according to the order of the repetition priority of the K information bits of the LDPC mother code in the rate matching process, to obtain the second LDPC codeword of the second code rate, where K is the number of information bits contained in the LDPC mother code and K is a positive integer.

[0377] The transceiver unit 1200 is used to transmit the second LDPC codeword.

[0378] Optionally, in one embodiment, the processing unit 1100 is further configured to:

[0379] Based on the required number of repeated bits L and the sorting of the repetition priorities of the K information bits during the rate matching process, the information bits in the first information bit set of the first LDPC codeword are repeated in descending order of repetition priority. The repetition priority of the information bit with the lowest repetition priority in the first information bit set is higher than or equal to the repetition priority of the remaining information bits in the first LDPC codeword excluding the information bits in the first information bit set, where L≤K and L is an integer.

[0380] Optionally, in one embodiment, the repetition priority of the K information bits is ordered as follows:

[0381] The parity-check matrix of an LDPC with K information bits, N mother code length, and R code rate is sorted by the repetition priority of the columns corresponding to the information bits in the parent matrix. Each column in the parent matrix corresponds to z codeword bits of the LDPC, where z = N / n, and n is the total number of columns in the parent matrix. The parity-check matrix of the LDPC is obtained by extending the parent matrix. Each element i in the parent matrix represents a z×z cyclic shift matrix, where i represents the cyclic shift value, i ≥ 0, and i is an integer. N ≥ K, where N is an integer, and R = K / N.

[0382] Optionally, in one embodiment, the mother code length is 1944, the code rate is 1 / 2, and the repetition priority of the columns corresponding to the information bits in the mother matrix is ​​ordered as follows, according to the repetition priority from high to low:

[0383] 10,6,8,11,4,3,12,7,2,5,9,1,

[0384] In this arrangement, each element 'a' in the sorting represents the 'a'th column of the parent matrix.

[0385] Optionally, in one embodiment, the mother code length is 1296, the code rate is 1 / 2, and the repetition priority of the columns corresponding to the information bits in the mother matrix is ​​ordered as follows, according to the repetition priority from high to low:

[0386] 8,12,7,3,11,10,4,6,2,5,9,1,

[0387] In this arrangement, each element 'a' in the sorting represents the 'a'th column of the parent matrix.

[0388] Optionally, in one embodiment, the mother code length is 648, the code rate is 1 / 2, and the repetition priority of the columns corresponding to the information bits in the mother matrix is ​​ordered as follows, according to the repetition priority from high to low:

[0389] 8,6,12,11,2,3,10,7,4,1,5,9,

[0390] In this arrangement, each element 'a' in the sorting represents the 'a'th column of the parent matrix.

[0391] Optionally, in one embodiment, the mother code length is 1944, the code rate is 2 / 3, and the repetition priority of the columns corresponding to the information bits in the mother matrix is ​​ordered as follows, according to the repetition priority from high to low:

[0392] 16,8,15,12,9,10,14,6,13,11,7,5,1,2,3,4,

[0393] In this arrangement, each element 'a' in the sorting represents the 'a'th column of the parent matrix.

[0394] Optionally, in one embodiment, the mother code length is 1296, the code rate is 2 / 3, and the repetition priority of the columns corresponding to the information bits in the mother matrix is ​​ordered as follows, according to the repetition priority from high to low:

[0395] 16,9,12,7,10,8,11,14,13,15,6,4,5,1,2,3,

[0396] In this arrangement, each element 'a' in the sorting represents the 'a'th column of the parent matrix.

[0397] Optionally, in one embodiment, the mother code length is 648, the code rate is 2 / 3, and the repetition priority of the columns corresponding to the information bits in the mother matrix is ​​ordered as follows, according to the repetition priority from high to low:

[0398] 16,9,12,7,10,8,11,14,13,15,6,4,5,1,2,3,

[0399] In this arrangement, each element 'a' in the sorting represents the 'a'th column of the parent matrix.

[0400] Optionally, in one embodiment, the mother code length is 1944, the code rate is 3 / 4, and the repetition priority of the columns corresponding to the information bits in the mother matrix is ​​ordered as follows, according to the repetition priority from high to low:

[0401] 12,16,11,10,14,17,15,8,13,18,7,9,1,2,3,4,5,6,

[0402] In this arrangement, each element 'a' in the sorting represents the 'a'th column of the parent matrix.

[0403] Optionally, in one embodiment, the mother code length is 1296, the code rate is 3 / 4, and the repetition priority of the columns corresponding to the information bits in the mother matrix is ​​ordered as follows, according to the repetition priority from high to low:

[0404] 9,11,13,15,17,8,10,12,14,16,18,1,2,3,4,5,6,7,

[0405] In this arrangement, each element 'a' in the sorting represents the 'a'th column of the parent matrix.

[0406] Optionally, in one embodiment, the mother code length is 648, the code rate is 3 / 4, and the repetition priority of the columns corresponding to the information bits in the mother matrix is ​​ordered as follows, according to the repetition priority from high to low:

[0407] 18,13,15,16,12,14,17,10,6,7,8,11,9,1,2,3,4,5,

[0408] In this arrangement, each element 'a' in the sorting represents the 'a'th column of the parent matrix.

[0409] Optionally, in one embodiment, the mother code length is 1944, the code rate is 5 / 6, and the repetition priority of the columns corresponding to the information bits in the mother matrix is ​​ordered as follows, according to the repetition priority from high to low:

[0410] 12,14,15,17,19,13,20,11,16,18,1,2,3,4,5,6,7,8,9,10,

[0411] In this arrangement, each element 'a' in the sorting represents the 'a'th column of the parent matrix.

[0412] Optionally, in one embodiment, the mother code length is 1296, the code rate is 5 / 6, and the repetition priority of the columns corresponding to the information bits in the mother matrix is ​​ordered as follows, according to the repetition priority from high to low:

[0413] 17, 20, 19, 18, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16,

[0414] Among them, each element a in the sorting represents the a-th column of the mother matrix.

[0415] Optionally, in one embodiment, the length of the mother code is 648, the code rate is 5 / 6, and in the order from the highest to the lowest repetition priority, the sorting of the repetition priorities of the columns corresponding to the information bits in the mother matrix is as follows:

[0416] 13, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 14, 15, 16, 17, 18, 19, 20,

[0417] Among them, each element a in the sorting represents the a-th column of the mother matrix.

[0418] Optionally, in one embodiment, the processing unit 1100 is specifically configured to:

[0419] If L < z, select L information bits from the z information bits corresponding to the column with the highest repetition priority in the mother matrix in the parity-check matrix for repetition;

[0420] If L = m × z, the sending end selects the first m columns with the higher repetition priorities in the mother matrix in the order from the highest to the lowest repetition priority, and repeats the mz information bits corresponding to them in the parity-check matrix, where m is a positive integer;

[0421] If (m - 1) × z < L < m × z, in the sorting order from the highest to the lowest repetition priority, select the first (m - 1) columns with the higher repetition priorities in the mother matrix, and repeat the (m - 1) × z information bits corresponding to them in the parity-check matrix, and p information bits from the z information bits corresponding to the m-th column in the parity-check matrix, where L = (m - 1) × z + p, p ≥ 1 and p is an integer, m > 1, and m is an integer.

[0422] Optionally, in one embodiment, the transceiver unit 1200 is further configured to send the first LDPC codeword;

[0423] Moreover, the processing unit 1100 is configured to determine that the first LDPC codeword has not been successfully decoded by the receiving end;

[0424] The transceiver unit 1200 is specifically configured to, according to the number of bits L to be repeated and the sorting of the repetition priorities of the K information bits, repeat and send the L information bits included in the first information bit set in the first LDPC codeword in the order from the highest to the lowest repetition priority;

[0425] Furthermore, the processing unit 1100 is also configured to determine that all information bits contained in the first LDPC codeword have been repeatedly transmitted and the receiving end has still failed to decode it.

[0426] Furthermore, the transceiver unit 1200 is also configured to send the parity bits that have been punctured in the first LDPC codeword according to the puncturing priority of the parity bits, wherein the parity bits with lower puncturing priority are sent first. The puncturing priority is used to indicate the priority of puncturing (NK) parity bits in rate matching, where N is the length of the LDPC mother code, N≥K, and N is an integer.

[0427] Optionally, in one embodiment, the transceiver unit 1200 is further configured to transmit the first LDPC codeword;

[0428] The processing unit 1100 is further configured to determine that the first LDPC codeword was not successfully decoded by the receiving end;

[0429] The transmitting unit 1200 is further configured to transmit the parity bits that have been punctured in the first LDPC codeword according to the priority of the parity bits, wherein the parity bits with lower puncturing priority are transmitted first. The puncturing priority is used to indicate the priority of puncturing (NK) parity bits in rate matching, where N is the length of the LDPC mother code, N≥K, and N is an integer.

[0430] Furthermore, the processing unit 1100 is also configured to determine that all the punctured check bits of the first LDPC codeword have been sent, and the receiving end has still not successfully decoded it.

[0431] The transceiver unit 1200 is further configured to transmit the information bits of the first LDPC codeword according to the repetition priority of the K information bits.

[0432] Optionally, the communication device 1000 can be a transmitting end, or the communication device 1000 can be a device, module, etc., internal to the transmitting end that implements the functions of each method embodiment.

[0433] In one implementation, the communication device 1000 is the transmitting end in the above-described method embodiments, and the communication device 1000 may have any of the functions of the transmitting end in each method embodiment. In this case, the processing unit 1100 may be a processor. The transceiver unit 1200 may be a transceiver. The transceiver may specifically include a receiver and a transmitter. The receiver is used to perform the function of receiving, and the transmitter is used to perform the function of transmitting.

[0434] Alternatively, in another implementation, the communication device 1000 can be a circuit system in the transmitting end. In this case, the processing unit 1100 can be a chip, logic circuit, integrated circuit, processing circuit, or system-on-chip (SoC) chip, etc., and the transceiver unit 1200 can be a communication interface, which can be an interface circuit, input / output interface, pins on the chip for transmitting signals, etc.

[0435] In one embodiment, the communication device 1000 can be an encoder in the transmitting end.

[0436] In the above embodiments, the function of the processing unit 1100 can be implemented by hardware or by hardware executing corresponding software.

[0437] For example, processing unit 1100 may include one or more processors for reading and executing computer programs or instructions stored in memory, such that operations and / or processes performed by the sending end in various method embodiments are executed. The memory is located outside of the one or more processors.

[0438] Furthermore, the processing unit 1100 may also include one or more memories, the one or more processors and the one or more memories are connected by circuits / wires, the one or more processors can read computer programs or instructions stored in the one or more memories, so that the operations and / or processes performed by the sending end in the various method embodiments of this application are executed.

[0439] For example, the processing unit 1100 is a processor, and the transceiver unit 1200 can be an interface circuit. The interface circuit receives computer code or instructions and transmits them to the processor, which executes the computer code or instructions, causing the operations and / or processes performed by the sending end in the various method embodiments of this application to be executed.

[0440] Optionally, the processing unit 1100 may also be a processing circuit or a logic circuit, etc.

[0441] In addition, this application also provides a computer-readable storage medium storing computer instructions that, when executed on a computer, enable the LDPC rate matching method provided in this application to be implemented.

[0442] This application also provides a computer program product, which includes computer code or instructions, wherein when the computer code or instructions are run on a computer, the LDPC rate matching method of the various method embodiments of this application is implemented.

[0443] This application also provides a communication device, including a processor and an interface circuit, wherein the interface circuit is used to receive computer code or instructions and transmit them to the processor, and the processor is used to execute the computer code or instructions, so that the LDPC rate matching method provided in this application is implemented.

[0444] This application also provides a chip including one or more processors. The one or more processors are configured to execute a computer program stored in a memory to perform operations and / or processes performed by a transmitting device in any of the method embodiments. The memory is located independently of the chip.

[0445] Furthermore, the chip may also include one or more communication interfaces. These communication interfaces may be input / output interfaces, interface circuits, etc. Furthermore, the chip may also include one or more of the aforementioned memories.

[0446] This application also provides a wireless communication system, including the transmitting end in the embodiments of this application.

[0447] Optionally, the sending end can be a network device (e.g., a base station) or a terminal device, without limitation.

[0448] The processor in this application embodiment can be an integrated circuit chip with the ability to process signals. In implementation, each step of the above method embodiment can be completed by integrated logic circuits in the processor's hardware or by instructions in software form. The processor can be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. A general-purpose processor can be a microprocessor or any conventional processor. The steps of the method disclosed in this application embodiment can be directly implemented by a hardware encoding processor, or by a combination of hardware and software modules in the encoding processor. The software modules can reside in random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, or other mature storage media in the art. This storage medium is located in memory; the processor reads information from the memory and, in conjunction with its hardware, completes the steps of the above method.

[0449] The memory in this application embodiment can be volatile memory or non-volatile memory, or it can include both volatile and non-volatile memory. The non-volatile memory can be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. The volatile memory can be random access memory (RAM), which is used as an external cache. By way of example, but not limitation, many forms of RAM are available, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous linked dynamic random access memory (SLDRAM), and direct rambus RAM (DRRAM). It should be noted that the memory used in the systems and methods described herein is intended to include, but is not limited to, these and any other suitable types of memory.

[0450] As used in this specification, the terms "unit," "system," etc., are used to refer to computer-related entities, hardware, firmware, combinations of hardware and software, software, or software in execution. For example, a component can be, but is not limited to, a process running on a processor, a processor, an object, an executable file, an execution thread, a program, and / or a computer. As illustrated, applications running on computing devices and computing devices can both be components. One or more components may reside in a process and / or an execution thread. Components may reside on a single computer and / or be distributed among two or more computers. Furthermore, these components may execute from various computer-readable media on which various data structures are stored. Components may communicate via local and / or remote processes based on signals having one or more data packets (e.g., data from two components interacting with another component between a local system, a distributed system, and / or a network, such as the Internet, which interacts with other systems via signals).

[0451] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0452] Those skilled in the art will understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0453] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0454] The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected to achieve the purpose of this embodiment according to actual needs.

[0455] In addition, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0456] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory, random access memory, magnetic disks, or optical disks.

[0457] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A method for rate matching in LDPC, characterized in that, include: The transmitting end performs rate matching on the first LDPC codeword of the first code rate according to the repetition priority of the K information bits of the low-density parity-check code (LDPC) mother code in rate matching to obtain the second LDPC codeword of the second code rate. The repetition priority is determined based on the sensitivity of bit position, and K is a positive integer. The transmitting end sends the second LDPC codeword; The transmitting end performs rate matching on the first LDPC codeword of the first code rate according to the repetition priority of the K information bits in rate matching, including: The transmitting end, based on the required number of repeated bits L and the order of the repetition priority of the K information bits in rate matching, repeatedly transmits the L information bits contained in the first information bit set of the first LDPC codeword in descending order of repetition priority. Wherein, the repetition priority of the information bit with the lowest repetition priority among the L information bits included in the first information bit set is higher than or equal to the repetition priority of the remaining information bits in the first LDPC codeword excluding the L information bits in the first information bit set, L≤K, and L is an integer.

2. The method according to claim 1, characterized in that, The repetition priority of the K information bits is ordered as follows: The parity-check matrix of an LDPC with K information bits, N mother code length, and R code rate is sorted by the repetition priority of the columns corresponding to the information bits in the parent matrix. Each column in the parent matrix corresponds to z codeword bits of the LDPC, where z = N / n, and n is the total number of columns in the parent matrix. The parity-check matrix of the LDPC is obtained by extending the parent matrix. Each element i in the parent matrix represents a z×z cyclic shift matrix, where i represents the cyclic shift value, i ≥ 0, and i is an integer. N ≥ K, where N is an integer, and R = K / N.

3. The method according to claim 2, characterized in that, The mother code has a length of 1944 and a code rate of 1 / 2. The repetition priority of the columns corresponding to the information bits in the mother matrix is ​​ordered from highest to lowest as follows: 10,6,8,11,4,3,12,7,2,5,9,1, In this arrangement, each element 'a' in the sorting represents the 'a'th column of the parent matrix.

4. The method according to claim 2, characterized in that, The mother code has a length of 1296 and a code rate of 1 / 2. The repetition priority of the columns corresponding to the information bits in the mother matrix is ​​ordered from highest to lowest as follows: 8,12,7,3,11,10,4,6,2,5,9,1, In this arrangement, each element 'a' in the sorting represents the 'a'th column of the parent matrix.

5. The method according to claim 2, characterized in that, The mother code has a length of 648 and a code rate of 1 / 2. The repetition priority of the columns corresponding to the information bits in the mother matrix is ​​ordered from highest to lowest as follows: 8,6,12,11,2,3,10,7,4,1,5,9, In this arrangement, each element 'a' in the sorting represents the 'a'th column of the parent matrix.

6. The method according to claim 2, characterized in that, The mother code has a length of 1944 and a code rate of 2 / 3. The repetition priority of the columns corresponding to the information bits in the mother matrix is ​​ordered from highest to lowest as follows: 16,8,15,12,9,10,14,6,13,11,7,5,1,2,3,4, In this arrangement, each element 'a' in the sorting represents the 'a'th column of the parent matrix.

7. The method according to claim 2, characterized in that, The length of the mother code is 1296, and the code rate is 2 / 3. According to the order of decreasing repetition priority, the sorting of the repetition priorities of the columns corresponding to the information bits in the mother matrix is as follows: 16,9,12,7,10,8,11,14,13,15,6,4,5,1,2,3, Among them, each element a in the sorting represents the a-th column of the mother matrix.

8. The method according to claim 2, characterized in that, The length of the mother code is 648, and the code rate is 2 / 3. According to the order of decreasing repetition priority, the sorting of the repetition priorities of the columns corresponding to the information bits in the mother matrix is as follows: 16,9,12,7,10,8,11,14,13,15,6,4,5,1,2,3, Among them, each element a in the sorting represents the a-th column of the mother matrix.

9. The method according to claim 2, characterized in that, The length of the mother code is 1944, and the code rate is 3 / 4. According to the order of decreasing repetition priority, the sorting of the repetition priorities of the columns corresponding to the information bits in the mother matrix is as follows: 12,16,11,10,14,17,15,8,13,18,7,9,1,2,3,4,5,6, Among them, each element a in the sorting represents the a-th column of the mother matrix.

10. The method according to claim 2, characterized in that, The length of the mother code is 1296, and the code rate is 3 / 4. According to the order of decreasing repetition priority, the sorting of the repetition priorities of the columns corresponding to the information bits in the mother matrix is as follows: 9,11,13,15,17,8,10,12,14,16,18,1,2,3,4,5,6,7, Among them, each element a in the sorting represents the a-th column of the mother matrix.

11. The method according to claim 2, characterized in that, The length of the mother code is 648, and the code rate is 3 / 4. According to the order of decreasing repetition priority, the sorting of the repetition priorities of the columns corresponding to the information bits in the mother matrix is as follows: 18,13,15,16,12,14,17,10,6,7,8,11,9,1,2,3,4,5, Among them, each element a in the sorting represents the a-th column of the mother matrix.

12. The method according to claim 2, characterized in that, The length of the mother code is 1944, and the code rate is 5 / 6. According to the order of decreasing repetition priority, the sorting of the repetition priorities of the columns corresponding to the information bits in the mother matrix is as follows: 12,14,15,17,19,13,20,11,16,18,1,2,3,4,5,6,7,8,9,10, Among them, each element a in the sorting represents the a-th column of the mother matrix.

13. The method according to claim 2, characterized in that, The length of the mother code is 1296, and the code rate is 5 / 6. According to the order of decreasing repetition priority, the sorting of the repetition priorities of the columns corresponding to the information bits in the mother matrix is as follows: 17,20,19,18,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16, Among them, each element a in the sorting represents the a-th column of the mother matrix.

14. The method according to claim 2, characterized in that, The length of the mother code is 648, and the code rate is 5 / 6. According to the order of decreasing repetition priority, the sorting of the repetition priorities of the columns corresponding to the information bits in the mother matrix is as follows: 13,1,2,3,4,5,6,7,8,9,10,11,12,14,15,16,17,18,19,20, Among them, each element a in the sorting represents the a-th column of the mother matrix.

15. The method according to any one of claims 2-14, characterized in that, The sender repeats the information bits with the top L repetition priorities in the first LDPC codeword according to the number L of bits to be repeated and the sorting of the repetition priorities of the K information bits, in the order of decreasing repetition priority, including: If L < z, the sender selects L information bits from the z information bits corresponding to the column with the highest repetition priority in the mother matrix in the parity-check matrix for repetition; If L = m × z, the sender repeats the mz information bits corresponding to the first m columns with higher repetition priorities selected from the mother matrix in the order of decreasing repetition priority, where m is a positive integer; If (m - 1)×z < L < m×z, the transmitting end selects, in the order of decreasing repetition priority, the (m - 1)×z information bits corresponding to the first (m - 1) columns with higher repetition priority in the mother matrix and p information bits out of the z information bits corresponding to the m-th column in the parity-check matrix for repetition, where L = (m - 1)×z + p, p ≥ 1 and p is an integer, m > 1 and m is an integer.

16. The method according to any one of claims 2-14, characterized in that, Before the transmitting end repeats the L information bits included in the first information bit set in the first LDPC codeword in the order of decreasing repetition priority according to the number of bits L to be repeated and the order of repetition priorities of the K information bits, the method further includes: The transmitting end transmits the first LDPC codeword; Moreover, the transmitting end repeats the L information bits included in the first information bit set in the first LDPC codeword in the order of decreasing repetition priority according to the number of bits L to be repeated and the order of repetition priorities of the K information bits, including: In the case where the first LDPC codeword is not successfully decoded by the receiving end, the transmitting end repeats the L information bits included in the first information bit set in the first LDPC codeword in the order of decreasing repetition priority according to the number of bits L to be repeated and the order of repetition priorities of the K information bits; Moreover, the method further includes: In the case where all the information bits included in the first LDPC codeword have been repeated and the receiving end still fails to successfully decode the information bits, the method further includes: The transmitting end transmits the punctured parity-check bits in the first LDPC codeword in the order of puncturing priorities of the parity-check bits, where the parity-check bits with lower puncturing priorities are transmitted first, and the puncturing priority is used to indicate the puncturing priority of the (N - K) parity-check bits in rate matching, N is the length of the mother code of LDPC, N ≥ K, and N is an integer.

17. The method according to any one of claims 2-14, characterized in that, Before the transmitting end repeats the L information bits included in the first information bit set in the first LDPC codeword in the order of decreasing repetition priority according to the number of bits L to be repeated and the order of repetition priorities of the K information bits, the method further includes: The transmitting end transmits the first LDPC codeword; In the case where the first LDPC codeword is not successfully decoded by the receiving end, the transmitting end transmits the punctured parity-check bits in the first LDPC codeword in the order of priorities of the parity-check bits, where the parity-check bits with lower priorities are transmitted first, and the priority is used to indicate the puncturing priority of the (N - K) parity-check bits in rate matching, N is the length of the mother code of LDPC, N ≥ K, and N is an integer; Furthermore, the transmitting end, based on the required number of repeated bits L and the sorting of the repetition priorities of the K information bits, repeatedly transmits the L information bits contained in the first information bit set of the first LDPC codeword in descending order of repetition priority, including: If all the punctured parity bits of the first LDPC codeword have been sent and the receiver has still not successfully decoded it, the sender sends the information bits of the first LDPC codeword according to the repetition priority of the K information bits.

18. A communication device, characterized in that, It includes units for implementing the function of the method as described in any one of claims 1-17.

19. A communication device, characterized in that, include: The method includes a processor and an interface circuit, the interface circuit being used to receive computer code or instructions and transmit them to the processor, the processor executing the computer code or instructions, as described in any one of claims 1-17.

20. A communication device, characterized in that, The device includes at least one processor coupled to at least one memory, the at least one processor being configured to execute a computer program or instructions stored in the at least one memory to cause the communication device to perform the method as described in any one of claims 1-17.

21. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions that, when executed on a computer, implement the method as described in any one of claims 1-17.

22. A communication device, characterized in that, Includes the communication device as described in claim 18.

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