Histogram equalization system and image processing device

Abstract

The present invention relates to a histogram equalization system and an image processing device. In the histogram equalization system, the grayscale of each pixel point of the image within a given grayscale interval is received row by row according to a system clock signal, and the statistical value of the number of occurrences of each grayscale level of the pixel points in the odd-numbered columns within the given grayscale interval is stored in a first memory through a time-sharing statistical method, and the statistical value of the number of occurrences of each grayscale level of the pixel points in the even-numbered columns within the given grayscale interval is stored in a second memory, which can alleviate the timing tension problem that is easy to occur when reading and writing data under a high-frequency system clock signal, and both the pixel points in the odd-numbered columns and the pixel points in the even-numbered columns are counted, which can ensure high statistical accuracy. The image processing device includes the histogram equalization system.

Description

Technical Field

[0001] The present invention relates to the field of image processing, and in particular to a histogram equalization system and an image processing device. Background Art

[0002] Histogram equalization is a method in the field of image processing that uses an image histogram to adjust contrast. It can be used to enhance local contrast without affecting overall contrast. Histogram equalization can be used to enhance the contrast of images where both the background and foreground are too bright or too dark (i.e., images with a small dynamic range), and can be used to perform tone mapping on high-dynamic range (HDR) images, including medical images and radar images. Tone mapping refers to a technique for compressing a high-dynamic range image so that the image meets the dynamic range required for display on a conventional display device, wherein the contrast, color and other information in the high-dynamic range image is retained as much as possible.

[0003] The basic operation of the algorithm for implementing histogram equalization includes counting the number of times each gray level appears in all pixels of the input image, and performing calculation processing to map the gray level of each pixel to a new gray level. The algorithm can be implemented through hardware circuits, in which a system clock signal of a certain frequency is used to control the operation of the corresponding functional modules in the histogram equalization system. For example, after the system receives the pixel points of a frame of input image, it then performs gray level statistics. The counting module needs to complete the process of reading the previous statistical value of the corresponding gray level from the memory, adding 1, and then writing it into the memory within one clock cycle of the system clock signal.

[0004] With the development of chip manufacturing technology, the size and power consumption of graphics processing chips are decreasing. For example, a 40-nanometer low-power (40LP) process has been developed. At the same time, the frequency of the system clock signal used is also increasing, such as reaching more than 150MHz, or even more than 200MHz. In this case, if you want to complete the grayscale statistics process as mentioned above and meet the timing of the overall system at the same time, one method is to use a high-frequency circuit with twice the system clock frequency to read and write the memory, but in this way, twice the system clock frequency may reach more than 300MHz, the timing will be very tight, and it is easy to cause output errors; another method is to use two system clock cycles to read and write separately, that is, the algorithm only performs grayscale statistics on pixels in odd or even columns, and discards the statistics of other pixels, which has the problem of poor statistical accuracy. The problems of tight timing and poor statistical accuracy will also affect the effect of tone mapping. Summary of the invention

[0005] In order to alleviate the timing tension problem under high-frequency clock signals and ensure high statistical accuracy, the present invention provides a histogram equalization system and an image processing device including the histogram equalization system.

[0006] On the one hand, the present invention provides a histogram equalization system, including a histogram equalization circuit, a first memory and a second memory, wherein the histogram equalization circuit includes: a histogram statistics module, wherein the histogram statistics module is used to receive the grayscale level of each pixel in an image within a given grayscale interval row by row according to a system clock signal, and to perform read and write operations on the first memory according to a first memory clock signal, so as to store statistical values ​​of the number of occurrences of each grayscale level of odd-numbered column pixels within the given grayscale interval into the first memory, and to perform read and write operations on the second memory according to a second memory clock signal, so as to store statistical values ​​of the number of occurrences of each grayscale level of even-numbered column pixels within the given grayscale interval into the second memory; wherein the first memory clock signal is set according to the received signal of the odd-numbered column pixels, and the second memory clock signal is set according to the received signal of the even-numbered column pixels.

[0007] Optionally, in the first memory clock signal and the second memory clock signal, the operation cycle of one pixel point includes a read operation time for reading out the corresponding statistical value and a write operation time for adding 1 and then writing it, and for odd-numbered column pixel points and even-numbered column pixel points arranged sequentially on the same row, the write operation time of the odd-numbered column pixel points overlaps with the read operation time of the even-numbered column pixel points.

[0008] Optionally, the histogram equalization system also includes a third memory; the histogram statistics module is also used to respectively read the statistical values ​​corresponding to each gray level stored in the first memory and the statistical values ​​corresponding to each gray level stored in the second memory, add them up respectively to obtain the total statistical values ​​corresponding to the gray levels, and store the total statistical values ​​in the third memory.

[0009] Optionally, the first memory, the second memory and the third memory are all single-port static random access memories (ie, single-port SRAMs).

[0010] Optionally, the histogram equalization circuit also includes a histogram cropping module and a histogram accumulation module; the histogram cropping module is used to determine whether the total statistical value corresponding to each gray level exceeds a cropping threshold before the histogram statistics module receives the next frame of image, calculate the total number of pixels exceeding the cropping threshold, and assign gray levels to the total number of pixels until the total statistical values ​​corresponding to each gray level do not exceed the cropping threshold; the histogram accumulation module is used to accumulate and calculate the total statistical values ​​corresponding to each gray level obtained by the histogram cropping module before the histogram statistics module receives the next frame of image, so as to obtain the cumulative statistical values ​​corresponding to each gray level; wherein the cumulative statistical value corresponding to 0 gray level is equal to the total statistical value corresponding to 0 gray level, and the cumulative statistical value corresponding to a gray level greater than 0 is the sum of the cumulative statistical value corresponding to the previous gray level and the total statistical value corresponding to the gray level greater than 0.

[0011] Optionally, in the process of allocating gray levels to the total number of pixels, for any of the gray levels, the histogram cropping module sequentially completes the following three operations within three consecutive clock cycles based on the system clock signal: a read operation on the corresponding address in the third memory, an operation of adding the read total statistical value to a specified allocation number, and a write operation of writing the updated total statistical value to the same address in the third memory based on a comparison result between the added value and the cropping threshold; wherein, when the added value of the read total statistical value and the specified allocation number exceeds the cropping threshold, the cropping threshold is used as the updated total statistical value, and when the added value of the read total statistical value and the specified allocation number does not exceed the cropping threshold, the added value is used as the updated total statistical value.

[0012] Optionally, the histogram cropping module performs the three operations on the gray levels in the third memory in groups of two; wherein, during a clock cycle in which the second operation is performed on the previous gray level in the same group, the first operation is performed on the subsequent gray level in the same group.

[0013] Optionally, for any of the gray levels, the histogram accumulation module sequentially completes the following three operations within three consecutive clock cycles based on the system clock signal: a read operation on the corresponding address in the third memory, an operation of calculating the cumulative statistical value corresponding to the gray level, and a write operation of writing the cumulative statistical value to the same address in the third memory; and the histogram accumulation module performs the three operations on each of the gray levels in the third memory in groups of two, wherein in the clock cycle in which the second operation is performed on the previous gray level in the same group, the first operation is performed on the subsequent gray level in the same group at the same time.

[0014] Optionally, the given grayscale interval is 0 to 2047; the frequency of the system clock signal is greater than or equal to 150 MHz; and the histogram equalization system is used to perform global tone mapping.

[0015] In one aspect, the present invention provides an image processing device including the above-mentioned histogram equalization system.

[0016] The histogram equalization system provided by the present invention comprises a histogram equalization circuit and a first memory and a second memory, wherein the histogram statistics module of the histogram equalization circuit receives the grayscale of each pixel in the image in a given grayscale interval row by row according to the system clock signal, and stores the statistical value of the number of occurrences of each grayscale of the odd-numbered column pixels in the given grayscale interval in the first memory according to the first memory clock signal, and stores the statistical value of the number of occurrences of each grayscale of the even-numbered column pixels in the given grayscale interval in the second memory according to the second memory clock signal, the first memory clock signal and the second memory clock signal are respectively set according to the received signals of the odd-numbered column pixels and the even-numbered column pixels, so that the histogram statistics module realizes the time-sharing statistics of the odd-numbered column pixels and the even-numbered column pixels, the frequencies of the first clock signal and the second clock signal are lower than the system clock signal, which can alleviate the timing tension problem that is easy to occur when reading and writing data under a high-frequency system clock signal, and the odd-numbered column pixels and the even-numbered column pixels are counted, so that the histogram equalization system can adapt to a wide clock frequency range while ensuring high statistical accuracy.

[0017] Furthermore, in the above-mentioned histogram equalization circuit, the histogram cropping module and the histogram accumulation module can complete the following three operations in sequence within three consecutive clock cycles for any of the grayscale levels based on the system clock signal: a read operation on the corresponding address in the third memory, an operation for calculating based on the read value, and an operation for writing the updated data to the same address of the third memory. By performing these three operations on each of the grayscale levels in groups of two, and performing the second operation on the previous grayscale level in the same group in the clock cycle, and performing the first operation on the subsequent grayscale level in the same group at the same time, it is convenient to shorten the average processing time for each of the grayscale levels to two clock cycles. Therefore, compared with the situation where it takes at least three clock cycles on average to perform these three operations on each grayscale level, the frame time can be shortened, that is, the frame rate is improved, thereby improving the performance of the histogram equalization system. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 It is a schematic diagram of the structure of a histogram equalization system according to an embodiment of the present invention.

[0019] Figure 2It is a schematic diagram of a timing signal in which the statistical values ​​of the pixels in the odd columns and the even columns are stored in the first memory and the second memory respectively by using the histogram statistical module in the embodiment of the present invention.

[0020] Figure 3 It is a schematic diagram of a timing signal for adding the statistical values ​​corresponding to each gray level stored in the first memory and the second memory and storing the total statistical value in the third memory by using the histogram statistical module in the embodiment of the present invention.

[0021] Figure 4A and Figure 4B A comparison of the example histogram before and after cropping.

[0022] Figure 5 A schematic diagram of timing signals for image processing by a histogram equalization system according to an embodiment of the present invention.

[0023] Figure 6 The diagram is a timing signal diagram of allocating the total number of pixels exceeding the clipping threshold to each gray level by using the histogram clipping module in the embodiment of the present invention.

[0024] Description of reference numerals:

[0025] 100 - histogram equalization system; 110 - histogram equalization circuit; 111 - histogram statistics module; 112 - histogram clipping module; 113 - histogram accumulation module; 120 - storage module; 130 - preprocessing module; 140 - equalization output module. DETAILED DESCRIPTION

[0026] The histogram equalization system and image processing device of the present invention are further described in detail below in conjunction with the accompanying drawings and specific embodiments. According to the following description, the advantages and features of the present invention will become clearer. It should be noted that the accompanying drawings are all in a very simplified form and use non-precise proportions, which are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. It should be noted that the terms "first", "second", etc. in the specification are used to distinguish between similar elements, and are not necessarily used to describe a specific order or time sequence. It is to be understood that, where appropriate, these terms used in this way are interchangeable, for example, so that the embodiments of the present invention described herein can be operated in a different order than that described or shown herein.

[0027] The histogram equalization system of the present invention adopts a histogram equalization algorithm, which can be used to implement global tone mapping. The following embodiments mainly illustrate the histogram equalization system of the present invention by using an example of implementing global tone mapping. Global tone mapping refers to processing all pixels in the entire image using the same transformation function, that is, pixels of the same grayscale in the original image still have the same grayscale after global tone mapping. The histogram equalization system involved in the embodiment of the present invention can alleviate the timing tension problem under a high-frequency clock signal, so that it can adapt to a wide clock frequency range and ensure high statistical accuracy. It should be noted that the histogram equalization system described below is used for global tone mapping, but the present invention is not limited thereto. According to the concept of the histogram equalization system, it can also be used for other purposes in other embodiments, such as performing histogram equalization on images with a small dynamic range.

[0028] Figure 1 Schematic diagram of the structure of the histogram equalization system of the embodiment of the present invention. Figure 1 The histogram equalization system 100 of one embodiment of the present invention includes a histogram equalization circuit 110, and the histogram equalization circuit 110 further includes a histogram statistics module 111, a histogram clipping module 112 and a histogram accumulation module 113. In general, the histogram statistics module 111, the histogram clipping module 112 and the histogram accumulation module 113 are circuit modules respectively arranged corresponding to the histogram statistics (Hist), the histogram clipping (Clip) and the histogram accumulation (Cdf) in the histogram equalization algorithm. The histogram equalization system 100 also includes a storage module 120. The storage module 120 includes a plurality of memories, and the memory is, for example, a static random access memory (hereinafter referred to as Sram). Sram can store the data inside without a refresh circuit, and has a very fast read and write speed, and can also be implemented using a programmable logic circuit. In order to reduce the circuit occupation area, the memory used in this embodiment is, for example, a single-port Sram, that is, the read operation or write operation for the same Sram is performed separately.

[0029] The image data to be processed by the histogram equalization system 100 of the present invention is, for example, output from a camera. Figure 1, the image data to be processed is, for example, a floating-point RGB image (RAW format) of a high dynamic range (HDR), and the image data to be processed is stored in a cache memory (referred to as Sram0). The histogram equalization system 100 also includes a preprocessing module 130 and an equalization output module 140. Before being input into the histogram statistics module 111 of the histogram equalization circuit 110, the original image data in the RAW format are transmitted to two paths respectively, one path of the original image data is transmitted to the preprocessing module 130 through Sram0, and the other path of the original image data is output to the equalization output module 140, and the image data output to the equalization output module 140 is delayed by one frame than the image data output to Sram0. The preprocessing module 130 is used to perform spatial domain conversion on the original image data of the image to be processed by histogram equalization and obtain the grayscale level of each pixel in the image within a given grayscale interval, and output the grayscale level of each pixel in the given grayscale interval to the histogram statistics module 111 according to the system clock signal. By performing spatial domain conversion, it is easier to compress and send on the channel of the histogram equalization circuit 110. In an embodiment of the present invention, the original image in RAW format can be converted to obtain the pixel value of each pixel, and the pixel value includes the logarithmic brightness (expressed as LogY), which is called Y transformation. The image after Y transformation is, for example, in the YUV color space. The Y transformation can adopt the method disclosed in the art, such as 3×3 matrix calculation. As an example, each pixel in a frame of the original image has a 20-bit bit width after Y transformation from the RAW format. The preprocessing module 130 also compresses the pixel from the 20-bit bit width to 11 bits to retain only the brightness data. The brightness data obtained here is the grayscale of the corresponding pixel. In this embodiment, the grayscale of the pixel obtained by the preprocessing module 130 is, for example, in the grayscale interval range of 0 to 2047. However, the present invention is not limited to this. In other embodiments, the histogram equalization system of the present invention can also perform histogram equalization for other given grayscale intervals (such as 0 to 255), and the system clock signal used can be a high frequency (for example, above 150 MHz) or a low frequency (for example, less than 150 MHz).

[0030] The balanced output module 140 is used to perform grayscale mapping on the pixels of the image so that each pixel has a new grayscale level and output an image with a balanced grayscale distribution. In the embodiment of the present invention, the balanced output module 140 uses the histogram mapping value obtained by the histogram equalization circuit 110 of the previous frame of the image to complete the grayscale mapping of each pixel in the current image.

[0031] In the histogram equalization system 100 of the embodiment of the present invention, the histogram statistics module 111 of the histogram equalization circuit 110 is used to receive the value of each pixel in an image (in this embodiment, the current image) row by row according to the system clock signal and perform histogram statistics, and the value of each pixel is represented by the gray level of the pixel in a given gray range. In addition, in order to alleviate the timing tension problem under the high-frequency clock signal and ensure high statistical accuracy, the histogram statistics module 111 adopts a method of performing time-sharing statistics on the pixels of the odd columns and the even columns and then adding them up.

[0032] Specifically, the histogram statistics module 111 performs read and write operations on the first memory Sram1 in the storage module 120 according to the first memory clock signal, so as to store the statistical value of the number of occurrences of each gray level of the odd-numbered column pixel points in the given gray level interval (0 to 2047 in this embodiment) in the first memory Sram1. Here, the odd-numbered column pixel points refer to the pixel points located on the odd-numbered column in the same row (such as the first pixel point, the third pixel point, the fifth pixel point, etc. in the row direction), and the statistical value corresponding to the odd-numbered column pixel points is a value obtained by counting the number of times the odd-numbered column pixel points appear in each gray level in the given gray level interval. The histogram statistics module 111 also performs read and write operations on the second memory Sram2 in the storage module 120 according to the second memory clock signal, so as to store the statistical value of the number of occurrences of each gray level of the even-numbered column pixel points in the given gray level interval in the second memory Sram2. Here, the even-numbered column pixel refers to the pixel located on the even-numbered column in the same row (such as the second pixel, the fourth pixel, the sixth pixel, etc. in the row direction), and the statistical value corresponding to the even-numbered column pixel is a value obtained by counting the number of times the even-numbered column pixel appears in each gray level in the given grayscale interval. In this embodiment, the first memory clock signal is set according to the received signal of the odd-numbered column pixel, and the second memory clock signal is set according to the received signal of the even-numbered column pixel.

[0033] Figure 2 1 is a schematic diagram of a timing signal in which the statistical values ​​of the pixels in the odd columns and the even columns are stored in the first memory and the second memory respectively using the histogram statistical module in the embodiment of the present invention. Figure 1 and Figure 2, pclk represents the system clock signal. pixy_valid represents the row output signal of the pixel point processed by the preprocessing module 130 (such as Y conversion and bit width compression), and a high level of pixy_valid corresponds to the output of a row of pixels. pixy<10:0> represents the output time of the grayscale of each pixel point (i.e., the time when the histogram statistics module 111 receives the pixel point). y00 represents the grayscale of the pixel point in the odd column with the coordinates (0,0) in the current image, and y01 represents the grayscale of the pixel point in the even column with the coordinates (0,1) in the current image. The 0 in the coordinate (0,1) represents the coordinate in the row direction, and 1 represents the coordinate in the column direction. For example, y08 represents the grayscale of the pixel point in the odd column with the coordinates (0,8) in the current image, and y10 represents the grayscale of the pixel point in the odd column with the coordinates (1,0) in the current image. pixy_tmp0<10:0> shows the receiving time of each pixel point in the odd column. pixy_tmp1<10:0> shows the receiving time of each even-numbered column pixel.

[0034] In this embodiment, the first memory Sram1 or the second memory Sram2 is provided with an address corresponding to each gray level of a given gray level interval (such as 0 to 2047), and the address is directly expressed in gray level, i.e., address 0, address 1, address 2, ..., address 2046, address 2047. Each address is used to store the statistical result (called statistical value) of how many gray levels received in the current image are the gray levels corresponding to the address, and the statistical result is obtained by classifying and counting the received pixels one by one through the histogram statistical module 111. After receiving the gray level of each pixel, the histogram statistical module 111 can read the statistical value in the address corresponding to the corresponding gray level in the first memory Sram1 or the second memory Sram2, add 1 (index quantity) and then store it in the same address. sram1_addr<10:0> shows the timing of selecting the corresponding address in the first memory Sram1 according to the receiving time of each odd-numbered column pixel. sram2_addr<10:0> shows the timing of selecting the corresponding address in the second memory Sram2 according to the receiving time of each even-numbered column of pixels.

[0035] In this embodiment, the histogram statistics module 111 performs read and write operations on the first memory Sram1 according to the first memory clock signal to store the statistical values ​​of the odd-numbered pixel points in the grayscale interval 0 to 2047 in the first memory Sram1. The first memory clock signal is generated according to the received signal of the odd-numbered pixel points. Figure 2, the first memory clock signal specifically includes a timing signal (as shown in sram1_addr<10:0>) for selecting the corresponding address in the first memory Sram1 according to the reception time of the odd-numbered column pixel point, a readout signal (as shown in sram1_me) and a write enable signal (as shown in sram1_we) of the first memory Sram1. When the readout signal sram1_me is at a high level, the histogram statistics module 111 reads the statistical value of the address in the first memory Sram1 according to the address given by sram1_addr<10:0> (as shown in sram1_rd_data<20:0>, as an example, q02 represents the statistical value stored at the same address as the grayscale value of the odd-numbered column pixel point with coordinates (0,2) in the first memory Sram1), and then writes the value after adding 1 to the readout statistical value (as the updated statistical value) to the original address (as shown in sram1_wr_data<20:0>) when the write enable signal sram1_we is converted from a high level to a low level. Since the histogram statistics module 111 receives the values ​​of two adjacent odd-numbered column pixels at intervals of twice the clock cycle of the system clock signal pclk, the time required to complete "reading out the statistical value, +1 and then writing" according to the first memory clock signal is twice the clock cycle of the system clock signal pclk, thereby alleviating the timing tension problem when the system clock signal pclk is at a high frequency and reducing the risk of output errors due to timing tension.

[0036] In this embodiment, the histogram statistics module 111 performs read and write operations on the second memory Sram2 according to the second memory clock signal to store the statistical values ​​of the even-numbered column pixels in the grayscale interval 0 to 2047 in the second memory Sram2. The second memory clock signal is generated according to the received signal of the even-numbered column pixels. Figure 2, the second memory clock signal specifically includes a timing signal (as shown in sram2_addr<10:0>) for selecting the corresponding address in the second memory Sram2 according to the reception time of the even-numbered column pixel point, a readout signal (as shown in sram2_me) and a write enable signal (as shown in sram2_we) of the second memory Sram2. When the readout signal sram2_me is at a high level, the histogram statistics module 111 reads out the statistical value of the address in the second memory Sram2 according to the address given by sram2_addr<10:0> (as shown in sram2_rd_data<20:0>, as an example, q11 represents the statistical value stored at the same address as the grayscale level of the even-numbered column pixel point with coordinates (1,1) in the second memory Sram2), and then writes the value after adding 1 to the readout statistical value (as the updated statistical value) to the original address in the second memory Sram2 (as shown in sram2_wr_data<20:0>) when the write enable signal sram2_we is converted from a high level to a low level. Since the histogram statistics module 111 receives the values ​​of two adjacent even-numbered column pixels at intervals of twice the clock cycle of the system clock signal pclk, the time required to complete "reading out the statistical value, +1 and then writing" according to the second memory clock signal is twice the clock cycle of the system clock signal pclk, thereby alleviating the timing tension problem when the system clock signal pclk is at a high frequency and reducing the risk of output errors due to timing tension.

[0037] By using the above method, the histogram statistics module 111 can traverse each pixel in the image (size is W×H, W represents the number of pixels in the row direction, H represents the number of pixels in the column direction), and count W×H times in total. After all the statistics of a frame of image are completed, the statistical values ​​of the pixels in the odd columns of the current image are stored in the first memory Sram1, and the statistical values ​​of the pixels in the even columns of the current image are stored in the second memory Sram2. Compared with the method of only counting the pixels in the odd columns or the even columns, the statistical accuracy is higher.

[0038] See also Figure 2The operation cycle of the first memory clock signal of the first memory Sram1 and the second memory clock signal of the second memory Sram2 for each pixel includes the time for reading out the statistical value and the time for adding 1 and then writing, and for the odd-numbered column pixels and the even-numbered column pixels arranged in sequence on the same row, the time when the first memory clock signal is used to complete the addition of 1 and then writing (i.e., writing operation) of the odd-numbered column pixels overlaps with the time when the second memory clock signal is used to complete the reading of the statistical value (i.e., reading operation) of the even-numbered column pixels, and the time when the second memory clock signal is used to complete the writing operation of the even-numbered column pixels overlaps with the time when the first memory clock signal performs the reading operation on the next odd-numbered column pixel.

[0039] In order to obtain the statistical value of all pixels in the image (i.e., the number of pixels corresponding to each gray level in the given gray interval when all pixels in the image are counted), the histogram statistics module 111 is also used to read the statistical value corresponding to each gray level stored in the first memory Sram1 and the statistical value corresponding to each gray level stored in the second memory Sram2, and add and calculate the total statistical value corresponding to each gray level of the current image. Figure 1 The histogram equalization system 100 of this embodiment further includes a third memory Sram3. The third memory Sram3 is similar to the first memory Sram1 and the second memory Sram2. Both are provided with an address corresponding to each gray level of a given gray range (0 to 2047 in this embodiment). The address can be directly represented by a gray level. Different from the first memory Sram1 and the second memory Sram2, each address in the third memory Sram3 is used to store the total statistical value of the gray level accumulated when all pixels in the current image are taken as statistical objects. This can be obtained by reading out the values ​​of the same address in the first memory Sram1 and the second memory Sram2 and adding them respectively. The histogram statistics module 111 stores the statistical value of the current image in the third memory Sram3.

[0040] Figure 3 This is a schematic diagram of a timing signal in which the histogram statistics module in an embodiment of the present invention is used to add the statistics corresponding to each gray level stored in the first memory and the second memory and store the total statistics in the third memory. Figure 1 and Figure 3After the histogram statistics module 111 has finished counting each pixel of the current image one by one, q00~q2047 represent the statistical values ​​stored at each grayscale address in the first memory Sram1, and p00~p2047 represent the statistical values ​​stored at each grayscale address in the second memory Sram2. The histogram statistics module 111 reads out the statistical values ​​located at the same address (i.e., the same grayscale level) from the first memory Sram1 and the second memory Sram2 respectively, and can read out 2048 groups of data in sequence, each group of data includes the statistical values ​​of the odd-numbered column pixels and the even-numbered column pixels corresponding to the same grayscale level, such as q00 and p00, q01 and p01, q02 and p02,..., q2047 and p2047. After reading out, the histogram statistics module 111 adds the two statistical values ​​in each group of data and writes them one by one into the third memory Sram3, such as Figure 3 sram3_wr_data<21:0> shows k0, k1, k2, ..., k2047, where k0 = q00 + p00, k1 = q01 + p01, k2 = q02 and p02, and so on, k2047 = q2047 + p2047, and a total of 2048 total statistical values ​​can be obtained. The 2048 total statistical values ​​stored in the third memory are the statistical results of the histogram statistical module (such as Figure 3 0> in hist<21:0>).

[0041] Next, the histogram clipping module 112 in the histogram equalization circuit 110 of the embodiment of the present invention is introduced. The histogram clipping module 112 is used to determine whether the total statistical value corresponding to each gray level exceeds the clipping threshold before the histogram statistics module 111 receives the next frame of image, calculate the total number of pixels exceeding the clipping threshold, and perform gray level allocation on the total number of pixels until the total statistical value corresponding to each gray level does not exceed the clipping threshold.

[0042] Figure 4A and Figure 4B The figure shows the comparison of the example histogram before and after cropping, where the horizontal axis represents the grayscale level and the vertical axis represents the statistical value corresponding to each grayscale level. Figure 4A This is a schematic diagram of the histogram distribution before clipping. Figure 4A , the pixel statistics corresponding to some gray levels are very high. In order to balance, the histogram distribution can be "clipped" (Hist Clip), and the "clipped" number can be evenly distributed to the gray levels with lower pixel statistics, such as Figure 4B The distribution diagram of the cropped histogram is shown in the figure.

[0043] In this embodiment, the histogram clipping module 112 may include an allocation number calculation unit and a statistical value allocation unit. The allocation number calculation unit is used to determine whether each total statistical value exceeds the clipping threshold (clipLimit) while the histogram statistics module 111 writes the total statistical value corresponding to each gray level in a given gray interval into the third memory Sram3, and sums the number of pixels exceeding the clipping threshold to obtain the total allocation number (Sumhist), and calculates the pre-allocated number (aveVal) that can be evenly allocated to each gray level through the total allocation number and the number of gray levels. If the total allocation number is less than the number of gray levels, it is not necessary to calculate the number that can be evenly allocated to each gray level, and the allocation can be performed directly according to the total allocation number (refer to the third allocation below). The clipping threshold can be set to represent the maximum total statistical value corresponding to each gray level.

[0044] After the total allocation number and the pre-allocation number are obtained by using the above-mentioned allocation number calculation unit, the statistical value allocation unit is used to allocate the total allocation number that exceeds the clipping threshold to each gray level at least once, and update the total statistical values ​​corresponding to each gray level stored in the third memory Sram3 until the total statistical values ​​corresponding to each gray level do not exceed the clipping threshold.

[0045] As an example, the total allocation number obtained by the allocation number calculation unit is greater than the number of gray levels. Theoretically, the number of pixels that can be evenly allocated to each gray level is recorded as the pre-allocated number (aveVal), and the pre-allocated number is recorded as the designated allocation number for this allocation. First, the following first allocation is performed: the statistical value allocation unit reads the total statistical values ​​stored in 2048 addresses from the third memory Sram3 one by one, and determines whether the total statistical value plus the pre-allocated number is greater than or equal to the clipping threshold. If so, the clipping threshold is used as the updated total statistical value corresponding to the gray level of the address. If not, the total statistical value after adding the pre-allocated number is used as the updated total statistical value corresponding to the gray level of the corresponding address. The calculation process of the first allocation is expressed as follows:

[0046]

[0047] Wherein, hist[i] is the total statistical value corresponding to the i-th gray level before allocation, hist[i]′ is the total statistical value corresponding to the i-th gray level after the first allocation, i=[0, 1, 2, ..., 2047] (i is in the range of 0 to 2047, i is an integer). ClipLimit is the clipping threshold.

[0048] If after the first allocation, the total number of pixels greater than the clipping threshold obtained by the allocation number calculation unit (i.e., the total allocation number) is not completely allocated, the remaining number of pixels is recorded as Res hist, if the number of remaining pixels Res hist Greater than the number of gray levels (in this embodiment, Res hist >2048), the number of pixels that can be evenly distributed to each gray level is recorded as aveValRes, and then the second distribution is performed as follows: the statistical value distribution unit reads the total statistical values ​​stored in 2048 addresses from the third memory Sram3 one by one, and determines whether the total statistical values ​​after adding aveValRes are greater than or equal to the clipping threshold. If so, the clipping threshold is used as the updated total statistical value corresponding to the gray level of the address. If not, the total statistical value after adding aveValRes is used as the updated total statistical value corresponding to the gray level of the address. The calculation process of the second distribution is expressed as follows:

[0049]

[0050] Wherein, hist[i]" is the statistical value corresponding to the i-th gray level after the second distribution, i = [0, 1, 2, ..., 2047].

[0051] If after the above two allocations, the total number of pixels greater than the clipping threshold obtained by the allocation number calculation unit (i.e., the total allocation number) has not been completely allocated, the remaining number of pixels is recorded as remainder. If the remaining number of pixels remainder is greater than or equal to the number of gray levels, the allocation can continue according to the above first allocation or second allocation method. If the remaining number of pixels remainder is less than the number of gray levels (remainder<2048 in this embodiment), the following third allocation is performed: the remaining pixels are allocated in the order of gray levels from small to large. The calculation process is expressed as follows:

[0052] histClip[i]=hist[k]"+1, where i=k, hist[k]" is not equal to the clipping threshold, and k=[0, 1, 2, ..., remainder-1].

[0053] It can be seen from the description of the first allocation to the third allocation that in this embodiment, when the histogram clipping module 112 performs grayscale allocation for the total number of pixels exceeding the clipping threshold (i.e., the total allocation number), for any of the grayscales, the following three operations are performed in sequence: a read operation (referred to as "read operation") performed on the corresponding address in the third memory Sram3, an operation of adding the read total statistical value to a specified allocation number (referred to as "addition operation"), and a write operation (referred to as "write operation") of writing the updated total statistical value to the corresponding address in the third memory Sram3 according to the comparison result between the added value and the clipping threshold; wherein, when the added value of the read total statistical value and the specified allocation number exceeds (i.e., is greater than or equal to) the clipping threshold, the clipping threshold is used as the updated total statistical value, and when the added value of the read total statistical value and the specified allocation number does not exceed the clipping threshold, the added value is used as the updated total statistical value of the grayscale. In an optional implementation, since there is no same address reuse in this process, each updated total statistical value can be stored back to the address of the third memory Sram3 before the update, which can avoid setting up a new memory and increasing the circuit volume. In the above-mentioned first allocation, second allocation and third allocation, the three operations of allocating the total allocation number exceeding the clipping threshold to each gray level can be completed in three consecutive clock cycles under the control of the system clock signal pclk.

[0054] Figure 5 Schematic diagram of timing signals for image processing by a histogram equalization system according to an embodiment of the present invention. Figure 5 Each frame of image is output to the histogram equalization circuit 100 under the control of the frame signal (corresponding to Figure 5 The histogram equalization circuit 110 delays one row to receive the corresponding image and starts the histogram statistics, histogram clipping and histogram accumulation process (corresponding to Figure 5 The timing curve at the bottom), wherein the high level of the frame signal and the histogram equalization signal represents the time in the frame, and the low level represents the time between frames. In the embodiment of the present invention, the histogram statistics module 111 of the histogram equalization circuit 110 performs histogram statistics of the odd and even columns of pixels in the frame time, and the time between two frames of images (referred to as the frame interval, corresponding to Figure 5The statistical values ​​of the odd-numbered columns and the even-numbered columns of pixels are summed up by using the low level in the control register (low level in the control register), and the obtained total statistical value is stored in the third memory Sram3. In the process of storing the total statistical value in the third memory Sram3, the histogram clipping module 112 can calculate the total allocated number and the pre-allocated number in parallel. Then, before the histogram statistics module 111 receives the next frame of image, the histogram clipping module 112 performs the above-mentioned "clipping" process, for example, the allocation process of the above-mentioned "read operation", "addition operation" and "write operation" is performed for each gray level. Among these three operations, if the gray level of the previous address is updated with the total statistical value (i.e., the "write operation" is completed) before the gray level of the next address is processed, the histogram clipping module 112 needs ((2048×3)+(2048×3)+(remainder×3)) clock cycles to complete the above three allocation processes, and the corresponding inter-frame time needs to be greater than this duration, which will result in a slower frame rate.

[0055] In order to shorten the inter-frame time, in the preferred solution, the histogram clipping module 112 processes each of the gray levels in the third memory Sram3 in groups of two when performing gray level allocation (i.e., performing the above-mentioned "read operation", "add operation" and "write operation"); and, in the clock cycle in which the second operation (i.e., "add operation") is performed on the previous gray level in the same group, the first operation (i.e., "read operation") is performed on the subsequent gray level in the same group. Further explanation is as follows.

[0056] Figure 6 This is a schematic diagram of a timing signal for allocating the total number of allocations exceeding the clipping threshold to each gray level using the histogram clipping module in an embodiment of the present invention. Figure 6 Specifically, when performing grayscale allocation, the address of each grayscale to be read is first sent to the third memory Sram3 (corresponding to sram3_addr<10:0>), and in order to be able to operate each grayscale in the third memory Sram3 in groups of two, the address corresponding to each grayscale to be read is sent in a manner of being repeated once in twos (such as the order of 0, 1, 0, 1, 2, 3, 2, 3 shown in sram3_addr<10:0>), and then the third memory Sram3 reads out the total statistical value stored in the corresponding address two by two under the control of the enable signal (sram3_we) and the read signal (sram3_me). For example, see Figure 6The sram3_me signal and sram3_rd_data<21:0> signal in the system clock signal pclk are used as the first clock beat (i.e., the first clock cycle) when sram3_me is converted to a high level. In the first clock beat, a read operation is performed on the address of gray level 0; in the second clock beat that follows, the total statistical value q00 corresponding to gray level 0 is read out and used for addition processing, i.e., "addition operation". Since the third memory Sram3 is already in a readable and writable state at the second clock beat, a read operation is also performed on the address of gray level 1 at the second clock beat; in the subsequent third clock beat, the result of the "addition operation" corresponding to gray level 0 (i.e., the added value obtained by adding the read total statistical value of gray level 0 to the specified allocated number) has been obtained. According to the comparison with the clipping threshold, the result of the "addition operation" or the clipping threshold is selected as the new total statistical value corresponding to gray level 0 after update, sram3_we is set to a high level, and the new total statistical value is written to the address of gray level 0 in the third memory (see Figure 6 sram3_wr_data<21:0> in the memory, represented by "p0+q0"), and at the same time, in the third clock beat, an "addition operation" is performed on the total statistical value q01 of the gray level 1 read out; in the subsequent fourth clock beat, the new total statistical value corresponding to the gray level 1 is written to the address of the gray level 1 in the third memory. Because the "addition operation" of the gray level 1 and the "write operation" of the gray level 0 are in the same clock beat, and for a single-port Sram, only a read operation or a write operation can be performed at the same time, the "read operation" corresponding to the gray level 2 is not performed in the same clock cycle as the "addition operation" of the gray level 1, but gray levels 2 and 3 are operated as another group of gray levels. Since the third memory Sram needs to perform a write operation on the address of the gray level 1 in the fourth clock beat, the read operation on the gray level 2 can be set to be performed in the fifth clock beat. For gray levels 2 and 3, the "read operation" corresponding to gray level 3 can be performed in the same clock beat as the "add operation" corresponding to gray level 2 in the same manner as gray level 0 and gray level 1. For clarity, this embodiment regards gray levels 0 and 1 as one group, 2 and 3 as one group, and so on. In the "cropping" process of gray level allocation for the total allocation number exceeding the clipping threshold, the "add operation" of the previous gray level and the "read operation" of the next gray level in the same group are completed using the same clock beat. For two adjacent groups of gray levels, the "read operation" of the previous gray level of the next group can be started at the next clock beat immediately after the "write operation" of the next gray level of the previous group is completed.

[0057] It can be seen that using Figure 6According to the timing method shown, when the histogram clipping module 112 performs grayscale distribution for the total distribution number exceeding the clipping threshold, the operation on the total statistical value of two consecutive grayscales can be completed within four clock cycles of the system clock signal pclk, that is, the average time required for each grayscale is two clock cycles, which is greatly shortened compared to the situation where three operations are performed separately for each grayscale through three clock cycles, thereby shortening the time between frames and improving the frame rate.

[0058] After being processed by the histogram cropping module 112, the histogram distribution of the pixels of the input image is adjusted (see Figure 4B ), the gray level histogram distribution is relatively balanced. Figure 1 In this embodiment, the histogram equalization circuit 110 also includes a histogram accumulation module 113, which is used to accumulate and calculate the total statistical values ​​corresponding to the gray levels obtained by the histogram cropping module 112 before the histogram statistics module 111 receives the next frame of image, so as to obtain the cumulative statistical values ​​corresponding to the gray levels; wherein the cumulative statistical value corresponding to the 0 gray level is equal to the total statistical value corresponding to the 0 gray level, and the cumulative statistical value corresponding to the gray level greater than 0 is the sum of the cumulative statistical value corresponding to the previous gray level and the total statistical value corresponding to the gray level greater than 0.

[0059] As an example, assume that the image obtained after being processed by the histogram clipping module 112 is a clipped histogram of the (n-1)th frame, denoted as histClip n-1 , n is an integer greater than or equal to 2. The histogram accumulation module 113 generates a clipping histogram according to the clipping histogram histClip n-1 To calculate the cumulative histogram histCdf n-1 . The subsequent cumulative histogram histCdf n-1 Can calculate the histogram mapping value histCdfMap n-1 .histCdf n-1 The calculation process is expressed as follows:

[0060] (1) When i = 0, histCdf n-1 [i]=histClip n-1 [i];

[0061] (2) When i>0, histCdf n-1 [i]=histClip n-1 [i-1]+histClip n-1 [i]; where, i=[0, 1, 2, ..., 2047].

[0062] In this embodiment, the clipping histogram histClipn-1 The total statistical value corresponding to each gray level in the given grayscale interval is obtained after histogram statistics and histogram clipping of the pixels of the (n-1)th frame image (including the pixels of odd columns and even columns), and the above cumulative histogram histCdf n-1 The cumulative statistical values ​​corresponding to each gray level in the given gray level interval are as follows: the cumulative statistical value corresponding to the gray level 0 is the same as the total statistical value corresponding to the gray level 0 after histogram clipping, and the cumulative statistical value corresponding to the gray level greater than 0 is the sum of the cumulative statistical value corresponding to the previous gray level and the total statistical value corresponding to the gray level greater than 0.

[0063] The cumulative statistical values ​​corresponding to each gray level can be stored in the third memory Sram3 to save the number of memories and reduce the circuit volume. In this embodiment, for any of the gray levels, the histogram accumulation module 113 performs a read operation on the corresponding address in the third memory Sram3, an operation to calculate the cumulative statistical value corresponding to the gray level, and a write operation to write the cumulative statistical value to the corresponding address in the third memory based on the system clock signal pclk in three consecutive clock cycles. Each of the cumulative statistical values ​​can be stored in the third memory The address of the corresponding gray level where the total statistical value was originally stored. For the gray range 0 to 2047, by performing these three operations on each gray level one by one, 2048 gray levels need to be completed through three times 2048, that is, 6144 clock cycles.

[0064] In this embodiment, the process of the histogram accumulation module 113 acquiring the cumulative statistical value of each gray level is also completed before the histogram equalization circuit 110 receives the next frame of image, and in order to shorten the inter-frame time and improve the frame rate, the histogram accumulation module 113 can adopt a timing configuration method similar to the histogram cropping module 112 for reading and writing operations on the third memory Sram3. Specifically, the histogram accumulation module 113 can perform three operations (a read operation on the corresponding address in the third memory Sram3, an operation of calculating the cumulative statistical value corresponding to the gray level, and a write operation of writing the cumulative statistical value to the corresponding address in the third memory) on each of the gray levels in the third memory Sram3 in groups of two; wherein, during the clock cycle (or clock beat) of performing the second operation (i.e., the operation of calculating the cumulative statistical value corresponding to the gray level) on the previous gray level in the same group, the first operation (i.e., the read operation on the corresponding address in the third memory Sram3) is performed on the subsequent gray level in the same group at the same time. In the next clock cycle after the third operation is completed for the next gray level in the same group, the first operation is started for the previous gray level of the next group.

[0065] After the cumulative statistical value is obtained, each pixel of the image needs to be mapped to obtain a new grayscale. For the histogram mapping value (or mapping table, each grayscale in a given grayscale interval corresponds to a mapping value) required for the mapping operation, this embodiment uses the histogram mapping value improved by the previous frame image as the mapping value used in the grayscale mapping of the current frame image, and the histogram mapping value improved by the current frame image is used as the mapping value used in the grayscale mapping of the next frame image.

[0066] As an example, the histogram mapping value of the (n-1)th frame image perfection is calculated according to the cumulative statistical value (corresponding to the cumulative histogram histCdf). The calculation process is expressed as follows:

[0067] Wherein i=[0, 1, 2, ..., 2047], W represents the number of pixels of the current image in the width direction, and H represents the number of pixels of the current image in the height direction. The histogram mapping value may also be stored in the third memory Sram3.

[0068] It can be seen from the above description that in the embodiment of the present invention, the histogram statistics module 111 of the histogram equalization circuit 110 receives the grayscale of each pixel in the image in a given grayscale interval row by row according to the system clock signal pclk, and stores the statistical value of the number of occurrences of each grayscale of the odd-numbered column pixel in the given grayscale interval (for example, 0 to 2047) in the first memory Sram1 according to the first memory clock signal, and stores the statistical value of the number of occurrences of each grayscale of the even-numbered column pixel in the given grayscale interval in the second memory Sram2 according to the second memory clock signal, and the first memory clock signal and the second memory clock signal are respectively set according to the received signals of the odd-numbered column pixel and the even-numbered column pixel. The histogram statistics module 111 performs the statistics of the odd-numbered column pixel and the statistics of the even-numbered column pixel in time-sharing, and the frequencies of the first clock signal and the second clock signal are reduced relative to the frequency of the system clock signal pclk, which can alleviate the timing tension problem that is easy to occur when reading and writing data under a high-frequency system clock signal, so that the histogram equalization circuit 110 can adapt to a wide clock frequency range while ensuring high statistical accuracy.

[0069] Moreover, in the above-mentioned histogram equalization circuit 110, for any of the grayscale levels, the histogram clipping module 112 and the histogram accumulation module 113 may include an operation of reading a corresponding address in the third memory Sram3, an operation of calculating a read value, and an operation of writing the updated data into the third memory Sram3 again. By performing these three operations on each grayscale level in the third memory Sram3 in groups of two, and performing the second operation on the previous grayscale level in the same group during a clock cycle, and performing the first operation on the subsequent grayscale level in the same group at the same time, it is convenient to shorten the average processing time for each of the grayscale levels to two clock cycles. Therefore, compared with the situation where the three operations are performed one by one on each grayscale level and an average of at least three clock cycles are required for each grayscale level, the time between frames can be shortened, that is, the frame rate is improved, thereby improving the performance of the histogram equalization system 100.

[0070] The histogram statistics system 100 of the embodiment of the present invention includes an equalization output module 140, which obtains the new grayscale of each pixel of the current image according to the grayscale of the pixel of the current image and the perfected histogram mapping value of the previous frame image, and outputs an image with equalized grayscale distribution.

[0071] As an example, given a grayscale interval of 0 to 2047, the pixel coordinates in the nth frame image are recorded as (r, c), where r represents the position of the pixel in the row direction and c represents the position of the pixel in the column direction. The pixel value of the pixel (r, c) after Y transformation is imageY n (r,c), imageY n The bit width of (r,c) is 20 bits, for example, imageY n (r,c)>>9 means shift right by 9 bits and retain 11 bits, which are used as the gray level before mapping (expressed as currentLevel). When performing gray level mapping, first calculate the next gray level nextLevel, and then calculate the pixel value imageYnew after the corresponding pixel is adjusted. n (r,c), specifically satisfying the following relationship:

[0072] currentLevel=imageY n (r,c)>>9;

[0073]

[0074]

[0075] Wherein, mod represents a remainder function. The equalization output module 140 also outputs the imageYnew n(r, c) and the image data of each pixel before Y transformation obtain new image data and output the image. The image output by the balanced output module 140 adopts the balanced grayscale distribution.

[0076] It should be noted that, in other embodiments, the given grayscale interval may also be different. The process of calculating the histogram mapping value and performing grayscale mapping in the present invention is not limited to the above example. The process can also be performed using the method of histogram equalization mapping operation disclosed in the art.

[0077] The embodiment of the present invention also includes an image processing device, including the image processing system 100 described above in the embodiment of the present invention. For example, the image processing device can be equipped with a chip integrating the image processing system 100, which can be used to enhance the contrast of images with too bright or too dark background and foreground, i.e., images with a small dynamic range, and can also perform tone mapping on high-dynamic range (HDR) images including medical images, radar images, etc. Since the image processing system 100 can alleviate the timing tension problem under a high-frequency clock signal while ensuring a high statistical accuracy, the image processing device has better image processing performance.

[0078] The processing and execution of the histogram processing system 100 and the image processing device in the above-mentioned embodiment are generally implemented in the form of a software program in conjunction with a device or equipment. Regardless of whether it is in the form of software or hardware, its individual parts can be implemented by personnel familiar with the electronics and software fields. Therefore, its details will not be repeated in this specification.

[0079] The structures in this embodiment are described in a progressive manner, and the later structures are mainly described to explain the differences from the previous structures, and the related parts can be understood by reference.

[0080] The above description is only a description of the preferred embodiment of the present invention, and is not any limitation on the scope of rights of the present invention. Any technical personnel in this field can make possible changes and modifications to the technical solution of the present invention by using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention shall fall within the protection scope of the technical solution of the present invention.

Claims

1. A histogram equalization system, characterized in that: The invention comprises a histogram equalization circuit, a first memory, a second memory and a third memory, wherein the histogram equalization circuit comprises: a histogram statistics module, the histogram statistics module being used to receive the grayscale level of each pixel in the image within a given grayscale interval row by row according to a system clock signal, and to perform read and write operations on the first memory according to a first memory clock signal, so as to store statistical values ​​of the number of occurrences of each grayscale level of the odd-numbered column pixel points within the given grayscale interval into the first memory, and to perform read and write operations on the second memory according to a second memory clock signal, so as to store statistical values ​​of the number of occurrences of each grayscale level of the even-numbered column pixel points within the given grayscale interval into the second memory; Among them, the first memory clock signal is set according to the received signal of the odd-numbered column pixel points, and the second memory clock signal is set according to the received signal of the even-numbered column pixel points. The histogram statistics module is also used to respectively read the statistical values ​​corresponding to each gray level stored in the first memory and the statistical values ​​corresponding to each gray level stored in the second memory, add them up respectively to obtain the total statistical values ​​corresponding to each gray level, and store the total statistical values ​​in the third memory.

2. The histogram equalization system according to claim 1, wherein: In the first memory clock signal and the second memory clock signal, the operation cycle of one pixel includes a read operation time for reading out the corresponding statistical value and a write operation time for adding 1 and then writing it, and for the odd-numbered column pixel points and the even-numbered column pixel points arranged sequentially on the same row, the write operation time of the odd-numbered column pixel points overlaps with the read operation time of the even-numbered column pixel points.

3. The histogram equalization system according to claim 1, wherein: The first memory, the second memory and the third memory are all single-port static random access memories.

4. The histogram equalization system according to claim 1, wherein: The histogram equalization circuit also includes: a histogram clipping module, the histogram clipping module being used to determine whether the total statistical value corresponding to each gray level exceeds a clipping threshold before the histogram statistics module receives the next frame of image, calculate the total number of pixels exceeding the clipping threshold, and perform gray level allocation on the total number of pixels until the total statistical value corresponding to each gray level does not exceed the clipping threshold; and A histogram accumulation module, wherein the histogram accumulation module is used to perform cumulative calculations according to the total statistical values ​​corresponding to the gray levels obtained by the histogram cropping module before the histogram statistics module receives the next frame of image, so as to obtain the cumulative statistical values ​​corresponding to the gray levels; wherein the cumulative statistical value corresponding to the 0 gray level is equal to the total statistical value corresponding to the 0 gray level, and the cumulative statistical value corresponding to the gray level greater than 0 is the sum of the cumulative statistical value corresponding to the previous gray level and the total statistical value corresponding to the gray level greater than 0.

5. The histogram equalization system according to claim 4, characterized in that: In the process of allocating gray levels to the total number of pixels, for any of the gray levels, the histogram clipping module sequentially completes the following three operations within three consecutive clock cycles based on the system clock signal: a read operation on the corresponding address in the third memory, an operation of adding the read total statistical value to a specified allocation number, and a write operation of writing the updated total statistical value to the same address in the third memory according to a comparison result between the added value and the clipping threshold; wherein, when the added value of the read total statistical value and the specified allocation number exceeds the clipping threshold, the clipping threshold is used as the updated total statistical value, and when the added value of the read total statistical value and the specified allocation number does not exceed the clipping threshold, the added value is used as the updated total statistical value.

6. The histogram equalization system according to claim 5, characterized in that: The histogram cropping module performs the three operations on the gray levels in the third memory in groups of two; wherein, during a clock cycle in which the second operation is performed on the previous gray level in the same group, the first operation is performed on the next gray level in the same group.

7. The histogram equalization system according to claim 4, characterized in that: For any of the gray levels, the histogram accumulation module sequentially completes the following three operations within three consecutive clock cycles based on the system clock signal: a read operation on the corresponding address in the third memory, an operation of calculating the cumulative statistical value corresponding to the gray level, and a write operation of writing the cumulative statistical value to the same address in the third memory; and the histogram accumulation module performs the three operations on each of the gray levels in the third memory in groups of two, wherein, in the clock cycle in which the second operation is performed on the previous gray level in the same group, the first operation is performed on the subsequent gray level in the same group at the same time.

8. The histogram equalization system according to any one of claims 1 to 7, characterized in that: The given grayscale range is 0 to 2047; the frequency of the system clock signal is greater than or equal to 150 MHz; and the histogram equalization system is used to perform global tone mapping.

9. An image processing device, characterized in that: The invention comprises a histogram equalization system as claimed in any one of claims 1 to 8.

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