Digital radio frequency transmitter and wireless communication device comprising the same

Abstract

A digital radio frequency (RF) transmitter and a wireless communication device including the same can be provided. The digital RF transmitter includes a processing circuit configured to generate a first pattern signal, a second pattern signal, and a third pattern signal based on a pattern of in-phase (I)-quadrature (Q) binary data pairs and a pattern of inverted I-Q binary data pairs, the first pattern signal to the third pattern signal having a same pattern and different phases; and a switched capacitor digital-to-analog converter (SC-DAC) configured to remove an n-th harmonic component in an RF analog signal by amplifying the first pattern signal to the third pattern signal to have a specific size ratio and synthesizing the amplified first pattern signal to the amplified third pattern signal into the RF analog signal, where "n" is an integer of at least 3.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2020-0062578, filed with the Korean Intellectual Property Office on May 25, 2020, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] The present invention relates to a digital RF transmitter for reducing or minimizing intermodulation distortion components caused by nonlinear amplification of an amplifier when generating radio frequency (RF) analog signals, and more specifically, to a digital RF transmitter and / or a wireless communication device including the thereof. Background Technology

[0004] Recently, wireless communication systems have evolved from single-mode systems to systems that simultaneously support multiple frequency bands and / or modes, such as second-generation (2G), third-generation (3G), fourth-generation (4G), and fifth-generation (5G) systems. To support multiple frequency bands and / or modes, wireless communication systems need to communicate via a frequency band corresponding to each standard, while attenuating signals in other frequency bands to reduce or minimize their impact. According to existing technology, the digital RF transmitter of wireless communication devices operates based on a nonlinear amplifier, thus generating unwanted harmonic components. Therefore, when an RF analog signal including harmonic components passes through a power amplifier, intermodulation distortion components are generated due to the nonlinearity of the power amplifier.

[0005] Filters are placed at the front or back end of the power amplifier to remove intermodulation distortion components. However, because modern wireless communication systems need to cover the millimeter-wave band, the number of filters has increased exponentially, thus increasing cost and footprint. Summary of the Invention

[0006] The present invention provides a digital radio frequency (RF) transmitter and / or a wireless communication device including the digital RF transmitter, the digital RF transmitter including a structure for suppressing intermodulation distortion components due to nonlinear amplification.

[0007] According to one aspect of the present invention, a digital RF transmitter may include: a processing circuit configured to generate a first mode signal, a second mode signal, and a third mode signal based on a mode of in-phase (I)-quadrature (Q) binary data pairs and a mode of in-phase IQ binary data pairs, the first mode signal, the second mode signal, and the third mode signal having the same mode and different phases, and the IQ binary data pairs being derived from baseband signals; and a switched capacitor digital-to-analog converter (SC-DAC) configured to remove an nth harmonic component from the RF analog signal by amplifying the first mode signal, the second mode signal, and the third mode signal to have a specific magnitude ratio and synthesizing the amplified first mode signal, the amplified second mode signal, and the amplified third mode signal into an RF analog signal, wherein "n" is an integer of at least 3.

[0008] According to another aspect of the present invention, a wireless communication device may include: a modem configured to modulate digital data and output "k" bits of I data, "k" bits of Q data, "k" bits of inverted I data, and "k" bits of inverted Q data, wherein "k" is an integer of at least 2; and a digital RF transmitter configured to generate a first mode signal having a mode corresponding to a mode of IQ binary data pairs and a mode of inverted IQ binary data pairs, wherein the IQ binary data pairs and the inverted IQ binary data are based on the I data, the Q data, the inverted I data, and the... The inverted Q data is generated by performing a thermometer-to-binary conversion, and the nth harmonic component of the RF analog signal is removed by generating a second mode signal and a third mode signal, wherein the second mode signal has a first phase difference with the first mode signal, and the third mode signal has a second phase difference with the first mode signal, wherein "n" is an integer of at least 3; and a power amplifier configured to receive the RF analog signal and generate an RF output signal by amplifying the RF analog signal, wherein the RF analog signal is generated by summing the first mode signal, the second mode signal, and the third mode signal.

[0009] According to another aspect of the present invention, a wireless communication device may include: a first SC-DAC circuit, the SC-DAC circuit including a plurality of first paths, each first path including a first amplifier and a first capacitor, the first SC-DAC circuit being configured to receive a plurality of first mode signals in parallel and output a first RF signal by summing the plurality of first mode signals; a second SC-DAC circuit, the second SC-DAC circuit including a plurality of second paths, each second path including a second amplifier and a second capacitor, the second SC-DAC circuit being configured to receive a plurality of second mode signals in parallel and output a second RF signal by summing the plurality of second mode signals; and a third SC-DAC circuit, the third SC-DAC circuit including a plurality of third paths, each third path including a third amplifier and a third capacitor, the third... The three SC-DAC circuits are configured to receive multiple third-mode signals in parallel and output a third RF signal by summing the multiple third-mode signals; a processing circuit configured to generate the multiple first-mode signals, the multiple second-mode signals, and the multiple third-mode signals based on IQ binary data pair modes and inverted IQ binary data pair modes, wherein the multiple second-mode signals lag the multiple first-mode signals by a first phase and the multiple third-mode signals lag the multiple first-mode signals by a second phase; and a first output terminal connected to the output terminal of each of the first, second, and third SC-DAC circuits and configured to output an RF analog signal by summing the first RF signal, the second RF signal, and the third RF signal. Attached Figure Description

[0010] Example embodiments of the inventive concept will become clearer from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0011] Figure 1 This is a schematic block diagram of a wireless communication device according to an example embodiment;

[0012] Figure 2 This is a block diagram of a wireless communication device according to an example embodiment;

[0013] Figures 3A to 3D It is used to describe according to the example embodiments Figure 2 A graphical representation of the operation of a switched capacitor digital-to-analog converter (SC-DAC);

[0014] Figure 4 This is a block diagram of a pattern signal generator according to an example embodiment;

[0015] Figures 5A to 5C It is used to describe Figure 4 Timing diagram of the operation of the pattern signal generator;

[0016] Figure 6 This is a circuit diagram of the first to third SC-DAC circuits according to the example embodiment;

[0017] Figure 7 This is a diagram illustrating a method for determining the magnitude of a first radio frequency (RF) signal in a first SC-DAC circuit according to an example embodiment;

[0018] Figure 8 It is used to describe Figure 6 A diagram showing the equivalent capacitors of the first to third SC-DAC circuits in the diagram;

[0019] Figure 9 It is used to describe what is applied to Figure 6 A diagram showing the power supply voltage of the amplifier in each of the first to third SC-DAC circuits;

[0020] Figure 10 It is used to describe through the Figure 6 A diagram illustrating the pattern of the RF analog signal generated by summing the first to third RF signals;

[0021] Figure 11 This is a block diagram of a pattern signal generator according to an example embodiment;

[0022] Figure 12A yes Figure 11 A block diagram of the first signal generation circuit in the diagram; Figure 12B It is shown by Figure 12A A diagram showing the RF analog signal generated by the first signal generation circuit; Figure 12C yes Figure 12A A diagram illustrating an example implementation of the first component signal generation logic to the third component signal generation logic;

[0023] Figure 13A yes Figure 11 A block diagram of the second signal generation circuit in the diagram; Figure 13B It is shown by Figure 13A A diagram showing the RF analog signal generated by the second signal generation circuit; Figure 13C yes Figure 13A A diagram illustrating an example implementation of the fourth to sixth component signal generation logic.

[0024] Figure 14A yes Figure 11 A block diagram of the third signal generation circuit in the diagram; Figure 14B It is shown by Figure 14AA diagram showing the RF analog signal generated by the third signal generation circuit; Figure 14C yes Figure 14A A diagram illustrating an example implementation of the seventh to ninth component signal generation logic.

[0025] Figure 15A yes Figure 11 Block diagram of the fourth signal generation circuit in the circuit; Figure 15B It is shown by Figure 15A A diagram showing the RF analog signal generated by the fourth signal generation circuit; Figure 15C yes Figure 15A A diagram illustrating an example implementation of the tenth-component signal generation logic to the twelfth-component signal generation logic;

[0026] Figure 16 This is a diagram illustrating the operation of the SC-DAC according to an example embodiment;

[0027] Figure 17 This is a diagram illustrating the configuration of a digital RF transmitter according to an example embodiment;

[0028] Figure 18 This applies the logic of deactivation of opposite cell (DOC) to... Figure 1 An example diagram of a wireless communication device is provided, in which DOC logic can be applied to the wireless communication device to reduce or minimize the power consumption of the SC-DAC; and

[0029] Figure 19 This is a block diagram of a wireless communication device according to an example embodiment. Detailed Implementation

[0030] In the following text, some exemplary embodiments will be described in detail with reference to the accompanying drawings.

[0031] Figure 1 This is a schematic block diagram of a wireless communication device 1 according to an example embodiment. For ease of description, the signal output from the digital radio frequency (RF) transmitter 10 can be defined as an RF analog signal, and the signal output from the power amplifier (PA) 40 can be defined as an RF output signal.

[0032] Reference Figure 1 The wireless communication device 1 may include a digital RF transmitter 10, an RF receiver 20, a modem 30, a power amplifier 40, a low-noise amplifier (LNA) 50, a duplexer 60, and an antenna 70. The wireless communication device 1 may also include a balun (balanced-to-unbalanced) converter located between the PA40 and the duplexer 60. Figure 1 (not shown in the image), this will be in Figure 2The modem 30 can modulate signals for information (e.g., digital information) transmission and provide digital signals to the digital RF transmitter 10, and can demodulate digital signals from the RF receiver 20 to reconstruct the original signals.

[0033] Digital RF transmitter 10 can generate an analog RF signal in the RF band from a digital signal received from modem 30 and provide the analog RF signal to PA 40. Digital RF transmitter 10 may include a switched-capacitor digital-to-analog converter (SC-DAC) 12 and a pattern signal generation circuit 14. In some example embodiments, digital RF transmitter 10 may include at least one SC-DAC. SC-DAC 12 may include multiple amplifiers and multiple capacitors and can convert the digital signal received from modem 30 into an analog signal. In example embodiments, each amplifier of SC-DAC 12 may be implemented by a switched amplifier including Class D or Class G. Therefore, when SC-DAC 12 amplifies a signal as part of the operation of converting a digital signal into an analog signal, it may generate an undesirable p-th harmonic component p. th _HM (where "p" is an integer of at least 2). Due to the nonlinearity of PA40, it is possible to obtain p-th harmonic components p th _HM generates intermodulation distortion components.

[0034] For example, when the SC-DAC 12 generates an RF analog signal corresponding to a digital signal, the RF analog signal may include a fundamental frequency component FFC corresponding to a first frequency fx and a p-th harmonic component p corresponding to a second frequency fy. th _HM. Subsequently, when the RF analog signal is amplified via PA 40, the p-th harmonic component p th The intermodulation between _HM and the fundamental frequency component FFC generates an intermodulation distortion component IMDp corresponding to the third frequency fz. This IMDp is difficult to remove using filters near the first frequency fx. As mentioned above, although undesirable, the p-th harmonic component p... th _HM cannot be removed by a frequency filter (not shown), and therefore will produce an intermodulation distortion component IMDp through intermodulation with other harmonic components. In other words, when including the fundamental frequency component FFC and the p-th harmonic component p... th When the RF analog signal of _HM is output from the SC-DAC 12 and passes through the PA40 with nonlinearity, an unwanted intermodulation distortion component IMDp may be generated due to intermodulation. Because the intermodulation distortion component IMDp is not removed by the low-pass filter and becomes critical noise in the generation of the RF output signal, it may be necessary to remove the p-th harmonic component p in advance. th _HM is used to reduce or prevent the generation of intermodulation distortion components IMDp.

[0035] According to the example embodiment, before the RF analog signal from the digital RF transmitter 10 passes through PA40, the mode signal generation circuit 14 can remove the p-th harmonic component p from the RF analog signal. th _HM. The mode signal generation circuit 14 can be configured in association with the SC-DAC 12 to generate an inverted component, which is related to the p-th harmonic component p of the RF analog signal. th _HM has opposite phase and is related to the p-th harmonic component p. th _HM have the same size. An inverting component can be added to the p-th harmonic component p of an RF analog signal. th _HM, thereby reducing or eliminating the p-th harmonic component p th _HM. For example, the SC-DAC 12 can be configured to: remove the p-value of the RF analog signal by amplifying the first mode signal to the third mode signal to have a specific magnitude ratio and synthesizing the amplified first mode signal to the amplified third mode signal into an RF analog signal. th _HM, where "p" is an integer of at least 2.

[0036] In other words, the digital RF transmitter 10 can use an additionally generated inverted component to remove the p-th harmonic component p of the RF analog signal. th Similar to or analogous to the SC-DAC 12, the mode signal generation circuit 14 may include multiple amplifiers and multiple capacitors. The mode signal generation circuit 14 may include capacitors with desired (or predetermined) capacitances such that the magnitude of the inverting component is related to the p-th harmonic component p of the RF analog signal. th The magnitudes of _HM are equal or substantially similar. Furthermore, a signal with a desired (or predetermined) phase difference from the signal input to the SC-DAC 12 can be input to the mode signal generation circuit 14, such that the inverting component has a phase difference with the p-th harmonic component p of the RF analog signal. th The phase of the _HM component is opposite. In some example embodiments, a power supply voltage with a different level than the power supply voltage applied to the SC-DAC 12 can be applied to the mode signal generation circuit 14, such that the magnitude of the inverted component is as close as possible to the p-th harmonic component p of the RF analog signal. th The size of _HM.

[0037] The PA40 can generate an RF output signal by amplifying an RF analog signal. The p-th harmonic component in the RF output signal is p. th The _HM has been reduced or removed, and the RF output signal is output to the duplexer 60. The antenna 70 connected to the duplexer 60 can transmit the RF output signal to a base station or another wireless communication device.

[0038] Antenna 70 can receive an RF analog signal generated according to the example embodiment and send it to duplexer 60, and low-noise amplifier 50 can perform low-noise amplification on the RF analog signal and provide the amplified RF analog signal to RF receiver 20. RF receiver 20 can convert the amplified RF analog signal into a baseband digital signal and provide the baseband digital signal to modem 30.

[0039] According to an example embodiment, the digital RF transmitter 10 can pre-remove the p-th harmonic component p generated due to nonlinear switching amplification from the RF analog signal. th _HM, thereby generating an RF output signal, in which intermodulation distortion components that may later become noise are suppressed. Therefore, wireless communication device 1 can support improved communication performance.

[0040] In the following text, for clarity, the description will focus on the p-th harmonic component p. th _HM represents the case of the third harmonic component. However, this is merely an example. According to some example embodiments, intermodulation distortion components caused by higher harmonics above the third can be suppressed.

[0041] Figure 2 This is a block diagram of a wireless communication device 100 according to an example embodiment.

[0042] Reference Figure 2 The wireless communication device 100 may include a digital signal processor 110, a controller 120, a memory 122, a thermometer-to-binary converter 130, a pattern signal generator 140, a crystal oscillator 150, an SC-DAC 160, a voltage regulator 170, a front-end circuit 180, and an antenna 190. The digital signal processor 110, controller 120, and memory 122 can form... Figure 1 The modem 30, thermometer-to-binary converter 130, mode signal generator 140, crystal oscillator 150, SC-DAC 160, and voltage regulator 170 can be configured to form a... Figure 1 The digital RF transmitter 10, thermometer-to-binary converter 130, and pattern signal generator 140 can form... Figure 1 The pattern signal generation circuit 14 in the middle.

[0043] The controller 120 can use the memory 122 to control the operation of circuit blocks of the digital signal processor 110 and the wireless communication device 100. The digital signal processor 110 can output in-phase (I) data I1, quadrature (Q) data Q1, inverted I data IB1, and inverted Q data QB1, each having "k" bits (where "k" is an integer of at least 2), to the thermometer-to-binary converter 130. The thermometer-to-binary converter 130 can perform thermometer-to-binary conversion on the I data I1, Q data Q1, inverted I data IB1, and inverted Q data QB1, and provide I binary data I2, Q binary data Q2, inverted I binary data IB2, and inverted Q binary data QB2 to the pattern signal generator 140. For example, when I data I1 has three bits "011" and Q data Q1 has three bits "010", the thermometer-to-binary converter 130 can generate I binary data I2 by converting I data I1 to seven bits "0000011", and Q binary data Q2 by converting Q data Q1 to seven bits "0000101". The thermometer-to-binary converter 130 can arrange I binary data I2, Q binary data Q2, inverted I binary data IB2, and inverted Q binary data QB2 bit by bit, and provide I binary data I2, Q binary data Q2, inverted I binary data IB2, and inverted Q binary data QB2 to the pattern signal generator 140 in parallel.

[0044] The mode signal generator 140 can use the frequency signal F_S received from the crystal oscillator 150 to generate a first mode signal group PT_Sa and a second mode signal group PT_Sb, and provide the first mode signal group PT_Sa and the second mode signal group PT_Sb to the SC-DAC 160. The first mode signal group PT_Sa and the second mode signal group PT_Sb include mode signals having specific modes corresponding to the modes of IQ binary data pairs and the modes of inverted IQ binary data pairs. For example, when the binary data I2 is "0000011", the binary data Q2 is "0000101", the inverted binary data IB2 is "1111100", and the inverted binary data QB2 is "1111010", the pattern of the IQ binary data pair corresponding to the last bit can be "11", and the pattern of the inverted IQ binary data pair corresponding to the last bit can be "00"; the pattern of the IQ binary data pair corresponding to the second to last bit can be "10", and the pattern of the inverted IQ binary data pair corresponding to the second to last bit can be "01"; the pattern of the IQ binary data pair corresponding to the third to last bit can be "01", and the pattern of the inverted IQ binary data pair corresponding to the third to last bit can be "10"; the pattern of the IQ binary data pair corresponding to the fourth to last bit can be "00", and the pattern of the inverted IQ binary data pair corresponding to the fourth to last bit can be "11". The mode of an IQ binary data pair, or the mode of an inverted IQ binary data pair, can be represented using four different expressions, and therefore, the mode signal can have four different modes, which will be referred to below. Figures 5A to 5CThis is described in detail. The pattern signal generator 140 described herein can be implemented using hardware components or a combination of software and hardware components. For example, hardware components may include microcontrollers, storage modules, sensors, amplifiers, bandpass filters, analog-to-digital converters, and processing devices, etc. The processing device can be implemented using one or more hardware devices configured to perform and / or run program code by performing arithmetic, logic, and input / output operations. One or more processing devices may include processing circuitry, processors, controllers and arithmetic logic units, digital signal processors, microcomputers, field-programmable arrays, programmable logic units, microprocessors, or any other device capable of responding to or executing instructions in a defined manner. One or more processing devices may run an operating system (OS) and one or more software applications running on the OS. The processing device may also access, store, manipulate, process, and create data in response to the execution of software. For simplicity, the processing device is described as singular. However, those skilled in the art will understand that the processing device may include multiple processing elements and various types of processing elements. For example, the processing device may include multiple processors, or one processor and one controller. In addition, different processing configurations are possible, such as parallel processors, multi-core processors, distributed processing, etc.

[0045] The first mode signal group PT_Sa can include mode signals generated based on the mode of IQ binary data pairs and the mode of inverted IQ binary data pairs. The second mode signal group PT_Sb can include mode signals with opposite phase to the mode signals of the first mode signal group PT_Sa. The mode signal generator 140 can provide the SC-DAC 160 with the same number of mode signals PT_S as the number of bits in I binary data I2, Q binary data Q2, inverted I binary data IB2, and inverted Q binary data QB2. For example, when I binary data I2, Q binary data Q2, inverted I binary data IB2, and inverted Q binary data QB2 each contain seven bits, the mode signal generator 140 can generate a first mode signal group PT_Sa containing 28 mode signals and can output the mode signals to the SC-DAC 160 in parallel.

[0046] In an example embodiment, the pattern signal generator 140 can generate a clock signal by dividing a frequency signal F_S having a specific frequency, and generate multiple clock signals with a specific phase difference from each other from the clock signal. The pattern signal generator 140 can use multiple clock signals to generate pattern signals, as will be described below. Figure 4 and Figure 11 This will be described in detail.

[0047] SC-DAC 160 may include first to sixth SC-DAC circuits 162a, 164a, 166a, 162b, 164b, and 166b. The first SC-DAC circuits 162a to 166a can receive a first mode signal group PT_Sa and perform digital-to-analog conversion on the first mode signal group PT_Sa. The fourth to sixth SC-DAC circuits 162b and 166b can receive a second mode signal group PT_Sb and perform digital-to-analog conversion on the second mode signal group PT_Sb. The second SC-DAC circuit 164a, the third SC-DAC circuit 166a, the fifth SC-DAC circuit 164b, and the sixth SC-DAC circuit 166b can correspond to... Figure 1 The mode signal generation circuit 14 is included. In the following description, the focus will be on the first SC-DAC circuit 162a to the third SC-DAC circuit 166a, and it will be understood that the description of the first SC-DAC circuit 162a to the third SC-DAC circuit 166a can also be applied to the fourth SC-DAC circuit 162b to the sixth SC-DAC circuit 166b.

[0048] The first SC-DAC circuit 162a to the third SC-DAC circuit 166a may include multiple paths for transmitting mode signals, each path including an amplifier and a capacitor. In an example embodiment, when the first mode signal group PT_Sa includes first mode signals to third mode signals, the first SC-DAC circuit 162a may include multiple first paths for receiving the first mode signal in parallel, each first path including a first amplifier and a first capacitor; the second SC-DAC circuit 164a may include multiple second paths for receiving the second mode signal in parallel, each second path including a second amplifier and a second capacitor; and the third SC-DAC circuit 166a may include multiple third paths for receiving the third mode signal in parallel, each third path including a third amplifier and a third capacitor.

[0049] For example, the pattern signal generator 140 can generate a first pattern signal, a second pattern signal having a first phase difference with the first pattern signal, and a third pattern signal having a second phase difference with the first pattern signal based on a pattern of an IQ binary data pair and a pattern of an inverted IQ binary data pair. A first SC-DAC circuit 162a can receive the first pattern signal through one of a plurality of first paths, a second SC-DAC circuit 164a can receive the second pattern signal through one of a plurality of second paths, and a third SC-DAC circuit 166a can receive the third pattern signal through one of a plurality of third paths. In an example embodiment, the equivalent capacitance of the second SC-DAC circuit 164a can be "m" times the equivalent capacitance of each of the first SC-DAC circuit 162a and the third SC-DAC circuit 166a, where "m" is a real number at least 1.

[0050] As described above, a first SC-DAC circuit 162a to a third SC-DAC circuit 166a that respectively receive a first mode signal to a third mode signal can be used to generate an inverted component for removing the p-th harmonic component that may produce intermodulation distortion. The first mode signal to the third mode signal have different phases, and each SC-DAC circuit has a desired (or predetermined) equivalent capacitance.

[0051] In an example embodiment, when the second SC-DAC circuit 164a and the third SC-DAC circuit 166a are configured to generate an inverted component for removing the third harmonic component, the phase of the first mode signal can be 45 degrees ahead of the phase of the second mode signal and 90 degrees ahead of the phase of the third mode signal, and the capacitance of the second SC-DAC circuit 164a can be the equivalent capacitance of the first SC-DAC circuit 162a and the third SC-DAC circuit 166a. This is because, in practice, it may be difficult to accurately replicate the capacitor of the second SC-DAC circuit 164a to the equivalent capacitance of the first SC-DAC circuit 162a and the third SC-DAC circuit 166a. Therefore, the capacitor of the second SC-DAC circuit 164a can be 1.4 times the equivalent capacitance of each of the first SC-DAC circuit 162a and the third SC-DAC circuit 166a, where 1.4 is approximately equal to... In some example embodiments, in order to compensate for the difficulty in making the capacitance of the second SC-DAC circuit 164a exactly the equivalent capacitance of each of the first SC-DAC circuit 162a and the third SC-DAC circuit 166a in practice, The voltage regulator 170 can control the power supply voltage V. DDThis causes the first power supply voltage V1 applied to the second SC-DAC circuit 164a to have a higher level than the second power supply voltage V2 applied to the first SC-DAC circuit 162a and the third SC-DAC circuit 166a. In some example embodiments, the first SC-DAC circuit 162a to the third SC-DAC circuit 166a may have the same equivalent capacitance, and the first power supply voltage V1 and the second power supply voltage V2 may be adjusted to have different levels (e.g., the first power supply voltage V1 may be a fraction of the second power supply voltage V2). (times), so that the first SC-DAC circuit 162a to the third SC-DAC circuit 166a generate an inverted component for removing the third harmonic component.

[0052] The first SC-DAC circuit 162a can generate a first RF signal from multiple first mode signals, the second SC-DAC circuit 164a can generate a second RF signal from multiple second mode signals, and the third SC-DAC circuit 166a can generate a third RF signal from multiple third mode signals. The first to third RF signals can be summed, and the summed RF signal can be used as an RF analog signal (e.g., an RF output signal) via the first output terminal 167a. OUT Provided to the front-end circuit 180.

[0053] The fourth SC-DAC circuit 162b can generate a fourth RF signal from multiple first inverted mode signals, the fifth SC-DAC circuit 164b can generate a fifth RF signal from multiple second inverted mode signals, and the sixth SC-DAC circuit 166b can generate a sixth RF signal from multiple third inverted mode signals. The fourth to sixth RF signals can be summed, and the summed RF signal can be output as an inverted RF analog signal (e.g., an inverted RF output signal) RFB via the second output terminal 167b. OUT Provided to the front-end circuit 180.

[0054] The front-end circuitry 180 may include a balun 182 and a power amplifier (PA) 184, the balun being connected to a first output terminal 167a and a second output terminal 167b. The balun 182 can receive an RF analog signal RF. OUT and inverted RF analog signal RFB OUT And perform a specific conversion operation on it. Through the specific conversion operation of the balun 182, a first intermodulation distortion component can be added to a second intermodulation distortion component, which is the first intermodulation distortion component in the RF analog signal RF. OUT The nonlinear amplification is generated by the second harmonic component (or even harmonic component), and this second intermodulation distortion component is generated in the inverted RF analog signal RFB.OUT The nonlinear amplification is generated by the second harmonic component (or even harmonic component), so the first intermodulation distortion component can be removed (e.g., canceled).

[0055] PA184 amplifies an RF analog signal that has had its third harmonic component (or odd harmonic component) removed by SC-DAC 160 and its second harmonic component (or even harmonic component) removed by balun 182, thereby generating an RF output signal in which intermodulation distortion caused by harmonic components has been reduced or minimized. The RF output signal of front-end circuit 180 can be transmitted to a base station or another wireless communication device via antenna 190.

[0056] Figures 3A to 3D It is used to describe according to the example embodiments Figure 2 A graphical representation of the operation of the SC-DAC 160. Figures 3A to 3D In this context, binary data I and binary data Q are represented by vectors. Assume that binary data I with a value of "1" or "0" has a phase of 0 degrees or 180 degrees, and binary data Q with a value of "1" or "0" has a phase of 90 degrees or 270 degrees.

[0057] Reference Figure 3A When the SC-DAC 160 receives a mode signal including binary data I corresponding to a 0-degree phase and binary data Q corresponding to a 90-degree phase, it can generate a third harmonic sub-component 3 during nonlinear amplification. rd _HD_sub. Third harmonic component 3 rd _HD_sub can have a phase of 0 degrees, which is three times the phase of 0 degrees, while another third harmonic sub-component is 3. rd _HD_sub can have a phase of 270 degrees, which is three times the phase of 90 degrees, thus generating a third harmonic subcomponent of size 3. rd The size of _HD_sub The third harmonic component with a phase of 315 degrees is twice that of the third harmonic component. rd _HD. Therefore, the SC-DAC 160 needs to generate a third harmonic sub-component of size 3. rd The size of _HD_sub The inverting component IPC, which is twice the size of the component and 135 degrees in phase, is used to remove the third harmonic component. rd _HD. For example, the SC-DAC 160 can generate a third harmonic subcomponent of size 3. rd The size of _HD_sub A signal with a phase of 45 degrees can be generated from this signal, and an inverted component IPC with a phase of 135 degrees can be generated from this signal, which is three times the phase of 45 degrees.

[0058] Reference Figure 3B When the SC-DAC 160 receives a mode signal comprising binary data I corresponding to a 180-degree phase and binary data Q corresponding to a 90-degree phase, it can generate a third harmonic sub-component 3 during nonlinear amplification. rd _HD_sub. Third harmonic component 3 rd _HD_sub can have a 180-degree phase, which is three times the 180-degree phase, while another third harmonic sub-component is 3. rd _HD_sub can have a phase of 270 degrees, which is three times the phase of 90 degrees, thus generating a third harmonic subcomponent of size 3. rd The size of _HD_sub The third harmonic component with a phase of 225 degrees is twice that of the third harmonic component. rd _HD. Therefore, the SC-DAC 160 needs to generate a third harmonic sub-component of size 3. rd The size of _HD_sub The inverted component IPC, which is twice the size of the component and 45 degrees in phase, is used to remove the third harmonic component. rd _HD. For example, the SC-DAC 160 can generate a third harmonic subcomponent of size 3. rd The size of _HD_sub A signal with a phase of 135 degrees can be generated from this signal, and an inverted component IPC with a phase of 45 degrees can be generated from this signal, which is three times the phase of 135 degrees.

[0059] Reference Figure 3C When the SC-DAC 160 receives a mode signal comprising binary data I corresponding to a 180-degree phase and binary data Q corresponding to a 270-degree phase, it can generate a third harmonic sub-component 3 during nonlinear amplification. rd _HD_sub. Third harmonic component 3 rd _HD_sub can have a 180-degree phase, which is three times the 180-degree phase, while another third harmonic sub-component is 3. rd _HD_sub can have a 90-degree phase, which is three times the 270-degree phase, thus generating a third harmonic subcomponent of size 3. rd The size of _HD_sub The third harmonic component with a phase of 135 degrees is twice that of the third harmonic component. rd _HD. Therefore, the SC-DAC 160 needs to generate a third harmonic sub-component of size 3.rd The size of _HD_sub The inverting component IPC, with a phase difference of 315 degrees, is used to remove the third harmonic component. rd _HD. For example, the SC-DAC 160 can generate a third harmonic subcomponent of size 3. rd The size of _HD_sub A signal with a phase of 225 degrees can be generated from this signal, and an inverted component IPC with a phase of 315 degrees can be generated from this signal, which is three times the phase of 225 degrees.

[0060] Reference Figure 3D When the SC-DAC 160 receives a mode signal including binary data I corresponding to a 0-degree phase and binary data Q corresponding to a 270-degree phase, it can generate a third harmonic sub-component 3 during nonlinear amplification. rd _HD_sub. Third harmonic component 3 rd _HD_sub can have a phase of 0 degrees, which is three times the phase of 0 degrees, while another third harmonic sub-component is 3. rd _HD_sub can have a 90-degree phase, which is three times the 270-degree phase, thus generating a third harmonic subcomponent of size 3. rd The size of _HD_sub The third harmonic component with a phase of 45 degrees is twice that of the third harmonic component. rd _HD. Therefore, the SC-DAC 160 needs to generate a third harmonic sub-component of size 3. rd The size of _HD_sub The inverting component IPC, with a phase difference of 225 degrees, is used to remove the third harmonic component. rd _HD. For example, the SC-DAC 160 can generate a third harmonic subcomponent of size 3. rd The size of _HD_sub A signal with a phase of 315 degrees can be generated from this signal, and an inverted component IPC with a phase of 225 degrees can be generated from this signal, which is three times the phase of 315 degrees.

[0061] Figure 4 This is a block diagram of a pattern signal generator 140_1 according to an example embodiment. Figures 5A to 5C It is used to describe Figure 4 Timing diagram of the operation of the pattern signal generator 140_1.

[0062] Reference Figure 4The pattern signal generator 140_1 may include a clock signal generation circuit 142_1 and a signal multiplication circuit 144_1. The clock signal generation circuit 142_1 can generate multiple clock signals CLK with target frequency, target duty cycle, and different phases by dividing a frequency signal F_S with a specific frequency. In an example embodiment, the clock signal generation circuit 142_1 can generate clock signals CLK with phases of 0 degrees, 45 degrees, 90 degrees, 135 degrees, 180 degrees, 225 degrees, 270 degrees, and 315 degrees, respectively, and a duty cycle of 1 / 4, such as... Figures 5A to 5C As shown, the target frequency of the clock signal CLK can be adjusted according to the RF band, and the clock signal CLK can be used to upconvert the frequency of the baseband digital signal to an RF band analog signal.

[0063] The signal multiplication circuit 144_1 can receive I binary data I[1] to I[k], Q binary data Q[1] to Q[k], inverted I binary data IB[1] to IB[k], and inverted Q binary data Q[1] to Q[k] bit by bit in parallel. The signal multiplication circuit 144_1 can multiply the clock signal CLK with I binary data I[1] to I[k], Q binary data Q[1] to Q[k], inverted I binary data IB[1] to IB[k], and inverted Q binary data Q[1] to Q[k], thereby generating multiple first mode signals PT_S1[1] to PT_S1[k], multiple second mode signals PT_S2[1] to PT_S2[k], and multiple third mode signals PT_S3[1] to PT_S3[k] bit by bit. As mentioned above, the first mode signals PT_S1[1] to PT_S1[k] can be input to Figure 2 In the first SC-DAC circuit 162a, the second mode signals PT_S2[1] to PT_S2[k] can be input to... Figure 2 The second SC-DAC circuit 164a in the middle, the third mode signals PT_S3[1] to PT_S3[k] can be input to Figure 2 The third SC-DAC circuit 166a in the example.

[0064] Further reference Figure 5AThe signal multiplication circuit 144_1 can multiply the clock signal CLK(0°) with 0-degree phase by I binary data I[k], the clock signal CLK(90°) with 90-degree phase by Q binary data Q[k], the clock signal CLK(180°) with 180-degree phase by inverted I binary data IB[k], and the clock signal CLK(270°) with 270-degree phase by inverted Q binary data QB[k], thereby generating multiplication result signals MR_S1 to MR_S4. The signal multiplication circuit 144_1 can generate the first mode signal PT_S1[k] by summing the multiplication result signals MR_S1 to MR_S4.

[0065] When the signal multiplication circuit 144_1 receives I binary data I[k], Q binary data Q[k], inverted I binary data IB[k], and inverted Q binary data QB[k] with values ​​“1”, “1”, “0”, and “0” respectively within the first interval INT1, the signal multiplication circuit 144_1 can generate a first mode signal PT_S1[k] with a first mode PT_11. When the signal multiplication circuit 144_1 receives I binary data I[k], Q binary data Q[k], inverted I binary data IB[k], and inverted Q binary data QB[k] with values ​​“1”, “0”, “0”, and “1” respectively within the second interval INT2, the signal multiplication circuit 144_1 can generate a first mode signal PT_S1[k] with a second mode PT_12. When the signal multiplication circuit 144_1 receives I binary data I[k], Q binary data Q[k], inverted I binary data IB[k], and inverted Q binary data QB[k] with values ​​“0”, “0”, “1”, and “1” respectively within the third interval INT3, the signal multiplication circuit 144_1 can generate a first mode signal PT_S1[k] with a third mode PT_13. When the signal multiplication circuit 144_1 receives I binary data I[k], Q binary data Q[k], inverted I binary data IB[k], and inverted Q binary data QB[k] with values ​​“0”, “1”, “1”, and “0” respectively within the fourth interval INT4, the signal multiplication circuit 144_1 can generate a first mode signal PT_S1[k] with a fourth mode PT_14.

[0066] Further reference Figure 5BThe signal multiplication circuit 144_1 can multiply a clock signal CLK (45°) with a 45-degree phase by I binary data I[k], a clock signal CLK (135°) with a 135-degree phase by Q binary data Q[k], a clock signal CLK (225°) with a 225-degree phase by inverted I binary data IB[k], and a clock signal CLK (315°) with a 315-degree phase by inverted Q binary data QB[k], thereby generating multiplication result signals MR_S1 to MR_S4. The signal multiplication circuit 144_1 can generate a second mode signal PT_S2[k] by adding the multiplication result signals MR_S1 to MR_S4.

[0067] When the signal multiplication circuit 144_1 receives I binary data I[k], Q binary data Q[k], inverted I binary data IB[k], and inverted Q binary data QB[k] with values ​​“1”, “1”, “0”, and “0” respectively within the first interval INT1, the signal multiplication circuit 144_1 can generate a second-mode signal PT_S2[k] with a first mode PT_21. When the signal multiplication circuit 144_1 receives I binary data I[k], Q binary data Q[k], inverted I binary data IB[k], and inverted Q binary data QB[k] with values ​​“1”, “0”, “0”, and “1” respectively within the second interval INT2, the signal multiplication circuit 144_1 can generate a second-mode signal PT_S2[k] with a second mode PT_22. When the signal multiplication circuit 144_1 receives I binary data I[k], Q binary data Q[k], inverted I binary data IB[k], and inverted Q binary data QB[k] with values ​​“0”, “0”, “1”, and “1” respectively within the third interval INT3, the signal multiplication circuit 144_1 can generate a second-mode signal PT_S2[k] with a third mode PT_23. When the signal multiplication circuit 144_1 receives I binary data I[k], Q binary data Q[k], inverted I binary data IB[k], and inverted Q binary data QB[k] with values ​​“0”, “1”, “1”, and “0” respectively within the fourth interval INT4, the signal multiplication circuit 144_1 can generate a second-mode signal PT_S2[k] with a fourth mode PT_24.

[0068] Further reference Figure 5CThe signal multiplication circuit 144_1 can multiply the clock signal CLK(90°) with 90-degree phase by I binary data I[k], the clock signal CLK(180°) with 180-degree phase by Q binary data Q[k], the clock signal CLK(270°) with 270-degree phase by inverted I binary data IB[k], and the clock signal CLK(0°) with 0-degree phase by inverted Q binary data QB[k], thereby generating multiplication result signals MR_S1 to MR_S4. The signal multiplication circuit 144_1 can generate the third mode signal PT_S3[k] by adding the multiplication result signals MR_S1 to MR_S4.

[0069] When the signal multiplication circuit 144_1 receives I binary data I[k], Q binary data Q[k], inverted I binary data IB[k], and inverted Q binary data QB[k] with values ​​“1”, “1”, “0”, and “0” respectively within the first interval INT1, the signal multiplication circuit 144_1 can generate a third-mode signal PT_S3[k] with a first mode PT_31. When the signal multiplication circuit 144_1 receives I binary data I[k], Q binary data Q[k], inverted I binary data IB[k], and inverted Q binary data QB[k] with values ​​“1”, “0”, “0”, and “1” respectively within the second interval INT2, the signal multiplication circuit 144_1 can generate a third-mode signal PT_S3[k] with a second mode PT_32. When the signal multiplication circuit 144_1 receives I binary data I[k], Q binary data Q[k], inverted I binary data IB[k], and inverted Q binary data QB[k] with values ​​“0”, “0”, “1”, and “1” respectively within the third interval INT3, the signal multiplication circuit 144_1 can generate a third-mode signal PT_S3[k] with a third mode PT_33. When the signal multiplication circuit 144_1 receives I binary data I[k], Q binary data Q[k], inverted I binary data IB[k], and inverted Q binary data QB[k] with values ​​“0”, “1”, “1”, and “0” respectively within the fourth interval INT4, the signal multiplication circuit 144_1 can generate a third-mode signal PT_S3[k] with a fourth mode PT_34.

[0070] Therefore, the signal multiplication circuit 144_1 can generate a first mode signal PT_S1[k], a second mode signal PT_S2[k] whose phase lags behind the first mode signal PT_S1[k] by 45 degrees, and a third mode signal PT_S3[k] whose phase lags behind the first mode signal PT_S1[k] by 90 degrees.

[0071] According to the example embodiment, even when the I binary data I[k] or Q binary data Q[k] has a value of "0", its direction can still be represented by its phase. Therefore, when the signal multiplication circuit 144_1 generates the mode signal, in addition to the I binary data I[k] and Q binary data Q[k] (or the IQ binary data pair), inverted I binary data IB[k] and inverted Q binary data QB[k] (or the inverted IQ binary data pair) are also used. Thus, according to the example embodiment, the digital RF transmitter can generate an inverted component with the opposite phase to the third harmonic component (or the odd harmonic component).

[0072] Figure 6 These are circuit diagrams of the first to third SC-DAC circuits 162a_1, 164a_1 and 166a_1 according to the example embodiments.

[0073] The first SC-DAC circuit 162a_1 may include a plurality of first amplifiers AMP1a to AMPka and a plurality of first capacitors C1a to Cka. Each of the first amplifiers AMP1a to AMPka and each of the first capacitors C1a to Cka may form a path through which a corresponding first mode signal among the first mode signals PT_S1[1] to PT_S1[k] is transmitted. In other words, the first SC-DAC circuit 162a_1 may include a plurality of paths through which the first mode signals PT_S1[1] to PT_S1[k] are transmitted, and a first RF signal RF1 may be output from the first mode signals PT_S1[1] to PT_S1[k].

[0074] The second SC-DAC circuit 164a_1 may include multiple second amplifiers AMP1b to AMPkb and multiple second capacitors C1b to Ckb. Each of the second amplifiers AMP1b to AMPkb and each of the second capacitors C1b to Ckb may form a path through which a corresponding second mode signal among the second mode signals PT_S2[1] to PT_S2[k] is transmitted. In other words, the second SC-DAC circuit 164a_1 may include multiple paths through which the second mode signals PT_S2[1] to PT_S2[k] are transmitted, and a second RF signal RF2 may be output from the second mode signals PT_S2[1] to PT_S2[k].

[0075] The third SC-DAC circuit 166a_1 may include multiple third amplifiers AMP1c to AMPkc and multiple third capacitors C1c to Ckc. Each of the third amplifiers AMP1c to AMPkc and each of the third capacitors C1c to Ckc may form a path through which a corresponding third mode signal among the third mode signals PT_S3[1] to PT_S3[k] is transmitted. In other words, the third SC-DAC circuit 166a_1 may include multiple paths through which the third mode signals PT_S3[1] to PT_S3[k] are transmitted, and a third RF signal RF3 may be output from the third mode signals PT_S3[1] to PT_S3[k]. The first RF signal RF1 to the third RF signal RF3 may be summed, and the summed RF signal may be used as an RF analog signal RF through the first output terminal 167a_1. OUT Output.

[0076] In an example embodiment, the capacitance of the second capacitors C1b to Ckb can be "m" times the capacitance of the first capacitors C1a to Cka and the third capacitors C1c to Ckc, where "m" is a real number at least 1. For example, when "m" is In this case, the capacitance of capacitor Ckb in the second SC-DAC circuit 164a_1 can be the capacitance of each of capacitor Cka in the first SC-DAC circuit 162a_1 and capacitor Ckc in the third SC-DAC circuit 166a_1. In other words, the equivalent capacitance of the second SC-DAC circuit 164a_1 can be times the equivalent capacitance of each of the first SC-DAC circuit 162a_1 and the third SC-DAC circuit 166a_1. Times. The following will refer to... Figure 8 The reasons for the capacitor configuration of the first to third SC-DAC circuits 162a_1, 164a_1 and 166a_1 are described in detail.

[0077] exist Figure 6In this configuration, the first to third capacitors C1a to Cka, C1b to Ckb, and C1c to Ckc can each include multiple unit capacitors. A unit capacitor can be an element with a specific capacitance. In an example embodiment, the number of unit capacitors in capacitor Ckb forming the second SC-DAC circuit 164a_1 can be greater than the number of unit capacitors in each of the capacitors Cka forming the first SC-DAC circuit 162a_1 and Ckc forming the third SC-DAC circuit 166a_1. For example, the number of unit capacitors in capacitor Ckb forming the second SC-DAC circuit 164a_1 can be seven, while the number of unit capacitors in each of the capacitors Cka forming the first SC-DAC circuit 162a_1 and Ckc forming the third SC-DAC circuit 166a_1 can be five. With this configuration, the capacitance of the second capacitors C1b to Ckb can be the capacitance of each of the first capacitors C1a to Cka and the third capacitors C1c to Ckc. times.

[0078] The phase of the first mode signals PT_S1[1] to PT_S1[k] input to the first SC-DAC circuit 162a_1 can be 45 degrees ahead of the phase of the second mode signals PT_S2[1] to PT_S2[k] input to the second SC-DAC circuit 164a_1, and 90 degrees ahead of the phase of the third mode signals PT_S3[1] to PT_S3[k] input to the third SC-DAC circuit 166a_1.

[0079] Figure 6 The first to third SC-DAC circuits 162a_1, 164a_1 and 166a_1 shown are merely examples and can be implemented in various ways to convert digital signals into analog signals, and are not limited to this example.

[0080] Figure 7 This is a diagram illustrating a method for determining the magnitude of a first RF signal RF1 in a first SC-DAC circuit 162a_2, according to an example embodiment. The following description can also be applied to other SC-DAC circuits. Figure 7 The first SC-DAC circuit 162a_2 is merely an example and can be implemented in various ways, and is not limited to this example.

[0081] Reference Figure 7The first SC-DAC circuit 162a_2 may include multiple amplifiers AMP1a to AMP3a and multiple capacitors C1a to C3a. First mode signals PT_S1[1] to PT_S1[3] can all pass through a path including one of the amplifiers AMP1a to AMP3a and one of the capacitors C1a to C3a. Based on the mode of each of the first mode signals PT_S1[1] to PT_S1[3], the level of the first RF signal RF1 can be determined as one of the first level LV1 to the fourth level LV4. In other words, through the first SC-DAC circuit 162a_2, different modes of the first mode signals PT_S1[1] to PT_S1[3] can be represented by different magnitudes of the first RF signal RF1. In this way, digital signals can be converted into analog signals. (See above reference...) Figure 6 As described, each of the capacitors C1a to C3a may include multiple unit capacitors.

[0082] Figure 8 It is used to describe Figure 6 The equivalent capacitor Ca of the first to third SC-DAC circuits 162a_1, 164a_1 and 166a_1 in the middle EQ Cb EQ and Cc EQ The illustration.

[0083] Reference Figure 8 The output of each of the first to third SC-DAC circuits 162a_1, 164a_1, and 166a_1 can be connected to the first output terminal 167a_1, and the equivalent capacitor Ca of the first to third SC-DAC circuits 162a_1, 164a_1, and 166a_1 EQ Cb EQ and Cc EQ The capacitance ratio between them can be 1:m:1. Therefore, the magnitude ratio between the first to third RF signals RF1 to RF3, which correspond to the first to third mode signals PT_S1, PT_S2, and PT_S3 respectively, having the same mode, can be 1:m:1. As mentioned above, the equivalent capacitor Ca EQ Cb EQ and Cc EQ Each can include multiple unit capacitors.

[0084] The second RF signal RF2 output from the second SC-DAC circuit 164a_1 may include a frequency component corresponding to the inverted component used to remove the third harmonic component (or odd harmonic component). The magnitude of the second RF signal RF2 may be "m" times the magnitude of each of the first RF signal RF1 and the third RF signal RF3. In the example embodiment, "m" may be... or approximately The real number.

[0085] Figure 9 It is used to describe what is applied to Figure 6 A diagram showing the power supply voltages of each of the first to third amplifiers AMP1a to AMPka, AMP1b to AMPkb, and AMP1c to AMPkc in the first to third SC-DAC circuits 162a_1, 164a_1, and 166a_1.

[0086] Reference Figure 9 Voltage regulator 170_1 can generate a first power supply voltage V1 and a second power supply voltage V2 from a specific power supply voltage, such that the second power supply voltage V2 has a different level than the first power supply voltage V1. For example, the first power supply voltage V1 can be greater than the second power supply voltage V2, and voltage regulator 170_1 can apply the first power supply voltage V1 to the second amplifiers AMP1b to AMPkb, and apply the second power supply voltage V2 to the first amplifiers AMP1a to AMPka and the third amplifiers AMP1c to AMPkc. Therefore, the second amplifiers AMP1b to AMPkb can amplify the received signal more than the first amplifiers AMP1a to AMPka and the third amplifiers AMP1c to AMPkc.

[0087] As mentioned above, in practice, it may be difficult to convert the equivalent capacitor Ca of the first to third SC-DAC circuits 162a_1, 164a_1, and 166a_1. EQ Cb EQ and Cc EQ The capacitance ratio between them is realized as like Figure 8 As shown in the example embodiment. By Figure 9 The example implementation can solve these problems in the actual process, and it generates an inverted component with the same magnitude as the third harmonic component.

[0088] Figure 10 It is used to describe through the Figure 6 The RF analog signal RF is generated by summing the first RF signal RF1 to the third RF signal RF3. OUT The diagrams illustrate modes PT_1 through PT_4. For clearer understanding, please refer to... Figure 10 The following scenario is described: a first mode signal (e.g., first mode signal PT_S1[k]) and a second mode signal PT_S2[k] and a third mode signal PT_S3[k] corresponding to the first mode signal PT_S1[k] are respectively input to the first to third SC-DAC circuits 162a_1, 164a_1 and 166a_1.

[0089] Reference Figure 6 and Figure 10 When the IQ binary data pair pattern is "1,1", the first to third SC-DAC circuits 162a_1, 164a_1, and 166a_1 can respectively output the first RF signal RF1 to the third RF signal RF3, and have the first mode PT_1 RF analog signal RF OUT It can be output through the first output terminal 167a_1. When the IQ binary data pair mode is "1,0", the first to third SC-DAC circuits 162a_1, 164a_1 and 166a_1 can respectively output the first RF signal RF1 to the third RF signal RF3, and have the second mode PT_2 RF analog signal RF OUT It can be output through the first output terminal 167a_1. When the IQ binary data pair mode is "0,0", the first to third SC-DAC circuits 162a_1, 164a_1 and 166a_1 can respectively output the first RF signal RF1 to the third RF signal RF3, and have the third mode PT_3 RF analog signal RF OUT It can be output through the first output terminal 167a_1. When the IQ binary data pair mode is "0,1", the first to third SC-DAC circuits 162a_1, 164a_1 and 166a_1 can respectively output the first RF signal RF1 to the third RF signal RF3, and have a fourth mode PT_4 RF analog signal RF. OUT It can be output through the first output terminal 167a_1.

[0090] In an example embodiment, the phase of the first RF signal RF1 can be 45 degrees ahead of the phase of the second RF signal RF2, and 90 degrees ahead of the phase of the third RF signal RF3. The magnitude of the second RF signal RF2 can be the magnitude of each of the first RF signal RF1 and the third RF signal RF3. times.

[0091] like Figure 10 As shown, the RF analog signal can be pre-determined based on the IQ binary data. OUT The first mode PT_1 to the fourth mode PT_4, therefore, can generate an RF analog signal corresponding to each IQ binary data pair by pre-generating multiple clock signals with different duty cycles and combining the clock signals according to the IQ binary data pairs. OUT . will refer to Figure 11 This will be described.

[0092] Figure 11 This is a block diagram of the pattern signal generator 140_2 according to an example embodiment.

[0093] Reference Figure 10 and Figure 11 The mode signal generator 140_2 may include a clock signal generation circuit 142_2, a mode signal output circuit 144_2, and a multiplexer 144_5. The clock signal generation circuit 142_2 can generate a clock signal CLK having a target frequency (or carrier frequency), a target duty cycle, and different phases from each other by dividing a frequency signal F_S having a specific frequency. The mode signal output circuit 144_2 can be configured to generate first to third mode signals using at least one clock signal CLK.

[0094] The mode signal output circuit 144_2 may include a control circuit 144_3 and a first signal generation circuit 144_4a to a fourth signal generation circuit 144_4d. The first signal generation circuit 144_4a to the fourth signal generation circuit 144_4d can all output the mode signal. Figure 10 The signal is one of the first mode PT_1 to the fourth mode PT_4. For example, the first signal generation circuit 144_4a can generate the component signal forming the first mode PT_1, the second signal generation circuit 144_4b can generate the component signal forming the second mode PT_2, the third signal generation circuit 144_4c can generate the component signal forming the third mode PT_3, and the fourth signal generation circuit 144_4d can generate the component signal forming the fourth mode PT_4.

[0095] The control circuit 144_3 can receive I binary data I[1] to I[k] and Q binary data Q[1] to Q[k] bit by bit in parallel, and can control the first signal generation circuit 144_4a to the fourth signal generation circuit 144_4d and the multiplexer 144_5 so that the component signals of the modes corresponding to the IQ binary data pairs in the first mode PT_1 to the fourth mode PT_4 are output as the first mode signals PT_S1[1] to PT_S1[k], the second mode signals PT_S2[1] to PT_S2[k] and the third mode signals PT_S3[1] to PT_S3[k]. For example, control circuit 144_3 can control the activation of the first signal generation circuit 144_4a to the fourth signal generation circuit 144_4d, and can control multiplexer 144_5 such that each component signal generated by each of the first signal generation circuit 144_4a to the fourth signal generation circuit 144_4d is output to the SC-DAC circuit allocated to each component signal. In some example embodiments, all of the first signal generation circuit 144_4a to the fourth signal generation circuit 144_4d can be activated to pre-generate component signals, and control circuit 144_3 can control multiplexer 144_5 to output each component signal to the SC-DAC circuit allocated to it.

[0096] For example, when the I binary data I[k] and Q binary data Q[k] corresponding to the bit index "k" are "1,1", the first signal generation circuit 144_4a can output the first component signal with a first duty cycle as the first mode signal PT_S1[k], the second component signal with a second duty cycle as the second mode signal PT_S2[k], and the third component signal with a third duty cycle as the third mode signal PT_S3[k]. In the example embodiment, the first duty cycle can be 1 / 4, the second duty cycle can be 1 / 2, and the third duty cycle can be 3 / 4.

[0097] In another example, the component signals can have different phases. Therefore, when the set of I binary data I[k] and Q binary data Q[k] corresponding to bit index "k" is "1,1", the first signal generation circuit 144_4a can generate the first to third component signals for generating the first mode PT_1. When the I binary data I[k_1] and Q binary data Q[k_1] corresponding to bit index k_1 are "1,0", the second signal generation circuit 144_4b can generate the fourth to sixth component signals for generating the second mode PT_2. When the I binary data I[k_2] and Q binary data Q[k_2] corresponding to bit index k_2 are "0,0", the third signal generation circuit 144_4c can generate the seventh to ninth component signals for generating the third mode PT_3. When the I binary data I[k_3] and Q binary data Q[k_3] corresponding to bit index k_3 are “0,1”, the fourth signal generation circuit 144_4d can generate the tenth to twelfth component signals for generating the fourth mode PT_4.

[0098] As described above, by configuring the mode signal generator 140_2 of the SC-DAC to output the component signals that have been pre-determined according to the pattern of the IQ binary data pair, it is possible to achieve the following: Figure 10 RF analog signal in OUT Outputting data can improve communication performance and simplify the structure.

[0099] Figure 12A Is with Figure 11 The block diagram of the first signal generation circuit 144_4a_1 corresponding to the first signal generation circuit 144_4a in the diagram. Figure 12B It is shown by Figure 12A A diagram showing the RF analog signal generated by the first signal generation circuit 144_4a_1. Figure 12C yes Figure 12AA diagram illustrating an example implementation of the first to third component signal generation logics 144_41a, 144_42a, and 144_43a.

[0100] Reference Figure 12A The first signal generation circuit 144_4a_1 may include first component signal generation logic 144_41a to third component signal generation logic 144_43a. The first component signal generation logic 144_41a to the third component signal generation logic 144_43a can respectively output signals to form... Figure 10 The first to third component signals CC11, CC21, and CC31 of the first mode PT_1. The output of each of the first component signal generation logics 144_41a to the third component signal generation logics 144_43a can be connected to the multiplexer 144_3_1.

[0101] The multiplexer 144_3_1 can be based on Figure 11 The control signal of the control circuit 144_3 selects and outputs the first component signal CC11 as the first mode signal among the first mode signals PT_S1[1] to PT_S1[k] corresponding to the mode of the IQ binary data pair, wherein the control signal corresponds to the mode of the IQ binary data pair. The multiplexer 144_3_1 can select and output the second component signal CC21 as the second mode signal among the second mode signals PT_S2[1] to PT_S2[k] corresponding to the mode of the IQ binary data pair based on the control signal. The multiplexer 144_3_1 can select and output the third component signal CC31 as the third mode signal among the third mode signals PT_S3[1] to PT_S3[k] corresponding to the mode of the IQ binary data pair based on the control signal. In other words, the multiplexer 144_3_1 can be configured to selectively connect at least one of the first component signal generation logic 144_41a to the third component signal generation logic 144_43a to the SC-DAC 160 in an IQ binary data pair-based mode.

[0102] Further reference Figure 12B The first component signal CC11 can have a 1 / 4 duty cycle, the second component signal CC21 can have a 1 / 2 duty cycle, and the third component signal CC31 can have a 3 / 4 duty cycle. The first component signal CC11 to the third component signal CC31 can have the same frequency (e.g., the carrier frequency of an RF analog signal). Each of the first component signal CC11 to the third component signal CC31 can have a specific phase difference with each other, such as... Figure 12B As shown, this makes the RF analog signal RF OUT It can have Figure 10The first mode PT_1 in the example embodiment. In the example embodiment, the second component signal CC21 has been passed through Figure 6 The magnitude of the second RF signal RF2 generated by the second SC-DAC circuit 164a_1 in the circuit can be that the first component signal CC11 has already passed through Figure 6 The first RF signal RF1 generated by the first SC-DAC circuit 162a_1 and the third component signal CC31 have already passed through Figure 6 The magnitude of each of the third RF signals RF3 generated by the third SC-DAC circuit 166a_1 in the circuit. times.

[0103] Further reference Figure 12C The first component signal generation logic 144_41a may include a first inverter IVT1 and a second inverter IVT2. A clock signal CLK(45°) with a duty cycle of 1 / 4 and a phase of 45 degrees is input to the first inverter IVT1. The second component signal generation logic 144_42a may include a first OR logic OR1, a third inverter IVT3, and a fourth inverter IVT4. Clock signals CLK(0°) with a duty cycle of 1 / 4 and a phase of 0 degrees and clock signals CLK(90°) with a duty cycle of 1 / 4 and a phase of 90 degrees are input to the first OR logic OR1. The third component signal generation logic 144_43a may include a fifth inverter IVT5, a sixth inverter IVT6, and a seventh inverter IVT7. A clock signal CLK(225°) with a duty cycle of 1 / 4 and a phase of 225 degrees is input to the fifth inverter IVT5. The first component signal generation logic 144_41a to the third component signal generation logic 144_43a can generate the first component signal CC11 to the third component signal CC31 respectively.

[0104] Figure 13A Is with Figure 11 The block diagram of the second signal generation circuit 144_4b_1 corresponding to the second signal generation circuit 144_4b in the diagram. Figure 13B It is shown by Figure 13A A diagram showing the RF analog signal generated by the second signal generation circuit 144_4b_1. Figure 13C yes Figure 13A A diagram illustrating an example implementation of the fourth to sixth component signal generation logics 144_41b, ​​144_42b, and 144_43b.

[0105] Reference Figure 13A The second signal generation circuit 144_4b_1 may include fourth component signal generation logic 144_41b to sixth component signal generation logic 144_43b. The fourth component signal generation logic 144_41b to the sixth component signal generation logic 144_43b can respectively output signals to form... Figure 10 The fourth to sixth component signals CC12, CC22, and CC32 in the second mode PT_2. The output of each of the fourth component signal generation logic 144_41b to the sixth component signal generation logic 144_43b can be connected to the multiplexer 144_3_1.

[0106] The multiplexer 144_3_1 can be based on Figure 11 The control signal of the control circuit 144_3 selects and outputs the fourth component signal CC12 as the first mode signal among the first mode signals PT_S1[1] to PT_S1[k] corresponding to the mode of the IQ binary data pair, wherein the control signal corresponds to the mode of the IQ binary data pair. The multiplexer 144_3_1 can select and output the fifth component signal CC22 as the second mode signal among the second mode signals PT_S2[1] to PT_S2[k] corresponding to the mode of the IQ binary data pair based on the control signal. The multiplexer 144_3_1 can select and output the sixth component signal CC32 as the third mode signal among the third mode signals PT_S3[1] to PT_S3[k] corresponding to the mode of the IQ binary data pair based on the control signal.

[0107] Further reference Figure 13B The fourth component signal CC12 can have a 1 / 4 duty cycle, the fifth component signal CC22 can have a 1 / 2 duty cycle, and the sixth component signal CC32 can have a 3 / 4 duty cycle. The fourth component signal CC12 to the sixth component signal CC32 can have the same frequency (e.g., the carrier frequency of an RF analog signal). Each of the fourth component signal CC12 to the sixth component signal CC32 can have a specific phase difference from each other, such as... Figure 13B As shown, this makes the RF analog signal RF OUT It can have Figure 10 The second mode PT_2 in the example embodiment. In the example embodiment, the fifth component signal CC22 has been passed through Figure 6 The magnitude of the second RF signal RF2 generated by the second SC-DAC circuit 164a_1 can be determined after the fourth component signal CC12 has passed through... Figure 6 The first RF signal RF1 generated by the first SC-DAC circuit 162a_1 and the sixth component signal CC32 have already passed through Figure 6 The magnitude of each of the third RF signals RF3 generated by the third SC-DAC circuit 166a_1 in the circuit. times.

[0108] Further reference Figure 13CThe fourth component signal generation logic 144_41b may include an eighth inverter IVT8 and a ninth inverter IVT9. A clock signal CLK(315°) with a duty cycle of 1 / 4 and a phase of 315 degrees is input to the eighth inverter IVT8. The fifth component signal generation logic 144_42b may include a second OR logic OR2, a tenth inverter IVT10, and an eleventh inverter IVT11. A clock signal CLK(270°) with a duty cycle of 1 / 4 and a phase of 270 degrees and a clock signal CLK(0°) with a duty cycle of 1 / 4 and a phase of 0 degrees are input to the second OR logic OR2. The sixth component signal generation logic 144_43b may include a twelfth inverter IVT12, a thirteenth inverter IVT13, and a fourteenth inverter IVT14. A clock signal CLK (135°) with a duty cycle of 1 / 4 and a phase of 135 degrees is input to the twelfth inverter IVT12. The fourth component signal generation logic 144_41b to the sixth component signal generation logic 144_43b can generate the fourth component signal CC12 to the sixth component signal CC32 respectively.

[0109] Figure 14A Is with Figure 11 The block diagram of the third signal generation circuit 144_4c_1 corresponding to the third signal generation circuit 144_4c in the diagram. Figure 14B It is shown by Figure 14A A diagram illustrating the RF analog signal generated by the third signal generation circuit 144_4c_1. Figure 14C yes Figure 14A A diagram illustrating an example implementation of the seventh to ninth component signal generation logics 144_41c, 144_42c, and 144_43c.

[0110] Reference Figure 14A The third signal generation circuit 144_4c_1 may include seventh component signal generation logic 144_41c to ninth component signal generation logic 144_43c. The seventh component signal generation logic 144_41c to the ninth component signal generation logic 144_43c can respectively output signals to form... Figure 10 The seventh to ninth component signals CC13, CC23, and CC33 of the third mode PT_4. The output of each of the seventh component signal generation logics 144_41c to the ninth component signal generation logics 144_43c can be connected to the multiplexer 144_3_1.

[0111] The multiplexer 144_3_1 can be based on Figure 11The control signal of the control circuit 144_3 selects and outputs the seventh component signal CC13 as the first mode signal among the first mode signals PT_S1[1] to PT_S1[k] corresponding to the mode of the IQ binary data pair, wherein the control signal corresponds to the mode of the IQ binary data pair. The multiplexer 144_3_1 can select and output the eighth component signal CC23 as the second mode signal among the second mode signals PT_S2[1] to PT_S2[k] corresponding to the mode of the IQ binary data pair based on the control signal. The multiplexer 144_3_1 can select and output the ninth component signal CC33 as the third mode signal among the third mode signals PT_S3[1] to PT_S3[k] corresponding to the mode of the IQ binary data pair based on the control signal.

[0112] Further reference Figure 14B The seventh component signal CC13 can have a 3 / 4 duty cycle, the eighth component signal CC23 can have a 1 / 2 duty cycle, and the ninth component signal CC33 can have a 1 / 4 duty cycle. The seventh to ninth component signals CC13 can have the same frequency, i.e., the carrier frequency of the RF analog signal. Each of the seventh to ninth component signals CC33 can have a specific phase difference from each other, such as... Figure 14B As shown, this makes the RF analog signal RF OUT It can have Figure 10 The third mode PT_3 in the example embodiment. In the example embodiment, the eighth component signal CC23 has been passed through... Figure 6 The magnitude of the second RF signal RF2 generated by the second SC-DAC circuit 164a_1 can be determined after the seventh component signal CC13 has passed through... Figure 6 The first RF signal RF1 generated by the first SC-DAC circuit 162a_1 and the ninth component signal CC33 have already passed through Figure 6 The magnitude of each of the third RF signals RF3 generated by the third SC-DAC circuit 166a_1 in the circuit. times.

[0113] Further reference Figure 14CThe seventh component signal generation logic 144_41c may include a fifteenth inverter IVT15, to which a clock signal CLK(45°) with a duty cycle of 1 / 4 and a phase of 45 degrees is input. The eighth component signal generation logic 144_42c may include a third OR logic OR3 and a sixteenth inverter IVT16. Clock signals CLK(0°) with a duty cycle of 1 / 4 and a phase of 0 degrees and CLK(90°) with a duty cycle of 1 / 4 and a phase of 90 degrees are input to the third OR logic OR3. The ninth component signal generation logic 144_43c may include a seventeenth inverter IVT17 and an eighteenth inverter IVT18. A clock signal CLK(225°) with a duty cycle of 1 / 4 and a phase of 225 degrees is input to the seventeenth inverter IVT17. The seventh component signal generation logic 144_41c to the ninth component signal generation logic 144_43c can generate the seventh component signal CC13 to the ninth component signal CC33 respectively.

[0114] Figure 15A Is with Figure 11 The block diagram of the fourth signal generation circuit 144_4d_1 corresponding to the fourth signal generation circuit 144_4d in the diagram. Figure 15B It is shown by Figure 15A A diagram showing the RF analog signal generated by the fourth signal generation circuit 144_4d_1. Figure 15C yes Figure 15A A diagram illustrating an example implementation of the signal generation logics 144_41d, 144_42d, and 144_43d for the tenth to twelfth components.

[0115] Reference Figure 15A The fourth signal generation circuit 144_4d_1 may include the tenth component signal generation logic 144_41d to the twelfth component signal generation logic 144_43d. The tenth component signal generation logic 144_41d to the twelfth component signal generation logic 144_43d can respectively output to form... Figure 10 The tenth to twelfth component signals CC14, CC24, and CC34 of the fourth mode PT_4. The output of each of the tenth component signal generation logic 144_41d to the twelfth component signal generation logic 144_43d can be connected to the multiplexer 144_3_1.

[0116] The multiplexer 144_3_1 can be based on Figure 11The control signal of the control circuit 144_3 selects and outputs the tenth component signal CC14 as the first mode signal among the first mode signals PT_S1[1] to PT_S1[k] corresponding to the mode of the IQ binary data pair, wherein the control signal corresponds to the mode of the IQ binary data pair. The multiplexer 144_3_1 can select and output the eleventh component signal CC24 as the second mode signal among the second mode signals PT_S2[1] to PT_S2[k] corresponding to the mode of the IQ binary data pair based on the control signal. The multiplexer 144_3_1 can select and output the twelfth component signal CC34 as the third mode signal among the third mode signals PT_S3[1] to PT_S3[k] corresponding to the mode of the IQ binary data pair based on the control signal.

[0117] Further reference Figure 15B The tenth component signal CC14 can have a 3 / 4 duty cycle, the eleventh component signal CC24 can have a 1 / 2 duty cycle, and the twelfth component signal CC34 can have a 1 / 4 duty cycle. The tenth to twelfth component signals CC14 to CC34 can have the same frequency, i.e., the carrier frequency of the RF analog signal. Each of the tenth to twelfth component signals CC14 to CC34 can have a specific phase difference from each other, such as... Figure 15B As shown, this makes the RF analog signal RF OUT It can have Figure 10 The fourth mode, PT_4, is used in the example embodiment where the eleventh component signal CC24 has already passed through... Figure 6 The magnitude of the second RF signal RF2 generated by the second SC-DAC circuit 164a_1 can be such that the tenth component signal CC14 has already passed through... Figure 6 The first RF signal RF1 generated by the first SC-DAC circuit 162a_1 and the twelfth component signal CC34 have already passed through Figure 6 The magnitude of each of the third RF signals RF3 generated by the third SC-DAC circuit 166a_1 in the circuit. times.

[0118] Further reference Figure 15CThe tenth component signal generation logic 144_41d may include a nineteenth inverter IVT19, to which a clock signal CLK(315°) with a duty cycle of 1 / 4 and a phase of 315 degrees is input. The eleventh component signal generation logic 144_42d may include a fourth OR logic OR4 and a twentieth inverter IVT20. Clock signals CLK(270°) with a duty cycle of 1 / 4 and a phase of 270 degrees and clock signals CLK(0°) with a duty cycle of 1 / 4 and a phase of 0 degrees are input to the fourth OR logic OR4. The twelfth component signal generation logic 144_43d may include a twenty-first inverter IVT21 and a twenty-second inverter IVT22. Clock signals CLK(135°) with a duty cycle of 1 / 4 and a phase of 135 degrees are input to the twenty-first inverter IVT21. The tenth component signal generation logic 144_41d to the twelfth component signal generation logic 144_43d can generate the tenth component signal CC14 to the twelfth component signal CC34 respectively.

[0119] Figure 16 This is a diagram illustrating the operation of the SC-DAC 160_3 according to an example embodiment.

[0120] Reference Figure 16 The SC-DAC 160_3 may include first to third SC-DAC circuits 162a_3, 164a_3, and 166a_3, and outputs an RF analog signal RF generated by the sum of the first to third RF signals output from the first to third SC-DAC circuits 162a_3, 164a_3, and 166a_3, respectively. OUT In the example embodiment, the first SC-DAC circuit 162a_3 can output a first RF signal with a rectangular pulse at a 1 / 4 duty cycle during the time period from the third time t3 to the fourth time t4; the second SC-DAC circuit 164a_3 can output a second RF signal with a rectangular pulse at a 1 / 2 duty cycle during the time period from the second time t2 to the fifth time t5; and the third SC-DAC circuit 166a_3 can output a third RF signal with a rectangular pulse at a 3 / 4 duty cycle during the time period from the first time t1 to the sixth time t6, so that SC-DAC 160_3 can output an RF analog signal RF that approximates a sinusoidal signal. OUT .

[0121] Figure 17 This is a diagram illustrating the configuration of a digital RF transmitter 1000 according to an example embodiment.

[0122] Reference Figure 17The digital RF transmitter 1000 may include a first SC-DAC 1100 and a second SC-DAC 1200. The first SC-DAC 1100 may include first to third SC-DAC circuits 1110, 1120, and 1130. Both the first SC-DAC circuit 1110 and the third SC-DAC circuit 1130 may include 2... A-1 Each unit includes an amplifier AMP and a capacitor cap with capacitance C. The second SC-DAC circuit 1120 may include 2 A-1 The second SC-DAC 1200 may include the fourth through sixth SC-DAC circuits 1210, 1220, and 1230. The fourth SC-DAC circuit 1210 and the sixth SC-DAC circuit 1230 may each include B units, each unit including an amplifier AMP and a capacitor cap with capacitance C. The fifth SC-DAC circuit 1220 may include B units, each unit including an amplifier AMP and a capacitor cap with capacitance 1.4C.

[0123] When the modem (not shown) generates a digital signal with "k" bits, the first SC-DAC1100 can receive the thermometer-to-binary data converted from A bits of the digital signal out of the "k" bits in the above configuration, and can perform the above reference. Figures 1 to 16 The conversion operation described. The second SC-DAC 1200 can receive a digital signal with B bits out of "k" bits and perform the above-described conversion operation. Figures 1 to 16 The described conversion operation. For example, A bits can correspond to the most significant bit (MSB) of "k" bits, while B bits can correspond to the least significant bit (LSB) of "k" bits.

[0124] When all SC-DACs of the digital RF transmitter 1000 are configured to receive thermometer data to binary, the number of units, including the amplifier AMP and capacitor cap, increases rapidly, making it difficult to reduce the size of the digital RF transmitter 1000. Therefore, when only some SC-DACs in the digital RF transmitter 1000 (e.g., only the first SC-DAC 1100) are configured to receive thermometer data to binary, such as... Figure 17 As shown, this ensures linear operation and also reduces the size of the digital RF transmitter 1000.

[0125] Figure 18 This involves applying the logic of disabling the opposite cell (DOC) to... Figure 1A diagram illustrating an example of a wireless communication device. DOC logic can be applied to wireless communication device 1 to reduce or minimize the power consumption of SC-DAC 12.

[0126] Reference Figure 1 and 18 After N modes of IQ binary data pairs are pre-calculated in the digital region where the modem 30 operates, some units in the SC-DAC 12 (each unit includes an amplifier and a capacitor) are deactivated, and other units are activated in the analog region, thus reducing or minimizing power consumption.

[0127] In other words, because modes “1,1” and “-1,-1” (hereinafter systematically referred to as ±1) cancel each other out when passing through SC-DAC12, modem figure 30 can detect in advance the number of modes “1,1” and “-1,-1” among N modes, thereby determining the number of units to be deactivated.

[0128] In the first case [CASE1], after the modes in the N modes cancel each other out, one mode "1,1" remains. Therefore, the modem 30 can activate only one unit of the SC-DAC 12, and the SC-DAC 12 can output the first RF analog signal RF. OUT1 .

[0129] In the second case [CASE2], after the modes in the N modes cancel each other out, five modes "-1,1" and two modes "1,1" remain. Therefore, the modem 30 can activate the seven units in the SC-DAC 12 that correspond to the remaining modes, and the SC-DAC 12 can output the second RF analog signal RF. OUT2 .

[0130] Figure 19 This is a block diagram of a wireless communication device 2000 according to an example embodiment.

[0131] Reference Figure 19 The wireless communication device 2000 may include a digital signal processor 2100, first digital RF transmitters 2200_1 to qth digital RF transmitters 2200_q, first wideband adjustable matching networks 2300_1 to qth wideband adjustable matching networks 2300_q, a multiplexer 2400, and a plurality of output terminals (e.g., first output terminals 2500_1 to eighth output terminals 2500_8). (Refer to the above.) Figures 1 to 18The described embodiments can be applied to first digital RF transmitters 2200_1 to qth digital RF transmitters 2200_q. Each of the first wideband adjustable matching networks 2300_1 to qth wideband adjustable matching networks 2300_q may include a balun (not shown) and a power amplifier (PA) (not shown), the balun and PA being adapted to be connected to the respective digital RF transmitters in the first digital RF transmitters 2200_1 to qth wideband adjustable matching networks 2300_q. The first wideband adjustable matching networks 2300_1 to qth wideband adjustable matching networks 2300_q may not include filters for removing intermodulation distortion components generated by the PA. Among the first output terminals 2500_1 to the eighth output terminal 2500_8, the first output terminal 2500_1 to the third output terminal 2500_3 can respectively correspond to the first low-frequency band LB1 to the third low-frequency band LB3, the fourth output terminal 2500_4 to the seventh output terminal 2500_7 can respectively correspond to the first intermediate frequency band MB1 to the fourth intermediate frequency band MB4, and the eighth output terminal 2500_8 can correspond to the high-frequency band HB. However, Figure 19 The configuration of the wireless communication device 2000 is merely an example embodiment, and the embodiments are not limited thereto. The wireless communication device can be implemented to support communication in various frequency bands.

[0132] In an example embodiment, when operating in time-division duplex mode, the digital signal processor 2100 can select one of the first digital RF transmitters 2200_1 to the qth digital RF transmitters 2200_q and provide the baseband digital signal as an IQ signal to the selected digital RF transmitter. In the following, it is assumed that the digital signal processor 2100 has already selected the first digital RF transmitter 2200_1. In some embodiments, the unselected second digital RF transmitters 2200_2 to the qth digital RF transmitters 2200_q and the second wideband adjustable matching network 2300_2 to the qth wideband adjustable matching network 2300_q can be deactivated.

[0133] The first digital RF transmitter 2200_1 can operate in the same manner as in the above embodiments to perform up-conversion and digital-to-analog conversion on the baseband digital signal, generating an RF analog signal and an inverted RF analog signal corresponding to the IQ mode and carrier frequency, and can output the RF analog signal and the inverted RF analog signal to the first broadband adjustable matching network 2300_1 connected thereto. The first broadband adjustable matching network 2300_1 can use the received RF analog signal and the inverted RF analog signal to generate an RF output signal, and can output the RF output signal to the output terminal corresponding to the frequency band of the RF analog signal among the first output terminal 2500_1 to the eighth output terminal 2500_8 through the multiplexer 2400 via the multiplexer 2100. The digital signal processor 2100 can control the switching operation of the multiplexer 2400.

[0134] While the inventive concept has been specifically shown and described with reference to some exemplary embodiments thereof, it will be understood that various changes in form and detail may be made to the disclosed exemplary embodiments without departing from the spirit and scope of the appended claims.

Claims

1. A digital radio frequency transmitter, comprising: The processing circuit is configured to generate a first mode signal, a second mode signal, and a third mode signal based on the modes of in-phase I-quadrature Q binary data pairs and the modes of in-phase I-Q binary data pairs, wherein the first mode signal, the second mode signal, and the third mode signal have the same mode and different phases. as well as A switched-capacitor digital-to-analog converter (SC-DAC) is configured to remove the nth harmonic component from a radio frequency (RF) analog signal by amplifying a first mode signal, a second mode signal, and a third mode signal to have a specific magnitude ratio, and then combining the amplified first mode signal, amplified second mode signal, and amplified third mode signal into an RF analog signal, where "n" is an integer of at least 3. Specifically, when the nth harmonic component is a third harmonic component, the phase of the first mode signal is 45 degrees ahead of the phase of the second mode signal and 90 degrees ahead of the phase of the third mode signal. The SC-DAC includes: A first SC-DAC circuit, comprising a first amplifier and a first capacitor, is configured to receive and amplify the first mode signal and output the amplified first mode signal through an output terminal. A second SC-DAC circuit, comprising a second amplifier and a second capacitor, is configured to receive and amplify the second mode signal, and output the amplified second mode signal through the output terminal; and A third SC-DAC circuit, comprising a third amplifier and a third capacitor, is configured to receive and amplify the third mode signal, and output the amplified third mode signal through the output terminal. Wherein, the equivalent capacitance of the second capacitor in the second SC-DAC circuit is "m" times the equivalent capacitance of each of the first capacitor in the first SC-DAC circuit and the third capacitor in the third SC-DAC circuit, where "m" is 1.

4.

2. The digital radio frequency transmitter according to claim 1, wherein, The first power supply voltage applied to the second SC-DAC circuit is greater than the second power supply voltage applied to each of the first SC-DAC circuit and the third SC-DAC circuit.

3. The digital radio frequency transmitter according to claim 2, wherein, The first power supply voltage is variable.

4. The digital radio frequency transmitter according to claim 1, further comprising: A thermometer-to-binary converter is configured to: receive "k" bits of I data, "k" bits of Q data, "k" bits of inverted I data, and "k" bits of inverted Q data from a digital signal processor; convert the I data, the Q data, the inverted I data, and the inverted Q data into I binary data, Q binary data, inverted I binary data, and inverted Q binary data, respectively; and output the I binary data, the Q binary data, the inverted I binary data, and the inverted Q binary data to the processing circuit, wherein "k" is an integer of at least 2.

5. The digital radio frequency transmitter according to claim 4, wherein, The processing circuit is further configured to: Generate multiple clock signals with target duty cycles and distinct phases; and The first mode signal, the second mode signal, and the third mode signal are generated by multiplying the plurality of clock signals with the I binary data, the Q binary data, the inverted I binary data, and the inverted Q binary data.

6. The digital radio frequency transmitter according to claim 5, wherein, The plurality of clock signals includes a first clock signal with a phase of 0 degrees, a second clock signal with a phase of 45 degrees, a third clock signal with a phase of 90 degrees, a fourth clock signal with a phase of 135 degrees, a fifth clock signal with a phase of 180 degrees, a sixth clock signal with a phase of 225 degrees, a seventh clock signal with a phase of 270 degrees, and an eighth clock signal with a phase of 315 degrees. The processing circuit is configured as follows: The first mode signal is generated by performing the following first multiplication and summing the results: multiplying the first clock signal by the I binary data, multiplying the third clock signal by the Q binary data, multiplying the fifth clock signal by the inverted I binary data, and multiplying the seventh clock signal by the inverted Q binary data. The second mode signal is generated by performing a second multiplication as follows and summing the results of the second multiplication: multiplying the second clock signal by the I binary data, multiplying the fourth clock signal by the Q binary data, multiplying the sixth clock signal by the inverted I binary data, and multiplying the eighth clock signal by the inverted Q binary data. The third mode signal is generated by performing a third multiplication as follows and summing the results of the third multiplication: multiplying the third clock signal with the I binary data, multiplying the fifth clock signal with the Q binary data, multiplying the seventh clock signal with the inverted I binary data, and multiplying the first clock signal with the inverted Q binary data.

7. The digital radio frequency transmitter according to claim 4, wherein, The processing circuit is further configured to: Generate multiple clock signals with target duty cycles and distinct phases, and The first mode signal, the second mode signal, and the third mode signal are generated by using at least one of the plurality of clock signals.

8. The digital radio frequency transmitter according to claim 7, wherein, The processing circuit includes: A first signal generation circuit is configured to generate component signals that are respectively output as a first mode signal, a second mode signal, and a third mode signal when the mode of the IQ binary data pair is a first mode. A second signal generation circuit is configured to generate component signals that are respectively output as a first mode signal, a second mode signal, and a third mode signal when the mode of the IQ binary data pair is a second mode. A third signal generation circuit is configured to generate component signals, which are respectively output as a first mode signal, a second mode signal, and a third mode signal, when the mode of the IQ binary data pair is a third mode; and A fourth signal generation circuit is configured to generate component signals that are respectively output as the first mode signal, the second mode signal, and the third mode signal when the mode of the IQ binary data pair is the fourth mode.

9. The digital radio frequency transmitter according to claim 8, wherein, The first signal generation circuit, the second signal generation circuit, the third signal generation circuit, and the fourth signal generation circuit each include: First component signal generation logic, the first component signal generation logic is configured to generate a first component signal having a first duty cycle; The second component signal generation logic is configured to generate a second component signal having a second duty cycle; and The third component signal generation logic is configured to generate a third component signal with a third duty cycle.

10. The digital radio frequency transmitter according to claim 9, wherein, The first duty cycle is 1 / 4, the second duty cycle is 1 / 2, and the third duty cycle is 3 / 4.

11. The digital radio frequency transmitter according to claim 1, wherein, The processing circuit is further configured to generate a first inverted mode signal, a second inverted mode signal, and a third inverted mode signal by inverting the first mode signal, the second mode signal, and the third mode signal. The SC-DAC is further configured to remove the nth harmonic component of the inverted radio frequency analog signal by amplifying the first inverted mode signal, the second inverted mode signal, and the third inverted mode signal to have a specific magnitude ratio and synthesizing the amplified first inverted mode signal, the amplified second inverted mode signal, and the amplified third inverted mode signal into an inverted radio frequency analog signal.

12. A wireless communication device, comprising: A modem configured to modulate digital data and output "k" bits of in-phase I data, "k" bits of quadrature Q data, "k" bits of out-of-phase I data and "k" bits of out-of-phase Q data, wherein "k" is an integer of at least 2; Digital radio frequency transmitter, the digital radio frequency transmitter being configured to: A first mode signal is generated, having modes corresponding to the modes of IQ binary data pairs and the modes of inverted IQ binary data pairs, wherein the IQ binary data pairs and the inverted IQ binary data are generated based on thermometer-to-binary conversion of the I data, the Q data, the inverted I data, and the inverted Q data. The nth harmonic component of the radio frequency analog signal is removed by generating a second mode signal and a third mode signal, wherein the second mode signal has a first phase difference with the first mode signal, and the third mode signal has a second phase difference with the first mode signal, wherein "n" is an integer of at least 3; and A power amplifier configured to receive the radio frequency analog signal and generate a radio frequency output signal by amplifying the radio frequency analog signal, the radio frequency analog signal being generated by summing a first mode signal, a second mode signal, and a third mode signal. The digital radio frequency transmitter further includes: a first capacitor for transmitting the first mode signal, a second capacitor for transmitting the second mode signal, and a third capacitor for transmitting the third mode signal, wherein the capacitance of the second capacitor is equal to the capacitance of each of the first capacitor and the third capacitor. times.

13. The wireless communication device according to claim 12, wherein, When the nth harmonic component is a third harmonic component, the phase of the first mode signal is 45 degrees ahead of the phase of the second mode signal and 90 degrees ahead of the phase of the third mode signal. The magnitude of the second mode signal is the magnitude of each of the first mode signal and the third mode signal. times.

14. The wireless communication device according to claim 12, wherein, The digital radio frequency transmitter is configured to generate a first component signal with a duty cycle of 1 / 4 as the first mode signal, a second component signal with a duty cycle of 1 / 2 as the second mode signal, and a third component signal with a duty cycle of 3 / 4 as the third mode signal by using at least one of a plurality of clock signals with a duty cycle of 1 / 4 and different phases from each other.

15. A wireless communication device, comprising: The first SC-DAC circuit, SC-DAC being a switched capacitor digital-to-analog converter, includes multiple first paths, each first path including a first amplifier and a first capacitor. The first SC-DAC circuit is configured to receive multiple first mode signals in parallel and output a first radio frequency signal by summing the multiple first mode signals. The second SC-DAC circuit includes a plurality of second paths, each second path including a second amplifier and a second capacitor. The second SC-DAC circuit is configured to receive a plurality of second mode signals in parallel and output a second radio frequency signal by summing the plurality of second mode signals. A third SC-DAC circuit, comprising a plurality of third paths, each of the third paths comprising a third amplifier and a third capacitor, is configured to receive a plurality of third mode signals in parallel and to output a third radio frequency signal by summing the plurality of third mode signals; The processing circuit is configured to generate the plurality of first mode signals, the plurality of second mode signals, and the plurality of third mode signals based on the modes of in-phase I-quadrature Q binary data pairs and the modes of in-phase I-Q binary data pairs, wherein the plurality of second mode signals lag the plurality of first mode signals by a first phase and the plurality of third mode signals lag the plurality of first mode signals by a second phase. as well as A first output terminal is connected to the output terminal of each of the first SC-DAC circuit, the second SC-DAC circuit, and the third SC-DAC circuit, and is configured to output an RF analog signal by summing the first RF signal, the second RF signal, and the third RF signal.

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