FPGA prototype verification device and method

Abstract

The present application discloses an FPGA prototype verification device and method, the device includes a PICE interface, a clock module, a memory and an FPGA chip arranged on a board; after the RTL code to be verified for implementing the MCTP protocol based on the PCIE bus is compiled to generate an execution file, the execution file is transplanted to the FPGA chip; the FPGA chip creates a CPU, a chip internal interconnection bus, a memory controller and an MCTP protocol processing module by running the execution file, and the CPU is connected to the memory and the MCTP protocol processing module respectively through the chip internal interconnection bus, and then the MCTP protocol data packet transmission and reception between the test host is verified through the PCIE interface. The present application provides a software and hardware verification platform for implementing the MCTP protocol using the PCIE bus, which helps to accelerate the time to market of the product and shorten the product development cycle.

Description

Technical Field

[0001] The present application relates to the field of electronic design technology, and in particular to an FPGA prototype verification device and method. Background Art

[0002] FPGA (Field Programmable Gate Array) prototype verification is a mature technology used in ASIC (Application Specific Integrated Circuit) design. By porting the RTL (Register Transfer Level) code in ASIC electronic design to FPGA and verifying the relevant functions of ASIC, it is possible to verify whether the ASIC implementation model matches the expected design performance.

[0003] MCTP (Management Component Transport Protocol) is a communication protocol used for data transmission between devices inside a computer. The protocol can be transmitted through buses such as IIC (Inter-Integrated Circuit), USB (Universal Serial Bus), and PCIE (Peripheral Component Interconnect Express). Among them, since the PCIE bus has a high communication rate and is easy to interconnect between devices, the PCIE can be used to implement the MCTP protocol for devices with a high data transmission rate. However, in the current related technology, there is no FPGA prototype verification device that uses the PCIE bus to implement the MCTP protocol.

[0004] In view of this, providing a solution to the above-mentioned technical problems has become an urgent concern for those skilled in the art. Summary of the invention

[0005] The purpose of this application is to provide an FPGA prototype verification device and method to effectively verify the PCIE bus implementation of the MCTP protocol.

[0006] To solve the above technical problems, on the one hand, the present application discloses an FPGA prototype verification device, including a PCIE interface, a clock module, a memory and an FPGA chip arranged on a board;

[0007] After compiling the RTL code to be verified for implementing the MCTP protocol based on the PCIE bus to generate an execution file, the execution file is transplanted to the FPGA chip; the FPGA chip creates a CPU, a chip internal interconnection bus, a memory controller, and an MCTP protocol processing module by running the execution file; the CPU is respectively connected to the memory, the memory controller, and the MCTP protocol processing module through the chip internal interconnection bus, and then the MCTP protocol data packet sending and receiving verification between the test host is performed through the PCIE interface connected to the MCTP protocol processing module.

[0008] Optionally, it also includes:

[0009] Other peripheral interfaces connected to the FPGA chip.

[0010] Optionally, when the FPGA prototype verification device sends the MCTP protocol data packet to the test host, it is specifically used to:

[0011] The CPU obtains the data to be sent and the BDF information of the test host, configures a packet header according to the BDF information, synthesizes the packet header and the data to be sent into an MCTP protocol data packet and writes it into the memory, and sends the MCTP protocol data packet to the MCTP protocol processing module through the chip internal interconnection bus, so that the MCTP protocol processing module sends the MCTP protocol data packet to the test host through the PCIE interface in the PCIE bus protocol.

[0012] Optionally, when the CPU sends the MCTP protocol data packet to the MCTP protocol processing module through the chip internal interconnection bus, the CPU is specifically configured to:

[0013] The memory controller is started, and the MCTP protocol data packet is sent to the MCTP protocol processing module via the chip internal interconnection bus.

[0014] Optionally, when receiving the MCTP protocol data packet sent by the test host, the FPGA prototype verification device is specifically used to:

[0015] The MCTP protocol processing module receives the MCTP protocol data packet sent by the test host through the PCIE interface in the PCIE bus protocol, and sends the MCTP protocol data packet to the CPU through the chip internal interconnection bus; the CPU performs data parsing on the MCTP protocol data packet according to the MCTP protocol.

[0016] Optionally, when the MCTP protocol processing module receives the MCTP protocol data packet sent by the test host through the PCIE interface in a PCIE bus protocol, it is specifically used to:

[0017] A PCIE protocol data packet sent by the test host is received through the PCIE interface using the PCIE bus protocol; and the MCTP protocol data packet is parsed and extracted from the PCIE protocol data packet.

[0018] Optionally, the memory is specifically DDR.

[0019] In another aspect, the present application further discloses an FPGA prototype verification method, which is applied to any of the FPGA prototype verification devices described above; the method comprises:

[0020] Compile the RTL code to be verified for implementing the MCTP protocol based on the PCIE bus to generate an execution file;

[0021] Transplanting the execution file to the FPGA chip;

[0022] The FPGA chip runs the execution file to create a CPU, a chip internal interconnection bus, a memory controller, and an MCTP protocol processing module, wherein the CPU is respectively connected to the memory, the memory controller, and the MCTP protocol processing module through the chip internal interconnection bus;

[0023] The CPU performs MCTP protocol data packet sending and receiving verification with the test host through a PCIE interface connected to the MCTP protocol processing module.

[0024] Optionally, the process of sending the MCTP protocol data packet to the test host includes the following steps:

[0025] The CPU obtains the data to be sent and the BDF information of the test host;

[0026] The CPU configures a packet header according to the BDF information, combines the packet header and the data to be sent into an MCTP protocol data packet, and then writes the data into the memory;

[0027] The CPU sends the MCTP protocol data packet to the MCTP protocol processing module through the chip internal interconnection bus;

[0028] The MCTP protocol processing module sends the MCTP protocol data packet to the test host via the PCIE interface using the PCIE bus protocol.

[0029] Optionally, the process of receiving the MCTP protocol data packet sent by the test host comprises the following steps:

[0030] The MCTP protocol processing module receives the MCTP protocol data packet sent by the test host through the PCIE interface in the PCIE bus protocol;

[0031] The MCTP protocol processing module sends the MCTP protocol data packet to the CPU through the chip internal interconnection bus;

[0032] The CPU performs data parsing on the MCTP protocol data packet according to the MCTP protocol

[0033] The FPGA prototype verification device and method provided by the present application have the following beneficial effects: the present application provides a software and hardware verification platform for implementing the MCTP protocol using the PCIE bus, and based on the full-scale verification of the unpacking and assembly of the MCTP protocol data packets, solves the problem that the software design work needs to be carried out after the ASIC tape-out is completed. In addition, the present application can find the timing problem of the RTL code during the code compilation process, solves the problem that the timing of the chip cannot be evaluated during the functional verification process, further improves the efficiency of software functional verification, and can help speed up the time to market of the product based on the simultaneous development of software and chips, and shorten the product development cycle. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] In order to more clearly illustrate the technical solutions in the prior art and the embodiments of the present application, the drawings required for use in the description of the prior art and the embodiments of the present application are briefly introduced below. Of course, the drawings described below in relation to the embodiments of the present application are only part of the embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without creative work, and the obtained other drawings also belong to the protection scope of the present application.

[0035] Figure 1 This is an application scenario diagram of an FPGA prototype verification device disclosed in an embodiment of the present application;

[0036] Figure 2 A structural block diagram of a system on chip of an FPGA prototype verification device disclosed in an embodiment of the present application;

[0037] Figure 3 A flowchart of an FPGA prototype verification method disclosed in an embodiment of the present application;

[0038] Figure 4 A flow chart of a method for sending an MCTP protocol data packet disclosed in an embodiment of the present application;

[0039] Figure 5 The present invention is a flowchart of a method for receiving an MCTP protocol data packet disclosed in an embodiment of the present application. DETAILED DESCRIPTION

[0040] The core of this application is to provide an FPGA prototype verification device and method to effectively verify the PCIE bus implementation of the MCTP protocol.

[0041] In order to describe the technical solutions in the embodiments of the present application more clearly and completely, the technical solutions in the embodiments of the present application will be introduced below in conjunction with the drawings in the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0042] In view of the problem that the current related technology has not yet provided an FPGA prototype verification device that uses a PCIE bus to implement the MCTP protocol, the present application provides an FPGA prototype verification solution that can effectively solve the above problem.

[0043] See also Figure 1 As shown, Figure 1 This is an application scenario diagram of an FPGA prototype verification device disclosed in an embodiment of the present application.

[0044] Among them, the FPGA prototype verification device disclosed in this application mainly includes a PCIE interface 100, a clock module 200, a memory 300 and an FPGA chip 400 arranged on a board;

[0045] After the RTL code to be verified for implementing the MCTP protocol based on the PCIE bus is compiled to generate an execution file, the execution file is transplanted to the FPGA chip 400; the FPGA chip 400 creates a CPU 401, a chip internal interconnection bus 402, a memory controller 403, and an MCTP protocol processing module 404 by running the execution file. The CPU 401 is connected to the memory 300, the memory controller 403, and the MCTP protocol processing module 404 through the chip internal interconnection bus, and then the MCTP protocol data packet sending and receiving verification between the test host is performed through the PCIE interface 100 connected to the MCTP protocol processing module 404.

[0046] Specifically, the FPGA prototype verification device provided in the present application can be connected to the test host through the PCIE interface on the board, and the communication verification of the MCTP protocol based on the PCIE bus is completed by sending and receiving MCTP protocol data packets with the test host.

[0047] During the test, first, after the user has created the RTL code to be verified based on the PCIE bus to implement the MCTP protocol (the correctness of the RTL code needs to be verified by running the FPGA prototype verification device, that is, the RTL code to be verified), it can be compiled in the tool software to generate an execution file; then the execution file is burned and transplanted into the FPGA. The FPGA with the RTL code to be verified, based on the IP core of the RTL code to be verified, creates a CPU, chip internal interconnection bus, memory controller, MCTP protocol processing module, plus the memory, clock module, and PCIE interface on the board, forming a complete SOC (System on Chip). SOC is an integrated circuit with a dedicated purpose that contains a complete system and embeds all the software content.

[0048] Among them, IP cores in the semiconductor industry refer to pre-designed circuit function modules used in ASIC or FPGA. IP cores can design some commonly used but relatively complex function blocks in digital circuits, such as FIR filters, SDRAM controllers, etc., into modules with modifiable parameters. In this way, using IP cores to design electronic systems is not only convenient to reference, but also easy to operate when modifying basic components.

[0049] For details, please refer to Figure 2 , Figure 2 This is a block diagram of a system on chip disclosed in an embodiment of the present application. The CPU implements control of the entire ASIC peripherals and data processing, and the chip internal interconnection bus implements data transmission between various interfaces and between various interfaces and the CPU. Among them, the memory implements the storage of local data; the memory controller can implement read and write operations on memory data; the MCTP protocol processing module implements the conversion of data formats between the CPU and the PCIE interface; that is, the MCTP protocol data packet sent by the CPU is processed into the communication data format of the PCIE interface, or the MCTP protocol data packet is parsed from the communication data format of the PCIE interface.

[0050] It is easy for a person skilled in the art to understand that the verification of the PCIE implementation of the MCTP protocol mainly includes two aspects: the sending of the MCTP protocol data packet, and the receiving of the MCTP protocol data packet. After the FPGA prototype verification device and the test host successfully and completely send and receive the MCTP protocol data packet, it can be proved that the ASIC design of the MCTP protocol implemented by the PCIE bus is correct.

[0051] Among them, when sending the MCTP protocol data packet, the SOC system in the FPGA prototype verification board provided by the present application completes the organization of the MCTP protocol data packet, and sends the MCTP protocol data packet to the PCIE interface through the internal interconnection bus of the chip, and then transmits it to the test host, and finally the test host completes the data parsing of the MCTP protocol data packet.

[0052] When receiving the MCTP protocol data packet, the test host organizes the MCTP protocol data packet and sends it to the SOC system in the FPGA prototype verification board through the PCIE bus. Finally, the SOC system completes the data parsing of the MCTP protocol data packet.

[0053] It can be seen that the FPGA prototype verification device provided by this application provides a software and hardware verification platform for implementing the MCTP protocol using the PCIE bus. Based on the full-scale verification of the unpacking and assembly of the MCTP protocol data packets, it solves the problem that the software design work needs to be carried out after the ASIC tape-out is completed. In addition, this application can find the timing problem of the RTL code during the code compilation process, solve the problem that the timing of the chip cannot be evaluated during the functional verification process, and further improve the efficiency of software function verification. It can help speed up the time to market of the product based on the simultaneous development of software and chips and shorten the product development cycle.

[0054] As a specific embodiment, the FPGA prototype verification device provided in the embodiment of the present application further includes: other peripheral interfaces 500 connected to the FPGA chip on the basis of the above content. Specifically, the peripheral interface 500 is used to realize data transmission with other peripherals (such as Ethernet). Further, in a specific embodiment, the memory can be specifically a DDR (Double Data Rate, double rate synchronous dynamic random access memory) with a higher data transmission rate.

[0055] As a specific embodiment, the FPGA prototype verification device provided in the embodiment of the present application is based on the above content. When the FPGA prototype verification device sends an MCTP protocol data packet to the test host, it is specifically used to:

[0056] The CPU obtains the BDF information of the data to be sent and the test host, configures the packet header according to the BDF information, combines the packet header and the data to be sent into an MCTP protocol data packet and writes it into the memory, and sends the MCTP protocol data packet to the MCTP protocol processing module through the internal interconnection bus of the chip, so that the MCTP protocol processing module sends the MCTP protocol data packet to the test host through the PCIE interface in the PCIE bus protocol.

[0057] Among them, BDF information is a protocol parameter used to help determine the device routing path, including bus (Bus), device (Device), and function (Function).

[0058] As a specific embodiment, the FPGA prototype verification device provided in the embodiment of the present application is based on the above content. When the CPU sends the MCTP protocol data packet to the MCTP protocol processing module through the chip internal interconnection bus, it is specifically used to:

[0059] The memory controller is started and the MCTP protocol data packet is sent to the MCTP protocol processing module via the chip internal interconnection bus.

[0060] The memory controller may be specifically a DMA (Direct Memory Access) controller. Specifically, DMA transmission is used to copy data from one address space to another address space. The transmission action itself is implemented and completed by the DMA controller, which can avoid CPU work delays, reduce CPU operation burden, and help improve operation efficiency.

[0061] As a specific embodiment, the FPGA prototype verification device provided in the embodiment of the present application is based on the above content. When receiving the MCTP protocol data packet sent by the test host, the FPGA prototype verification device is specifically used to:

[0062] The MCTP protocol processing module receives the MCTP protocol data packet sent by the test host through the PCIE interface using the PCIE bus protocol, and sends the MCTP protocol data packet to the CPU through the chip's internal interconnection bus; the CPU parses the MCTP protocol data packet according to the MCTP protocol.

[0063] As a specific embodiment, the FPGA prototype verification device provided in the embodiment of the present application is based on the above content, and the MCTP protocol processing module receives the MCTP protocol data packet sent by the test host through the PCIE interface using the PCIE bus protocol, and is specifically used to:

[0064] The PCIE protocol data packet sent by the test host is received through the PCIE interface in the PCIE bus protocol; the MCTP protocol data packet is parsed and extracted from the PCIE protocol data packet.

[0065] Specifically, the receiving process of the MCTP protocol data packet is the reverse process of the sending process. When receiving, the MCTP protocol processing module strips and parses the MCTP protocol data packet from the received data packet, and then sends it to the CPU through the chip internal interconnection bus for MCTP protocol parsing.

[0066] See also Figure 3As shown, the embodiment of the present application discloses an FPGA prototype verification method, which is applied to any FPGA prototype verification device as described above, and mainly includes:

[0067] S201: Compile the RTL code to be verified for implementing the MCTP protocol based on the PCIE bus to generate an execution file.

[0068] S202: Migrate the execution file to the FPGA chip.

[0069] S203: The FPGA chip runs the execution file to create a CPU, a chip internal interconnection bus, a memory controller, and an MCTP protocol processing module. The CPU is connected to the memory, the memory controller, and the MCTP protocol processing module respectively through the chip internal interconnection bus.

[0070] S204: The CPU verifies the sending and receiving of MCTP protocol data packets with the test host through the PCIE interface connected to the MCTP protocol processing module.

[0071] In S204, during the process of using the FPGA prototype verification device and the test host to verify the sending and receiving of the MCTP protocol data packet, the process of sending the MCTP protocol data packet to the test host can be seen in Figure 4 , mainly including:

[0072] S301: The CPU obtains the data to be sent and the BDF information of the test host.

[0073] S302: The CPU configures the packet header according to the BDF information, combines the packet header and the data to be sent into an MCTP protocol data packet, and writes the data into the memory.

[0074] S303: The CPU sends the MCTP protocol data packet to the MCTP protocol processing module through the chip internal interconnection bus.

[0075] S304: The MCTP protocol processing module sends the MCTP protocol data packet to the test host via the PCIE interface in the PCIE bus protocol.

[0076] Correspondingly, in the process of using the FPGA prototype verification device and the test host to perform MCTP protocol data packet transmission and reception verification in S204, the process of receiving the MCTP protocol data packet sent by the test host can be seen in Figure 5 , mainly including:

[0077] S401: The MCTP protocol processing module receives an MCTP protocol data packet sent by a test host through a PCIE interface using a PCIE bus protocol.

[0078] S402: The MCTP protocol processing module sends the MCTP protocol data packet to the CPU through the chip internal interconnection bus.

[0079] S403: The CPU performs data parsing on the MCTP protocol data packet according to the MCTP protocol.

[0080] It can be seen that the FPGA prototype verification method disclosed in the embodiment of the present application provides a software and hardware verification platform for implementing the MCTP protocol using the PCIE bus. Based on the full-scale verification of the unpacking and assembly of the MCTP protocol data packets, it solves the problem that the software design work needs to be carried out after the ASIC tape-out is completed. In addition, the present application can find the timing problem of the RTL code during the code compilation process, solves the problem that the timing of the chip cannot be evaluated during the functional verification process, and further improves the efficiency of software function verification. It can help speed up the time to market of the product based on the simultaneous development of software and chips and shorten the product development cycle.

[0081] For specific contents of the above-mentioned FPGA prototype verification method, please refer to the aforementioned detailed introduction of the FPGA prototype verification device, which will not be repeated here.

[0082] In this application, each embodiment is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part.

[0083] It should also be noted that, in this application document, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. In addition, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the statement "comprises a ..." does not exclude the presence of other identical elements in the process, method, article or device including the element.

[0084] The technical solution provided by the present application is described in detail above. The principle and implementation method of the present application are described in detail using specific examples herein, and the description of the above embodiments is only used to help understand the method and core idea of ​​the present application. It should be pointed out that for ordinary technicians in this technical field, without departing from the principle of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall within the scope of protection of the present application.

Claims

1. An FPGA prototype verification device, characterized in that: It includes a PCIE interface, a clock module, a memory and an FPGA chip on the board; After compiling the RTL code to be verified for implementing the MCTP protocol based on the PCIE bus to generate an execution file, the execution file is transplanted to the FPGA chip; the FPGA chip creates a CPU, a chip internal interconnection bus, a memory controller, and an MCTP protocol processing module by running the execution file, and the CPU is respectively connected to the memory, the memory controller, and the MCTP protocol processing module through the chip internal interconnection bus, and then the MCTP protocol data packet sending and receiving verification between the test host and the test host is performed through the PCIE interface connected to the MCTP protocol processing module; When the FPGA prototype verification device sends the MCTP protocol data packet to the test host, it is specifically used to: The CPU obtains the data to be sent and the BDF information of the test host, configures the packet header according to the BDF information, combines the packet header and the data to be sent into an MCTP protocol data packet and writes the packet into the memory, and sends the MCTP protocol data packet to the MCTP protocol processing module through the chip internal interconnection bus, so that the MCTP protocol processing module sends the MCTP protocol data packet to the test host through the PCIE interface in the PCIE bus protocol; When receiving the MCTP protocol data packet sent by the test host, the FPGA prototype verification device is specifically used to: The MCTP protocol processing module receives the MCTP protocol data packet sent by the test host through the PCIE interface in the PCIE bus protocol, and sends the MCTP protocol data packet to the CPU through the chip internal interconnection bus; the CPU performs data parsing on the MCTP protocol data packet according to the MCTP protocol.

2. The FPGA prototype verification device according to claim 1, characterized in that: Also includes: Other peripheral interfaces connected to the FPGA chip.

3. The FPGA prototype verification device according to claim 1, characterized in that: When the CPU sends the MCTP protocol data packet to the MCTP protocol processing module through the chip internal interconnection bus, the CPU is specifically used to: The memory controller is started, and the MCTP protocol data packet is sent to the MCTP protocol processing module via the chip internal interconnection bus.

4. The FPGA prototype verification device according to claim 1, characterized in that: When the MCTP protocol processing module receives the MCTP protocol data packet sent by the test host through the PCIE interface in the PCIE bus protocol, the MCTP protocol processing module is specifically used to: A PCIE protocol data packet sent by the test host is received through the PCIE interface using the PCIE bus protocol; and the MCTP protocol data packet is parsed and extracted from the PCIE protocol data packet.

5. The FPGA prototype verification device according to any one of claims 1 to 4, characterized in that: The memory is specifically DDR.

6. A FPGA prototype verification method, characterized in that: Applied to the FPGA prototype verification device according to any one of claims 1 to 5; the method comprises: Compile the RTL code to be verified for implementing the MCTP protocol based on the PCIE bus to generate an execution file; Transplanting the execution file to the FPGA chip; The FPGA chip runs the execution file to create a CPU, a chip internal interconnection bus, a memory controller, and an MCTP protocol processing module, wherein the CPU is respectively connected to the memory, the memory controller, and the MCTP protocol processing module through the chip internal interconnection bus; The CPU verifies the sending and receiving of MCTP protocol data packets with the test host through a PCIE interface connected to the MCTP protocol processing module; The process of sending the MCTP protocol data packet to the test host includes the following steps: The CPU obtains the data to be sent and the BDF information of the test host; The CPU configures a packet header according to the BDF information, combines the packet header and the data to be sent into an MCTP protocol data packet, and then writes the data into the memory; The CPU sends the MCTP protocol data packet to the MCTP protocol processing module through the chip internal interconnection bus; The MCTP protocol processing module sends the MCTP protocol data packet to the test host in the PCIE bus protocol through the PCIE interface; The process of receiving the MCTP protocol data packet sent by the test host comprises the following steps: The MCTP protocol processing module receives the MCTP protocol data packet sent by the test host through the PCIE interface in the PCIE bus protocol; The MCTP protocol processing module sends the MCTP protocol data packet to the CPU through the chip internal interconnection bus; The CPU performs data parsing on the MCTP protocol data packet according to the MCTP protocol.

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