Display substrate and display device

Abstract

A display substrate and a display device. The display substrate includes a base substrate, a plurality of first connection lines, and a plurality of second connection lines. The base substrate includes a display area, the display area includes a first display area and a second display area, the first display area includes a plurality of first light-emitting devices and a plurality of second light-emitting devices, and the second display area includes a plurality of first pixel circuits and a plurality of second pixel circuits; at least part of the plurality of first connection lines extends along a first direction, at least part of the plurality of second connection lines extends along the first direction, the plurality of first connection lines are at least partly located in the second direction on the first side of the row where the first electrodes of the plurality of first light-emitting devices and the plurality of second light-emitting devices are located, and at least part of the plurality of first connection lines are located in the second direction on the second side of the row where the first electrodes of the plurality of first light-emitting devices and the plurality of second light-emitting devices are located.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a display substrate and a display device. Background Art

[0002] At present, the display screens used in electronic devices are developing towards large screens and full screens to provide users with a better visual experience. Taking mobile phones, tablet computers and other electronic products as an example, since these electronic devices need to be combined with components such as cameras and light sensors, and these components usually occupy the display area of ​​the display screen, it is difficult to achieve a full-screen design for the display screen. In order to ensure the light transmittance of the camera area in the display screen and the camera's photo effect, only the light-emitting device of the pixel circuit is retained in the camera area. Summary of the invention

[0003] At least one embodiment of the present disclosure provides a display substrate, which has a first side for display and a second side opposite to the first side, and includes a substrate substrate, a plurality of first connecting wires, and a plurality of second connecting wires. The substrate substrate includes a display area, the display area includes a first display area and a second display area at least partially surrounding the first display area, wherein the first display area includes a first sub-pixel array, and the first display area allows light from the first side of the display substrate to be at least partially transmitted to the second side of the display substrate, the first sub-pixel array includes a plurality of light-emitting devices arranged in an array, the plurality of light-emitting devices include a plurality of first light-emitting devices and a plurality of second light-emitting devices, the second display area includes a first pixel circuit array, the first pixel circuit array includes a plurality of first pixel circuit units, the plurality of first pixel circuit units include a plurality of first pixel circuits and a plurality of second pixel circuits; at least a portion of the plurality of first connecting wires extends along a first direction, and connects the plurality of first pixel circuits and the plurality of first light-emitting devices one by one, the first pixel circuit is configured to drive the first light-emitting device through the first connecting wire, and the plurality of second connecting wires are connected to the plurality of first pixel circuits and the plurality of first light-emitting devices. At least part of the first display area extends along the first direction, and the plurality of second pixel circuits and the plurality of second light-emitting devices are connected one by one, the second pixel circuit is configured to drive the second light-emitting device through the second connecting wire, wherein each of the plurality of light-emitting devices includes a first electrode, and the first electrodes of the plurality of first light-emitting devices and the plurality of second light-emitting devices are arranged in the same row along the first direction, and in the first display area, the plurality of first connecting wires are at least partially located in the second direction on the first side of the row where the first electrodes of the plurality of first light-emitting devices and the plurality of second light-emitting devices are located, and the plurality of first connecting wires are at least partially located in the second direction on the second side of the row where the first electrodes of the plurality of first light-emitting devices and the plurality of second light-emitting devices are located, wherein the second direction intersects with the first direction, and the first side and the second side of the row where the first electrodes of the plurality of first light-emitting devices and the plurality of second light-emitting devices are located are opposite in the second direction.

[0004] For example, in the display substrate provided in at least one embodiment of the present disclosure, in the first direction, the plurality of first light-emitting devices are located on a side of the plurality of second light-emitting devices close to the second display area.

[0005] For example, in the display substrate provided in at least one embodiment of the present disclosure, each of the multiple first connecting traces includes a first main body portion and at least one first bending portion, the first main body portion extends along the first direction and is located on the first side of the row where the first electrodes of the multiple first light-emitting devices and the multiple second light-emitting devices are located, the first main body portion is connected to the first electrodes of the multiple first light-emitting devices in a one-to-one correspondence, the at least one first bending portion is connected to the first pixel circuit and the first main body portion, and the at least one first bending portion extends from the first pixel circuit to the first side of the first pixel circuit, so that the first main body portion is away from the first electrodes of the multiple first light-emitting devices in the first display area.

[0006] For example, in the display substrate provided in at least one embodiment of the present disclosure, at least a portion of the at least one first bending portion extends along a third direction toward the first side of the first pixel circuit, wherein the third direction intersects the first direction and the second direction.

[0007] For example, in the display substrate provided in at least one embodiment of the present disclosure, at least one first bending portion of at least one of the multiple first connecting lines includes a first sub-bending portion, the first sub-bending portion is located on the first side of the first pixel circuit and extends along the third direction, the first sub-bending portion is connected to the first pixel circuit and the first main body, and one of the first pixel circuits connected to the first sub-bending portion is adjacent to the second pixel circuit.

[0008] For example, in the display substrate provided in at least one embodiment of the present disclosure, at least one first bending portion of at least one of the multiple first connecting wires extends from the second side of the first pixel circuit to the first side of the first pixel circuit, and includes a second sub-bending portion, a third sub-bending portion, a first sub-connecting portion and a second sub-connecting portion, wherein the first sub-connecting portion and the second sub-bending portion are located on the second side of the first pixel circuit, the second sub-bending portion extends along the third direction, the first sub-connecting portion extends along the first direction and is connected to the first pixel circuit and the second sub-bending portion, the second sub-connecting portion extends along the second direction and is located between two adjacent first pixel circuits, the second sub-connecting portion is connected to the second sub-bending portion and the third sub-bending portion, the third sub-bending portion is located on the first side of the first pixel circuit, the third sub-bending portion extends along the third direction and is connected to the first main portion of the first connecting wire, and the second side of the first pixel circuit is opposite to the first side in the second direction.

[0009] For example, in the display substrate provided in at least one embodiment of the present disclosure, at least one first bending portion of at least one of the multiple first connecting traces includes a second sub-bending portion, a third sub-bending portion, a first sub-connecting portion and a second sub-connecting portion, wherein the first sub-connecting portion and the second sub-bending portion are located on the second side of the first pixel circuit, the second sub-bending portion extends along the third direction, the first sub-connecting portion extends along the first direction and is connected to the first pixel circuit and the second sub-bending portion, the second sub-connecting portion extends along the second direction and is located between adjacent first pixel circuits and second sub-pixel circuits, the second sub-connecting portion is connected to the second sub-bending portion and the third sub-bending portion, the third sub-bending portion is located on the first side of the first pixel circuit, the third sub-bending portion extends along the third direction and is connected to the first main portion of the first connecting trace, and the second side of the first pixel circuit is opposite to the first side in the second direction.

[0010] For example, in the display substrate provided in at least one embodiment of the present disclosure, each of the plurality of second connecting wires includes a second main body portion, the second main body portion extends along the first direction and is located on the second side of the row where the first electrodes of the plurality of first light-emitting devices and the plurality of second light-emitting devices are located, the second main body portion is connected to the first electrode of the second light-emitting device and the second pixel circuit, and in the first display area, the orthographic projection of the main body portion of the second connecting wire on the base substrate overlaps with the orthographic projection of the first electrode of at least one of the plurality of second light-emitting devices and the plurality of first light-emitting devices on the base substrate.

[0011] For example, in the display substrate provided in at least one embodiment of the present disclosure, the first main body portions of the plurality of first connecting wires and the second main body portions of the plurality of second connecting wires are arranged in parallel in the first direction.

[0012] For example, in the display substrate provided in at least one embodiment of the present disclosure, the plurality of first connection lines and the plurality of second connection lines are transparent conductive traces.

[0013] For example, the display substrate provided by at least one embodiment of the present disclosure also includes a first insulating layer, a second insulating layer, a third insulating layer, a first transparent routing layer and a second transparent routing layer, wherein the first insulating layer is located on a side of the multiple first pixel circuits and the multiple second pixel circuits away from the base substrate, the second insulating layer is located on a side of the first insulating layer away from the base substrate, the third insulating layer is located on a side of the second insulating layer away from the base substrate, the first transparent routing layer is located between the first insulating layer and the second insulating layer, the second transparent routing layer is located on a side of the second insulating layer away from the base substrate, the first electrodes of the multiple first light-emitting devices are located on a side of the third insulating layer away from the base substrate, the first transparent routing layer includes one of two adjacent ones of the multiple first connecting routings, and one of two adjacent ones of the multiple second connecting routings, the second transparent routing layer includes the other of the two adjacent ones of the first connecting routings, and the other of the two adjacent ones of the multiple second connecting routings.

[0014] For example, the display substrate provided by at least one embodiment of the present disclosure also includes a plurality of pixel circuit connection holes, which are located in the second display area and include a plurality of first pixel circuit connection holes and a plurality of second pixel circuit connection holes, wherein the first pixel circuit connection holes penetrate the first insulating layer, the second pixel circuit connection holes penetrate the first insulating layer and the second insulating layer, the first connecting wiring and the second connecting wiring located in the first transparent wiring layer are respectively connected to the first pixel circuit and the second pixel circuit through the first pixel circuit connection holes, and the first connecting wiring and the second connecting wiring located in the second transparent wiring layer are respectively connected to the first pixel circuit and the second pixel circuit through the second pixel circuit connection holes.

[0015] For example, the display substrate provided by at least one embodiment of the present disclosure also includes a plurality of electrode connection holes, which are located in the first display area and on the first side of the row where the first electrodes of the plurality of first light-emitting devices and the plurality of second light-emitting devices are located, and include a plurality of first electrode connection holes and a plurality of second electrode connection holes, wherein the first electrode connection hole passes through the second insulating layer and the third insulating layer, the second electrode connection hole passes through the third insulating layer, the first connecting wiring and the second connecting wiring located in the first transparent wiring layer are respectively connected to the first electrodes of the first light-emitting device and the second light-emitting device through the first electrode connection hole, and the first connecting wiring and the second connecting wiring located in the second transparent wiring layer are respectively connected to the first electrodes of the first light-emitting device and the second light-emitting device through the second electrode connection hole.

[0016] For example, the display substrate provided by at least one embodiment of the present disclosure also includes at least one first virtual routing line located in the first display area, the at least one first virtual routing line is located between the first electrodes of the plurality of first light-emitting devices and the plurality of second light-emitting devices in adjacent rows and extends along the second direction, the at least one first virtual routing line is connected to one end of the second connecting routing line connected to the electrode connecting hole, and extends from the electrode connecting hole in a direction away from the first electrode of the second light-emitting device, and the orthographic projection of the at least one first virtual routing line on the substrate does not overlap with the first connecting routing line and the second connecting routing line.

[0017] For example, the display substrate provided by at least one embodiment of the present disclosure also includes a pixel defining layer, which is located on a side of the first electrodes of the multiple light-emitting devices away from the base substrate and includes a plurality of first pixel openings, and the plurality of first pixel openings correspond one-to-one to the multiple light-emitting devices to form a light-emitting area of ​​the multiple light-emitting devices, each of the multiple light-emitting devices also includes a first light-emitting layer and a second electrode, the second electrode is located on a side of the pixel defining layer away from the base substrate, the first light-emitting layer is located in the first pixel opening and between the first electrode and the second electrode, and at least part of the first electrodes of the multiple light-emitting devices include a first electrode main body and a first electrode connecting portion, the first electrode main body is located in the light-emitting area of ​​the light-emitting device, and the first electrode connecting portion connects the electrode connecting hole and the first electrode main body.

[0018] For example, in the display substrate provided in at least one embodiment of the present disclosure, the second display area also includes the second sub-pixel array, the second sub-pixel array includes a plurality of first pixel units, the plurality of first pixel units and the plurality of first pixel circuit units are alternately arranged, each of the plurality of first pixel units includes a third light-emitting device and a third pixel circuit, the third pixel circuit is electrically connected to the third light-emitting device to drive the third light-emitting device, wherein the first sub-pixel array and the second sub-pixel array include a plurality of first sub-pixels, a plurality of second sub-pixels and a plurality of third sub-pixels, and each pixel of the first sub-pixel array and the second sub-pixel array includes at least one first sub-pixel, at least one second sub-pixel and at least one third sub-pixel.

[0019] For example, in the display substrate provided in at least one embodiment of the present disclosure, the display area also includes a third display area, the third display area at least partially surrounds the second display area, the third display area includes a third sub-pixel array, the third sub-pixel array includes a plurality of second pixel units, each of the plurality of second pixel units includes a fourth light-emitting device and a fourth pixel circuit, the fourth pixel circuit is electrically connected to the fourth light-emitting device to drive the fourth light-emitting device, the third sub-pixel array includes a plurality of first sub-pixels, a plurality of second sub-pixels and a plurality of third sub-pixels, one of two adjacent pixels of the third sub-pixel array respectively includes at least one of the first sub-pixels and at least one of the second sub-pixels, the other of the two adjacent pixels includes at least one of the first sub-pixels and at least one of the third sub-pixels, and each second sub-pixel and each third sub-pixel are respectively shared by at least two adjacent pixels.

[0020] For example, in a display substrate provided in at least one embodiment of the present disclosure, the first sub-pixel is a green sub-pixel, the second sub-pixel is a red sub-pixel, and the third sub-pixel is a blue sub-pixel.

[0021] At least one embodiment of the present disclosure further provides a display device, which includes any display substrate as described above.

[0022] For example, the display device provided by at least one embodiment of the present disclosure further includes a sensor, wherein the sensor is disposed on the second side of the display substrate, and the sensor is configured to receive light from the first side of the display substrate.

[0023] For example, in the display device provided in at least one embodiment of the present disclosure, the orthographic projection of the sensor on the base substrate at least partially overlaps with the first display area. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, but are not intended to limit the present disclosure.

[0025] Figure 1A A schematic plan view of a display substrate;

[0026] Figure 1B For along Figure 1A Schematic diagram of the cross section along the center line I-I';

[0027] Figure 1C A simulation diagram showing a display area of ​​a display substrate being illuminated by a point light source;

[0028] Figure 1DAnother simulation diagram showing a display area of ​​a display substrate being illuminated by a point light source;

[0029] Figure 1E A display schematic diagram of a display substrate;

[0030] Figure 1F for Figure 1E Enlarged view of the middle A0 area;

[0031] Figure 2A for Figure 1A A plan view of the wiring arrangement in the display area of ​​the display substrate shown in FIG.

[0032] Figure 2B for Figure 1A Another plan view of the wiring arrangement in the display area of ​​the display substrate shown in ;

[0033] Figure 3A A schematic plan view of a display substrate provided by at least one embodiment of the present disclosure;

[0034] Figure 3B For along Figure 3A Schematic diagram of the cross section along the midline B-B';

[0035] Figure 4 A partially enlarged schematic diagram of a display substrate provided by at least one embodiment of the present disclosure;

[0036] Figure 5 A schematic plan view of wiring arrangement in a display area of ​​a display substrate provided in at least one embodiment of the present disclosure;

[0037] Figure 6 A schematic plan view of wiring arrangement in a display area of ​​a display substrate provided in at least another embodiment of the present disclosure;

[0038] Figure 7 A partial schematic diagram of a display substrate provided by at least one embodiment of the present disclosure;

[0039] Fig. 8A At least one embodiment of the present disclosure provides Figure 7 Enlarged view of the middle A1 area;

[0040] Figure 8B At least another embodiment of the present disclosure provides Figure 7 Enlarged view of the middle A1 area;

[0041] Figure 8C At least one embodiment of the present disclosure provides Figure 7 Enlarged view of the middle A1 area;

[0042] Fig. 9A For along Figure 6Schematic diagram of the cross section along the midline B1-B2;

[0043] Fig. 9B For along Figure 6 A schematic cross-sectional view of the midline B3-B4;

[0044] Fig. 10A A schematic plan view of a display area of ​​a display substrate provided in at least one embodiment of the present disclosure;

[0045] Fig. 10B At least one embodiment of the present disclosure provides Fig. 10A Enlarged view of the middle A2 area;

[0046] Fig.11 A schematic cross-sectional view of a second display area in a display substrate provided in at least one embodiment of the present disclosure;

[0047] Fig.12 A schematic cross-sectional view of a third display area in a display substrate provided for at least one embodiment of the present disclosure; and

[0048] Fig.13 A schematic diagram of a display device provided by at least one embodiment of the present disclosure. DETAILED DESCRIPTION

[0049] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0050] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, similar words such as "one", "one" or "the" do not indicate a quantitative limitation, but indicate that there is at least one. Similar words such as "include" or "comprise" mean that the elements or objects appearing in front of the word cover the elements or objects listed after the word and their equivalents. For the convenience of description, in some drawings, "up", "down", "front" and "back" are given. In the embodiment of the present disclosure, the vertical direction is the direction from top to bottom, the vertical direction is the direction of gravity, the horizontal direction is the direction perpendicular to the vertical direction, and the horizontal direction from right to left is the direction from front to back.

[0051] In order to maximize the screen-to-body ratio of mobile display products, technologies such as bangs screen, water drop screen, and in-screen hole have emerged one after another. This type of technology can be used to install sensors (such as image sensors, infrared sensors, distance sensors) and other components by partially digging holes in the display area. This part of the display area is designed as a light-transmitting display area, and a camera is placed under it to reduce the screen-to-body ratio problem caused by the camera occupying the frame. As a result, the light-transmitting display area can facilitate the installation of components such as sensors while realizing the display function, so that these sensors can perform functions such as imaging, infrared sensing, distance sensing, etc. through the light-transmitting display area without basically affecting the display function of the light-transmitting display area, thereby helping to realize electronic devices with full screens.

[0052] However, the above technology still needs to dig out part of the display area, and the overall effect is still to form an irregular display area, which affects the visual experience. In order to avoid sacrificing the display area, a technology has emerged to reduce the pixel resolution PPI (Pixels Per Inch) in local areas and increase the transmittance to place the camera. The camera is placed in an area with low resolution PPI. In this area, due to the low resolution PPI and high light transmittance, light can reach the camera through the low PPI area. However, although the light transmittance is improved, the horizontal and vertical cross wiring of the pixel drive circuit forms a grating, which still has an adverse effect on camera imaging.

[0053] For example, Figure 1A A schematic plan view of a display substrate; Figure 1B For along Figure 1A Schematic diagram of the cross section along the center line II'.

[0054] like Figure 1A as well as Figure 1B As shown, the display area of ​​the display substrate 01 includes a light-transmitting display area 1, a peripheral display area 2, and a main display area 3. The peripheral display area 2 at least partially surrounds the light-transmitting display area 1, and the main display area 3 at least partially surrounds the light-transmitting display area 1 and the peripheral display area 2. Figure 1A As shown, the light-transmitting display area 1, the peripheral display area 2 and the main display area 3 form a rectangular or approximately rectangular display area as a whole to display a complete (rectangular) picture.

[0055] like Figure 1BAs shown, the display substrate 01 includes a display structure layer 510 and a sensing layer 520 for realizing a display area. Correspondingly, the display structure layer 510 also includes a light-transmitting display area 1 and a peripheral display area 2. The sensing layer 520 is arranged on the non-display side S02 (i.e., the side facing away from the user) of the display substrate 01. The sensing layer 520 includes a sensor 521, which at least partially overlaps with the light-transmitting display area 1 in the normal direction F1 of the display surface of the display substrate, and is configured to receive and process light signals passing through the light-transmitting display area 1 from the display side S01 (i.e., the side facing the user) of the display substrate 01. For example, the sensor 521 is an image sensor, an infrared sensor, a distance sensor, etc., and the sensor 521 can be implemented in the form of a chip, etc.

[0056] For example, the main display area 3 is the main display area (or called the conventional display area), and has a higher resolution (PPI, Pixel Per Inch) than the light-transmitting display area 1 and the peripheral display area 2, that is, a plurality of sub-pixels for display are arranged with a higher density in the main display area 3. In the main display area 3, each sub-pixel includes a light-emitting device and a pixel circuit for driving the light-emitting device.

[0057] For example, the light-transmitting display area 1 and the peripheral display area 2 also respectively include a plurality of sub-pixels for performing display operations. For example, the light-transmitting display area 1 and the peripheral display area 2 have the same resolution.

[0058] The light-transmitting display area 1 can allow light incident from the display side S01 of the display substrate 01 to pass through the display substrate 01 and reach the non-display side S02 of the display substrate 01, so as to be used for normal sensing work of components such as the sensor 521 located on the non-display side S02 of the display substrate 01. However, since the pixel circuit of the sub-pixel includes a plurality of electrodes, wirings, active layers and other structures, it is usually not light-transmitting. In order to improve the light transmittance of the light-transmitting display area 1, the light-emitting device of the sub-pixel of the light-transmitting display area 1 is physically separated from the pixel circuit driving the light-emitting device.

[0059] For example, Figure 2A for Figure 1A A plan view of the wiring arrangement in the display area of ​​the display substrate shown in FIG. Figure 2B for Figure 1A Another plan view of the wiring arrangement in the display area of ​​the display substrate shown in FIG.

[0060] like Figure 2A as well as Figure 2BAs shown, the sub-pixels of the light-transmitting display area 1 include a light-emitting device 02 located in the light-transmitting display area 1 and a pixel circuit D01 located in the peripheral display area 2. The light-emitting device 02 of the sub-pixel of the light-transmitting display area 1 is still retained at a predetermined position in the light-transmitting display area 1 to realize the display function of the light-transmitting display area 1, but the pixel circuit D01 connected to the light-emitting device 02 and used to drive the light-emitting device 02 is removed from the light-transmitting display area 1 to be set in the peripheral display area 2. Therefore, these pixel circuits D01 occupy part of the space of the peripheral display area 2, and the remaining space of the peripheral display area 2 is used to set the sub-pixels P0 of the peripheral display area 2 itself (for example Figure 2A The sub-pixels P0 and P1 are shown in the dotted box in the peripheral display area 2, that is, the sub-pixels that realize the display function in the peripheral display area 2. The sub-pixels P0 include a first sub-pixel P01, a second sub-pixel P02, and a third sub-pixel P03. For example, the first sub-pixel P01 is a red sub-pixel, the second sub-pixel P02 is a green sub-pixel, and the third sub-pixel P03 is a blue sub-pixel.

[0061] For example, the sub-pixels P0 of the peripheral display area 2 and the pixel circuits D01 of the sub-pixels in the light-transmitting display area 1 are arranged in an array in the peripheral display area 2. As described above, the sub-pixels P0 of the peripheral display area 2 and the sub-pixels in the light-transmitting display area 1 have the same resolution. For example, the resolution of the light-transmitting display area 1 and the peripheral display area 2 can be set lower than the resolution of the main display area 3, that is, the density of the sub-pixels for display arranged in the light-transmitting display area 1 and the peripheral display area 2 is lower than the sub-pixel density of the main display area 3.

[0062] For example, Figure 2A as well as Figure 2B As shown, the light-emitting device 02 of the sub-pixel in the light-transmitting display area 1 is electrically connected to the pixel circuit D01 in the peripheral display area 2 in the same row through the connecting wire LSn, and the connecting wire LSn is arranged along the X0 direction, that is, the row direction. In other words, the connecting wire LSn connects the pixel circuit D01 in the peripheral display area 2 in the same row with the light-emitting device 02 in the light-transmitting display area 1. For example, the connecting wire LSn is at least partially a transparent wire to improve the transmittance of the light-transmitting display area 1, and the preparation material of the connecting wire LSn may include a transparent conductive material, such as ITO (Indium Tin Oxide). The connecting wire LSn can cross the sub-pixel P0 in the peripheral display area 2 to electrically connect the light-emitting device 02 of the sub-pixel in the light-transmitting display area 1 and the pixel circuit D01 in the peripheral display area 2 for driving the light-emitting device 02.

[0063] Furthermore, if Figure 2AAs shown, the data line DSn for driving the pixel circuit D01 of each sub-pixel in the light-transmitting display area 1 can be arranged in a winding manner at the boundary of the peripheral display area 2 close to the light-transmitting display area 1, so as to be moved out of the light-transmitting display area 1 and electrically connected to the pixel circuit D01 located in the peripheral display area 2 to provide the data signal required for display. For example, the data line DSn is routed around the light-transmitting display area 1 between the upper side and the lower side of the light-transmitting display area 1. The pixel circuits of the sub-pixels located in the same column in the display area (here including the main display area 3, the peripheral display area 2 and / or the light-transmitting display area 1) can be electrically connected to the same data line, so that the sub-pixels located in the same column can be driven by the same data line, and there is no need to change or add the data driving circuit. The gate line GSn of the pixel circuit D01 for driving each sub-pixel in the light-transmitting display area 1 can be arranged in a winding manner at the boundary of the peripheral display area 2 close to the light-transmitting display area 1, and is routed around the light-transmitting display area 1 between the left and right sides of the light-transmitting display area 1, thereby being moved out of the light-transmitting display area 1 and electrically connected to the pixel circuit D01 located in the peripheral display area 2 to provide the gate scanning signal required for display.

[0064] For example, Figure 2B As shown, one end of the connecting wire LSn (located at one end of the peripheral display area 2) is connected to the pixel circuit D01 through the pixel circuit via H01, and one end of the other end of the connecting wire LSn (located at the light-transmitting display area 1) is connected to the first pole 0111 (for example, the anode of the light-emitting device 02) of the light-emitting device 02 through the electrode via H02. The first pole 0111 of the light-emitting device 02 is connected to the electrode via H02 through the wire 0112. The first pole 0111 and the wire 0112 can be formed integrally. In other words, the first pole 0111 of the light-emitting device 02 is connected to the connecting wire LSn through the electrode via H02. Since the multiple connecting wires LSn are located on the same side of the row of the light-emitting device 02 in the light-transmitting display area 1, the multiple connecting wires LSn need to occupy more wiring space, so that the electrode via H02 is far away from the first pole 0111 (that is, the light-emitting device 02 occupies a larger space in the direction Y0), making it difficult to increase the arrangement density of the light-emitting devices 02 in the light-transmitting display area 1, and it is difficult to increase the resolution in the light-transmitting display area 1.

[0065] For example, Figure 1C A simulation diagram showing a display area of ​​a display substrate being illuminated by a point light source; Figure 1D FIG. 1 is another simulation diagram of a display area of ​​a display substrate being illuminated by a point light source. Figure 1C as well as Figure 1DAs shown, in order to test the light transmission effect of the light-transmitting display area 1 and the peripheral display area 2, the light-transmitting display area 1 and the peripheral display area 2 can be simulated under the illumination of a light source, and the light source can be a point light source, for example, the point light source is set on one side of the light-transmitting display area 1 and the peripheral display area 2 (for example, the display side). Figure 1C or Figure 1D The grating effect appears in the Figure 1C The grating effect in the light-transmitting display area 1 and the peripheral display area 2 is mainly generated by the crisscrossing wirings (such as the dense connection wirings LSn) passing through the light-transmitting display area 1 and the peripheral display area 2.

[0066] For example, Figure 1E A display schematic diagram of a display substrate; Figure 1F for Figure 1E A magnified view of the A0 area in the middle. Figure 1F as well as Figure 1E As shown, the light-transmitting display area 1 and the peripheral display area 2 show a strong sense of graininess. After the resolution of the light-transmitting display area 1 and the peripheral display area 2 is reduced, the brightness is reduced, resulting in a strong visual difference with the main display area 3, resulting in a reduced display effect.

[0067] At least one embodiment of the present disclosure provides a display substrate, which has a first side for display and a second side opposite to the first side, and includes a substrate, a plurality of first connecting wires, and a plurality of second connecting wires. The substrate includes a display area, the display area includes a first display area and a second display area at least partially surrounding the first display area, the first display area includes a first sub-pixel array, and the first display area allows light from the first side of the display substrate to be at least partially transmitted to the second side of the display substrate, the first sub-pixel array includes a plurality of light-emitting devices arranged in an array, the plurality of light-emitting devices include a plurality of first light-emitting devices and a plurality of second light-emitting devices, the second display area includes a first pixel circuit array, the first pixel circuit array includes a plurality of first pixel circuit units, and the plurality of first pixel circuit units include a plurality of first pixel circuits and a plurality of second pixel circuits. At least part of the plurality of first connecting wires extends along the first direction, and connects the plurality of first pixel circuits and the plurality of first light-emitting devices one by one, the first pixel circuit is configured to drive the first light-emitting device through the first connecting wire, at least part of the plurality of second connecting wires extends along the first direction, and connects the plurality of second pixel circuits and the plurality of second light-emitting devices one by one, the second pixel circuit is configured to drive the second light-emitting device through the second connecting wire. Each of the plurality of light-emitting devices includes a first electrode, and the first electrodes of the plurality of first light-emitting devices and the plurality of second light-emitting devices are arranged in the same row along the first direction. In the first display area, at least part of the plurality of first connecting wires is located on the first side of the row where the first electrodes of the plurality of first light-emitting devices and the plurality of second light-emitting devices are located in the second direction, and at least part of the plurality of first connecting wires is located on the second side of the row where the first electrodes of the plurality of first light-emitting devices and the plurality of second light-emitting devices are located in the second direction, the second direction intersects with the first direction, and the first side and the second side of the row where the first electrodes of the plurality of first light-emitting devices and the plurality of second light-emitting devices are located are opposite in the second direction.

[0068] In the display substrate provided by the above-mentioned embodiments, by respectively arranging the first connecting wire and the second connecting wire along the first direction on the first side and the second side of the row where the first electrodes of the plurality of first light-emitting devices and the plurality of second light-emitting devices are located, the wiring space occupied by the first connecting wire and the second connecting wire in the second direction can be reduced, thereby increasing the arrangement density of the light-emitting devices in the first display area and / or the number of the light-emitting devices arranged along the first direction, which is beneficial to improving the resolution of the first display area and / or increasing the size along the first direction (for example, the number of pixels), and also helping to reduce the grating effect caused by the first connecting wire and the second connecting wire in the second display area.

[0069] The embodiments and examples of the present disclosure are described in detail below with reference to the accompanying drawings.

[0070] For example, Figure 3AA schematic plan view of a display substrate provided in at least one embodiment of the present disclosure; Figure 3B For along Figure 3A Schematic diagram of the cross section along the midline B-B'. Figure 3A As shown, the display substrate 1000 according to the embodiment of the present invention includes a base substrate 14. The base substrate 14 includes a display area and a peripheral area 40 surrounding the display area. The display area includes a first display area 10 (for example, a light-transmitting display area), a second display area 20, and a third display area 30 (for example, a normal display area) in parallel. The second display area 20 surrounds (for example, at least partially surrounds) the first display area 10. Figure 3A In FIG. 1 , the first display area 10 is marked by a circular frame.

[0071] For example, the display substrate provided in the embodiment of the present disclosure may be an organic light emitting diode (OLED) display substrate or a quantum dot light emitting diode (QLED) display substrate, and the embodiment of the present disclosure does not limit the specific type of the display substrate.

[0072] For example, Figure 3B As shown, the first display area 10 is a light-transmitting display area, that is, the incident light from the display side S1 (e.g., the first side) of the display substrate 1000 is allowed to be transmitted through the area to reach the non-display side S2 (e.g., the second side) of the display substrate 1000. A sensor 192 may also be provided on the non-display side S2 of the display substrate 1000 to receive the transmitted light, thereby realizing corresponding functions (e.g., imaging, infrared sensing, distance sensing, etc.). For example, the sensor 192 is provided on the non-display side S2 of the display substrate 1000, and the orthographic projection of the sensor 192 on the base substrate 14 at least partially overlaps with the first display area 10, and is configured to receive and process light from the display side S1 of the display substrate 1000. The light from the display side S1 of the display substrate 1000 may be collimated light along the normal direction of the display substrate 1000 (e.g., the Z0 direction), or may be non-collimated light.

[0073] For example, the sensor 192 is an image sensor, an infrared sensor, a distance sensor, etc. The sensor 192 can be implemented in the form of a chip, etc. The sensor 192 is arranged on the non-display side S2 (the side facing away from the user) of the display substrate. The sensor 192 at least partially overlaps with the first display area 10 in the normal direction of the display surface of the display substrate.

[0074] For example, the sensor 192 may be an image sensor, and may be used to collect an image of the external environment facing the light-collecting surface of the sensor 192, such as a CMOS image sensor or a CCD image sensor; the sensor 192 may also be an infrared sensor, a distance sensor, etc. The sensor 192 may be used to implement a camera of a mobile terminal such as a mobile phone or a notebook, and may further include optical devices such as a lens, a reflector, or an optical waveguide to modulate the optical path as required. The embodiments of the present disclosure do not limit the type, function, and configuration of the sensor 192.

[0075] The sensor 192 is arranged on the non-display side S2 of the display panel by means of double-sided adhesive or the like, and the orthographic projection of the sensor 192 on the base substrate 14 at least partially overlaps with the first display area 10, and is configured to receive light from the first side S1. Thus, the first display area 10 facilitates the arrangement of the sensor 192 while realizing display.

[0076] For example, Figure 4 A partially enlarged schematic diagram of a display substrate provided by at least one embodiment of the present disclosure. Figure 4 As shown, the first display area 10 includes a first sub-pixel array (composed of white squares in the first display area 10). The first sub-pixel array includes a plurality of light-emitting devices 11 (white squares in the first display area 10) arranged in an array.

[0077] The second display area 20 includes a first pixel circuit array (composed of gray boxes in the second display area 20), and the first pixel circuit array includes a plurality of first pixel circuit units D arranged in an array (gray boxes in the second display area 20). The second display area 20 also includes a second sub-pixel array (composed of white boxes in the second display area 20). The second sub-pixel array includes a plurality of first pixel units P arranged in an array, and the plurality of first pixel units P and the plurality of first pixel circuit units D are arranged alternately.

[0078] The third display area 30 at least partially surrounds the second display area 20 . The third display area 30 includes a third sub-pixel array. The third sub-pixel array includes a plurality of second pixel units C arranged in an array (white boxes in the third display area 30 ).

[0079] A plurality of first pixel circuit units D are used to drive a plurality of light-emitting devices 11 in the first display area 10 in a one-to-one correspondence. That is, the pixel circuit D for the first sub-pixel array in the first display area 10 is arranged in the second display area 20, and the pixel circuit and the light-emitting device of each sub-pixel unit are separated from each other in position. The incident light from the display side S1 can be transmitted through the blank area between adjacent light-emitting devices 11 to ensure the light transmittance of the first display area 10. Each first pixel unit P includes a third light-emitting device and a third pixel circuit directly connected to each other, and the third light-emitting device and the third pixel circuit are located in the same pixel area and are not separated from each other in position. Each second pixel unit C includes a fourth light-emitting device and a fourth pixel circuit directly connected to each other, and the fourth light-emitting device and the fourth pixel circuit are located in the same pixel area and are not separated from each other in position.

[0080] For example, Figure 4 As shown, the array of first pixel units P in the second display area 20 and the array of multiple light emitting devices 11 in the first display area 10 are aligned with each other to be distributed in multiple rows and columns (such as Figure 4 ), thereby forming a new (complete) array including multiple rows and columns, so that the first display area 10 and the second display area 20 have the same resolution.

[0081] For example, Figure 5 A schematic plan view of wiring arrangement in a display area of ​​a display substrate provided by at least one embodiment of the present disclosure. Figure 5 As shown, the plurality of light emitting devices 11 in the first display area 10 include a first light emitting device 114 and a second light emitting device 115. Correspondingly, the plurality of first pixel circuit units D in the second display area 20 include a first pixel circuit D10 and a second pixel circuit D20, which are respectively used to receive a driving signal to drive the first light emitting device 114 and the second light emitting device 115 to emit light. For example, the first pixel circuit D10, the second pixel circuit D20, the first light emitting device 114 and the second light emitting device 115 are located in a row (e.g. Figure 5 In the first display area 10, the first light emitting device 114 is connected to the first pixel circuit D10 in a corresponding manner in the first direction X1, thereby functionally constituting a sub-pixel in the first display area 10. The second light emitting device 115 is connected to the second pixel circuit D20 in a corresponding manner in the first direction X1, thereby functionally constituting a sub-pixel in the first display area 10.

[0082] It should be noted that Figure 5 In the figure, two rows in the first display area 10 and the second display area 20 are taken as examples, and the arrangement of other rows is the same and is not shown in the figure.

[0083] For example, Figure 5 As shown, the display substrate 1000 also includes a plurality of first connection lines 101 and a plurality of second connection lines 102. The plurality of first connection lines 101 generally extend along the first direction X1, and the plurality of second connection lines 102 also generally extend along the first direction X1. The plurality of first connection lines 101 and the plurality of first connection lines 102 are arranged in parallel in the first direction X1, and the orthographic projections of the plurality of first connection lines 101 and the plurality of second connection lines 102 on the substrate do not cross to avoid signal crosstalk between each other. The plurality of first connection lines 101 and the plurality of second connection lines 102 are located in the first display area 10 and the second display area 20, that is, they extend through the first display area 10 and the second display area 20.

[0084] For example, Figure 5 As shown, a plurality of first connection lines 101 electrically connect a plurality of first pixel circuits D10 and a plurality of first light-emitting devices 114 in one-to-one correspondence, and the first pixel circuit D10 is configured to drive the first light-emitting device 114 to emit light through the first connection line 101. The first connection line 101 electrically connects the first pixel circuits D10 and the first light-emitting devices 114 located in the same row. A plurality of second connection lines 102 electrically connect a plurality of second pixel circuits D20 and a plurality of second light-emitting devices 115 in one-to-one correspondence, and the second pixel circuit D20 is configured to drive the second light-emitting device 115 to emit light through the second connection line 102. The second connection line 102 electrically connects the second pixel circuits D20 and the second light-emitting devices 115 located in the same row.

[0085] For example, Figure 5 As shown, each of the plurality of light emitting devices 11 includes a first electrode 111 (eg, an anode of the light emitting device 11). The first electrodes 111 of the plurality of first light emitting devices 114 and the plurality of second light emitting devices 115 are arranged in the same row along a first direction (eg, Figure 5 In the first display area 10, the plurality of first connection wires 101 and the plurality of second connection wires 102 are electrically connected to the plurality of first light emitting devices 114 and the plurality of second light emitting devices 115 in the same row, respectively.

[0086] The plurality of first connection traces 101 are at least partially located on the first side HS1 of the row where the first electrodes 111 of the plurality of first light-emitting devices 114 and the plurality of second light-emitting devices 115 are located in the second direction Y1, and the plurality of second connection traces 102 are at least partially located on the second side HS2 of the row where the first electrodes 111 of the plurality of first light-emitting devices 114 and the plurality of second light-emitting devices 115 are located in the second direction Y1. The first side HS1 and the second side HS2 of the row where the first electrodes 111 of the plurality of first light-emitting devices 114 and the plurality of second light-emitting devices 115 are located are opposite in the second direction Y1. That is, the first side HS1 and the second side HS2 respectively represent the upper side and the lower side of the row where the first electrodes 111 of the plurality of first light-emitting devices 114 and the plurality of second light-emitting devices 115 are located.

[0087] As shown in the figure, a plurality of first connection lines 101 extend from the second display area 20 to the first display area 10 from the first side HS1, and a plurality of first connection lines 102 extend from the second display area 20 to the first display area 10 from the second side HS2. Thus, increasing the utilization rate of the wiring space in the second direction Y1 by the plurality of first connection lines 101 and the plurality of first connection lines 102 is beneficial to increasing the arrangement density of the plurality of first light-emitting devices 114 and the plurality of second light-emitting devices 115. For example, within the same spatial range in the second direction Y1, the number of rows of light-emitting devices arranged increases, and correspondingly, the number of rows of the first pixel units P in the second display area 20 can also be increased, thereby increasing the resolution of the first display area and the second display area, thereby reducing the difference between the display effects of the first display area and the second display area and the display effect of the third display area.

[0088] For example, in some embodiments, the second direction X1 and the first direction Y1 intersect each other. Figure 4 In the example, the second direction X1 is a horizontal direction (row direction), the first direction Y1 is a vertical direction (column direction), and the second direction X1 is perpendicular to the first direction Y1. It should be noted that the second direction X1 and the first direction Y1 may also cross each other instead of being perpendicular. Figure 5 The embodiment shown in the figure is only an example, and the embodiments of the present disclosure are not limited thereto.

[0089] For example, Figure 5As shown, in the second display area 20, the first pixel circuit D10 is located on the left side of the first display area 10 in the first direction X1 (i.e., the side away from the first display area 10). For example, the first light-emitting device 114 is located on the left side of the first display area 10 in the first direction X1 (i.e., the side close to the second display area 20). When the plurality of first connecting wires 101 are electrically connected from the first side HS1 and the plurality of second connecting wires 102 are electrically connected from the second side HS2 to the plurality of first light-emitting devices 114 and the plurality of second light-emitting devices 115 in the same row, the wiring density between the plurality of first connecting wires 101 and the plurality of second connecting wires 102 can be improved, and no overlap occurs between them.

[0090] For example, Figure 4 As shown, the light emitting device 11 of the first display area 10 can be divided into a light emitting device 11 on the left and a light emitting device 11 on the right from the center line Y11 of the first display area 10. The light emitting device 11 on the left can be connected to the first pixel circuit unit D in the second display area 20 located on the left side of the first display area 10 according to Figure 5 The light emitting device 11 on the right side is connected to the first pixel circuit unit D in the second display area 20 located on the right side of the first display area 10 in accordance with Figure 5 That is, the structure of the light emitting device 11 on the right and the part of the second display area 20 on the right and the structure of the light emitting device 11 on the left and the part of the second display area 20 on the left can be symmetrical about the center line Y11.

[0091] For example, Figure 5 As shown, when the second connecting line 102 is electrically connected to the second light-emitting devices 115 in the same row from the second side HS2, in the first display area 10, the orthographic projection of the second connecting line 102 on the substrate substrate 14 overlaps with the first electrodes 111 of the plurality of second light-emitting devices 115 it passes through, and when the first connecting line 102 is electrically connected to the second light-emitting devices 115 in the same row from the first side HS2, in the first display area 10, the orthographic projection of the first connecting line 102 on the substrate substrate 14 does not overlap with the first light-emitting devices 114 and the first electrodes 111 of the second light-emitting devices 115, so the number of connecting lines overlapping with the light-emitting devices 111 is reduced, thereby improving the transmittance of the first display area.

[0092] For example, the first connecting wire 101 and the second connecting wire 102 (for example, at least in the portion of the first display area 10) are transparent conductive wires, so that the first connecting wire 101 and the second connecting wire 102 have high light transmittance, which can ensure that the first display area 10 has high light transmittance.

[0093] For example, the material of the first connecting trace 151 and the second connecting trace 152 may include a transparent conductive material, such as transparent metal oxides such as indium tin oxide (ITO) and indium zinc oxide (IZO), and the material of the metal trace layer may include metal materials such as silver (Ag), aluminum (Al), molybdenum (Mo) or titanium (Ti) or their alloy materials.

[0094] For example, Figure 4 As shown, the array arrangement density of the plurality of second pixel units C is greater than the array arrangement density of the plurality of first pixel units P in the second display area 20, and is also greater than the array arrangement density of the plurality of light-emitting devices 11 in the first display area 10, so that the display resolution of the third display area 30 is higher than the display resolutions of the second display area 20 and the first display area 10.

[0095] For example, Figure 4 As shown, the density of the array arrangement of the light-emitting devices 11 in the first display area 10 is the same as the density of the array arrangement of the first pixel units P in the second display area, and the first pixel circuit arrays are alternately arranged in the gaps after the array arrangement of the first pixel units P in the second display area 20, which are used to be electrically connected to the array of the light-emitting devices 11 in the first direction Y1 and the second direction X1 respectively to drive the light-emitting devices 11 to emit light.

[0096] For example, each of the plurality of first connecting traces includes a first main body portion and at least one first bending portion. Figure 5 As shown, each of the plurality of first connecting traces 101 includes a first main body portion 1011 and a first bending portion 1012 .

[0097] The first main body 1011 is located in the first display area 10 and the second display area 20 and extends along the first direction X1. In the first display area 10, the first main body 1011 is located on the first side HS1 of the row where the first electrodes 111 of the plurality of first light-emitting devices 114 and the plurality of second light-emitting devices 115 are located, and in the second display area 20, the first main body 1011 is located on the first side HS1 of the row where the first pixel circuit D10 is located. It should be noted that, since the first pixel circuit D10 and the light-emitting device 11 are located in the same row, the row where the first electrodes 111 of the plurality of first light-emitting devices 114 and the plurality of second light-emitting devices 115 are located is the same row as the row where the first pixel circuit D10 is located, and the first side HS1 also refers to the same side, that is, the side away from the first electrode 111 of the light-emitting device 11. In addition, the second side HS2 mentioned in the embodiment also refers to the side close to the first electrode 111 of the light-emitting device 11. The first main body 1011 is connected to the first electrodes 111 of the plurality of first light-emitting devices 114 in a one-to-one correspondence to provide a light-emitting driving current.

[0098] The first bending portion 1012 is located in the second display area 20 and is connected to the first pixel circuit D10 and the first main body 1011. The first bending portion 1012 extends from the first pixel circuit D10 to the first side HS1 of the first pixel circuit D10. That is, when the plurality of first connecting wires 101 are led out from the first pixel circuit D10, they first pass through the bending wires and then are routed along the first direction X1.

[0099] For example, the first connecting line 101 connecting the first pixel circuit D10 in the first column (leftmost side) shown in the figure is first led out from the second side HS2 of the first pixel circuit D10 and then extends to the first side HS1 of the first pixel circuit D10. The first connecting line 101 may include two chamfered portions and a line extending along the first direction X1 and a line extending along the second direction Y1.

[0100] For example, as shown in the figure, the first connection line 101 connecting the first pixel circuit D10 of the second column (the second to last on the left) is first led out from the first side HS1 of the first pixel circuit D10, first extends in a direction away from the first pixel circuit D10, and then connects to the main body 1011. The first connection line 101 may include a chamfered portion. The first bending portion 1012 may make the first main body 1011 away from the first electrodes 111 of the plurality of first light-emitting devices 114 in the first display area 10, so as to improve the utilization rate of the wiring space.

[0101] For example, the second side HS2 of the first pixel circuit D10 is opposite to the first side HS1 in the second direction Y1.

[0102] For example, in other embodiments, when the connection lines do not overlap each other, the first bending portion 1012 may also be in the form of a partially arcuate line, for example, the chamfered portion is an arc.

[0103] For example, at least a portion of at least one first bent portion extends along the third direction toward the first side of the first pixel circuit. Figure 5 As shown, at least part of the first bent portion 1012 extends along the third direction G1 toward the first side HS1 of the first pixel circuit D10. For example, two chamfered portions of the first connecting wire 101 connecting the first pixel circuit D10 of the first column (the leftmost side) shown in the figure extend along the third direction G1. One chamfered portion of the first connecting wire 101 connecting the first pixel circuit D10 of the second column (the second to last on the left side) shown in the figure extends along the third direction G1. The third direction G1 intersects the first direction X1 and the second direction Y1, that is, the third direction G1 is different from the first direction X1 and the second direction Y1.

[0104] For example, Figure 5As shown, the first bending portion 1012 of the first row in the figure and the first bending portion 1012 of the second row do not cross each other when routing. For example, the chamfered portion of the first connecting wire 101 connecting the first pixel circuit D10 of the first row and the first column (the leftmost side) shown in the figure and the chamfered portion of the first connecting wire 101 connecting the first pixel circuit D10 of the second row and the second column (the second to last on the left side) shown in the figure are arranged in parallel with each other. Thus, the spacing between different connecting wires is increased to avoid signal crosstalk.

[0105] For example, at least one first bending portion of at least one of the plurality of first connecting traces includes a first sub-bending portion.

[0106] Figure 6 A schematic plan view of wiring arrangement in a display area of ​​a display substrate provided in at least another embodiment of the present disclosure. Figure 6 As shown, the first bending portion 1012 of the first connecting line 101 includes a first sub-bending portion 1013 (eg, a chamfered portion). The first sub-bending portion 1013 is located in the first pixel circuit D10 (eg, Figure 6 The first side HS1 of the first pixel circuit D10 located in the 5th column from the left in the figure extends along the third direction G1. The first sub-bending portion 1013 is connected to the first pixel circuit D10 and the first main body 1011. The first pixel circuit D10 connected to the first sub-bending portion 1013 is adjacent to the second pixel circuit D20. That is to say, the first pixel circuit D10 connected to the first sub-bending portion 1013 is the first pixel circuit D10 closest to the second pixel circuit D20. The first connecting line 101 including the first sub-bending portion 1013 is closest to the inner connecting line of the previous row. That is to say, in the second direction Y1, the other connecting lines are arranged on the lower side of the first connecting line 101 including the first sub-bending portion 1013. The above-mentioned arrangement can make the best use of the wiring space of the display substrate while ensuring that the connecting lines do not cross.

[0107] For example, at least one first bending portion of at least one of the multiple first connecting lines extends from the second side of the first pixel circuit to the first side of the first pixel circuit, and includes a second sub-bending portion, a third sub-bending portion, a first sub-connecting portion and a second sub-connecting portion.

[0108] like Figure 6 As shown, the first bending portion 1012 of the first connecting wire 101 extends from the second side HS2 of the first pixel circuit D10 to the first side HS1 of the first pixel circuit D10. Figure 6The connection lines of the first pixel circuit D10 in the first four columns on the left side. The first connection line 101 includes a second sub-bending portion 1014 (e.g., a chamfered portion), a third sub-bending portion 1015 (e.g., a chamfered portion), a first sub-connection portion 1016, and a second sub-connection portion 1017. The first sub-connection portion 1016 and the second sub-bending portion 1014 are located at the second side HS2 of the first pixel circuit DH10, the second sub-bending portion 1014 extends along the third direction G1, the first sub-connection portion 1016 extends along the first direction X1 and is connected to the first pixel circuit DH10 and the second sub-bending portion 1014. The second sub-connection portion 1017 extends along the second direction Y1 and is located between the adjacent first pixel circuit D10 (connected to the first connection line 101 including the first sub-bending portion 1013) and the second sub-pixel circuit D20, and the second sub-connection portion 1017 is connected to the second sub-bending portion 1014 and the third sub-bending portion 1015. The third sub-bending portion 1015 is located on the first side HS1 of the first pixel circuit D10, and the third sub-bending portion 1015 extends along the third direction G1 and is connected to the first main body 1011 of the first connecting wiring 101, so that the first main body 1011 of the first connecting wiring 101 is located on the first side HS1 of the first light-emitting device 114 in the first display area.

[0109] For example, Figure 6 As shown, connect Figure 6 The first connection line 101 of the first pixel circuit D10 in the first four columns on the left is located at the connection Figure 6 The first connection line 101 of the first pixel circuit D10 in the fifth column from the left is connected to the first light-emitting devices 114 in the first to fourth columns from the left in the first display area. Figure 6 The first connection line 101 of the first pixel circuit D10 in the fifth column on the left side is also connected to the first light-emitting device 114 in the fifth column in the first display area.

[0110] For example, in other embodiments, the first connecting wires 101 are all configured to be connected to the Figure 6 The first connection wiring 101 of the first pixel circuit D10 in the first four columns on the left side is the same as the wiring mode. That is, the first connection wiring 101 including the first sub-bending portion 1013 is not provided (for example, the connection wiring Figure 6 In this variant embodiment, the connection Figure 6 The second sub-connection portion 1017 of the first connection line 101 of the first pixel circuit D10 in the first four columns on the left side is from, Figure 6 The first pixel circuit D10 of the fourth column and the fifth column on the left side passes through, and the connection Figure 6The first connection line 101 of the first pixel circuit D10 in the fifth column on the left side is also connected to the first light emitting device 114 on the leftmost side (first column) in the first display area, and the connection line 101 of the first pixel circuit D10 in the fifth column on the left side is also connected to the first light emitting device 114 on the leftmost side (first column) in the first display area. Figure 6 The first connection line 101 of the first pixel circuit D10 in the first four columns on the left is located at the connection Figure 6 A side of the first connection wiring 101 of the first pixel circuit D10 in the fifth column from the left, away from the first pixel circuit D10, is respectively connected to the first light-emitting devices 114 in the second to fifth columns from the left in the first display area.

[0111] For example, as shown in the figure Figure 5 As shown in Figure 6, each of the plurality of second connecting wires 102 includes a second main body 1021. The second main body 1021 extends along the first direction X1 and is located at the second side HS2 of the row where the first electrodes 111 of the plurality of first light-emitting devices 114 and the plurality of second light-emitting devices 115 are located. The second main body 1021 is connected to the first electrode 111 of the second light-emitting device 115 and the second pixel circuit connection D20. The second main body 1021 is located on a side of the first main body 1011 of the first connecting wire 101 close to the first electrodes 111 of the plurality of first light-emitting devices 114 and the plurality of second light-emitting devices 115. In the first display area 10, the orthographic projection of the main body 1021 of the second connecting wire 102 on the base substrate overlaps with the orthographic projection of the first electrodes 111 of the plurality of second light-emitting devices 114 and the plurality of first light-emitting devices 115 on the base substrate, thereby increasing the utilization of the wiring space and improving the resolution of the first display area and the second display area.

[0112] For example, Figure 6 As shown, the first main bodies 1011 of the plurality of first connection traces 101 and the second main bodies 1021 of the plurality of second connection traces 102 are arranged in parallel in the first direction X1, thereby increasing the utilization of the wiring space and improving the resolution of the first display area and the second display area.

[0113] For example, Fig. 9A For along Figure 6 Schematic diagram of the cross section along the midline B1-B2; Fig. 9B For along Figure 6 Schematic diagram of the cross section along the midline B3-B4. Figure 6 The line B1-B2 in FIG. 1 passes through the dark first connecting trace 101 (or the dark second connecting trace 102), Figure 6 The line B3-B4 in FIG. 1 passes through the light-colored first connecting trace 101 (or the light-colored second connecting trace 102). For example, Figure 6 The line B1-B2 and the line B3-B4 in FIG. 1 may be two adjacent lines passing through the first connection line 101, or two adjacent lines passing through the second connection line 102. Fig. 9A as well as Fig. 9B As shown, the display substrate 1000 also includes a first insulating layer (ie, a first planarizing layer 144 ), a second insulating layer (ie, a second planarizing layer 145 ), a third insulating layer (ie, a third planarizing layer 146 ), a first transparent wiring layer 151 , and a second transparent wiring layer 152 .

[0114] For example, Fig. 9A as well as Fig. 9B As shown, the first planarization layer 144 is located on the side of the first pixel circuit D10 or the second pixel circuit D20 away from the substrate 14 to provide a planarized surface, the second planarization layer 145 is located on the side of the first planarization layer 144 away from the substrate 14 to provide a planarized surface, the third planarization layer 146 is located on the side of the second planarization layer 145 away from the substrate 14 to provide a planarized surface, and the first transparent wiring layer 151 is located between the first planarization layer 144 and the second planarization layer 145 ( Fig. 9A The second transparent wiring layer 152 is located on the side of the second planarization layer 145 away from the base substrate 14 ( Fig. 9B The first light emitting device 114 or the second light emitting device 115 is located on a side of the third planarization layer 146 away from the substrate 14. The first electrode 111 of the first light emitting device 114 or the second light emitting device 115 is located on a side of the third planarization layer 146 away from the substrate 14.

[0115] For example, the materials of the first transparent wiring layer 151 and the second transparent wiring layer 152 may include transparent conductive materials, such as transparent metal oxides such as indium tin oxide (ITO) and indium zinc oxide (IZO), and the material of the metal wiring layer may include metal materials such as silver (Ag), aluminum (Al), molybdenum (Mo) or titanium (Ti) or their alloy materials.

[0116] For example, the materials of the first planarization layer 144, the second planarization layer 145, and the third planarization layer 146 include inorganic insulating materials such as silicon oxide, silicon nitride, and silicon oxynitride, and may also include organic insulating materials such as polyimide, polyphthalimide, polyphthalamide, acrylic resin, benzocyclobutene, or phenolic resin, but the embodiments of the present disclosure are not limited to this.

[0117] For example, Figure 6 as well as Fig. 9A As shown, the first transparent wiring layer 151 includes one of two adjacent first connection wirings 101 and one of two adjacent second connection wirings 102. That is, the first transparent wiring layer 151 includes Figure 6 The dark-colored first connecting trace 101 and the dark-colored second connecting trace 102 are shown in FIG.

[0118] For example, Figure 6 as well as Fig. 9B As shown, the second transparent wiring layer 152 includes the other of two adjacent first connection wirings 101 and the other of two adjacent second connection wirings 102. That is, the second transparent wiring layer 152 includes Figure 6 The second connection trace 102 of the light-colored first connection trace 101 in the first connection trace 101. The dark-colored first connection trace 101 in the first connection trace 101 is arranged at intervals with the light-colored first connection trace 101, and is respectively located in different film layers to reduce crosstalk between signals. The dark-colored second connection trace 102 in the second connection trace 102 is arranged at intervals with the light-colored second connection trace 102, and is respectively located in different film layers to reduce crosstalk between signals.

[0119] like Figure 5 , Fig. 9A as well as Fig. 9B As shown, the display substrate 1000 further includes a plurality of pixel circuit connection holes DH1. The plurality of pixel circuit connection holes DH1 are located in the second display area 20 and include a plurality of first pixel circuit connection holes DH11 and a plurality of second pixel circuit connection holes DH12. Fig. 9A As shown in FIG. 1 , the first pixel circuit connection hole DH11 penetrates the first planarization layer 144. The first connection wiring 101 or the second connection wiring 102 located in the first transparent wiring layer 151 is electrically connected to the first pixel circuit D10 or the second pixel circuit D20 through the first pixel circuit connection hole DH11. Fig. 9B As shown in the figure, the second pixel circuit connection hole DH12 passes through the first planarization layer 144 and the second planarization layer 145, and the first connection wiring 101 or the second connection wiring 102 located in the second transparent wiring layer 152 is electrically connected to the first pixel circuit D10 or the second pixel circuit D20 through the second pixel circuit connection hole DH12.

[0120] For example, Figure 7 A partial schematic diagram of a display substrate provided in at least one embodiment of the present disclosure. Figure 7 , a wiring layout diagram of the first display area 10 and the second display area 20 is shown, and the wiring layout is symmetrical about the center line Y11. Figure 7 The middle A1 area is a part of the first display area 10 .

[0121] Fig. 8A At least one embodiment of the present disclosure provides Figure 7 Enlarged view of the middle A1 area; Figure 8B At least another embodiment of the present disclosure provides Figure 7 Enlarged view of the middle A1 area; Figure 8C At least one embodiment of the present disclosure provides Figure 7 Magnified view of area A1 in the middle.

[0122] For example, Figure 5 as well as Fig. 8A As shown, the display substrate 1000 further includes a plurality of electrode connection holes PH1. The plurality of electrode connection holes PH1 are located in the first display region 10 and are located on the first side HS1 of the row where the first electrodes 111 of the plurality of first light emitting devices 114 and the plurality of second light emitting devices 115 are located, and include a plurality of first electrode connection holes PH11 and a plurality of second electrode connection holes PH12.

[0123] For example, Fig. 9A As shown, the first electrode connection hole PH11 penetrates the second planarization layer 144 and the third planarization layer 145, and the first connection wiring 101 or the second connection wiring 102 located in the first transparent wiring layer 151 is electrically connected to the first electrode 111 of the first light-emitting device 114 or the second light-emitting device 115 through the first electrode connection hole PH11.

[0124] For example, Fig. 9B As shown, the second electrode connection hole PH12 penetrates the third planarization layer 145, and the first connection wiring 101 and the second connection wiring 102 located in the second transparent wiring layer 152 are electrically connected to the first electrode 111 of the first light-emitting device 114 or the second light-emitting device 115 through the second electrode connection hole PH12.

[0125] For example, Figure 8C As shown, the display substrate 1000 further includes a first virtual line DML1 located in the first display area 10. The first virtual line DML1 is located between the first electrodes 111 of the plurality of first light emitting devices 114 and the plurality of second light emitting devices 115 in adjacent rows and extends along the second direction Y1. In other words, the first virtual line DML1 is located between the first electrodes 111 of the plurality of first light emitting devices 114 and the plurality of second light emitting devices 115 in adjacent rows and extends along the second direction Y1. Figure 8CThe first virtual routing line DML1 is connected to one end of the second connecting routing line 102 connected to the electrode connecting hole PH1. That is, the first virtual routing line DML1 can be regarded as a portion of the second connecting routing line 102 extending from the electrode connecting hole PH1 to the first side HS1. The first virtual routing line DML1 extends from the electrode connecting hole PH1 in a direction away from the first electrode 111 of the second light-emitting device 115. The orthographic projection of the first virtual routing line DML1 on the base substrate 14 does not overlap with the first connecting routing line 101 and the second connecting routing line 102. When the second connecting wire 102 is connected to the first electrode 111 of the second light-emitting device 115 through the electrode connecting hole PH1, the second connecting wire 102 passes through the first electrode 111 of the second light-emitting device 115, so that there is no wire on the side of the electrode connecting hole PH1 away from the first electrode 111 of the second light-emitting device 115, and the first connecting wire corresponding to the area has no wire on the side away from the first electrode 111 of the first light-emitting device 114. In order to make the wiring uniform and the light transmittance uniform, a first virtual wire DML1 is set.

[0126] For example, Fig. 9A as well as Fig. 9B As shown, the display substrate 1000 also includes a pixel defining layer 147. The pixel defining layer 147 is located on the side of the first electrode 111 of the plurality of light-emitting devices 11 (the first light-emitting device 114 or the second light-emitting device 115) away from the substrate 14, and includes a plurality of first pixel openings 147A. The plurality of first pixel openings 147A correspond one-to-one to the plurality of light-emitting devices 11 (the first light-emitting device 114 or the second light-emitting device 115) to form the light-emitting area 116 of the plurality of light-emitting devices 11 (the first light-emitting device 114 or the second light-emitting device 115). Each of the plurality of light-emitting devices 11 also includes a first light-emitting layer 112 and a second electrode 113 (for example, a cathode). The second electrode 113 is located on the side of the pixel defining layer 147 away from the substrate 14. The light-emitting layer 112 is located in the first pixel opening 147 and between the first electrode 111 and the second electrode 112 ; the portion of the light-emitting layer 112 directly sandwiched between the first electrode 111 and the second electrode 112 will emit light after being energized, so that the area occupied by this portion corresponds to the above-mentioned light-emitting area 116 .

[0127] For example, the material of the pixel defining layer 147 may include an organic insulating material such as polyimide, polyphthalimide, polyphthalamide, acrylic resin, benzocyclobutene or phenolic resin, or an inorganic insulating material such as silicon oxide or silicon nitride, which is not limited in the embodiments of the present disclosure.

[0128] For example, the material of the first electrode 111 may include at least one transparent conductive oxide material including indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), etc. In addition, the first electrode 111 may include a metal with high reflectivity as a reflective layer, such as silver (Ag).

[0129] For example, for OLED, the first light-emitting layer 112 may include small molecule organic materials or polymer molecule organic materials, and may be fluorescent luminescent materials or phosphorescent luminescent materials, and may emit red light, green light, blue light, or white light; and, as required, the light-emitting layer may further include functional layers such as an electron injection layer, an electron transport layer, a hole injection layer, and a hole transport layer. For QLED, the light-emitting layer may include quantum dot materials, such as silicon quantum dots, germanium quantum dots, cadmium sulfide quantum dots, cadmium selenide quantum dots, cadmium telluride quantum dots, zinc selenide quantum dots, lead sulfide quantum dots, lead selenide quantum dots, indium phosphide quantum dots, and indium arsenide quantum dots, and the particle size of the quantum dots is 2-20 nm.

[0130] For example, the second electrode 113 may include various conductive materials, such as lithium (Li), aluminum (Al), magnesium (Mg), silver (Ag), and the like.

[0131] For example, Figure 5 , Figure 8B , Fig. 9A as well as Fig. 9B As shown, at least part of the first electrode 111 of the plurality of light-emitting devices 11 (the first light-emitting device 114 or the second light-emitting device 115) includes a first electrode main body 1111 and a first electrode connecting portion 1112. The first electrode main body 1111 is located in the light-emitting area 116 of the light-emitting device 11 (the first light-emitting device 114 or the second light-emitting device 115). The first electrode connecting portion 1112 connects the electrode connecting hole PH1 (the first electrode connecting hole PH11 or the second electrode connecting hole PH12) and the first electrode main body 1111. In addition, for example, at least part of the first electrode 111 of the plurality of light-emitting devices 11 (the first light-emitting device 114 or the second light-emitting device 115) includes only the first electrode main body 1111, which is directly electrically connected to the electrode connecting hole PH1, thereby reducing the resistance between the transistor and the light-emitting area. Since the first connecting wire 101 and the second connecting wire 102 are located on both sides of the light-emitting device 11, the arrangement density of the first electrode 111 of the light-emitting device 11 is increased and the length of the first electrode connecting portion 1112 in the second direction Y2 is reduced, thereby increasing the transmittance of the first display area 10.

[0132] For example, Figure 8BAs shown, the shapes of the first electrode main body 1111 of the first electrode 111 of the light-emitting device 11 may be different. The shape of the first electrode 111 is roughly hexagonal and extends along the second direction Y1. For example, as shown in the figure, the length of the first electrode main body 1111 of the leftmost first electrode 111 in the second direction Y1 is larger, while the length of the first electrode main body 1111 of the two middle first electrodes 111 in the second direction Y1 is smaller than that of the first electrode main body 1111 of the leftmost first electrode 111, and the width of the first electrode main body 1111 of the first electrode 111 in the first direction X1 is larger than that of the first electrode main body 1111 of the leftmost first electrode 111. The shape of the first electrode main body 1111 of the first electrode 111 of the light-emitting device 11 can be designed according to the needs of more actual display, and the embodiments of the present disclosure are not limited thereto. For example, the shapes of the first electrode connecting portion 1112 of the first electrode 111 of the light-emitting device 11 may be different. Due to the different positions of the first connecting wire 101 or the second connecting wire 102 connected to the first electrode 111 of the light-emitting device 11 and the difference in the shape of the first electrode main body 1111 of the first electrode 111, the extension direction of the first electrode connecting portion 1112 or the length in the second direction Y1 is also different. For example, the first electrode connecting portion 1112 of the first electrode 111 on the far left in the figure extends along the first direction X1, while the first electrode connecting portion 1112 of the second electrode 111 on the left extends along the second direction Y1. The first electrode 111 of the light-emitting device 11 can be regarded as not having the first electrode connecting portion 1112, such as the first electrodes 111 of the two light-emitting devices 11 on the right side of the figure. Since the first connecting wire 101 or the second connecting wire 102 connected to the first electrode 111 of the light-emitting device 11 are respectively located on both sides of the first electrode 111 of the light-emitting device 11, the length of the first electrode connecting portion 1112 in the second direction Y1 is reduced (the first electrode connecting portion 1112 may or may not be provided), thereby increasing the light transmittance of the first display area. For example, Fig. 10A A schematic plan view of a display area of ​​a display substrate provided in at least one embodiment of the present disclosure. Fig. 10A The A2 area is located at the junction of the third display area 30 and the second display area 20. Fig. 10B At least one embodiment of the present disclosure provides Fig. 10A A magnified view of area A2 in the middle. Fig. 10BAs shown, the second sub-pixel array (the first sub-pixel array and the second sub-pixel array are arranged in the same manner) includes a plurality of first sub-pixels P1, a plurality of second sub-pixels P2, and a plurality of third sub-pixels P3. Each pixel P11 of the second sub-pixel array includes a first sub-pixel P1, a second sub-pixel P2, and a third sub-pixel P3. For example, the first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3 are arranged along the first direction X1. The pixel circuit connection via DH1 is located between the first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3. In other words, each of the pixels of the second sub-pixel array includes three sub-pixels and is arranged along the row direction. For example, the first sub-pixel P1 is a green sub-pixel G, the second sub-pixel P2 is a red sub-pixel R, and the third sub-pixel P3 is a blue sub-pixel B. The arrangement of the pixels of the first display area 10 and the second display area 20 can increase the pixel density, that is, improve the resolution of the first display area 10 and the second display area 20, and reduce the granularity of the display of the first display area 10 and the second display area 20.

[0133] For example, Fig. 10B As shown, the third sub-pixel array of the third display area 30 includes a plurality of first sub-pixels P1', a plurality of second sub-pixels P2' and a plurality of third sub-pixels P3'. One of two adjacent pixels of the third sub-pixel array, for example, pixel P12' includes a first sub-pixel P1' and a second sub-pixel P2', and the other of two adjacent pixels, for example, pixel P11' includes a first sub-pixel P1' and a third sub-pixel P3', and each second sub-pixel P2' and each third sub-pixel P3' are respectively shared by at least two adjacent pixels. The arrangement of pixels in the third display area 30 is different from that in the first display area 10 and the second display area 20. As mentioned above, the resolution of the third display area 30 is higher than that of the first display area 10 and the second display area 20.

[0134] The embodiments of the present disclosure do not limit the pixel circuit of the sub-pixel. For example, it can be a 2T1C (i.e., 2 transistors and 1 capacitor) type pixel circuit, the two transistors are respectively a data writing transistor and a driving transistor, the one capacitor is a signal storage capacitor, the pixel circuit can generate a driving current for driving the light-emitting element to emit light according to the received scanning signal and data signal, and the light-emitting element generates light of different intensities according to the magnitude of the driving current. The pixel circuit can also be other types of pixel circuits, for example, it can further have a compensation function, a reset function, a sensing function, etc., and thus can include more than 2 thin film transistors.

[0135] For example, Fig. 9A as well as Fig. 9BAs shown, the display substrate 1000 further includes a first gate insulating layer 141, a second gate insulating layer 142 and an interlayer insulating layer 143. The first pixel circuit D10 (or the second pixel circuit D20) includes a thin film transistor 12 and a storage capacitor 13. The thin film transistor 12 includes an active layer 121, a gate 122, and a source-drain electrode (a source 123 and a drain 124). The storage capacitor 13 includes a first capacitor plate 131 and a second capacitor plate 132. The active layer 121 is disposed on the base substrate 14, the first gate insulating layer 141 is disposed on a side of the active layer 121 away from the base substrate 100, the gate 122 and the first capacitor plate 131 are disposed in the same layer on a side of the first gate insulating layer 141 away from the base substrate 14, and the second gate insulating layer 142 is disposed on a side of the gate 122 and the first capacitor plate away from the base substrate 14. The second capacitor plate 132 is disposed on a side of the second gate insulating layer 142 away from the base substrate 14, and the interlayer insulating layer 143 is disposed on a side of the second capacitor plate 132 away from the base substrate 14. The source electrode 123 and the drain electrode 124 are disposed on a side of the interlayer insulating layer 143 away from the base substrate 14, and are electrically connected to the active layer 121 through the first gate insulating layer 141, the second gate insulating layer 142 and the via holes in the interlayer insulating layer 143. The first transparent wiring layer 151 is electrically connected to one of the source and drain electrodes through the first pixel circuit connection via DH11 in the first planarizing layer 144 (such as Fig. 9A The second transparent wiring layer 152 is electrically connected to one of the source and drain electrodes through the first planarization layer 144 and the second pixel circuit connection via DH12 in the second planarization layer 145 (as shown in FIG. Fig. 9B as shown electrically connected to drain 124).

[0136] It should be noted that in the embodiments of the present disclosure, "same-layer arrangement" includes two functional layers or structural layers being formed of the same material in the hierarchical structure of the display substrate, that is, in the preparation process, the two functional layers or structural layers can be formed of the same material layer and can be formed into the required pattern and structure by the same composition process. A single composition process, for example, includes the formation of photoresist, exposure, development, etching and other processes.

[0137] In another example, as Fig. 9A as well as Fig. 9B In a variation of the example shown, the first capacitor plate 131 of the storage capacitor 13 is still arranged in the same layer as the gate 122, while the second capacitor plate 132 of the storage capacitor 13 is arranged in the same layer as the source 123 and the drain 124, thereby the first capacitor plate 131 and the second capacitor plate 132 use the stack of the second gate insulation layer 142 and the interlayer insulation layer 143 as dielectric materials to form a storage capacitor.

[0138] In yet another example, as Fig. 9Aas well as Fig. 9B In a variation of the example shown, the first capacitor plate 13 of the storage capacitor is no longer arranged in the same layer as the gate 223, but is located between the second gate insulation layer 142 and the interlayer insulation layer 143, while the second capacitor plate 132 of the storage capacitor 13 is arranged in the same layer as the source 123 and the drain 124, thereby the first capacitor plate 131 and the second capacitor plate 132 use the interlayer insulation layer 143 as a dielectric material to form a storage capacitor.

[0139] For example, Fig. 9A as well as Fig. 9B As shown, the first display area 10 further includes a transparent support layer 191 located on the base substrate 14, and the light-emitting devices 11 (the first light-emitting device 114 and the second light-emitting device 115) are located on a side of the transparent support layer 191 away from the base substrate 14. Thus, relative to the base substrate 14, the light-emitting devices 11 in the first display area 10 can be aligned with the third light-emitting devices 21 ( Fig.11 ) and the fourth light emitting device 31 ( Fig.12 As shown in the figure, the two substrates are at substantially the same height, thereby improving the display effect of the display substrate.

[0140] For example, the transparent supporting layer 191 is disposed in the same layer as at least one of the first gate insulating layer 141, the second gate insulating layer 142, the interlayer insulating layer 143, and the first planarizing layer 144. For example, the transparent supporting layer 191 is disposed in the same layer as the first gate insulating layer 141, the second gate insulating layer 142, the interlayer insulating layer 143, and the first planarizing layer 144, so that the light emitting device 11 in the first display area 10 and the third light emitting device 21 ( Fig.11 ) and the fourth light emitting device 31 ( Fig.12 ) are at substantially the same height and simplify the preparation process of the display substrate.

[0141] For example, one or more of the first gate insulating layer 141, the second gate insulating layer 142 and the interlayer insulating layer 143 may include insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, etc. The materials of the first gate insulating layer 141, the second gate insulating layer 142 and the interlayer insulating layer 143 may be the same or different.

[0142] For example, the material of the active layer 121 may include polysilicon or an oxide semiconductor (e.g., indium gallium zinc oxide). The material of the gate 122 may include a metal material or an alloy material, such as a metal single layer or multilayer structure formed by molybdenum, aluminum, and titanium, for example, the multilayer structure is a multi-metal layer stack (e.g., a titanium, aluminum, and titanium three-layer metal stack (Ti / Al / Ti)). The material of the source 123 and the drain 124 may include a metal material or an alloy material, such as a metal single layer or multilayer structure formed by molybdenum, aluminum, and titanium, for example, the multilayer structure is a multi-metal layer stack (e.g., a titanium, aluminum, and titanium three-layer metal stack (Ti / Al / Ti)). The embodiments of the present disclosure do not specifically limit the materials of each functional layer.

[0143] For example, a passivation layer may be further provided between the first planarization layer and the source electrode 123 and the drain electrode 124. The passivation layer may be provided to include a via hole to expose one of the source electrode 123 and the drain electrode 124, for example, to expose the drain electrode 124. The passivation layer may protect the source electrode 123 and the drain electrode 124 from being corroded by water vapor. For example, the material of the passivation layer may include an organic insulating material or an inorganic insulating material, for example, a silicon nitride material, which has a relatively high dielectric constant and has a good hydrophobic function, and can well protect the first pixel circuit D10 or the second pixel circuit D20 from being corroded by water vapor.

[0144] For example, Fig. 9A as well as Fig. 9B As shown, the display substrate 1000 also includes an encapsulation layer 148. The encapsulation layer 148 is located on the side of the second electrode 113 away from the base substrate 148. The encapsulation layer 148 seals the light-emitting device 11 (the first light-emitting device 114 or the second light-emitting device 115), thereby reducing or preventing the degradation of the light-emitting device 11 caused by moisture and / or oxygen included in the environment. The encapsulation layer 148 can be a single-layer structure or a composite layer structure, and the composite layer structure includes a structure in which an inorganic layer and an organic layer are stacked. The encapsulation layer 148 includes at least one encapsulation sublayer. For example, the encapsulation layer 148 may include a first inorganic encapsulation layer, a first organic encapsulation layer, and a second inorganic encapsulation layer arranged in sequence.

[0145] For example, the material of the encapsulation layer 148 may include insulating materials such as silicon nitride, silicon oxide, silicon oxynitride, and polymer resin. Inorganic materials such as silicon nitride, silicon oxide, and silicon oxynitride have high density and can prevent the intrusion of water, oxygen, etc.; the material of the organic encapsulation layer may be a polymer material containing a desiccant or a polymer material that can block water vapor, such as a polymer resin, etc., to planarize the surface of the display substrate, and to relieve the stress of the first inorganic encapsulation layer and the second inorganic encapsulation layer, and may also include a desiccant and other water-absorbing materials to absorb water, oxygen, and other substances that intrude into the interior.

[0146] For example, Fig.11A cross-sectional schematic diagram of a second display area in a display substrate provided in at least one embodiment of the present disclosure. Fig.12 A schematic cross-sectional view of a third display area in a display substrate provided in at least one embodiment of the present disclosure.

[0147] For example, Fig.11 As shown, each of the plurality of first pixel units P of the second display area 20 of the display substrate 1000 includes a third light emitting device 21 and a third pixel circuit, and the third pixel circuit is electrically connected to the third light emitting device 21 to drive the third light emitting device 21. For example, the second pixel circuit includes a thin film transistor 22 and a storage capacitor 23 and other structures. The third light emitting device 21 includes a third electrode 211, a fourth electrode 213, and a second light emitting layer 212 between the third electrode 211 and the fourth electrode 213. The third electrode 211 is electrically connected to the third pixel circuit through a via. For example, the third electrode 211 is an anode of the third light emitting device 21, and the fourth electrode 213 is a cathode of the third light emitting device 21. The pixel defining layer 147 is disposed on a side of the third electrode 211 away from the base substrate 14, and includes a plurality of openings. The second light emitting layer 212 is disposed in a plurality of openings of the pixel defining layer 147. The fourth electrode 213 is disposed on a side of the second light emitting layer 212 and the pixel defining layer 147 away from the base substrate 14. The third electrode 211 is disposed in the same layer and made of the same material as the first electrode 111, and the fourth electrode 213 is disposed in the same layer and made of the same material as the second electrode 113. The second light emitting layer 212 is disposed in the same layer and made of the same material as the first light emitting layer 112.

[0148] For example, the thin film transistor 22 includes an active layer 221 , a gate 222 , source-drain electrodes (ie, a source 223 and a drain 224 ), a first switching electrode 215 and other structures, and the storage capacitor 23 includes a first capacitor plate 231 and a second capacitor plate 232 . The active layer 221 is arranged on the base substrate 14, the first gate insulating layer 141 is arranged on the side of the active layer 221 away from the base substrate 14, the gate 222 and the first capacitor plate 231 are arranged in the same layer on the side of the first gate insulating layer 141 away from the base substrate 14, the second gate insulating layer 142 is arranged on the side of the gate 222 and the first capacitor plate 231 away from the base substrate 14, the second capacitor plate 232 is arranged on the side of the second gate insulating layer 142 away from the base substrate 14, the interlayer insulating layer 143 is arranged on the side of the second capacitor plate 232 away from the base substrate 14, the source and drain electrodes are arranged on the side of the interlayer insulating layer 143 away from the base substrate 14, and are electrically connected to the active layer 221 through vias in the first gate insulating layer 141, the second gate insulating layer 142 and the interlayer insulating layer 143, and the first planarization layer 144 is arranged on the side of the source and drain electrodes away from the base substrate 14 to provide a first planarization surface to planarize the third pixel circuit.

[0149] For example, the active layer 221, gate 222, source-drain electrode (i.e., source 223 and drain 224) of the thin film transistor 22 are respectively arranged in the same layer and made of the same material as the source layer 121, gate 122, and source-drain electrode (source 123 and drain 124) of the thin film transistor 12. The first capacitor plate 231 and the second capacitor plate 232 of the storage capacitor 23 are respectively arranged in the same layer and made of the same material as the first capacitor plate 131 and the second capacitor plate 132 of the storage capacitor 13.

[0150] For example, Fig.11 As shown, the first planarization layer 144 has a first via hole 144A, and the first transfer electrode 215 is arranged on a side of the first planarization layer 144 away from the base substrate 14, and is electrically connected to the source 223 (or drain 224) of the source-drain electrode through the first via hole 144A. The second planarization layer 145 and the third planarization layer 146 have a second via hole 145A, and the fourth electrode 213 of the third light-emitting device 21 is electrically connected to the first transfer electrode 215 through the second via hole 145A.

[0151] For example, in other embodiments, the first transfer electrode 215 may also be disposed on a side of the second planarization layer 145 away from the base substrate 14. In this case, the first via 144A penetrates the first planarization layer 144 and the second planarization layer 145, and the second via 145A penetrates the third planarization layer 146.

[0152] For example, Fig.12 As shown, each of the plurality of second pixel units C of the third display area 30 of the display substrate 1000 includes a fourth light emitting device 31 and a fourth pixel circuit, and the fourth pixel circuit is electrically connected to the fourth light emitting device 31 to drive the fourth light emitting device 31. For example, the fourth pixel circuit includes a thin film transistor 32 and a storage capacitor 33 and other structures. The fourth light emitting device 31 includes a fifth electrode 311, a sixth electrode 313, and a third light emitting layer 312 between the fifth electrode 311 and the sixth electrode 313. The fifth electrode 311 is electrically connected to the fourth pixel circuit through a via. For example, the fifth electrode 311 is an anode of the fourth light emitting device 31, and the sixth electrode 313 is a cathode of the fourth light emitting device 31. The pixel defining layer 147 is disposed on a side of the fifth electrode 311 away from the base substrate 14, and includes a plurality of openings. The third light layer 312 is disposed in a plurality of openings of the pixel defining layer 147. The sixth electrode 313 is disposed on a side of the third light emitting layer 312 and the pixel defining layer 147 away from the base substrate 14. The fifth electrode 311 is disposed in the same layer and made of the same material as the first electrode 111, and the sixth electrode 213 is disposed in the same layer and made of the same material as the second electrode 113. The third light emitting layer 312 is disposed in the same layer and made of the same material as the first light emitting layer 112.

[0153] For example, the thin film transistor 32 includes an active layer 321 , a gate 322 , source-drain electrodes (ie, a source 323 and a drain 324 ), a first switching electrode 315 and other structures, and the storage capacitor 33 includes a first capacitor plate 331 and a second capacitor plate 332 . The active layer 321 is arranged on the base substrate 14, the first gate insulating layer 141 is arranged on the side of the active layer 321 away from the base substrate 14, the gate 322 and the first capacitor plate 331 are arranged in the same layer on the side of the first gate insulating layer 141 away from the base substrate 14, the second gate insulating layer 142 is arranged on the side of the gate 322 and the first capacitor plate 331 away from the base substrate 14, the second capacitor plate 332 is arranged on the side of the second gate insulating layer 142 away from the base substrate 14, the interlayer insulating layer 143 is arranged on the side of the second capacitor plate 332 away from the base substrate 14, the source and drain electrodes are arranged on the side of the interlayer insulating layer 143 away from the base substrate 14, and are electrically connected to the active layer 221 through vias in the first gate insulating layer 141, the second gate insulating layer 142 and the interlayer insulating layer 143, and the first planarization layer 144 is arranged on the side of the source and drain electrodes away from the base substrate 14 to provide a first planarization surface to planarize the third pixel circuit.

[0154] For example, the active layer 321, gate 322, source-drain electrode (i.e., source 323 and drain 324) of the thin film transistor 32 are respectively arranged in the same layer and made of the same material as the source layer 121, gate 122, and source-drain electrode (source 123 and drain 124) of the thin film transistor 12. The first capacitor plate 331 and the second capacitor plate 332 of the storage capacitor 33 are respectively arranged in the same layer and made of the same material as the first capacitor plate 131 and the second capacitor plate 132 of the storage capacitor 13.

[0155] For example, Fig.12 As shown, the first planarization layer 144 has a first via hole 144A, and the first transfer electrode 315 is arranged on a side of the first planarization layer 144 away from the base substrate 14, and is electrically connected to the source 323 (or drain 324) of the source-drain electrode through the first via hole 144A. The second planarization layer 145 and the third planarization layer 146 have a second via hole 145A, and the sixth electrode 313 of the fourth light-emitting device 31 is electrically connected to the first transfer electrode 315 through the second via hole 145A.

[0156] For example, in other embodiments, the first transfer electrode 315 may also be disposed on a side of the second planarization layer 145 away from the base substrate 14. In this case, the first via 144A penetrates the first planarization layer 144 and the second planarization layer 145, and the second via 145A penetrates the third planarization layer 146.

[0157] It should be noted that the first pixel circuit, the second pixel circuit and the third pixel circuit in the second display area 20 have the same structure as the fourth pixel circuit in the third display area 30, and therefore can be formed by the same patterning process in the preparation process. For example, the first gate insulating layer 141, the second gate insulating layer 142, the interlayer insulating layer 143, the first planarizing layer 144, the second planarizing layer 145, the third planarizing layer 146, the pixel defining layer 147 and the encapsulation layer 148 are arranged in the same layer in the second display area 20 and the third display area 30, and in some embodiments, they are integrated, such as the same insulating layer, and therefore the same reference numerals are used in the drawings.

[0158] For example, Fig. 9A , Fig. 9B , Fig.11 as well as Fig.12 As shown, the base substrate 14 may be a glass plate, a quartz plate, a metal plate or a resin plate, etc. For example, the material of the base substrate may include an organic material, such as a resin material such as polyimide, polycarbonate, polyacrylate, polyetherimide, polyethersulfone, polyethylene terephthalate and polyethylene naphthalate; for example, the base substrate 14 may be a flexible substrate or a non-flexible substrate, which is not limited in the embodiments of the present disclosure.

[0159] Fig.13 A schematic diagram of a display device provided by at least one embodiment of the present disclosure. At least one embodiment of the present disclosure provides a display device 2000, and the display device 2000 may include the display substrate 1000 of any of the above embodiments.

[0160] For example, Fig.13 As shown, the display device 2000 may further include a flexible circuit board and a control chip. For example, the flexible circuit board is bonded to the bonding area of ​​the display substrate 1000, and the control chip is mounted on the flexible circuit board, thereby being electrically connected to the display area; or the control chip is directly bonded to the bonding area, thereby being electrically connected to the display area.

[0161] For example, the control chip may be a central processing unit, a digital signal processor, a system-on-chip (SoC), etc. For example, the control chip may also include a memory, a power module, etc., and realize power supply and signal input and output functions through additionally provided wires, signal lines, etc. For example, the control chip may also include hardware circuits and computer executable codes, etc. The hardware circuit may include conventional very large scale integration (VLSI) circuits or gate arrays and existing semiconductors or other discrete components such as logic chips and transistors; the hardware circuit may also include field programmable gate arrays, programmable array logic, programmable logic devices, etc.

[0162] For example, the display device 2000 provided in at least one embodiment of the present disclosure may be any product or component with a display function, such as an OLED panel, an OLED TV, a QLED panel, a QLED TV, a mobile phone, a tablet computer, a notebook computer, a digital photo frame, a navigator, etc. The display device 2000 may also include other components, such as a data drive circuit, a timing controller, etc., which are not limited in the embodiments of the present disclosure.

[0163] For example, Figure 3B , Fig. 9A as well as Fig. 9B As shown, the display device 2000 further includes a sensor 192. The sensor 192 is disposed on the second side S2 (e.g., the non-display side) of the display substrate 1000. The sensor 192 is configured to receive light (e.g., collimated light or collimated light) from the first side S1 (e.g., the display side of the display substrate) of the display substrate 1000. The orthographic projection of the sensor 192 on the base substrate 14 at least partially overlaps with the first display area 10.

[0164] For example, the sensor 192 is an image sensor, an infrared sensor, a distance sensor, etc. The sensor 192 can be implemented in the form of a chip, etc. The sensor 192 is disposed on the non-display side S2 (the side facing away from the user) of the display substrate.

[0165] For example, the sensor 192 and the first display area 10 at least partially overlap in the normal direction of the display surface of the display substrate.

[0166] For example, the sensor 192 may be an image sensor, and may be used to collect an image of the external environment facing the light-collecting surface of the sensor 192, such as a CMOS image sensor or a CCD image sensor; the sensor 192 may also be an infrared sensor, a distance sensor, etc. The sensor 192 may be used to implement a camera of a mobile terminal such as a mobile phone or a notebook, and may further include optical devices such as a lens, a reflector, or an optical waveguide to modulate the optical path as required. The embodiments of the present disclosure do not limit the type, function, and configuration of the sensor 192.

[0167] The sensor 192 is arranged on the non-display side S2 of the display panel by means of double-sided adhesive or the like, and the orthographic projection of the sensor 192 on the base substrate 14 at least partially overlaps with the first display area 10, and is configured to receive light from the first side S1. Thus, the first display area 10 facilitates the arrangement of the sensor 192 while realizing display.

[0168] It should be noted that, for the sake of clarity and simplicity, the embodiments of the present disclosure do not provide all the components of the display device. To realize the substrate function of the display device, those skilled in the art may provide and set other structures not shown according to specific needs, and the embodiments of the present disclosure are not limited to this.

[0169] The technical effects of the display device provided in the above embodiments may refer to the technical effects of the display substrate provided in the embodiments of the present disclosure, which will not be described in detail here.

[0170] There are a few points to note:

[0171] (1) The drawings of the embodiments of the present disclosure only relate to the structures related to the embodiments of the present disclosure, and other structures may refer to the general design.

[0172] (2) In the absence of conflict, the embodiments of the present disclosure and the features therein may be combined with each other to obtain new embodiments.

[0173] The above are only specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A display substrate having a first side for display and a second side opposite to the first side, comprising: A substrate substrate, comprising: display area, the display area comprising a first display area and a second display area at least partially surrounding the first display area, The first display area includes a first sub-pixel array, and the first display area allows light from the first side of the display substrate to be at least partially transmitted to the second side of the display substrate, the first sub-pixel array includes a plurality of light-emitting devices arranged in an array, and the plurality of light-emitting devices include a plurality of first light-emitting devices and a plurality of second light-emitting devices, The second display area includes a first pixel circuit array, the first pixel circuit array includes a plurality of first pixel circuit units, and the plurality of first pixel circuit units include a plurality of first pixel circuits and a plurality of second pixel circuits; a plurality of first connecting wires, at least partially extending along a first direction, and connecting the plurality of first pixel circuits and the plurality of first light-emitting devices in a one-to-one correspondence, wherein the first pixel circuits are configured to drive the first light-emitting devices through the first connecting wires; a plurality of second connecting wires, at least partially extending along the first direction, and connecting the plurality of second pixel circuits and the plurality of second light-emitting devices in a one-to-one correspondence, wherein the second pixel circuits are configured to drive the second light-emitting devices through the second connecting wires, Each of the plurality of light emitting devices comprises a first electrode, and the first electrodes of the plurality of first light emitting devices and the plurality of second light emitting devices are arranged in the same row along a first direction, In the first display area, the plurality of first connecting wires are at least partially located in the second direction on a first side of a row where the first electrodes of the plurality of first light-emitting devices and the plurality of second light-emitting devices are located, and the plurality of second connecting wires are at least partially located in the second direction on a second side of a row where the first electrodes of the plurality of first light-emitting devices and the plurality of second light-emitting devices are located, The second direction intersects the first direction, and the first side and the second side of the row where the first electrodes of the plurality of first light-emitting devices and the plurality of second light-emitting devices are located are opposite in the second direction. The multiple first pixel circuits and the multiple second pixel circuits are located in the same row, the multiple first connecting wires and the multiple second connecting wires do not cross each other, one end of each of at least one of the first connecting wires is connected to the first light-emitting device, and extends from the first side along the first direction to the second display area, and extends from the first side of the row where the multiple first pixel circuits are located to the second side of the row where the multiple first pixel circuits are located opposite in the second direction, so as to be connected to the corresponding first pixel circuits.

2. The display substrate according to claim 1, wherein: Each of the plurality of first connecting traces includes a first main body portion and at least one first bending portion, at least a portion of the at least one first bending portion extends toward a first side of the first pixel circuit along a third direction, and the third direction intersects the first direction and the second direction. At least one first bending portion of the plurality of first connecting wires includes a first sub-bending portion, the first sub-bending portion is located at a first side of the first pixel circuit and extends along the third direction, the first sub-bending portion is connected to the first pixel circuit and the first main body, one of the first pixel circuits connected to the first sub-bending portion is adjacent to the second pixel circuit, At least one first bending portion of the multiple first connecting traces includes a second sub-bending portion, a third sub-bending portion, a first sub-connecting portion and a second sub-connecting portion, wherein the first sub-connecting portion and the second sub-bending portion are located on the second side of the first pixel circuit, the second sub-bending portion extends along the third direction, the first sub-connecting portion extends along the first direction and is connected to the first pixel circuit and the second sub-bending portion, the second sub-connecting portion extends along the second direction and is located between the adjacent first pixel circuit and the second sub-pixel circuit, the second sub-connecting portion is connected to the second sub-bending portion and the third sub-bending portion, the third sub-bending portion is located on the first side of the first pixel circuit, the third sub-bending portion extends along the third direction and is connected to the first main portion of the first connecting trace, and the second side of the first pixel circuit is opposite to the first side in the second direction.

3. The display substrate according to claim 1, wherein: In the first direction, the plurality of first light emitting devices are located on a side of the plurality of second light emitting devices close to the second display area.

4. The display substrate according to claim 1, wherein: Each of the plurality of first connecting lines comprises a first main body portion and at least one first bending portion, The first main body extends along the first direction and is located on a first side of a row where the first electrodes of the plurality of first light emitting devices and the plurality of second light emitting devices are located, and the first main body is connected to the first electrodes of the plurality of first light emitting devices in a one-to-one correspondence. The at least one first bending portion is connected to the first pixel circuit and the first main body, and the at least one first bending portion extends from the first pixel circuit to the first side of the first pixel circuit so that the first main body is away from the first electrodes of the plurality of first light-emitting devices in the first display area.

5. The display substrate according to claim 4, wherein: At least a portion of the at least one first bent portion extends along a third direction toward a first side of the first pixel circuit, The third direction intersects with the first direction and the second direction.

6. The display substrate according to claim 5, wherein: At least one first bending portion of at least one of the plurality of first connecting lines comprises a first sub-bending portion, The first sub-bending portion is located at a first side of the first pixel circuit and extends along the third direction, and the first sub-bending portion is connected to the first pixel circuit and the first main body. One of the first pixel circuits connected to the first sub-bending portion is adjacent to the second pixel circuit.

7. The display substrate according to claim 5, wherein: At least one first bending portion of at least one of the plurality of first connecting wires extends from the second side of the first pixel circuit to the first side of the first pixel circuit, and includes a second sub-bending portion, a third sub-bending portion, a first sub-connecting portion, and a second sub-connecting portion, wherein: The first sub-connecting portion and the second sub-bending portion are located on the second side of the first pixel circuit, the second sub-bending portion extends along the third direction, and the first sub-connecting portion extends along the first direction and is connected to the first pixel circuit and the second sub-bending portion. The second sub-connection portion extends along the second direction and is located between two adjacent first pixel circuits, and the second sub-connection portion is connected to the second sub-bending portion and the third sub-bending portion. The third sub-bend portion is located at a first side of the first pixel circuit, the third sub-bend portion extends along a third direction and is connected to the first main body portion of the first connecting wire, The second side of the first pixel circuit is opposite to the first side in the second direction.

8. The display substrate according to claim 6, wherein: At least one first bending portion of at least one of the plurality of first connecting lines comprises a second sub-bending portion, a third sub-bending portion, a first sub-connecting portion, and a second sub-connecting portion, wherein The first sub-connecting portion and the second sub-bending portion are located on the second side of the first pixel circuit, the second sub-bending portion extends along the third direction, and the first sub-connecting portion extends along the first direction and is connected to the first pixel circuit and the second sub-bending portion. The second sub-connection portion extends along the second direction and is located between the adjacent first pixel circuit and the second sub-pixel circuit, and the second sub-connection portion is connected to the second sub-bending portion and the third sub-bending portion. The third sub-bend portion is located at the first side of the first pixel circuit, the third sub-bend portion extends along the third direction and is connected to the first main body portion of the first connecting wire, The second side of the first pixel circuit is opposite to the first side in the second direction.

9. The display substrate according to claim 4, wherein: Each of the plurality of second connecting traces comprises a second main body portion, The second main body extends along the first direction and is located at a second side of a row where the first electrodes of the plurality of first light emitting devices and the plurality of second light emitting devices are located, and the second main body is connected to the first electrodes of the second light emitting devices and the second pixel circuit. In the first display area, an orthographic projection of a main portion of the second connecting wire on the base substrate overlaps with an orthographic projection of a first electrode of at least one of the plurality of second light-emitting devices and the plurality of first light-emitting devices on the base substrate.

10. The display substrate according to claim 9, wherein: The first main bodies of the plurality of first connecting wires and the second main bodies of the plurality of second connecting wires are arranged in parallel in the first direction.

11. The display substrate according to any one of claims 1 to 10, wherein: The plurality of first connection lines and the plurality of second connection lines are transparent conductive traces.

12. The display substrate according to claim 11, further comprising a first insulating layer, a second insulating layer, a third insulating layer, a first transparent wiring layer and a second transparent wiring layer, wherein The first insulating layer is located on a side of the plurality of first pixel circuits and the plurality of second pixel circuits away from the substrate, the second insulating layer is located on a side of the first insulating layer away from the substrate, the third insulating layer is located on a side of the second insulating layer away from the substrate, the first transparent wiring layer is located between the first insulating layer and the second insulating layer, the second transparent wiring layer is located on a side of the second insulating layer away from the substrate, and the first electrodes of the plurality of first light-emitting devices are located on a side of the third insulating layer away from the substrate. The first transparent routing layer includes one of two adjacent first connecting routings and one of two adjacent second connecting routings, and the second transparent routing layer includes the other of two adjacent first connecting routings and the other of two adjacent second connecting routings.

13. The display substrate according to claim 12, further comprising a plurality of pixel circuit connection holes, wherein the plurality of pixel circuit connection holes are located in the second display area and include a plurality of first pixel circuit connection holes and a plurality of second pixel circuit connection holes, wherein: The first pixel circuit connection hole penetrates the first insulating layer, and the second pixel circuit connection hole penetrates the first insulating layer and the second insulating layer. The first connecting wire and the second connecting wire located in the first transparent wiring layer are respectively connected to the first pixel circuit and the second pixel circuit through the first pixel circuit connection hole. The first connecting wiring and the second connecting wiring located in the second transparent wiring layer are respectively connected to the first pixel circuit and the second pixel circuit through the second pixel circuit connecting hole.

14. The display substrate according to claim 12, further comprising a plurality of electrode connection holes, the plurality of electrode connection holes being located in the first display area and being located on a first side of a row where the first electrodes of the plurality of first light emitting devices and the plurality of second light emitting devices are located, and comprising a plurality of first electrode connection holes and a plurality of second electrode connection holes, wherein: The first electrode connection hole penetrates the second insulating layer and the third insulating layer, and the second electrode connection hole penetrates the third insulating layer. The first connecting wire and the second connecting wire located in the first transparent wiring layer are respectively connected to the first electrodes of the first light-emitting device and the second light-emitting device through the first electrode connecting holes. The first connecting wire and the second connecting wire located in the second transparent wiring layer are respectively connected to the first electrodes of the first light-emitting device and the second light-emitting device through the second electrode connecting holes.

15. The display substrate according to claim 14, further comprising at least one first dummy wiring located in the first display area, The at least one first virtual wiring is located between the first electrodes of the plurality of first light emitting devices and the plurality of second light emitting devices in adjacent rows and extends along the second direction, The at least one first virtual wire is connected to one end of the second connecting wire connected to the electrode connecting hole, and extends from the electrode connecting hole in a direction away from the first electrode of the second light-emitting device. The orthographic projection of the at least one first virtual routing line on the substrate does not overlap with the first connecting routing line and the second connecting routing line.

16. The display substrate according to claim 12, further comprising a pixel defining layer, the pixel defining layer being located on a side of the first electrodes of the plurality of light-emitting devices away from the base substrate, and comprising a plurality of first pixel openings, the plurality of first pixel openings corresponding to the plurality of light-emitting devices one by one to form light-emitting areas of the plurality of light-emitting devices, Each of the plurality of light-emitting devices further comprises a first light-emitting layer and a second electrode, wherein the second electrode is located on a side of the pixel defining layer away from the base substrate, and the first light-emitting layer is located in the first pixel opening and between the first electrode and the second electrode. At least part of the first electrodes of the plurality of light emitting devices include a first electrode main body portion and a first electrode connecting portion, The first electrode main body is located in a light emitting area of ​​the light emitting device, and the first electrode connecting part connects the electrode connecting hole and the first electrode main body.

17. The display substrate according to claim 1, wherein: The second display area further includes a second sub-pixel array, the second sub-pixel array includes a plurality of first pixel units, the plurality of first pixel units and the plurality of first pixel circuit units are alternately arranged, Each of the plurality of first pixel units comprises a third light emitting device and a third pixel circuit, wherein the third pixel circuit is electrically connected to the third light emitting device to drive the third light emitting device. The first sub-pixel array and the second sub-pixel array include a plurality of first sub-pixels, a plurality of second sub-pixels, and a plurality of third sub-pixels. Each pixel of the first sub-pixel array and the second sub-pixel array includes at least one of the first sub-pixel, at least one of the second sub-pixel, and at least one of the third sub-pixel.

18. The display substrate according to claim 1, wherein: The display area further includes a third display area, the third display area at least partially surrounds the second display area, the third display area includes a third sub-pixel array, and the third sub-pixel array includes a plurality of second pixel units. Each of the plurality of second pixel units comprises a fourth light emitting device and a fourth pixel circuit, wherein the fourth pixel circuit is electrically connected to the fourth light emitting device to drive the fourth light emitting device. The third sub-pixel array includes a plurality of first sub-pixels, a plurality of second sub-pixels, and a plurality of third sub-pixels. One of the two adjacent pixels of the third sub-pixel array includes at least one of the first sub-pixel and at least one of the second sub-pixel, and the other of the two adjacent pixels includes at least one of the first sub-pixel and at least one of the third sub-pixel, and each second sub-pixel and each third sub-pixel are shared by at least two adjacent pixels.

19. The display substrate according to claim 17 or 18, wherein: The first sub-pixel is a green sub-pixel, The second sub-pixel is a red sub-pixel, The third sub-pixel is a blue sub-pixel.

20. A display device, comprising the display substrate according to any one of claims 1 to 19.

21. The display device according to claim 20, further comprising a sensor, wherein: The sensor is disposed on the second side of the display substrate, and the sensor is configured to receive light from the first side of the display substrate.

22. The display device according to claim 21, wherein: The orthographic projection of the sensor on the base substrate at least partially overlaps with the first display area.

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