Apparatus, system and method for content addressable memory unit

Abstract

Embodiments of the present disclosure relate to apparatus and methods for content-addressable memory (CAM) cells. Each CAM cell may include a latch portion that stores a bit of information. Each CAM cell may also include a comparator portion that compares an external bit with the stored bit. A group of CAM cells may be organized into a CAM register, wherein each CAM cell is commonly coupled to a signal line. If the external bit does not match the stored bit, any of the CAM cells may change the voltage on the signal line.

Description

[0001] Cross-reference to related applications

[0002] This application claims the benefit of U.S. Patent Application No. 16 / 411,573, filed May 14, 2019, which is incorporated herein by reference in its entirety for any purpose. Background Art

[0003] The present disclosure relates generally to semiconductor devices, and more specifically, to semiconductor components for storing bits. Semiconductor logic devices can typically operate with binary logic, where signals and information are stored as one or more bits, each of which can be at a high logic level or a low logic level. There can be several applications in which it is useful to store information and compare the stored information with external information. For example, a memory device can use a bit string as a row address to refer to a particular group of memory cells. One or more row addresses can be stored and compared to an incoming row address to determine whether there is a match between any of the stored row addresses and the incoming row address. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Figure 1 is a block diagram of a content addressable memory (CAM) cell according to the present disclosure.

[0005] Figure 2 is a schematic diagram of a CAM cell according to an embodiment of the present disclosure.

[0006] Figure 3 is a block diagram of a CAM cell register according to an embodiment of the present disclosure.

[0007] Figure 4 is a block diagram illustrating a register stack according to an embodiment of the present disclosure.

[0008] Figure 5 is a block diagram of a semiconductor device according to at least one embodiment of the present disclosure.

[0009] Figure 6 is a block diagram of a memory array according to an embodiment of the present disclosure.

[0010] Figure 7 is a block diagram of a refresh control circuit according to an embodiment of the present disclosure.

[0011] Figure 8 is a block diagram of an address sampler according to an embodiment of the present disclosure. Summary of the Invention

[0012] In at least one aspect, the present disclosure relates to an apparatus comprising a latch circuit and a comparator circuit. The latch circuit stores a first signal and a second signal, wherein the second signal is complementary to the first signal. The comparator circuit receives a third signal and a fourth signal, wherein the third signal is complementary to the fourth signal. The comparator circuit comprises a first portion that activates when the fourth signal is at a first logic level and, when active, couples a signal line to a voltage when the first signal is at the first logic level. The comparator circuit comprises a second portion that activates when the third signal is at the first logic level and, when active, couples the signal line to the voltage when the second signal is at the first logic level.

[0013] The latch circuit may receive a fifth signal and a sixth signal complementary to the fifth signal, and replace the first signal with the fifth signal and replace the second signal with the sixth signal when a write signal is valid. The latch circuit may include a first write transistor coupled between the fifth signal and the first signal and a second write transistor coupled between the sixth signal and the second signal, wherein the first write transistor and the second write transistor may have gates commonly coupled to the write signal.

[0014] The logic state of the first signal may represent the logic state of a bit stored by the latch circuit.The latch circuit may include a first plurality of transistors all having a first size, and the comparator circuit may include a second plurality of transistors all having a second size different from the first size.

[0015] The latch circuit may include: a first transistor that can couple a first voltage to the first signal when the second signal is at a second logic level; a second transistor that can couple the first voltage to the second signal when the first signal is at the second logic level; a third transistor that can couple a second voltage to the first signal when the second signal is at the first logic level; and a fourth transistor that can couple the second voltage to the second signal when the first signal is at the first logic level, wherein the first voltage is associated with the first logic level and the second voltage is associated with the second logic level. The first portion of the comparator circuit may include a fifth transistor and a sixth transistor coupled in series between the signal line and the first voltage, wherein the fifth transistor can be activated by the first signal at the first logic level and the sixth transistor can be activated by the fourth signal at the first logic level. The second portion of the comparator circuit may include a seventh transistor and an eighth transistor coupled in series between the signal line and the first voltage, wherein the seventh transistor can be activated by the second signal at the first logic level and the eighth transistor can be activated by the third signal at the first logic level.

[0016] In at least one aspect, the present disclosure relates to an apparatus comprising a plurality of content-addressable memory (CAM) registers and a plurality of signal lines. Each of the CAM registers may include a plurality of CAM cells that store respective bits of stored information and further compare the respective bits of stored information with respective bits of external information. Each of the plurality of signal lines is coupled to one of the CAM registers, wherein if the respective bits of stored information do not match the respective bits of external information, each of the plurality of CAM cells of a given one of the plurality of CAM registers changes the voltage of the associated one of the plurality of signal lines to a first voltage.

[0017] The apparatus may also include a driver circuit that can set the voltages of the plurality of signal lines to a second voltage different from the first voltage before any of the CAM cells compares the corresponding bit of stored information with the corresponding bit of external information. A plurality of external bits can be commonly provided to each of the plurality of CAM registers. The same number of the plurality of external bits and the plurality of CAM cells can be present in each of the plurality of CAM registers.

[0018] Each of the plurality of CAM registers can store a memory address associated with a memory cell group of a memory device, and each of the plurality of CAM cells of a given CAM register can store a bit of the memory address. Each of the plurality of CAM cells can store a first signal representing the logic level of the stored bit and a second signal complementary to the first signal, can receive a third signal representing the logic level of the bit of external information and a fourth signal complementary to the third signal, and can compare the first signal with the fourth signal and the second signal with the third signal. If the first signal and the fourth signal match, or if the second signal and the third signal match, each of the plurality of CAM cells can change the voltage of the associated one of the plurality of signal lines to the first voltage.

[0019] In at least one aspect, the present disclosure relates to an apparatus comprising: a fuse array that provides a row address comprising a plurality of bits; a fuse latch; and a row control. The fuse latch is associated with a redundant memory cell group. The fuse latch comprises a plurality of content addressable memory (CAM) cells, each of the CAM cells comprising a latch portion that stores a corresponding one of the plurality of bits of the row address and a comparator portion. The row control provides an access address comprising a plurality of bits. The comparator portion compares a corresponding bit of the access address with the corresponding stored bit, and if the bit of the access address does not match the stored bit, each of the CAM cells changes the state of the matching bit from a high level to a low level.

[0020] The apparatus may also include fuse logic circuitry that can provide the row address to a write signal, wherein each of the plurality of CAM cells in the fuse latch is configured to store the corresponding one of the plurality of bits of the row address in response to the row address and the write signal. If the match bit remains high after comparing the access address with the row address, the row control can perform an access operation on the redundant memory cell group.

[0021] The apparatus may also include an inverter circuit capable of inverting a plurality of first signals, each first signal representing one of the plurality of bits of the row address to a complementary plurality of second signals, wherein each of the CAM cells stores a corresponding one of the plurality of first signals and a corresponding one of the plurality of second signals. The apparatus may also include an inverter circuit capable of inverting a plurality of third signals, each third signal representing one of the bits of the access address to a complementary plurality of fourth signals, wherein each of the CAM cells of the fuse latch compares the corresponding first and fourth signals and the corresponding second signal to the third signal. If the corresponding first signal matches the fourth signal or if the corresponding second signal matches the third signal, each of the CAM cells may change the state of the match bit. DETAILED DESCRIPTION

[0022] The following description of certain embodiments is merely exemplary in nature and is in no way intended to limit the scope of the present disclosure or its application or use. In the following detailed description of embodiments of the present system and method, reference is made to the accompanying drawings that form a part thereof and that show, by way of illustration, specific embodiments in which the described system and method may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the presently disclosed system and method, and it should be understood that other embodiments may be utilized and structural and logical changes may be made without departing from the spirit and scope of the present disclosure. In addition, for clarity purposes, when certain features will be apparent to those skilled in the art, their detailed description will not be discussed in order to avoid confusing the description of the embodiments of the present disclosure. Therefore, the following detailed description should not be considered restrictive, and the scope of the present disclosure is defined solely by the appended claims.

[0023] Information in a semiconductor device can typically be represented by one or more binary bits, each of which is at a high logic level (e.g., 1) or a low logic level (e.g., 0). Information can be stored in circuits included in the semiconductor device, such as latch circuits. A latch circuit can store a specific information bit that can later be retrieved and / or overwritten by a new information bit to be stored. Groups of latch circuits can be organized together to form registers that store information (e.g., data) comprising several bits. Several registers can be organized into stacks to store multiple pieces of information (e.g., each register may have N latch circuits to store information comprising N bits, and there may be M registers in the stack). The number of registers in a stack is typically referred to as the stack depth. There may be many applications where being able to search for a register containing specific information in a given register stack is useful, however, such circuits may be relatively space- and power-consuming.

[0024] The present disclosure relates to apparatus, systems, and methods for content-addressable memory cells. In some embodiments of the present disclosure, a content-addressable memory (CAM) cell can store bits of information and allow memory cells (e.g., within a group of CAM cells) to be addressed based on the content stored in the CAM cell. The CAM cells of the present disclosure include a layout that can allow each CAM cell to occupy a relatively small space on a semiconductor device (e.g., by using fewer and / or smaller components) and can also allow for less power to be drawn when addressing the CAM cell.

[0025] According to some embodiments of the present disclosure, a CAM cell includes a latch portion and a comparator portion. In such embodiments, the latch portion can store an information bit, while the comparator portion can compare the stored bit with a supplied external bit. If the comparator portion determines that there is no match, the state of the match signal can change from a high logic level to a low logic level. If there is a match, the comparator portion can do nothing and the latch signal can remain at a high logic level. When multiple CAM cells are organized into a register, they can be commonly coupled to a signal line and can share a latch signal.

[0026] Figure 1 1 is a block diagram of a content addressable memory (CAM) cell according to an embodiment of the present disclosure. The CAM cell 100 includes a latch portion 102 and a comparator portion 104.

[0027] Latch portion 102 stores a bit and provides signals Q and QF that indicate the logic level of the stored bit. Signals Q and QF can be binary signals at a high logic level (e.g., a first voltage) or a low logic level (e.g., a second voltage). The Q and QF signals are complementary to each other and have opposite logic values. For example, if signal Q is logic high, signal QF can be logic low, and vice versa. Signal Q can represent the logic level of the stored bit, while signal QF can be complementary to the logic level of the stored bit. Latch portion 102 can continue to provide signals Q and QF as long as latch portion 102 receives power. In some embodiments, latch portion 102 can receive power whenever a device containing CAM cell 100 is powered on.

[0028] CAM cell 100 may receive an input signal D and a complementary input signal DF. Input signals D and DF are complementary to each other and have opposite logic values. Input bit D may represent the logic value of an input bit provided to overwrite a stored bit currently in the CAM cell. When a write signal, Write, is at a high logic level, the values of signals D and DF may be written to CAM cell 100. This may cause the values of input signals D and DF to overwrite the current values of stored signals Q and QF, respectively. When signal Write is at a low logic level, the values of stored signals Q and QF may be maintained even when input signals D and DF are provided.

[0029] The CAM cell 100 may also include a comparator portion 104. The comparator portion 104 may be used when external signals X_Compare and XF_Compare are provided. During a comparison operation, the external signals X_Compare and XF_Compare are complementary to each other. Signal X_Compare may represent the logic level of the external bit, while signal XF_Compare may represent the complement of the logic level of the external bit. When a comparison operation is not performed (e.g., when signal X_Compare does not represent the external bit), both X_Compare and XF_Compare may be at a low logic level. The comparator portion 104 determines whether the external signal X_Compare matches the stored signal Q and whether the complementary external signal XF_Compare matches the complementary stored signal QF. If the external signal X_Compare does not match the stored signal Q (and therefore the complementary external signal XF_Compare does not match the complementary stored signal QF), the comparator portion 104 may provide a BitMatch signal having a low logic level. Conversely, if the external signal X_Compare does match the stored signal Q (and thus the inverted external signal XF_Compare matches the inverted stored signal QF), the comparator portion 104 may provide a BitMatch signal having a high logic level.

[0030] In some embodiments of the present disclosure, the BitMatch signal may have a high logic level before performing a comparison operation (e.g., before providing X_Compare and XF_Compare). Therefore, if there is no match between the external signal and the stored signal, the CAM cell 100 may change the state of the BitMatch signal to a low logic level. If the signals Q and X_Compare (and QF and XF_Compare) match, the BitMatch signal may remain at a high logic level.

[0031] In some embodiments, comparator portion 104 may include a first portion 101 and a second portion 103. Both first portion 101 and second portion 103 may be coupled to signal BitMatch, and either first portion 101 or second portion 103 may be capable of changing the logic level of signal BitMatch. First portion 101 may be activated when signal XF_Compare is at a high logic level and may be inactive otherwise. Second portion 103 may be activated when signal X_Compare is at a high logic level. Because signals X_Compare and XF_Compare are complementary to each other, only one of first portion 101 or second portion 103 may be active at a given time. When active, if signal Q is at a high logic level (e.g., if signals Q and XF_Compare match), first portion 101 may change signal BitMatch from a high logic level to a low logic level. Similarly, when active, if signal QF is at a high logic level (e.g., if signals QF and X_Compare match), second portion 102 may change signal BitMatch from a high logic level to a low logic level.

[0032] Figure 2 2 is a schematic diagram of a CAM unit according to an embodiment of the present disclosure. In some embodiments, the CAM unit 200 may implement Figure 1 CAM cell 100. CAM cell 200 includes a latch portion 202 and a comparator portion 204. CAM cell 200 may typically use voltages to represent the value of each bit. CAM cell 200 may include a conductive element (e.g., a node, a conductive line) that carries a voltage representing the logic value of that bit. For example, a high logic level may be represented by a first voltage (e.g., a system voltage such as VPERI), while a low logic level may be represented by a second voltage (e.g., a ground voltage such as VSS).

[0033] Latch portion 202 includes a first transistor 206 having a source coupled to a node providing a voltage VPERI, which may represent a high logic level. First transistor 206 has a drain coupled to node 217 having a voltage representing the value of signal Q, and a gate coupled to node 219 having a voltage representing the value of complementary signal QF. Signal Q represents the logic level of a bit stored in latch portion 202. First transistor 206 may be a p-type transistor. Latch portion 202 also includes a second transistor 207 having a source coupled to the node providing VPERI, a gate coupled to node 217, and a drain coupled to node 219. Second transistor 207 may be a p-type transistor.

[0034] Latch portion 202 includes a third transistor 208 having a drain coupled to node 217, a gate coupled to node 219, and a source coupled to a node providing ground voltage VSS, which may represent a low logic level. Third transistor 208 may be an n-type transistor. Latch portion 202 includes a fourth transistor 209 having a drain coupled to node 219, a gate coupled to node 217, and a source coupled to a node providing ground voltage VSS. Fourth transistor 209 may be an n-type transistor. Transistors 206 and 208 may form an inverter circuit, and transistors 207 and 209 may form another inverter circuit, with the two inverter circuits cross-coupled with each other.

[0035] In operation, the first, second, third, and fourth transistors 206-209 can operate to store the values of stored signals Q and QF. Transistors 206-209 can work together to couple node 217, which carries Q, and node 219, which carries QF, to nodes that provide a system voltage (e.g., VPERI or VSS) associated with the values of signals Q and QF. For example, if stored signal Q is at a high logic level, inverted signal QF is at a low logic level. First transistor 206 can be active, and VPERI can be coupled to node 217. Second transistor 207 and third transistor 208 can be inactive. Fourth transistor 209 can be active and can couple VSS to node 219. This can maintain node 217 at a voltage of VPERI, which represents a high logic level, and maintain node 219 at a voltage of VSS, which represents a low logic level. In another example, if stored signal Q is at a low logic level, inverted signal QF can be at a high logic level. The first transistor 206 and the fourth transistor 209 can both be inactive. The second transistor 207 can be active and can couple VPERI to the node 219. The third transistor 208 can also be active and can couple VSS to the node 217. In this manner, the stored signals Q and QF can be coupled to respective system voltages corresponding to their current logic levels, which can maintain the current logic value of the stored bit.

[0036] Latch portion 202 also includes a fifth transistor 210 and a sixth transistor 211. Transistors 210 and 211 can function as switches that can couple a signal line carrying input data D and a signal line carrying inverted input data DF to nodes 217 and 219 carrying Q and QF, respectively, when a write signal, Write, is active. Fifth transistor 210 has a gate coupled to a line carrying the Write signal, a drain coupled to signal D, and a source coupled to node 219. Sixth transistor 211 has a gate coupled to the Write signal, a drain coupled to signal DF, and a source coupled to node 219. Thus, when the Write signal is high (e.g., at a voltage such as VPERI), transistors 210 and 211 can be active, and the voltages of signals D and DF can be coupled to nodes 217 and 219 carrying Q and QF, respectively.

[0037] In some embodiments, the first through sixth transistors 206-211 may all generally have the same size as one another. For example, transistors 206-211 may have a gate width of approximately 300 nm. In other examples, other sizes of transistors 206-211 may be used. CAM cell 200 also includes a comparator portion 204. Comparator portion 204 may compare signals Q and QF with signals X_Compare and XF_Compare. Signal X_Compare may represent the logic level of an external bit provided to comparator portion 204. If there is no match between signals Q and X_Compare (and therefore between QF and XF_Compare), comparator portion 204 may change the state of the BitMatch signal from a first logic level (e.g., a high logic level) to a second logic level (e.g., a low logic level). For example, if the stored bit and the external bit do not match, comparator portion 204 may couple ground voltage VSS to the signal line carrying signal BitMatch. In some embodiments, if there is a match between the stored bit and the external bit, the comparator portion 204 may do nothing. In some embodiments, the signal BitMatch may be precharged to a voltage associated with a high logic level (e.g., VPERI) prior to the comparison operation. During the precharge operation, both X_Compare and XF_Compare may remain at a low logic level.

[0038] The comparator portion includes a seventh transistor 212, an eighth transistor 213, a ninth transistor 214, and a tenth transistor 215. The seventh transistor 212 and the ninth transistor 214 may implement Figure 1 The eighth transistor 213 and the tenth transistor 215 can implement Figure 1The seventh transistor 212 includes a drain coupled to the signal BitMatch, a gate coupled to the node 217 (e.g., the signal Q), and a source coupled to the drain of the ninth transistor 214. The ninth transistor 214 also has a gate coupled to the signal XF_Compare and a source coupled to a signal line providing a ground voltage VSS.

[0039] The eighth transistor 213 has a drain coupled to the signal BitMatch, a gate coupled to the node 219 (eg, the signal QF), and a source coupled to the drain of the tenth transistor 215. The tenth transistor has a gate coupled to the signal X_Compare and a source coupled to the ground voltage VSS.

[0040] Since signal Q is complementary to signal QF, comparator portion 202 may operate by comparing external signal X_Compare to signal QF to see if they match and comparing inverted external signal XF_Compare to stored signal Q to see if they match. If they match, it may indicate that signal X_Compare does not match signal Q and signal XF_Compare does not match signal QF, and therefore the external bit does not match the associated stored bit.

[0041] Comparator section 204 can use relatively few components because it changes signal BitMatch from a known state (e.g., a precharged high logic level) to a low logic level. Therefore, it may not be necessary to include additional components (e.g., additional transistors) to change the logic level of signal BitMatch from low to high, or from an unknown level to low or high. Comparator section 204 can take advantage of this to provide dynamic logic. For example, comparator section 204 has two sections (e.g., transistors 212 / 214 and transistors 213 / 215), either of which can couple signal BitLine to voltage VSS if there is no match between the stored bit and the external bit. Since only one of the sections is active at a time, the active section only needs to check the state of signal Q or QF. Either of the two sections is equally capable of changing signal BitMatch to a low logic level.

[0042] In example operation, if the stored signal Q is at a logic high level (and therefore signal QF is low) and the external signal X_Compare is also high (and signal XF_Compare is low), the external signal may match the stored signal, and transistors 212 and 215 may be active, while transistors 214 and 213 are inactive. This may prevent ground voltage VSS from coupling to signal BitMatch. If signal X_Compare is low (e.g., if there is no match), the external signal may not match the stored signal, and transistors 212 and 214 may be active, while transistors 213 and 215 are inactive. Transistors 212 and 214 being active simultaneously may couple ground voltage VSS to signal BitMatch.

[0043] In another example operation, if the stored signal Q is low (and therefore signal QF is high), transistor 212 may be inactive, while transistor 213 is active. If the external signal X_Compare is low (and XF_Compare is high), the external signal may match the stored bit, and transistor 214 is active, while transistor 215 is inactive. If the signal X_Compare is high (and signal XF_Compare is low), the external signal may not match the stored signal and transistor 214 may be inactive, while transistor 215 is active. Thus, signal BitMatch may be coupled to ground voltage VSS through active transistors 213 and 215.

[0044] In some embodiments, the transistors 212-215 of the comparator portion 204 may all be generally the same size as one another. In some embodiments, the transistors 212-215 of the comparator portion 204 may have different sizes than the transistors 206-211 of the latch portion 202. For example, the transistors 212-215 may have a gate width of approximately 400 nm and a gate length of approximately 45 nm. In other examples, other sizes of the transistors 212-215 may be used.

[0045] Figure 3 3 is a block diagram of a CAM cell register according to an embodiment of the present disclosure. The CAM cell register 300 includes a plurality of CAM cells 318(0)-318(n), each of which may be Figure 1 CAM unit 100 and / or Figure 2200. The CAM cell register 300 can store a plurality of information bits (e.g., stored bits Q(0) to Q(n)). The CAM cells 318 of the CAM cell register 300 can be commonly coupled to a signal line providing a signal RegisterMatch having a voltage representing a match bit having a logic state based on a comparison between the information stored across the CAM cells 318 of the CAM cell register 300 and an external signal X_Compare.

[0046] The CAM cell register 300 includes a number of individual CAM cells 318, each of which can store a bit of information and provide signals Q and QF, where signal QF has a complementary logic level to signal Q. Signal Q can have a logic level that matches the logic level of the stored bit. The CAM cell register 300 can include a number of CAM cells 318 to hold multiple bits of information. For example, the CAM cell register 300 can hold a row address that can be n bits long, and thus there can be n different CAM cells 318. Input terminals (e.g., which can receive a Figure 1-2 Input signals D and DF) and write signals not shown here (for example, Figure 1-2 The CAM register 300 may be loaded with a signal Write to load the bits into the CAM register 300. A first information bit Q(0) may be loaded into the first CAM cell 318(0), a second information bit Q(2) may be loaded into the second CAM cell 318(1), and so on. In some embodiments, the input data D(0)-(n) may be provided along with complementary input data DF(0)-(n). In some embodiments, only the input data D(0)-(n) may be provided, and one or more inverter circuits may be used to generate the complementary data DF(0)-(n) and provide it to the respective CAM cells 318.

[0047] During a compare operation, data X_Compare may be provided to the CAM cell register 300. The data X_Compare may be the same type of information as that stored in the CAM cell register 300 (e.g., a row address). The data X_Compare may be a multi-bit signal and may have n bits to match the number of CAM cells 318 of the CAM cell register 300. When the data X_Compare is provided, it may be separated into different individual bits and provided to the associated CAM cells 318. Thus, the first external bit X_Compare(0) may be provided to the CAM cell 318(0) containing the stored bit Q(0), the second external bit X_Compare(1) may be provided to the CAM cell 318(1) containing the stored bit Q(1), and so on. In some embodiments, the external data X_Compare may be provided along with complementary data XF_Compare. In some embodiments, only the data X_Compare may be provided, and one or more inverter circuits may be used to generate the complementary data XF_Compare and provide it to the CAM cells 318 of the CAM cell register 318.

[0048] Each of the CAM cells 318 may be commonly coupled to a signal line providing a signal RegisterMatch. The signal RegisterMatch may implement Figure 1-2 . The signal RegisterMatch can be coupled to a RegisterMatch driver 316. The RegisterMatch driver 316 can precharge the voltage of the signal RegisterMatch to a first voltage representing a high logic level. In some embodiments, the RegisterMatch driver 316 can precharge the voltage of the RegisterMatch to the first voltage each time the external signal X_Compare is provided. If the stored signal Q(i) in the memory cell 318 does not match the associated external signal X_Compare(i), any of the CAM cells 318 can couple the signal RegisterMatch to a second voltage representing a low logic level (e.g., a ground voltage). As previously described, the stored signal Q(i) can be compared with the external signal X_Compare(i) and the complementary stored signal QF(i) can be compared with the complementary external signal XF_Compare(i). In some embodiments, if the stored signal Q(i) matches the complementary external signal XF_Compare(i) or the complementary stored signal QF(i) matches the external signal X_Compare(i), then the signal RegisterMatch may be coupled to the second voltage.

[0049] Thus, the signal RegisterMatch will only remain at the first voltage (e.g., a high logic level) if each bit of the external signal X_Compare matches each of the associated stored signals Q. In other words, RegisterMatch may provide a match signal (e.g., a high logic level) as if each of the CAM cells 318 were matched. Figure 1-2 The match signal is provided as input to an AND gate which in turn provides a signal RegisterMatch.

[0050] Figure 4 4 is a block diagram showing a register stack according to an embodiment of the present disclosure. The register stack 400 includes a plurality of CAM unit registers 420, each of which may be Figure 3 There may be m different CAM cell registers 420 in the stack (eg, the stack may be m deep). Each of the CAM cell registers 420 may be coupled to a respective signal line RegisterMatch (eg, RegisterMatch(0-m)).

[0051] During a search operation, the external information X_Compare may be provided to each of the CAM cell registers 420. The external information X_Compare may be provided collectively to the CAM cell registers 420 and may serve as Figure 3 The information X_Compare may be a multi-bit signal, and each of the CAM cell registers 420 may have the same number of individual CAM cells as the number of bits in X_Compare (e.g., Figure 1 100). Each of the CAM cell registers 420, register 0 to register m, is coupled to a respective signal line RegisterMatch(0) to RegisterMatch(m). Each of the RegisterMatch signal lines can provide a signal indicating whether the provided information X_Compare fully matches the data stored in the associated CAM cell register 420. The RegisterMatch signal line can carry a voltage that can represent the logic level of a match bit, and if the information X_Compare matches the contents of the CAM cell register 420 associated with the respective RegisterMatch signal line, the match bit can be at a logic high (e.g., a first voltage). If there are one or more bits of X_Compare that do not match the data stored in the CAM cell register 420, the respective signal line RegisterMatch can be at a second voltage, which indicates that the match bit is at a low logic level.

[0052] After the compare operation, the state of RegisterMatch(0-m) can be used to determine which of the CAM cell registers 420 contain an exact match for X_Compare. For example, if each of the CAM cell registers is associated with a physical location, that location can be accessed provided that the associated signal line RegisterMatch is at a first voltage (e.g., the match bit is at a high logic level).

[0053] An example environment in which the CAM cells, registers, and stacks of the present disclosure may be useful is a semiconductor memory device. A memory device may be used to store one or more bits of information in a memory cell array that contains a plurality of memory cells, each of which includes one or more bits of information. The memory cells may be organized at the intersection of rows (word lines) and columns (bit lines). During various operations, the memory device may access one or more memory cells along a specified word line or bit line by providing a row and / or column address that specifies the word line and bit line. There may be a semiconductor memory device in which the CAM cells, registers, and stacks of the present disclosure (e.g., as Figure 1-4 ) is useful for comparing row and / or column addresses with row and / or column addresses stored in a CAM cell stack.

[0054] One example application is a memory repair operation in a memory device. One or more of the memory cells of the memory device may become defective. The row and / or column addresses associated with the defective memory cell(s) may be reassigned to redundant rows / columns of the memory array. For example, this may be accomplished by changing the state(s) of one or more fuses (and / or antifuses) in a fuse array. The state of the fuse may represent the row / column address to be repaired, which may be broadcast out to the fuse latches associated with the redundant rows / columns. When the memory attempts to access the repaired row / column, if the incoming row / column address matches the row / column address stored in the fuse latch, then the redundant row / column associated with that fuse latch is accessed instead of the defective row / column. The CAM cell registers (e.g., Figure 3 300) can be used as a fuse latch and the match bit can be used to determine whether the incoming row / column address completely matches the row / column address stored in the fuse latch.

[0055] Another example application of the CAM cells, registers, and stacks of the present disclosure is in refresh operations in memory devices. Information in a memory cell may decay over time and may need to be periodically refreshed (e.g., by rewriting the original value of the information to the memory cell). Due to, for example, electromagnetic coupling between particular rows of memory (e.g., aggressor rows), repeated accesses to the rows may cause the decay rate of adjacent rows (e.g., victim rows) to increase. This may generally be referred to as a 'hammering' row or row hammer event. To prevent information from being lost due to row hammering, it may be necessary to identify the aggressor row so that the corresponding victim row can be refreshed (a 'row hammer refresh' or RHR). The row addresses of the accessed rows may be stored and compared to the new row addresses to determine if an RHR operation is required for one or more rows. A CAM cell stack (e.g., Figure 4 400) can be used to store accessed addresses and corresponding match bits can be used to determine whether the incoming row address matches any of the row addresses stored in the CAM cell stack. This can allow accesses to the rows to be counted in order to determine whether they are hammered.

[0056] Figure 5 is a block diagram of a semiconductor device according to at least one embodiment of the present disclosure. The semiconductor device 500 may be a semiconductor memory device, such as a DRAM device integrated on a single semiconductor chip. The semiconductor device 500 may include one or more CAM units (e.g., Figure 1-2 CAM unit 100 and / or 200, Figure 3 CAM cell register 300 and / or Figure 4 CAM cell stack 400).

[0057] Semiconductor device 500 includes a memory array 542. In some embodiments, memory array 542 may include multiple memory banks. Each memory bank includes multiple word lines WL, multiple bit lines BL and / BL, and multiple memory cells MC arranged at the intersections of the multiple word lines WL and the multiple bit lines BL and / BL. The word lines WL are selected by a row control 538, and the bit lines BL and / BL are selected by a column control 540. The bit lines BL and / BL are coupled to corresponding sense amplifiers (SAMPs). Read data from bit lines BL or / BL is amplified by sense amplifier SAMP 547 and transmitted to a read / write amplifier 550 via a complementary local data line (LIOT / B), a transfer gate (TG) 548, and a complementary main data line (MIO). Conversely, write data output from the read / write amplifier 550 is transmitted to a sense amplifier 547 via a complementary main data line MIO, a transfer gate 548, and a complementary local data line LIOT / B, and is written into the memory cell MC coupled to the bit line BL or / BL.

[0058] The semiconductor device 500 may employ a plurality of external terminals including a command and address (C / A) terminal coupled to a command and address bus to receive commands and addresses, a clock terminal for receiving clocks CK and / CK, a data terminal DQ for providing data, and a power supply terminal for receiving power supply potentials VDD, VSS, VDDQ, and VSSQ.

[0059] The clock terminal is supplied with external clocks CK and / CK, which are provided to the clock input circuit 552. The external clocks may be complementary. The clock input circuit 552 generates an internal clock ICLK based on the CK and / CK clocks. The ICLK clock is provided to the command control unit 536 and the internal clock generator 554. The internal clock generator 554 provides various internal clocks LCLK based on the ICLK clock. The LCLK clock can be used to time operations of various internal circuits. The internal data clock LCLK is provided to the input / output circuit 556 to time the operation of the circuits included in the input / output circuit 556, for example, to the data receiver to time the receipt of write data.

[0060] The C / A terminal may be supplied with a memory address. The memory address supplied to the C / A terminal is transmitted to the address decoder 534 via the command / address input circuit 532. The address decoder 534 receives the address and supplies the decoded row address XADD to the row control 538 and the decoded column address YADD to the column control 540. The address decoder 534 may also supply a decoded bank address BADD, which may indicate the bank of the memory array 548 containing the decoded row address XADD and column address YADD. The C / A terminal may be supplied with a command. Examples of commands include timing commands for controlling the timing of various operations, access commands for accessing memory, such as a read command for performing a read operation and a write command for performing a write operation, and other commands and operations. An access command may be associated with one or more row addresses XADD, column addresses YADD, and bank addresses BADD to indicate the memory cell(s) to be accessed.

[0061] Commands may be provided as internal command signals to command control 536 via command / address input circuit 532. Command control 536 includes circuitry for decoding the internal command signals to generate various internal signals and commands for performing operations. For example, command control 536 may provide row command signals for selecting word lines and column command signals for selecting bit lines.

[0062] The device 500 may receive an access command as a row active command ACT. When the row active command ACT is received, the memory address BADD and the row address XADD are supplied with the row active command ACT in a timely manner.

[0063] The device 500 can receive an access command as a read command. When the read command is received, the read command is supplied to the bank address and column address in a timely manner, and read data is read from the memory cell corresponding to the row address and column address in the memory array 542. The read command is received by the command control 536, which provides an internal command so that the read data from the memory array 542 is provided to the read / write amplifier 550. The read data is output to the outside from the data terminal DQ via the input / output circuit 556.

[0064] The device 500 can receive an access command as a write command. Upon receiving the write command, the write command is supplied to the bank address and column address in a timely manner, and the write data supplied to the data terminal DQ is written to the memory cell corresponding to the row address and column address in the memory array 542. The write command is received by the command control 536, which provides an internal command so that the write data is received by the data receiver in the input / output circuit 556. A write clock may also be supplied to the external clock terminal to time the receipt of the write data by the data receiver in the input / output circuit 556. The write data is supplied to the read / write amplifier 550 via the input / output circuit 556, and then supplied to the memory array 542 by the read / write amplifier 550 to be written into the memory cell MC.

[0065] One example application of the CAM cells described in this disclosure is as fuse latches 564 associated with redundant word lines (and / or redundant bit lines) of a memory array 542. While repair operations may generally be described with respect to redundant rows (and row latches), it should be understood that redundant columns (and column latches) may operate in a similar manner.

[0066] Fuse latch 564 can be used as part of a repair operation. During a repair operation, a memory address previously associated with a defective memory row can be reassigned so that it is instead associated with one of the redundant word lines. The repair operation can be performed by 'blowing' one or more fuses (and / or antifuses) in fuse array 560. Fuse array 560 can include a number of fuses, each of which can have a state representing a bit. The state of one or more fuses can be permanently changed (blown) to program in a specific binary data segment. During a repair operation, the address to be repaired can be programmed into fuse array 560 by blowing the fuses.

[0067] Each redundant word line (and / or redundant bit line) can be associated with a fuse latch 564. The states of the fuses in the fuse array 560 can be provided along a fuse bus. The fuse logic circuit 562 can provide a select signal (e.g., a write signal) that causes a repaired address represented by the value of the fuse in the fuse array 560 to be stored in the fuse latch 564. When the memory performs an access operation, the row address XADD can be compared with the address in the fuse latch 564, and if there is a match, the access operation can be performed on the redundant row associated with the fuse latch 564 instead of the original word line referred to by the address. In this way, the repaired address can be redirected to the redundant row.

[0068] Each of the fuse latches 564 may be a CAM cell register, such as Figure 3 CAM cell register 300. If any address has been repaired, the fuse array 560 can provide the row address along the fuse bus, and the fuse logic 562 can provide a select signal (which can act as a Figure 1-2 A signal Write is sent to allow the bits of the repaired address to be written as stored bits Q and QF (e.g., the bits of the repaired address may be input bits D and DF) in the CAM cells of the fuse latch 564. In some embodiments, one or more inverter circuits may be used to generate an inverted input bit DF based on the input bit D provided along the fuse bus.

[0069] When the row address XADD is provided, it can act as (for example, Figure 3-4 The 1000A is a register that reads the external data X_Compare of the row address and if any of the external data bits do not match the corresponding stored bits, the fuse latch may change the value of the match bit. If the match bit remains high, it may indicate that the row address XADD matches the address stored in the fuse latch 564 and an access operation may be performed on the associated redundant word line.

[0070] Another example application of the CAM cell described in this application involves tracking aggressor addresses in order to refresh victim word lines associated with those aggressor addresses. Device 500 can also receive commands that cause it to perform a refresh operation. Refresh signal AREF can be a pulse signal that is activated when command control 536 receives a signal indicating refresh mode. In some embodiments, the refresh command can be externally issued to memory device 500. In some embodiments, the refresh command can be periodically generated by a component of the device. In some embodiments, refresh signal AREF can also be activated when an external signal indicates a refresh enter command. Refresh signal AREF can be activated once immediately after the command is input and can be activated cyclically thereafter at desired internal timing. Thus, refresh operations can continue automatically. A self-refresh exit command can cause the automatic activation of refresh signal AREF to cease and return to the IDLE state.

[0071] A refresh signal AREF is supplied to the refresh control circuit 546. The refresh control circuit 546 supplies a refresh row address RXADD to the row control element 538, which can refresh the word line WL indicated by the refresh row address RXADD. The refresh control circuit 546 can control the timing of the refresh operation and can generate and provide the refresh address RXADD. The refresh control circuit 546 can be controlled to change the details of the refresh address RXADD (e.g., how the refresh address is calculated, the timing of the refresh address), or can operate based on internal logic.

[0072] The memory device 500 can perform two types of refresh operations: an auto-refresh operation and a targeted refresh operation. An auto-refresh operation can involve sequentially refreshing different word lines of the memory array 542 such that each word line is refreshed at least once in a cycle based on the expected decay rate of the information in the memory cells. The refresh control circuit 546 can provide a refresh address RXADD from a refresh address sequence. In some embodiments, the refresh address RXADD associated with the auto-refresh operation can cause multiple word lines of the memory array 542 to be refreshed simultaneously.

[0073] A targeted refresh operation can be used to refresh the victim word line of an identified aggressor word line. In some embodiments, a refresh operation that would normally be used for an auto-refresh operation can be 'stolen' and used instead for a targeted refresh operation. The victim word line can be physically close to the aggressor word line. For example, in some embodiments, the victim word line can include word lines that are physically adjacent to the aggressor word line (e.g., R+1 and R-1). In some embodiments, the victim word line can include word lines that are adjacent to neighboring word lines (e.g., R+2 and R-2).

[0074] To perform a target refresh operation, the aggressor word line must be identified based on the access pattern to the word line. The refresh control circuit 546 may store the row address XADD in a CAM register stack (e.g., Figure 4 The CAM register stack 400 is a CAM register stack. Each CAM cell register can store a row address XADD. The incoming row address can be compared with previously stored row addresses to determine whether a particular row is frequently accessed. In some embodiments, each register in the stack can be associated with a count value that can be used to track the number of accesses to the row address stored in the associated register. Once an aggressor is identified, one or more victim addresses can be calculated based on the aggressor address and then provided as the refresh address RXADD.

[0075] The power supply terminals are supplied with power supply potentials VDD and VSS. The power supply potentials VDD and VSS are supplied to the internal voltage generator circuit 558. The internal voltage generator circuit 558 generates various internal potentials VPP, VOD, VARY, VPERI, etc. based on the power supply potentials VDD and VSS supplied to the power supply terminals. The internal potential VPP is mainly used in the row control element 538, the internal potentials VOD and VARY are mainly used in the sense amplifier SAMP included in the memory array 542, and the internal potential VPERI is used in many peripheral circuit blocks.

[0076] The power supply terminals are also supplied with power supply potentials VDDQ and VSSQ. The power supply potentials VDDQ and VSSQ are supplied to the input / output circuit 556. In one embodiment of the present disclosure, the power supply potentials VDDQ and VSSQ supplied to the power supply terminals may be the same potential as the power supply potentials VDD and VSS supplied to the power supply terminals. In another embodiment of the present disclosure, the power supply potentials VDDQ and VSSQ supplied to the power supply terminals may be different potentials from the power supply potentials VDD and VSS supplied to the power supply terminals. The power supply potentials VDDQ and VSSQ supplied to the power supply terminals are used for the input / output circuit 556 so that power supply noise generated by the input / output circuit 556 does not propagate to other circuit blocks.

[0077] Figure 6 is a block diagram of a memory array according to an embodiment of the present disclosure. Figure 6 Shows where the CAM cell of the present disclosure can be used to implement a fuse latch (e.g., Figure 5 An example environment of a fuse latch 564). Figure 6 The transmission path of the fuse bus from a pair of fuse arrays 560a and 560b through the memory array 600 is shown. In some embodiments, the memory array 600 may be Figure 1 Implementation of the memory array 542 of FIG. The memory array 200 includes 16 memory banks 668. The 16 memory banks 668 are organized into four memory bank groups (BG0-BG3) of four memory banks 668 each. Each of the memory banks 668 is associated with a fuse latch, such as a set of row latches 664 and column latches 666. The row latches 664 and column latches 666 may implement Figure 5 Each of the row latch 664 and / or column latch 666 may include Figure 3 CAM unit register 300.

[0078] Each row latch 664 and column latch 666 may be associated with a corresponding redundant row or column of memory. Each row latch 664 and column latch 666 may be a CAM cell register having a plurality of CAM cells. The row latch 664 may have a number of CAM cells equal to the number of bits in the row address, while the column latch 666 may have a number of CAM cells equal to the number of bits in the column address. Taking the operation of the row latch 664 as an example, the row latch may receive a repaired row address from the fuse array 660a-b along the fuse bus. The row address may be accompanied by a select signal, which may serve as a write signal for the CAM cell of the row latch 664. Each bit of the row address may be stored in the latch portion of the corresponding one of the CAM cells (e.g., Figure 1 The latch portion 102 or Figure 2 202). Each bit of the row address may be accompanied by a portion of a select signal that acts as a write signal to the CAM cell that will store that bit.

[0079] The row latches 664 may collectively receive an incoming row address XADD. In some embodiments, only some of the row latches 664 (e.g., the row latches 664 of a given bank) may collectively receive the row address XADD. The row latch 664 that receives the row address may compare the row address with the address stored in the row latch 664. For example, each row latch 664 may be coupled to a signal line (e.g., a 100 bit) that may carry a voltage associated with the value of the match bit. Figure 3 Before comparing the row address, the driver circuit (for example, Figure 3 316) can precharge the signal line to a voltage associated with a high logic level. Each CAM cell of a given row latch 664 can compare a bit of the row address with a stored bit and, if there is no match, change the voltage of the signal line. In this way, the signal line can only remain at a first voltage (e.g., a high logic level) if all bits of the address match all bits of the row address. While the signal line remains at a high logic level, only the row associated with the row latch 664 can be accessed.

[0080] The fuse bus can be used to provide addresses from fuse arrays 660a-b to row latches 664 and column latches 666. Figure 6 In a particular embodiment, there may be a pair of fuse arrays 660a and 660b. Fuse array 660a may include a set of fuses and / or antifuses that may generally be used to store address information for a first portion of a row address. Fuse array 660b may include a set of fuses and / or antifuses that may generally be used to store address information for a second portion of a row address. In some embodiments, the row address may be divided between the first portion and the second portion based on a numerical value assigned to the address.

[0081] Fuse arrays 660a-b may include fuse groups that can be used to record memory addresses for repair. For example, when a defective memory row is identified, the address associated with the defective row can be programmed into one of fuse arrays 660a-b by blowing one or more fuses. The blown fuse group can be associated with a specific row of redundant memory. During a broadcast operation, fuse arrays 660a-b can broadcast the row addresses stored in fuse arrays 660a-b along a fuse bus. In some embodiments, fuse logic circuit 662 can receive addresses from both fuse arrays 660a-b and can alternately provide addresses from the first fuse array 660a and the second fuse array 660b along the fuse bus to row latch 664 and column latch 666.

[0082] After leaving the fuse logic circuit 662, the fuse bus can pass the data through one or more option circuits 663. The option circuits 663 can include various settings for the memory that can interact with the addresses along the fuse bus. For example, the option circuits 663 can include fuse settings such as test mode and power supply fuses. The data stored in the fuse arrays 660a-b can be latched and / or read by the option circuits 663, which can then determine one or more properties of the memory based on the option data provided along the fuse bus.

[0083] After passing through the option circuit 663, the fuse bus may pass through the row latches 664 of all memory banks 668 before passing through the column latches 666 of all memory banks 668. In addition to providing data (including address data) along the fuse bus, the fuse logic circuit 662 may also provide one or more select signals along the fuse bus. The select signals may be associated with a particular data packet along the fuse bus and may determine which circuit along the fuse bus a particular data packet is associated with. The select signals may act as Figure 1-2 664 and may allow data to be written to the latch portion of the row latch 664 or column latch 666 associated with that select signal. For example, if the row latch select signal is in an active state, it may indicate that the data packet is to be stored in the row latch 664. In some embodiments, this may overwrite the address already stored in the row latch 664 with the address from the fuse bus. Further select signals may be used to specify a particular location of a particular row latch 664 where a data packet is to be stored (e.g., a bank group select signal, a bank select signal, etc.).

[0084] Figure 7 is a block diagram of a refresh control circuit according to an embodiment of the present disclosure. Figure 7An example application of the CAM cell of the present disclosure is shown as a way to track accesses to a word line of a memory in order to detect a row hammer event. In some embodiments, the refresh control circuit 746 may implement Figure 5 746. Dashed line 742 is shown to indicate that in certain embodiments, each of the components (e.g., refresh control circuit 746 and row control 738) may correspond to a specific memory bank, and these components may be repeated for each of the memory banks. Thus, there may be multiple refresh control circuits 746 and row controls 738. For the sake of brevity, only the components of a single bank will be described.

[0085] The DRAM interface 733 may provide one or more signals to the address refresh control circuit 746 and the row control 738. The refresh control circuit 746 may include a sampling signal generator 768, an address sampler 767, a row hammer refresh (RHR) state controller 765, and a refresh address generator 769. The DRAM interface 733 may represent a memory device (e.g., Figure 5 The one or more components of the device 500 provide one or more control signals, such as the auto-refresh signal AREF and the row address XADD, to the refresh control circuit 746 and / or the row control element 738. The sampling signal generator 768 generates the sampling signal ArmSample at random timing.

[0086] The address sampler 767 may sample (e.g., latch) the current row address XADD in response to activation of ArmSample. The address sampler 767 may also provide one or more of the latched addresses as matched addresses HitXADD to the refresh address generator 769. The address sampler 767 may include a CAM register stack (e.g., Figure 4 The CAM register stack 400 may be used to count accesses to different row addresses XADD.

[0087] The RHR state controller 765 may provide a signal RHR to indicate that a row hammer refresh (e.g., a refresh of a victim row corresponding to an identified aggressor row) should occur. The RHR state controller 765 may also provide an internal refresh signal IREF to indicate that an auto-refresh should occur. In response to activation of RHR, the refresh address generator 769 may provide a refresh address RXADD, which may be an auto-refresh address or may be one or more victim addresses corresponding to a victim row corresponding to an aggressor row corresponding to the matching address HitXADD. The row control element 738 may perform a refresh operation in response to the refresh address RXADD and the row hammer refresh signal RHR. The row control element 738 may perform an auto-refresh operation based on the refresh address RXADD and the internal refresh signal IREF.

[0088] DRAM interface 733 may represent one or more components that provide signals to components of a memory bank. For example, DRAM interface 733 may represent, for example, Figure 5 Components of the command address input circuit 532, address decoder 534, and / or command decoder 536 of the DRAM interface 733. The DRAM interface 733 may provide a row address XADD, an auto-refresh signal AREF, an activation signal ACT, and a precharge signal Pre. The auto-refresh signal AREF may be a periodic signal that may indicate when an auto-refresh operation will occur. The activation signal ACT may be provided to activate a given bank of memory. The precharge signal Pre may be provided to precharge a given bank of memory. The row address XADD may be a signal comprising multiple bits (which may be transmitted serially or in parallel) and may correspond to a particular row of activated memory banks.

[0089] The sampling signal generator 768 provides a sampling signal ArmSample. The address sampler 767 may receive a row address XADD from the DRAM interface 733 and receive ArmSample from the sampling signal generator 768. The row address XADD may direct access operations (eg, read and write operations) to the memory cell array (eg, Figure 5 Each time the address sampler 767 receives an activation (eg, a pulse) of ArmSample, the address sampler 767 may sample the current value of XADD and may save the current value of XADD in a CAM register of the CAM stack.

[0090] The address sampler 767 can determine whether one or more rows are aggressor rows based on the sampled row address XADD and can provide the identified aggressor row as a matching address HitXADD. As part of this determination, the address sampler 767 can record (e.g., by latching and / or storing in a register) the current value of XADD in response to the activation of ArmSample. The current value of XADD can be compared with previously recorded addresses in the address sampler 767 (e.g., addresses stored in latches / registers) to determine the access pattern of the sampled addresses over time. If the address sampler 767 determines that the current row address XADD is repeatedly accessed (e.g., is an aggressor row), the activation of ArmSample can also cause the address sampler 767 to provide the address of the aggressor row as a matching address HitXADD. In some embodiments, the matching address (e.g., aggressor address) HitXADD can be stored in a latch circuit for later retrieval by the refresh address generator 769.

[0091] The address sampler 767 may store the sampled address value in a CAM stack (eg, Figure 4The CAM register stack 420 may store a CAM cell register in a CAM register stack 420 and may have a counter associated with each of the stored addresses. When ArmSample is activated, if the current row address XADD matches one of the stored addresses, the value of the counter may be incremented. In response to the activation of ArmSample, the address sampler 767 may provide the address associated with the highest value counter as the matching address HitXADD. Other methods of identifying aggressor addresses may be used in other examples.

[0092] The RHR state controller 765 can receive the auto-refresh signal AREF and provide a row hammer refresh signal RHR. The auto-refresh signal AREF can be generated periodically and can be used to control the timing of refresh operations. A memory device can implement an auto-refresh operation sequence to periodically refresh rows of the memory device. The RHR signal can be generated to indicate that the device should refresh a specific target row (e.g., a victim row) rather than an address from the auto-refresh address sequence. The RHR state controller 765 can use internal logic to provide the RHR signal. In some embodiments, the RHR state controller 765 can provide the RHR signal based on a specific number of activations of AREF (e.g., every 4 activations of AREF). The RHR state controller 765 can also provide an internal refresh signal IREF, which can indicate that an auto-refresh operation should occur. In some embodiments, the RHR and IREF signals can be generated so that they are not simultaneously active (e.g., both are not at a high logic level at the same time).

[0093] The refresh address generator 769 may receive a row hammer refresh signal RHR and a matching address HitXADD. The matching address HitXADD may represent an aggressor row. The refresh address generator 769 may determine the locations of one or more victim rows based on the matching address HitXADD and provide them as refresh addresses RXADD. In some embodiments, the victim rows may include rows that are physically adjacent to the aggressor rows (e.g., HitXADD+1 and HitXADD-1). In some embodiments, the victim rows may also include rows that are physically adjacent to physically adjacent rows of the aggressor rows (e.g., HitXADD+2 and HitXADD-2). In other examples, other relationships between the victim rows and the identified aggressor rows may be used.

[0094] The refresh address generator 769 may determine the value of the refresh address RXADD based on the row hammer refresh signal RHR. In some embodiments, when the signal RHR is not active, the refresh address generator 769 may provide one of the auto-refresh address sequences. When the signal RHR is active, the refresh address generator 769 may provide a target refresh address, such as a victim address, as the refresh address RXADD.

[0095] The row control 738 can perform one or more operations on the memory array (not shown) based on the received signal and address. For example, in response to the activation signal ACT and the row address XADD (and IREF and RHR at low logic levels), the row control 738 can direct one or more access operations (e.g., read operations) to the specified row address XADD. In response to either the RHR or IREF signal (or both) being active, the row control 738 can refresh the refresh address RXADD.

[0096] Figure 8 800 is a block diagram of an address sampler according to an embodiment of the present disclosure. In some embodiments, the address sampler 800 may be used to implement Figure 7 The address sampler 767. The address sampler 800 includes a Figure 4 The address sampler 800 may include a CAM register stack 870 of the CAM register stack 400. The address sampler 800 may include a CAM register stack 870, wherein each of the CAM register stacks 870 may have a corresponding counter 871. The counter 871 may be coupled to a comparator 872, which may be coupled to a pointer 874 via a counter scrambler 873. The register 870 may be coupled to an address latch 875, which may store and provide the identified row hammer address as the match address HitXADD.

[0097] The address sampler 800 may sample the current row address XADD in response to a sampling signal ArmSample. The sampling signal ArmSample may also cause the address sampler 800 to determine whether the sampled address (e.g., an address stored in one of the registers 870) is a row hammer address and store it on the address latch 875, where the sampled address may be provided as a matching address HitXADD to a refresh address generator (e.g., Figure 7 Refresh address generator 769).

[0098] Each time the sampling signal ArmSample is provided, the current row address XADD may be compared with the address stored in the CAM register stack 870. The current row address XADD may be used as external data X_Compare (e.g., as in Figure 3-4 ) is provided to each of the CAM registers of the CAM register stack 870. Each of the CAM registers of the CAM register stack 870 may provide a match bit that indicates whether the row address XADD exactly matches the address already stored in each of the CAM registers.

[0099] If the current address XADD is already stored in one of the registers (e.g., if at least one of the matching bits is at a high logic level), the counter 871 associated with that register 870 may be incremented. If the current address XADD is not already stored in one of the CAM cell registers in the stack 870 (e.g., if all matching bits are at a low logic level), it may be added to one of the registers in the CAM register stack 870. If there is an open CAM cell register (e.g., a register without a latched address), the sampled address XADD may be stored in that open register. If there is no open register, the register associated with the counter 871 with the lowest value (as indicated by pointer 874) may have its latched address replaced with the sampled address XADD. In either case, the row address XADD may be written along with a write signal at a high logic level (e.g., Figure 1-2 This may cause the bits of the row address XADD to overwrite the data previously stored in the CAM cell register.

[0100] The ArmSample signal may also cause the comparator 872 to determine the counter 871 with the maximum and minimum values. These may be provided to the counter scrambler 873, which may match the maximum and minimum counters 871 with their respective associated registers 870. The pointer 874 may point to the CAM cell register of the CAM stack 870 associated with the maximum count value in the counter 871 and may point to the CAM register stack 870 associated with the minimum count value in the counter 871. When a new address XADD is sampled and there is no open register 870 to store it, the register 870 may be overwritten with the minimum pointer. The signal ArmSample may cause the address stored in the CAM register stack 870 indicated by the maximum pointer to be stored in the address latch 875.

[0101] The address stored in the address latch 875 may be provided to match the address HitXADD. When a target refresh operation is carried out based on the address HitXADD (eg, when a victim address associated with HitXADD is refreshed), the counter 871 associated with the refresh operation may be reset.

[0102] Of course, it should be understood that any of the examples, embodiments, or processes described herein may be combined with one or more other examples, embodiments, and / or processes, or separated and / or performed in separate devices or device portions, in accordance with the present systems, devices, and methods.

[0103] Finally, the above discussion is intended only to illustrate the present system and should not be construed as limiting the appended claims to any particular embodiment or group of embodiments. Thus, while the present system has been described in particular detail with reference to exemplary embodiments, it should be understood that those skilled in the art may devise numerous modifications and alternative embodiments without departing from the broader and intended spirit and scope of the present system as set forth in the appended claims. Accordingly, the specification and drawings are to be regarded as illustrative and not intended to limit the scope of the appended claims.

Claims

1. A device comprising: a latch circuit configured to store a first signal and a second signal, wherein the second signal is complementary to the first signal; A comparator circuit configured to receive a third signal and a fourth signal, wherein the third signal is complementary to the fourth signal, the comparator circuit comprising: a first portion configured to activate when the fourth signal is at a first logic level and configured to, when active, couple a signal line to a voltage when the first signal is at the first logic level; and a second portion configured to activate when the third signal is at the first logic level and configured to, when active, couple the signal line to the voltage when the second signal is at the first logic level, The latch circuit is configured to receive a fifth signal and a sixth signal complementary to the fifth signal, and replace the first signal with the fifth signal and replace the second signal with the sixth signal when a write signal is valid.

2. The apparatus of claim 1 , wherein the latch circuit comprises a first write transistor coupled between the fifth signal and the first signal and a second write transistor coupled between the sixth signal and the second signal, wherein the first write transistor and the second write transistor have gates commonly coupled to the write signal.

3. The apparatus of claim 1, wherein the logic state of the first signal represents the logic state of a bit stored by the latch circuit.

4. The apparatus of claim 1, wherein the latch circuit comprises a first plurality of transistors all having a first size, and wherein the comparator circuit comprises a second plurality of transistors all having a second size different from the first size.

5. A device comprising: A latch circuit configured to store a first signal and a second signal, wherein the second signal is complementary to the first signal, wherein the latch circuit comprises: a first transistor configured to couple a first voltage to the first signal when the second signal is at a second logic level; a second transistor configured to couple the first voltage to the second signal when the first signal is at the second logic level; a third transistor configured to couple a second voltage to the first signal when the second signal is at a first logic level; and a fourth transistor configured to couple the second voltage to the second signal when the first signal is at the first logic level, wherein the first voltage is associated with the first logic level and the second voltage is associated with the second logic level; and A comparator circuit configured to receive a third signal and a fourth signal, wherein the third signal is complementary to the fourth signal, the comparator circuit comprising: a first portion configured to activate when the fourth signal is at the first logic level and configured to, when active, couple a signal line to a voltage when the first signal is at the first logic level; and A second portion is configured to activate when the third signal is at the first logic level and is configured to, when active, couple the signal line to the voltage when the second signal is at the first logic level.

6. The apparatus of claim 5 , wherein the first portion of the comparator circuit comprises a fifth transistor and a sixth transistor coupled in series between the signal line and the first voltage, wherein the fifth transistor is activated by the first signal at the first logic level and the sixth transistor is activated by the fourth signal at the first logic level, and wherein the second portion of the comparator circuit includes a seventh transistor and an eighth transistor coupled in series between the signal line and the first voltage, wherein the seventh transistor is activated by the second signal at the first logic level and the eighth transistor is activated by the third signal at the first logic level.

7. A device comprising: a plurality of content addressable memory (CAM) registers, each of the CAM registers comprising a plurality of CAM cells configured to store respective bits of stored information and further configured to compare the respective bits of stored information with respective bits of external information; and a plurality of signal lines, each of the plurality of signal lines coupled to one of the CAM registers, wherein each of the plurality of CAM cells of a given one of the plurality of CAM registers is configured to change a voltage of an associated one of the plurality of signal lines to a first voltage if the corresponding bit of stored information does not match the corresponding bit of external information, wherein each of the plurality of CAM cells is configured to store a first signal representing a logic level of the stored bit and a second signal complementary to the first signal, to receive a third signal representing a logic level of the bit of external information and a fourth signal complementary to the third signal, and to compare the first signal with the fourth signal and the second signal with the third signal, and Wherein if the first signal and the fourth signal match or if the second signal and the third signal match, each of the plurality of CAM cells is configured to change the voltage of the associated one of the plurality of signal lines to the first voltage.

8. The apparatus of claim 7 , further comprising a driver circuit configured to set a voltage of the plurality of signal lines to a second voltage different from the first voltage before any of the CAM cells compares the corresponding bit of stored information with the corresponding bit of external information.

9. The apparatus of claim 7, wherein a plurality of external bits are commonly provided to each of the plurality of CAM registers.

10. The apparatus of claim 9, wherein there are the same number of the plurality of external bits and the plurality of CAM cells in each of the plurality of CAM registers.

11. The apparatus of claim 7, wherein each of the plurality of CAM registers is configured to store a memory address associated with a group of memory cells of a memory device, and wherein each of the plurality of CAM cells of a given CAM register is configured to store a bit of the memory address.

12. A device comprising: a fuse array configured to provide a row address comprising a plurality of bits; a fuse latch associated with a redundant group of memory cells, the fuse latch comprising a plurality of content addressable memory (CAM) cells, each of the CAM cells comprising a latch portion and a comparator portion configured to store a respective one of the plurality of bits of the row address; a row control configured to provide an access address comprising a plurality of bits, wherein the comparator portion is configured to compare respective bits of the access address with the respective stored bits, and wherein each of the CAM cells is configured to change the state of a match bit from a high level to a low level if the bit of the access address does not match the stored bit; a first inverter circuit configured to invert a plurality of first signals, each first signal representing one of the plurality of bits of the row address to a complementary plurality of second signals, wherein said each of the CAM cells is configured to store a corresponding one of the plurality of first signals and a corresponding one of the plurality of second signals; and a second inverter circuit configured to invert a plurality of third signals, each third signal representing one of the bits of the access address to a complementary plurality of fourth signals, wherein each of the CAM cells of the fuse latch is configured to compare the respective first and fourth signals and the respective second signal with the third signal, Wherein each of the CAM cells is configured to change the state of the match bit if the respective first signal matches the fourth signal or the respective second signal matches the third signal.

13. The apparatus of claim 12 , further comprising fuse logic circuitry configured to provide the row address to a write signal, wherein each of the plurality of CAM cells in the fuse latch is configured to store the respective one of the plurality of bits of the row address in response to the row address and the write signal.

14. The apparatus of claim 12, wherein the row control is configured to perform an access operation on the redundant group of memory cells if the match bit remains high after comparing the access address with the row address.

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