Device for measuring event delay

Abstract

The present disclosure provides an apparatus for measuring a time delay between a first event and a second event in a DToF system, including: a delay circuit, wherein the delay circuit includes: N delay units, the N delay units being connected in series to form a ring oscillator, where N is an odd number greater than 1; and N first latches configured to determine states of the N delay units based on the second event and latch N first current output values of the N delay units; and a delay unit selection circuit configured to randomly determine states of the N delay units in response to the first event and determine a starting delay unit according to the states of the N delay units; wherein the time delay between the first event and the second event is determined based on the determined starting delay unit and the latched first current output values.

Description

Technical Field

[0001] The present disclosure relates to the field of 3D depth sensing, and more particularly, to an apparatus for measuring the time delay between a first event and a second event in a DToF system. Background Art

[0002] In a time-to-digital converter (TDC) in a direct-time of flight (D-ToF) system, generally, a delay unit can be used as the minimum timing unit, and a fine TDC can be composed of multiple delay units. The delay time of the delay unit determines the timing accuracy of the time-to-digital converter, and the number of delay units determines the timing range of the time-to-digital converter. Additionally, an extra counter can be set as a coarse TDC to expand the timing range.

[0003] However, due to the characteristics of semiconductor manufacturing processes, different delay units may have specific deviations in performance (for example, different delay units may have different delay times), resulting in timing deviations of the time-to-digital converter. Eventually, it may lead to different widths of different statistical bins (bins) of the histogram generated by the D-ToF system, as Figure 1 shown. Therefore, a measuring device that can effectively reduce the influence caused by the deviation of the delay units in the time-to-digital converter is needed. Summary of the Invention

[0004] The present disclosure provides an apparatus for measuring the time delay between a first event and a second event in a DToF system. The apparatus can arbitrarily specify a starting delay unit, and each timing can start from any delay unit. In this method, for the same time difference, after traversing all the starting delay units once, the delay deviation of the delay units will be canceled or averaged out. Furthermore, through averaging or peak finding, a more accurate time difference between events can be measured.

[0005] One aspect of the present disclosure provides an apparatus for measuring the delay between a first event and a second event in a DToF system, including: a delay circuit, wherein the delay circuit includes: N delay units, the N delay units being connected in series to form a ring oscillator, where N is an odd number greater than 1; and N first latches configured to determine the states of the N delay units based on the second event and latch N first current output values of the N delay units; and a delay unit selection circuit configured to randomly determine the states of the N delay units in response to the first event and determine a starting delay unit according to the states of the N delay units; wherein the delay between the first event and the second event is determined based on the determined starting delay unit and the latched first current output values.

[0006] One aspect of the present disclosure provides an apparatus for measuring the delay between a first event and a second event in a DToF system, wherein the first event is a timing start event and the second event is a timing end event.

[0007] One aspect of the present disclosure provides an apparatus for measuring the delay between a first event and a second event in a DToF system, wherein the delay unit selection circuit includes a first selection circuit, and the first selection circuit includes: a first random number generation encoder configured to generate a first random control signal; and N multiplexers configured to determine the states of the N delay units according to the first random control signal and the first event and determine a starting delay unit according to the states of the N delay units.

[0008] One aspect of the present disclosure provides an apparatus for measuring the delay between a first event and a second event in a DToF system, wherein the first random control signal is an N-bit first encoded signal, a random one of the N bits has a first value, and the other bits have a second value; and wherein the N multiplexers determine the states of the N delay units related to the first event according to the N-bit first encoded signal and the first event to determine a starting delay unit.

[0009] One aspect of the present disclosure provides an apparatus for measuring the delay between a first event and a second event in a DToF system, wherein the clock input terminals of each of the N first latches are respectively connected to a second signal associated with the second event.

[0010] One aspect of the present disclosure provides an apparatus for measuring the delay between a first event and a second event in a DToF system, wherein the apparatus further includes a first decoder, and the first decoder is configured to decode the output value of the determined starting delay unit and the latched first current output value, and determine the delay through the difference generated by the decoding.

[0011] One aspect of the present disclosure provides an apparatus for measuring the delay between a first event and a second event in a DToF system, wherein the delay unit selection circuit includes a second selection circuit, and the second selection circuit includes: a second random number generation encoder configured to generate a second random control signal; a delay chain configured to randomly delay a pre-start signal based on the second random control signal to output a signal related to the first event with a random delay; and N second latches configured to determine the states of the N delay units as the states of the starting delay unit based on the first event with a random delay, and latch the states of the starting delay unit.

[0012] One aspect of the present disclosure provides an apparatus for measuring the delay between a first event and a second event in a DToF system, wherein the delay is determined according to the difference between the values latched by the N second latches and the values latched by the N first latches.

[0013] One aspect of the present disclosure provides an apparatus for measuring the delay between a first event and a second event in a DToF system, wherein the second random control signal is a (K + 1)-bit second encoded signal, one random bit in the (K + 1) bits has a first value, and the other bits have a second value, where K is an integer greater than or equal to 1.

[0014] One aspect of the present disclosure provides an apparatus for measuring the delay between a first event and a second event in a DToF system, wherein the data input terminals of each of the N second latches are respectively connected to the output terminals of the N delay units.

[0015] One aspect of the present disclosure provides an apparatus for measuring the delay between a first event and a second event in a DToF system, wherein the delay chain includes: K buffers, wherein the input terminal of the first buffer among the K buffers is connected to the pre-start signal, and the input terminal of the k-th buffer among the K buffers is connected to the output terminal of the (k - 1)-th buffer, where 1 < k ≤ K; and K + 1 transistors, wherein the gates of each of the K + 1 transistors are respectively and sequentially connected to the K + 1 output terminals of the second random number generation encoder; the source of each of the first K transistors among the K + 1 transistors is connected to the input terminals of the K buffers, and the source of the (K + 1)-th transistor among the K + 1 transistors is connected to the output terminal of the K-th buffer; and the drain of each of the K + 1 transistors is connected to the output terminal of the delay chain to output a signal related to the first event with a random delay.

[0016] One aspect of the present disclosure provides an apparatus for measuring the delay between a first event and a second event in a DToF system, wherein the clock input terminals of each of the N second latches are respectively connected to the output terminal of the delay chain. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] From the following description in conjunction with the accompanying drawings, the above and other aspects, features, and advantages of certain embodiments of the present disclosure will become more apparent, wherein:

[0018] Figure 1 An example histogram showing statistical bars with different widths due to performance deviations of delay units in a D-ToF system is shown.

[0019] Figure 2 An example apparatus for measuring the delay between a first event and a second event in a DToF system according to an embodiment of the present disclosure is shown.

[0020] Figure 3 An example apparatus for measuring the delay between a first event and a second event in a DToF system according to an embodiment of the present disclosure is shown.

[0021] Figure 4 A diagram showing a random delay link and its corresponding signal timing according to an embodiment of the present disclosure is shown.

[0022] Figure 5 A signal timing diagram showing an example timing process according to an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0023] Before proceeding with the following detailed description, it may be advantageous to set forth definitions of certain words and phrases used throughout this patent document. The terms "coupled," "connected," and their derivatives refer to any direct or indirect communication or connection between two or more elements, whether or not those elements are in physical contact with each other. The terms "transmit," "receive," and "communicate," and their derivatives, encompass both direct and indirect communication. The terms "comprise" and "include," and their derivatives, mean including but not limited to. The term "or" is inclusive, meaning and / or. The phrase "associated with," and its derivatives, means including, included within, interconnected with, containing, contained within, connected or connected to, coupled or coupled to, communicating with, cooperating with, interwoven with, juxtaposed with, proximate to, bound or bound to, having, having the attribute of, having a relationship or relationship with, and so on. The term "controller" refers to any device, system, or portion thereof that controls at least one operation. Such a controller may be implemented in hardware, or a combination of hardware, software, and / or firmware. The functions associated with any particular controller may be centralized or distributed, whether local or remote. The phrase "at least one," when used in conjunction with a list of items, means that different combinations of one or more of the listed items may be used, and only one item in the list may be required. For example, "at least one of A, B, C" includes any of the following combinations: A, B, C, A and B, A and C, B and C, A and B and C.

[0024] Definitions of other specific words and phrases are provided throughout this patent document. Those of ordinary skill in the art should understand that, in many instances, if not most instances, such definitions apply to both the prior and future use of the words and phrases so defined.

[0025] In this patent document, the application combination of modules and the hierarchical division of sub-modules are only for illustration purposes, and without departing from the scope of the present disclosure, the application combination of modules and the hierarchical division of sub-modules may have different forms.

[0026] Embodiments of the present disclosure will be further described below in conjunction with the accompanying drawings.

[0027] Figure 2 An example apparatus 200 for measuring the delay between a first event and a second event in a DToF system according to an embodiment of the present disclosure is shown.

[0028] As Figure 2As shown, the exemplary device 200 according to an embodiment of the present disclosure may include a delay circuit 202. In some embodiments, the delay circuit 202 may include N delay units, such as A0 - A4, where N may be an odd number greater than 1. The first input terminal of the nth delay unit among the N delay units may be connected to the output terminal of the (n - 1)th delay unit, and the first input terminal of the first delay unit may be connected to the output terminal of the Nth delay unit, where 1 < n ≤ N.

[0029] In some embodiments, NAND gates may be used as delay units. In other embodiments, any circuit or unit with a specific delay, such as buffers, inverters, etc., may also be used as delay units, which is not limited here. In the following, NAND gates are used as delay units for exemplary description.

[0030] In some embodiments, the delay circuit 202 may further include N first latches, such as L0 - L4. The data input terminal of each of the N first latches may be respectively connected to the output terminal of the corresponding delay unit. The output terminal of each of the N first latches may be connected to the input terminal of a decoder (not shown) for decoding the latched values of the N latches. The clock input terminal of each of the N first latches may be connected to a timing end signal (e.g., STOP signal) associated with a timing end event (the second event).

[0031] In some embodiments, the exemplary device 200 according to an embodiment of the present disclosure may further include a first selection circuit 203. The first selection circuit 203 may include a first random number generation encoder 201 and N two - to - one selectors.

[0032] The first random number generation encoder 201 may be configured to generate a first random control signal, which may be an N - bit first encoded signal. Each bit of the N - bit first encoded signal (e.g., S0S1S2S3S4) generated by the first random number generation encoder 201 may be sequentially input to the strobe input terminal of each selector. The input terminal 0 of each selector may be connected to a power supply VDD (e.g., high level), and the other input terminal 1 may be connected to a timing start signal START associated with a timing start event.

[0033] More specifically, as Figure 2As shown, the exemplary device 200 according to an embodiment of the present disclosure may use a NAND gate as a delay unit. At the same time, one of the input terminals (e.g., the first input terminal) of each NAND gate may be connected to a multiplexer, and the other input terminal (e.g., the second input terminal) may be connected to the output terminal of the previous-stage NAND gate. N (N is an odd number greater than 1) NAND gates are connected end to end to form a ring oscillator. The strobe input terminals of the N multiplexers may be controlled by an external encoder (e.g., the first random number generation encoder 201). The input terminal 0 of each multiplexer may be connected to the power supply VDD (e.g., high level), and the other input terminal 1 may be connected to the timing start signal START of the first event. In the initial state, the START signal may be at a low level, and the ring oscillator remains stable. At the same time, the STOP signal may remain at a high level, making the first latches L0-L4 in a transparent state, and the output Q value is the same as the input D value. For simplicity, Figure 2 Taking the ring oscillator composed of 5 NAND gates as an example to illustrate the timing process.

[0034] First, the first random number generation encoder 201 may generate a 5-bit first coding signal corresponding to a random number (e.g., the 5-bit first coding signal S0S1S2S3S4). Among them, it is assumed that one of the bits has a first value (e.g., 1), and the other bits are all second values (e.g., 0). Each bit of the first coding signal generated by the encoder 201 may be sequentially input to the strobe input terminal of each multiplexer, so as to control the 5 multiplexers, so that the START signal can be input to the corresponding delay unit through a random multiplexer.

[0035] (1) First timing:

[0036] Since the output of the encoder is a random value, it is assumed that the first coding signal output by the encoder in this timing is "10000", which means that the strobe input of the first multiplexer is 1, and the strobe inputs of the other multiplexers are all 0.

[0037] Initial state determination: Assume that the START signal is 0 in the initial state. At this time, the values of the outputs D0, D1, D2, D3, D4 of the 5 NAND gates are 1, 0, 1, 0, 1 respectively, and remain stable. At this time, the state of the delay unit corresponding to the first event is determined.

[0038] Timing start: Assume that the rising edge of the START signal is used as the timing start event (or the first event). When the START signal changes from 0 to 1, the timing starts. After a fixed time Delay0 (for example, the delay corresponding to delay unit A0), the state of the delay unit changes from the initial state. For example, the value of D0 changes from 1 to 0; after Delay1 (for example, the delay corresponding to delay unit A1), the value of D1 changes from 0 to 1. And so on, the transition of the D value starts to propagate over time.

[0039] Timing end: Assume that the falling edge of the STOP signal is used as the timing end event (or the second event). When the STOP signal changes from 1 to 0, the timing ends. At this time, latches L0 - L4 latch the current D values (i.e., D0 - D4), and output the latched values Q (i.e., Q0 - Q4).

[0040] After that, in combination with the latched value Q and decoder S (not shown), the latched value Q can be decoded according to a predetermined decoding rule, so that the time difference between the timing start event and the timing end event can be calculated. Table 1 below shows a part of an example predetermined decoding rule according to an embodiment of the present disclosure. As shown in Table 1, assume that the encoder output in this timing is "10000", and the latched value Q latched by the latch when the timing end event occurs is "01001", then the time difference between the timing start event and the timing end event can be decoded as 3 delays. As shown in Table 1, in this way, 5 delay units can record a maximum of 10 delays.

[0041] Table 1 Example Time Difference Decoding Table

[0042]

[0043] (2) Second timing:

[0044] Since the output of the encoder is a random value, assume that the first encoded signal output by the encoder in this timing is "01000", which means that the selected input of the second selector is 1, and the selected inputs of other selectors are all 0. After that, the second timing can be carried out in a similar timing process as described above.

[0045] And so on, in the DToF system, each light emission can perform a timing. Since the output of the encoder is a random value, during multiple light emission processes, all delay units can be used as the starting delay units for timing, and in the case of a large number of timings, all delay units can be used as the starting delay units and be traversed multiple times. In this way, for the same time difference, after traversing one or more starting delay units, the delay deviations of different delay units can be cancelled out or averaged, so that a more accurate time difference can be measured.

[0046] Figure 3 FIG. 300 shows an example apparatus for measuring the time delay between a first event and a second event in a DToF system according to an embodiment of the present disclosure.

[0047] As Figure 3 shown, based on the delay circuit 202 as Figure 2 shown, the apparatus 300 according to an embodiment of the present disclosure may further include a second selection circuit 303. The second selection circuit 303 may include a second random number generation encoder 301, a delay chain 302, and N second latches.

[0048] In some embodiments, the second random number generation encoder 301 may be configured to generate a second random control signal. In some embodiments, referring Figure 3 , the second random control signal may be an (N + 1)-bit second encoded signal, where a random one of the (N + 1) bits may have a first value and the other bits have a second value. The (N + 1)-bit second encoded signal may be output through (N + 1) output terminals S0 - SN of the second random number generation encoder 301. Wherein, N may be an integer greater than or equal to 1.

[0049] In some embodiments, the delay chain 302 may be configured to randomly delay a pre-start signal (e.g., Pre_START) associated with a first event (timing start event) based on the second random control signal to output a signal associated with the first event (e.g., START signal). For example, the falling edge of the START signal may be regarded as the timing start event.

[0050] In some embodiments, the delay chain 302 may include N buffers and (N + 1) transistors. Each buffer may have a specific delay. The input terminal of the first buffer among the N buffers is connected to the Pre_START signal, and the input terminal of the nth buffer among the N buffers is connected to the output terminal of the (n - 1)th buffer, where 1 < n ≤ N. As Figure 3 shown, the gate of each of the (N + 1) transistors may be sequentially connected to the (N + 1) output terminals of the second random number generation encoder 301 respectively; the source (or drain) of each of the first N transistors among the (N + 1) transistors may be connected to the input terminals of the N buffers, and the source (or drain) of the (N + 1)th transistor among the (N + 1) transistors may be connected to the output terminal of the Nth buffer; the drain (or source) of each of the (N + 1) transistors may be connected to the output terminal of the delay chain 302 and connected to the clock input terminal of each second latch.

[0051] In some embodiments, the data input terminals of each of the second latches (e.g., C0 - C4) can be respectively connected to the output terminals of the delay units, and can be configured to determine the state of the delay unit associated with the first event (i.e., the timing start event) based on the occurrence of the first event (e.g., the falling edge of the START signal), and latch the second current output value of the delay unit.

[0052] Next, the timing process according to the embodiments of the present disclosure will be further described in conjunction with Figure 3 Further describe the timing process according to the embodiments of the present disclosure.

[0053] As Figure 3 shown, as described above, two sets of latches can be configured in the device 300 to record the time information of two events (e.g., the timing start event and the timing end event). For example, based on a set of first latches L0 - L4 (for recording the time information of the timing end event) included in the delay circuit 202 as shown in Figure 2 shown, another set of second latches C0 - C4 can be configured to record the time information of the first event (the timing start event). The ring oscillator can be turned on in advance before the timing starts. For example, set OSC_start to 1. As described above, the rising edge or falling edge of the START signal can be used as the timing start point, and the falling edge or rising edge of the STOP signal can be used as the timing end point. The difference between the time information corresponding to the two events recorded by the two sets of latches can be used as the time difference between the timing start event and the timing end event. In the following example, the falling edge of the START signal is used as the timing start point for illustration.

[0054] A programmable random delay link (e.g., delay chain 302) regarding the input signal Pre_START and the output signal START as shown in Figure 3 shown can be set. Wherein, Pre_START can be a periodic input signal, which can change from 1 to 0 before each light-on. In this way, the falling edge of the START signal can have a random delay T compared to the falling edge of Pre_START. Thus, after the random delay T, the falling edge of the START signal arrives, triggering the timing start event, indicating the start of timing.

[0055] (1) First timing: Assume that currently only the S0 value of the encoder 302 output is 1, and other outputs are all 0. The change of the Pre_START signal from 1 to 0 indicates the start of measurement, as shown in Figure 4As shown, the Pre_START signal is transmitted out of the delay link (i.e., the START signal without delay) via S0 (without passing through any buffer). After a fixed optical delay, it is transmitted to the Light signal, indicating the start of lighting. When the falling edge of the START signal arrives, the states of delay units A0 - A4 can be determined, and the second latch C0 - C4 is triggered to latch the second current output values D0 - D4 of the delay units A0 - A4. After a specific time of flight (i.e., Time of Flight), the emitted photons are reflected back to the receiver, triggering the falling edge of STOP (i.e., the timing end signal) to stop the timing. At this time, the states of delay units A0 - A4 are determined, and the first latch L0 - L4 is triggered to latch the first current output values D0' - D4' of the delay units A0 - A4. The difference between the two time information recorded by the falling edge of the STOP signal and the falling edge of the START signal can be regarded as the delay between the timing start event and the timing end event. The corresponding signal timing diagram is as shown in Figure 4 the right column and Figure 5 as shown.

[0056] In some embodiments, the second current output values D0 - D4 corresponding to the timing start event and the first current output values D0' - D4' corresponding to the timing end event can still be decoded respectively by one or more decoders using the predetermined decoding rules shown in Table 1, so as to calculate the time difference between the timing start event and the timing end event. For example, in one timing, assuming that the output values D0 - D4 corresponding to the timing start event are "00101" and the output values D0' - D4' corresponding to the timing end event are "01011", then the time difference between the two events can be determined to be 4 - 1 = 3 delays.

[0057] (2) Second timing: Assume that the current random number encoder output has only S1 with a value of 1. Then the Pre_START signal is transmitted out of the delay chain via S1 (through a buffer) (i.e., the START signal with a buffer delay). After that, the second timing can be performed in a similar timing process as described above. The corresponding signal timing diagram is as shown in Figure 4 the right column.

[0058] And so on. Each time the light is turned on, timing can be performed once. Since the output of the random number encoder is a random value, during multiple light - on processes, all delay units can be used as the starting delay unit for timing. And when the number of timings is very large, all delay units can be used as the starting delay unit and be traversed multiple times. In this way, for the same time difference, after traversing one or more starting delay units, the delay deviations of different delay units can be mutually offset or averaged out, so that a more accurate time difference can be measured. In addition, in this way, due to the randomness and self - synchronization of the light - on time, the interference caused by the emission of other light sources can also be effectively reduced.

[0059] Although the present disclosure has been described with exemplary embodiments, various changes and modifications can be suggested to those skilled in the art. The present disclosure aims to cover such changes and modifications that fall within the scope of the appended claims. The various embodiments of the present disclosure can be combined and implemented.

[0060] Any description in the present disclosure should not be construed as implying that any particular element, step, or function is an essential element that must be included within the scope of the claims. The scope of the patent subject matter is defined only by the claims.

Claims

1. An apparatus for measuring the time delay between a first event and a second event in a DToF system, comprising: A time delay circuit, wherein the time delay circuit includes: N time delay units, the N time delay units being connected in series to form a ring oscillator, where N is an odd number greater than 1; and N first latches, configured to determine the states of the N time delay units based on the second event, and latch N first current output values of the N time delay units; and A time delay unit selection circuit, configured to control the input of a first signal associated with the first event to the time delay circuit, such that a randomly selected one of the N time delay units is selected as the starting time delay unit corresponding to the first event, wherein the time delay between the first event and the second event is determined based on the determined starting time delay unit and the latched N first current output values, wherein the time delay unit selection circuit includes a second selection circuit, and the second selection circuit includes: A second random number generation encoder, configured to generate a second random control signal; and A time delay chain, configured to randomly delay a pre-start signal associated with the first event based on the second random control signal, to output the first signal associated with the first event having a random delay.

2. The device according to claim 1, wherein The first event is a timing start event, and the second event is a timing end event.

3. The device according to claim 1, wherein, The time delay unit selection circuit further includes a first selection circuit, and the first selection circuit includes: A first random number generation encoder, configured to generate a first random control signal; and N multiplexers, configured to determine the states of the N time delay units according to the first random control signal and the first event, and determine the starting time delay unit according to the states of the N time delay units.

4. The apparatus according to claim 3, wherein The first random control signal is an N-bit first encoded signal, a randomly selected one of the N bits has a first value, and the other bits have a second value; and wherein the N multiplexers determine the states of the N time delay units related to the first event according to the N-bit first encoded signal and the first event, to determine the starting time delay unit.

5. The device according to claim 1, wherein, The clock input terminals of each of the N first latches are respectively connected to a second signal associated with the second event.

6. The device according to claim 1, wherein The apparatus further includes a first decoder, wherein the first decoder is configured to decode the output value of the determined starting time delay unit and the latched first current output values, and determine the time delay through the difference generated by the decoding.

7. The device according to claim 2, wherein, The second selection circuit further includes: N second latches, configured to determine the states of the N time delay units based on the first event having a random delay as the states of the starting time delay unit, and latch the states of the starting time delay unit.

8. The apparatus according to claim 7, wherein The time delay is determined according to the difference between the values latched by the N second latches and the values latched by the N first latches.

9. The apparatus according to claim 7, wherein The second random control signal is a (K + 1)-bit second encoding signal, with a random one of the (K + 1) bits having a first value and the other bits having a second value, where K is an integer greater than or equal to 1.

10. The apparatus according to claim 7, Among them, The data input terminals of each of the N second latches are respectively connected to the output terminals of the N delay units.

11. The device according to claim 9, wherein The delay chain includes: K buffers, where The input terminal of the first buffer among the K buffers is connected to the pre-start signal, and the input terminal of the k-th buffer among the K buffers is connected to the output terminal of the (k - 1)-th buffer, where 1 < k ≤ K; and (K + 1) transistors, where The gate of each of the (K + 1) transistors is respectively and sequentially connected to the (K + 1) output terminals of the second random number generation encoder; The source of each of the first K transistors among the (K + 1) transistors is connected to the input terminals of the K buffers, and the source of the (K + 1)-th transistor among the (K + 1) transistors is connected to the output terminal of the K-th buffer; and The drain of each of the (K + 1) transistors is connected to the output terminal of the delay chain to output a signal related to the first event with a random delay.

12. The apparatus according to claim 7, wherein Among them, The clock input terminals of each of the N second latches are respectively connected to the output terminal of the delay chain.

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