Hardware identification method, device, electronic device and computer-readable storage medium

Abstract

The present invention discloses a hardware identification method, device, electronic device and computer-readable storage medium, the method comprising: when the internal pull-up resistor and the internal pull-down resistor are both in a suspended state, obtaining a first level signal received by the internal port; when the internal pull-up resistor is in a conducting state, obtaining a second level signal received by the internal port; when the internal pull-down resistor is in a conducting state, obtaining a third level signal received by the internal port; according to the first level signal, the second level signal and the third level signal, different types of hardware are identified. The method can increase the number of hardware types identified by a single IO, thereby releasing IO interface resources.

Description

Technical Field

[0001] Embodiments of the present invention relate to the technical field of hardware identification, and in particular, to a hardware identification method, device, electronic device, and computer-readable storage medium. Background Art

[0002] In the process of terminal equipment development, in order to reduce the workload of software development and maintenance, it is necessary to implement a single set of software to adapt to a variety of different hardware. Usually, the type of hardware is identified by using an analog-to-digital converter (Analog-to-Digital Converter) or an input-output (Input Output) interface, or a combination of the two.

[0003] In the prior art, when ADC is used for identification, the ADC resources of some systems are tight, resulting in the inability to use ADC to identify the hardware type. When IO interface is used for identification, the current single IO interface can only realize the identification of two types of hardware. When some hardware states need to be distinguished, more IO interface resources will be occupied. Summary of the invention

[0004] The present disclosure provides a hardware identification method, device, electronic device and computer-readable storage medium, which can increase the number of hardware types identified by a single IO, thereby releasing IO interface resources.

[0005] In a first aspect, the present disclosure provides a hardware identification method, which is applied to at least one input / output IO interface, wherein an internal port of the IO interface is electrically connected to a high level via an internal pull-up resistor, and the internal port is also grounded via an internal pull-down resistor;

[0006] The method comprises:

[0007] When both the internal pull-up resistor and the internal pull-down resistor are in a suspended state, obtaining a first level signal received by the internal port;

[0008] When the internal pull-up resistor is in an on state, obtaining a second level signal received by the internal port;

[0009] When the internal pull-down resistor is in a conducting state, obtaining a third level signal received by the internal port;

[0010] Different types of hardware are identified according to the first level signal, the second level signal, and the third level signal.

[0011] Optionally, the identifying different types of hardware according to the first level signal, the second level signal, and the third level signal includes:

[0012] If the first level signal, the second level signal and the third level signal are all low level signals, identifying a first type of hardware;

[0013] If the first level signal and the third level signal are both low level signals, and the second level signal is a high level signal, identifying a second type of hardware;

[0014] If the first level signal and the second level signal are both high level signals, and the third level signal is a low level signal, identifying a third type of hardware;

[0015] If the first level signal, the second level signal and the third level signal are all high level signals, a fourth type of hardware is identified.

[0016] Optionally, before acquiring the first level signal received by the internal port, the method further includes:

[0017] Determining a target resistance range of the pull-up resistor and a target resistance range of the pull-down resistor according to the resistance value of the internal pull-up resistor, the resistance value of the internal pull-down resistor, and a level threshold range;

[0018] Determine a target resistance value of the pull-up resistor and a target resistance value of the pull-down resistor from within the target resistance range;

[0019] Based on the target resistance value of the pull-up resistor and / or the target value of the pull-down resistor and the corresponding relationship with the hardware type, a pull-up resistor and / or a pull-down resistor with corresponding resistance value is set for different types of hardware.

[0020] Optionally, determining a target resistance range of the pull-up resistor and a target resistance range of the pull-down resistor according to the resistance of the internal pull-up resistor, the resistance of the internal pull-down resistor, and a level threshold range includes:

[0021] Determining a first target resistance range of the pull-down resistor according to the resistance value of the internal pull-up resistor and the high level threshold range;

[0022] Determining a second target resistance range of the pull-down resistor according to the resistance value of the internal pull-up resistor and the low level threshold range;

[0023] Determining a third target resistance range of the pull-up resistor according to the resistance value of the internal pull-down resistor and the high level threshold range;

[0024] A fourth target resistance range of the pull-up resistor is determined according to the resistance of the internal pull-down resistor and the low level threshold range.

[0025] Optionally, before determining the first target resistance range of the pull-down resistor according to the resistance value of the internal pull-up resistor and the high level threshold range, the method further includes:

[0026] Determining the high level threshold range according to the high level judgment coefficient, system power supply and voltage parameters;

[0027] The low level threshold range is determined according to the low level judgment coefficient, the system power supply and the voltage parameter.

[0028] Optionally, determining the high level threshold range according to the high level judgment coefficient, system power supply and voltage parameters includes:

[0029] Determining a first high level threshold value according to the product of the high level determination coefficient and the system power supply;

[0030] Determining a second high level threshold value according to the sum of the system power supply and the voltage parameter;

[0031] A threshold range that is greater than or equal to the first high level threshold and less than or equal to the second high level threshold is determined as the high level threshold range.

[0032] Optionally, determining the low level threshold range according to the low level judgment coefficient, the system power supply and the voltage parameter includes:

[0033] Determining a first low level threshold value according to the negative value of the voltage parameter;

[0034] Determining a second low level threshold value according to the product of the low level determination coefficient and the system power supply;

[0035] A threshold range that is greater than or equal to the first low level threshold and less than or equal to the second low level threshold is determined as the low level threshold range

[0036] In a second aspect, the present disclosure provides a hardware identification device, which is applied to at least one input / output IO interface, wherein an internal port of the IO interface is electrically connected to a high level via an internal pull-up resistor, and the internal port is also grounded via an internal pull-down resistor;

[0037] The identification device comprises:

[0038] an acquisition module, configured to acquire a first level signal received by the internal port when both the internal pull-up resistor and the internal pull-down resistor are in a suspended state; acquire a second level signal received by the internal port when the internal pull-up resistor is in a conducting state; and acquire a third level signal received by the internal port when the internal pull-down resistor is in a conducting state;

[0039] an identification module, configured to identify different types of hardware according to the first level signal, the second level signal and the third level signal

[0040] In a third aspect, the present disclosure provides an electronic device, including a memory and a processor, wherein the memory stores a computer program, and the processor implements the steps of any one of the methods provided in the first aspect when executing the computer program.

[0041] In a fourth aspect, the present disclosure provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the steps of any one of the methods provided in the first aspect.

[0042] In the technical solution provided by the present disclosure, when both the internal pull-up resistor and the internal pull-down resistor are in a suspended state, a first level signal received by the internal port is obtained; when the internal pull-up resistor is in an on state, a second level signal received by the internal port is obtained; when the internal pull-down resistor is in an on state, a third level signal received by the internal port is obtained; different types of hardware are identified according to the first level signal, the second level signal and the third level signal. Since each level signal may be a high level signal or a low level signal, there are eight possible results for the three level signals, each possibility being a different type of hardware. Therefore, a single IO can identify multiple different types of hardware, which can increase the number of hardware types identified by a single IO, thereby releasing IO interface resources. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

[0044] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0045] Figure 1 A schematic diagram of a structure of an application scenario provided by the present disclosure;

[0046] Figure 2 A flowchart of a hardware identification method provided by the present disclosure;

[0047] Figure 3 A flowchart of another hardware identification method provided by the present disclosure;

[0048] Figure 4 A flowchart of another hardware identification method provided by the present disclosure;

[0049] Figure 5 A flowchart of another hardware identification method provided by the present disclosure;

[0050] Figure 6 A flowchart of another hardware identification method provided by the present disclosure;

[0051] Figure 7 A flowchart of another hardware identification method provided by the present disclosure;

[0052] Figure 8 A flowchart of another hardware identification method provided by the present disclosure;

[0053] Fig. 9 A schematic diagram of the structure of a hardware identification device provided by the present disclosure;

[0054] Fig.10 A schematic diagram of the internal structure of a computer device provided by the present invention. DETAILED DESCRIPTION

[0055] In order to more clearly understand the above-mentioned objectives, features and advantages of the present disclosure, the scheme of the present disclosure will be further described below. It should be noted that the embodiments of the present disclosure and the features in the embodiments can be combined with each other without conflict.

[0056] In the following description, many specific details are set forth to facilitate a full understanding of the present disclosure, but the present disclosure may also be implemented in other ways different from those described herein; it is obvious that the embodiments in the specification are only part of the embodiments of the present disclosure, rather than all of the embodiments.

[0057] Figure 1 A schematic diagram of a structural application scenario provided by the present disclosure, such as Figure 1 As shown, it includes: an IO interface 10, and the IO interface 10 internally includes: an internal port A, an internal pull-up resistor Ru and an internal pull-down resistor Rd.

[0058] The internal port A is electrically connected to the high level Vcc through the internal pull-up resistor Ru, and the internal port A is also grounded through the internal pull-down resistor Rd.

[0059] The software is electrically connected to the hardware through the IO interface. The port connected to the software through the IO interface is the internal port A, and the port electrically connected to the hardware is the external port B. The internal port A is electrically connected to the high level Vcc through the internal pull-up resistor Ru and the first switch K1 in turn, and the internal port A is grounded through the internal pull-down resistor Rd and the second switch K2 in turn. By controlling the on-off state of the first switch K1 and the second switch K2, the state of the internal pull-up resistor Ru and the internal pull-down resistor Rd can be changed. For example, when the first switch K1 is disconnected, the internal pull-up resistor Ru is in a suspended state. When the first switch K1 is turned on, the internal port A and the high level Vcc are turned on, and the internal pull-up resistor Ru is in a turned-on state; when the second switch K2 is disconnected, the internal pull-down resistor Rd is in a suspended state. When the second switch K2 is turned on, the internal port A and the ground are turned on, and the internal pull-down resistor Rd is in a turned-on state.

[0060] The peripheral circuit of the hardware is provided with a pull-up resistor R1 and / or a pull-down resistor R2. After the hardware is electrically connected to the IO interface, Figure 1 As shown, the external port B is electrically connected to the high level Vcc through the pull-up resistor R1, and / or the external port B is grounded through the pull-down resistor R2.

[0061] It should be noted that Figure 1 It is only exemplarily shown that the peripheral circuit of the hardware is provided with a pull-up resistor R1 and a pull-down resistor R2. In other implementations, the pull-up resistor R1 or the pull-down resistor R2 may be provided.

[0062] It should also be noted that Figure 1 Only one IO interface is exemplarily shown as an application scenario. In other application scenarios, multiple IO interfaces may be included. The structure of each IO interface is similar to that of Figure 1 The structures shown are the same.

[0063] Figure 2 A flowchart of a hardware identification method provided by the present disclosure is shown in FIG. Figure 2 The embodiment shown is applied to Figure 1 In the IO interface shown, Figure 2 As shown, the specific steps of the method include:

[0064] S101, when both the internal pull-up resistor and the internal pull-down resistor are in a suspended state, obtaining a first level signal received by the internal port.

[0065] For example, Figure 1 As shown, the first switch K1 and the second switch K2 are controlled to be disconnected, so that the internal pull-up resistor Ru is disconnected from the high level Vcc, and the internal pull-down resistor Rd is disconnected from the ground, that is, the internal pull-up resistor Ru and the internal pull-down resistor Rd are both in a suspended state.

[0066] When both the internal pull-up resistor Ru and the internal pull-down resistor Rd are in a suspended state, if the peripheral circuit of the hardware is only provided with the pull-up resistor R1, since the pull-up resistor R1 is conductive with the high level Vcc, the voltage at the internal port A is pulled up to a high level, that is, the first level signal received by the internal port A is a high level signal. If the peripheral circuit of the hardware is only provided with the pull-down resistor R2, since the pull-down resistor R2 is grounded, the voltage at the internal port A is pulled down to a low level, that is, the first level signal received by the internal port A is a low level signal.

[0067] S103, when the internal pull-up resistor is in an on state, obtaining a second level signal received by the internal port.

[0068] For example, Figure 1 As shown, the first switch K1 is turned on and the second switch K2 is turned off, so that the internal pull-up resistor Ru is connected to the high level Vcc, and the internal pull-down resistor Rd is disconnected from the ground, that is, the internal pull-up resistor Ru is in a conducting state, and the internal pull-down resistor Rd is in a suspended state.

[0069] When the internal pull-up resistor Ru is in the on state, and the internal pull-down resistor Rd is in the suspended state, if the peripheral circuit of the hardware is only provided with the pull-up resistor R1, at this time, the pull-up resistor R1 and the internal pull-up resistor Ru are both connected to the high level Vcc, and the voltage at the internal port A is pulled up to a high level, that is, the second level signal received by the internal port A is a high level signal. If the peripheral circuit of the hardware is only provided with the pull-down resistor R2, at this time, the high level signal is released to the ground through the internal pull-up resistor Ru and the pull-down resistor R2 in sequence, and the voltage at the internal port A depends on the resistance value of the pull-down resistor R2 and the resistance value of the internal pull-up resistor Ru, that is, the second level signal received by the internal port A may be a low level signal or a high level signal.

[0070] S105 , when the internal pull-down resistor is in the on state, obtaining a third level signal received by the internal port.

[0071] For example, Figure 1 As shown, the first switch K1 is controlled to be disconnected and the second switch K2 is turned on, so that the internal pull-up resistor Ru is disconnected from the high level Vcc, and the internal pull-down resistor Rd is connected to the ground, that is, the internal pull-up resistor Ru is in a suspended state, and the internal pull-down resistor Rd is in a turned-on state.

[0072] When the internal pull-up resistor Ru is in a suspended state and the internal pull-down resistor Rd is in a conducting state, if the peripheral circuit of the hardware is only provided with the pull-up resistor R1, at this time, the high-level signal is released to the ground through the pull-up resistor R1 and the internal pull-down resistor Rd in sequence, and the voltage at the internal port A depends on the resistance value of the pull-up resistor R1 and the resistance value of the internal pull-down resistor Rd, that is, the third-level signal received by the internal port A may be a low-level signal or a high-level signal. If the peripheral circuit of the hardware is only provided with the pull-down resistor R2, at this time, the pull-down resistor R2 and the internal pull-down resistor Rd are both grounded, and the voltage at the internal port A is pulled to a low level, that is, the third-level signal received by the internal port A is a low-level signal.

[0073] S107 , identifying different types of hardware according to the first level signal, the second level signal, and the third level signal.

[0074] Based on the above analysis, the first level signal, the second level signal and the third level signal can all be low level signals or high level signals, so there are eight possible results composed of the first level signal, the second level signal and the third level signal. Based on a single IO, eight different results can be identified, and each result corresponds to a type of hardware. Obviously, a single IO can identify multiple different types of hardware.

[0075] In this embodiment, when both the internal pull-up resistor and the internal pull-down resistor are in a suspended state, a first level signal received by the internal port is obtained; when the internal pull-up resistor is in an on state, a second level signal received by the internal port is obtained; when the internal pull-down resistor is in an on state, a third level signal received by the internal port is obtained; different types of hardware are identified according to the first level signal, the second level signal and the third level signal. Since each level signal may be a high level signal or a low level signal, the three level signals have eight possible results, each possibility being a different type of hardware. Therefore, a single IO can identify multiple different types of hardware, which can increase the number of hardware types identified by a single IO, thereby releasing IO interface resources.

[0076] Figure 3 A flowchart of another hardware identification method provided by the present disclosure is shown below. Figure 3 for Figure 2 Based on the illustrated embodiment, a possible implementation method for executing S107 is specifically described as follows:

[0077] S1071: If the first level signal, the second level signal, and the third level signal are all low level signals, identify first type hardware.

[0078] If the first level signal is a low level signal, it is determined that a pull-down resistor is provided in the peripheral circuit of the hardware, or a pull-down resistor and a pull-up resistor are provided. If the third level signal is a low level signal, it is determined that a pull-down circuit is provided in the peripheral circuit. If the second level signal is a low level signal, it is determined that the resistance value of the pull-down resistor meets the condition of the low level signal. Based on this, it can be determined that a pull-down resistor that meets the condition of the low level signal is provided in the peripheral circuit of this type of hardware, and this type of hardware is regarded as the first type of hardware, so the first type of hardware can be identified.

[0079] S1072: If the first level signal and the third level signal are both low level signals, and the second level signal is a high level signal, identify second type hardware.

[0080] If the first level signal is a low level signal, it is determined that a pull-down resistor is provided in the peripheral circuit of the hardware, or a pull-down resistor and a pull-up resistor are provided. If the third level signal is a low level signal, it is determined that a pull-down resistor is provided in the peripheral circuit. If the second level signal is a high level signal, it is determined that the resistance value of the pull-down resistor meets the condition of the high level signal. Based on this, it can be determined that a pull-down resistor that meets the condition of the high level signal is provided in the peripheral circuit of this type of hardware, and this type of hardware is regarded as the second type of hardware, so the second type of hardware can be identified.

[0081] S1073: If the first level signal and the second level signal are both high level signals, and the third level signal is a low level signal, identify third type hardware.

[0082] If the first level signal is a high level signal, it is determined that a pull-up resistor is provided in the peripheral circuit of the hardware, or a pull-down resistor and a pull-up resistor are provided. If the second level signal is a high level signal, it is determined that a pull-up resistor is provided in the peripheral circuit. If the third level signal is a low level signal, it is determined that the resistance value of the pull-up resistor meets the condition of the low level signal. Based on this, it can be determined that a pull-up resistor that meets the condition of the low level signal is provided in the peripheral circuit of this type of hardware, and this type of hardware is regarded as the third type of hardware, so the third type of hardware can be identified.

[0083] S1074: If the first level signal, the second level signal, and the third level signal are all high level signals, identify fourth type hardware.

[0084] If the first level signal is a high level signal, it is determined that a pull-up resistor is provided in the peripheral circuit of the hardware, or a pull-down resistor and a pull-up resistor are provided. If the second level signal is a high level signal, it is determined that a pull-up resistor is provided in the peripheral circuit. If the third level signal is a high level signal, it is determined that the resistance value of the pull-up resistor meets the condition of the high level signal. Based on this, it can be determined that a pull-up resistor that meets the high level signal condition is provided in the peripheral circuit of this type of hardware, and this type of hardware is regarded as the fourth type of hardware, so the fourth type of hardware can be identified.

[0085] This embodiment only exemplifies four types of hardware with pull-up resistors or pull-down resistors identified by three level signals. In other implementations, multiple types of hardware with pull-up resistors and pull-down resistors may also be identified by three level signals.

[0086] In this embodiment, by identifying the first type of hardware if the first level signal, the second level signal and the third level signal are all low level signals; identifying the second type of hardware if the first level signal and the third level signal are all low level signals and the second level signal is a high level signal; identifying the third type of hardware if the first level signal and the second level signal are both high level signals and the third level signal is a low level signal; identifying the fourth type of hardware if the first level signal, the second level signal and the third level signal are all high level signals, at least four different types of hardware can be identified based on the three level signals.

[0087] Figure 4 A flowchart of another hardware identification method provided by the present disclosure is shown below. Figure 4 for Figure 2 Based on the embodiment shown, before executing S101, the following step is also included:

[0088] S201, determining a target resistance range of the pull-up resistor and a target resistance range of the pull-down resistor according to the resistance value of the internal pull-up resistor, the resistance value of the internal pull-down resistor, and a level threshold range.

[0089] As a specific description of a possible implementation of S201, Figure 5 As shown:

[0090] S2011, determining a first target resistance range of the pull-down resistor according to the resistance of the internal pull-up resistor and a high level threshold range.

[0091] Based on the above embodiment, the internal pull-up resistor is in the on state. If the peripheral circuit of the hardware is only provided with the pull-down resistor R2, the voltage Ua at the internal port A is Vcc*R2(Ru+R2). Exemplarily, the high level threshold range is [VH1, VH2], and the first target resistance range is determined according to the following formula:

[0092] VH1≤Vcc*R2(Ru+R2)≤VH2

[0093] By solving the above inequality, the first target resistance range can be obtained.

[0094] S2012: Determine a second target resistance range of the pull-down resistor according to the resistance of the internal pull-up resistor and the low level threshold range.

[0095] Based on the above embodiment, illustratively, the low level threshold range is [VL1, VL2], and the second target resistance range is determined according to the following formula:

[0096] VL1≤Vcc*R2(Ru+R2)≤VL2

[0097] By solving the above inequality, the second target resistance range can be obtained.

[0098] S2013: Determine a third target resistance range of the pull-up resistor according to the resistance of the internal pull-down resistor and the high level threshold range.

[0099] Based on the above embodiment, the internal pull-down resistors are all in the on state. If the peripheral circuit of the hardware is only provided with the pull-up resistor R1, the voltage Ua at the internal port A=Vcc*R1(Rd+R1).

[0100] Exemplarily, the high level threshold range is [VH1, VH2], and the third target resistance range is determined according to the following formula:

[0101] VH1≤Vcc*R1(Rd+R1)≤VH2

[0102] By solving the above inequality, the third target resistance range can be obtained.

[0103] S2014: Determine a fourth target resistance range of the pull-up resistor according to the resistance of the internal pull-down resistor and the low level threshold range.

[0104] Based on the above embodiment, exemplarily, the low level threshold range is [VL1, VL2], and the fourth target resistance range is determined according to the following formula:

[0105] VL1≤Vcc*R1(Rd+R1)≤VL2

[0106] By solving the above inequality, the fourth target resistance range can be obtained.

[0107] A specific embodiment is given below:

[0108] Assume that in the IO interface, the internal pull-up resistor Ru=20K, the internal pull-down resistor Rd=20K, the high level threshold range is [1.26V, 2.1V], the low level threshold range is [-0.3V, 0.54V], and the system power supply Vcc=1.8V. Based on 1.26V≤1.8*R2(R2+20)≤2.1V, the first target resistance range R2≥46.7K is determined; based on -0.3V≤1.8*R2(R2+20)≤0.54V, the second target resistance range R2≤8.57K is determined; based on 1.26V≤1.8*R1(R1+20)≤2.1V, the third target resistance range R1≥46.7K is determined; based on -0.3V≤1.8*R1(R1+20)≤0.54V, the fourth target resistance range R2≤8.57K is determined.

[0109] S203, determining a target resistance value of the pull-up resistor and a target resistance value of the pull-down resistor within the target resistance range.

[0110] Exemplarily, based on the above embodiment, within the first target resistance range R2≥46.7K, a resistance is arbitrarily determined as the target resistance of the pull-down resistor, for example, the target resistance of the pull-down resistor is 46.7K; within the second target resistance range R2≤8.57K, a resistance is arbitrarily determined as another target resistance of the pull-down resistor, for example, another target resistance of the pull-down resistor is 8.57K. Within the third target resistance range R1≥46.7K, a resistance is arbitrarily determined as the target resistance of the pull-up resistor, for example, the target resistance of the pull-up resistor is 46.7K; within the fourth target resistance range R2≤8.57K, a resistance is arbitrarily determined as another target resistance of the pull-up resistor, for example, another target resistance of the pull-up resistor is 8.57K.

[0111] S205 , based on the target resistance value of the pull-up resistor and / or the target value of the pull-down resistor and the corresponding relationship with the hardware type, set a pull-up resistor and / or a pull-down resistor with corresponding resistance value for different types of hardware.

[0112] Exemplarily, based on the above embodiment, a corresponding relationship is established between a pull-down resistor with a resistance value of 8.57K and the first type of hardware, a corresponding relationship between a pull-down resistor with a resistance value of 46.7K and the second type of hardware, a corresponding relationship between a pull-up resistor with a resistance value of 8.57K and the third type of hardware, and a corresponding relationship between a pull-up resistor with a resistance value of 46.7K and the fourth type of hardware. Based on the above corresponding relationships, a pull-down resistor with a resistance value of 8.57K is set in the peripheral circuit of the first type of hardware, a pull-down resistor with a resistance value of 46.7K is set in the peripheral circuit of the second type of hardware, a pull-up resistor with a resistance value of 8.57K is set in the peripheral circuit of the third type of hardware, and a pull-up resistor with a resistance value of 46.7K is set in the peripheral circuit of the fourth type of hardware.

[0113] In this embodiment, a target resistance range of the pull-up resistor and a target resistance range of the pull-down resistor are determined according to the resistance value of the internal pull-up resistor, the resistance value of the internal pull-down resistor, and the level threshold range; the target resistance value of the pull-up resistor and the target resistance value of the pull-down resistor are determined from within the target resistance range; based on the target resistance value of the pull-up resistor and / or the target value of the pull-down resistor, and the corresponding relationship with the hardware type, pull-up resistors and / or pull-down resistors of corresponding resistance values ​​are set for different types of hardware, and pull-up resistors and / or pull-down resistors with different resistance values ​​can be set for different types of hardware, ensuring that different types of hardware can be recognized by a single IO interface.

[0114] Figure 6 A flowchart of another hardware identification method provided by the present disclosure is shown below. Figure 6 for Figure 5 Based on the embodiment shown, before executing S2011, the method further includes:

[0115] S301, determining the high level threshold range according to the high level judgment coefficient, system power supply and voltage parameters.

[0116] As a specific description of a possible implementation method when executing S301, Figure 7 As shown:

[0117] S3011, determining a first high level threshold value according to the product of the high level judgment coefficient and the system power supply.

[0118] Exemplarily, according to the high level determination coefficient m and the system power supply Vcc, the first high level threshold VH1 is determined based on the following formula:

[0119] VH1=m*Vcc

[0120] For example, the system power supply Vcc=1.8V, the high level determination coefficient m=0.7, and the first high level threshold VH1=1.26V is determined according to the above formula.

[0121] S3012: Determine a second high level threshold according to the sum of the system power supply and the voltage parameter.

[0122] Exemplarily, the second high level threshold VH2 is determined based on the following formula according to the system power supply Vcc and the voltage parameter ΔV:

[0123] VH1=Vcc+ΔV

[0124] For example, based on the above embodiment, the voltage parameter ΔV=0.3V, and the second high level threshold VH2=2.1V is determined according to the above formula.

[0125] S3013: Determine a threshold range that is greater than or equal to the first high level threshold and less than or equal to the second high level threshold as the high level threshold range.

[0126] Exemplarily, based on the above embodiment, the high level threshold range may be [1.26V, 2.1V].

[0127] S303: Determine the low level threshold range according to the low level judgment coefficient, the system power supply and the voltage parameter.

[0128] As a specific description of a possible implementation method when executing S303, Figure 8 As shown:

[0129] S3031: Determine a first low level threshold according to the negative value of the voltage parameter.

[0130] Exemplarily, the negative value -ΔV of the voltage parameter is determined as the first low level threshold VL1. For example, the voltage parameter ΔV=0.3V, and the first high level threshold VL1=-0.3V.

[0131] S3032: Determine a second low level threshold value according to the product of the low level judgment coefficient and the system power supply.

[0132] Exemplarily, according to the low level judgment coefficient n and the system power supply Vcc, the second low level threshold VL2 is determined based on the following formula:

[0133] VL2=n*Vcc

[0134] For example, the system power supply Vcc=1.8V, the low level judgment coefficient n=0.3, and the second low level threshold VL2=0.54V is determined according to the above formula.

[0135] S3033: Determine a threshold range that is greater than or equal to the first low level threshold and less than or equal to the second low level threshold as the low level threshold range.

[0136] Exemplarily, based on the above embodiment, the low level threshold range may be [-0.3V, 0.54V].

[0137] The present disclosure also provides a hardware identification device, Fig. 9 A schematic diagram of the structure of a hardware identification device provided by the present disclosure is shown in FIG. Fig. 9 The embodiment shown is applied to Figure 1 In the IO interface shown, Fig. 9 As shown, the hardware identification device 100 includes:

[0138] The acquisition module 110 is used to acquire the first level signal received by the internal port when the internal pull-up resistor and the internal pull-down resistor are both in a suspended state; to acquire the second level signal received by the internal port when the internal pull-up resistor is in an on state; and to acquire the third level signal received by the internal port when the internal pull-down resistor is in an on state.

[0139] The identification module 120 is configured to identify different types of hardware according to the first level signal, the second level signal and the third level signal.

[0140] Optionally, the identification module 120 is further used to identify the first type of hardware if the first level signal, the second level signal and the third level signal are all low level signals; identify the second type of hardware if the first level signal and the third level signal are all low level signals and the second level signal is a high level signal; identify the third type of hardware if the first level signal and the second level signal are both high level signals and the third level signal is a low level signal; and identify the fourth type of hardware if the first level signal, the second level signal and the third level signal are all high level signals.

[0141] Optionally, the hardware identification device 100 further includes:

[0142] A determination module is used to determine a target resistance range of the pull-up resistor and a target resistance range of the pull-down resistor according to the resistance of the internal pull-up resistor, the resistance of the internal pull-down resistor and a level threshold range; and determine a target resistance value of the pull-up resistor and a target resistance value of the pull-down resistor from within the target resistance range.

[0143] The setting module is used to set pull-up resistors and / or pull-down resistors with corresponding resistance values ​​for different types of hardware based on the corresponding relationship between the target resistance value of the pull-up resistor and / or the target value of the pull-down resistor and the hardware type.

[0144] Optionally, the determination module is further used to determine a first target resistance range of the pull-down resistor based on the resistance of the internal pull-up resistor and a high-level threshold range; determine a second target resistance range of the pull-down resistor based on the resistance of the internal pull-up resistor and a low-level threshold range; determine a third target resistance range of the pull-up resistor based on the resistance of the internal pull-down resistor and the high-level threshold range; and determine a fourth target resistance range of the pull-up resistor based on the resistance of the internal pull-down resistor and the low-level threshold range.

[0145] Optionally, the determination module is also used to determine the high level threshold range based on the high level judgment coefficient, the system power supply and the voltage parameters; and to determine the low level threshold range based on the low level judgment coefficient, the system power supply and the voltage parameters.

[0146] Optionally, the determination module is further used to determine a first high level threshold based on the product of the high level judgment coefficient and the system power supply; determine a second high level threshold based on the sum of the system power supply and the voltage parameter; and determine a threshold range that is greater than or equal to the first high level threshold and less than or equal to the second high level threshold as the high level threshold range.

[0147] Optionally, the determination module is further used to determine a first low-level threshold based on the negative value of the voltage parameter; determine a second low-level threshold based on the product of the low-level judgment coefficient and the system power supply; and determine a threshold range that is greater than or equal to the first low-level threshold and less than or equal to the second low-level threshold as the low-level threshold range.

[0148] The hardware identification device provided in this embodiment is used to execute the steps of any of the above method embodiments, and has the technical solutions and technical effects of the method embodiments, which will not be described in detail here.

[0149] The embodiment of the present invention further provides a computer device, which may be a terminal, and its internal structure diagram may be as shown in FIG. Fig.10 As shown. The computer device includes a processor, a memory, a communication interface, a display screen and an input device connected through a system bus. Among them, the processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The communication interface of the computer device is used to communicate with an external terminal in a wired or wireless manner, and the wireless manner can be achieved through WIFI, an operator network, near field communication (NFC) or other technologies. When the computer program is executed by the processor, a switching method for a customized application is implemented. The display screen of the computer device can be a liquid crystal display screen or an electronic ink display screen, and the input device of the computer device can be a touch layer covered on the display screen, or a button, a trackball or a touch pad set on the computer device housing, or an external keyboard, touch pad or mouse, etc.

[0150] Those skilled in the art will understand that Fig.10The structure shown in the figure is only a block diagram of a part of the structure related to the solution of the present application, and does not constitute a limitation on the computer device to which the solution of the present application is applied. The specific computer device may include more or fewer components than those shown in the figure, or combine certain components, or have a different arrangement of components.

[0151] In one embodiment, the hardware identification device provided by the present application can be implemented in the form of a computer program. The computer program can be Fig.10 The memory of the computer device may store various program modules constituting the switching device, for example, Fig. 9 The acquisition module 110 and the identification module 120 are shown. The computer program composed of various program modules enables the processor to execute the steps in the above-mentioned method embodiments.

[0152] For example, Fig.10 The computer device shown can be Fig. 9 The acquisition module 110 in the hardware identification device shown executes steps S101, S103 and S105. The computer device can execute step S107 through the identification module 120.

[0153] An embodiment of the present invention further provides an electronic device, including a memory and a processor, wherein the memory stores a computer program, and when the processor executes the computer program, the following steps are implemented:

[0154] S101, when both the internal pull-up resistor and the internal pull-down resistor are in a suspended state, obtaining a first level signal received by the internal port.

[0155] S103, when the internal pull-up resistor is in an on state, obtaining a second level signal received by the internal port.

[0156] S105 , when the internal pull-down resistor is in the on state, obtaining a third level signal received by the internal port.

[0157] S107 , identifying different types of hardware according to the first level signal, the second level signal, and the third level signal.

[0158] In one embodiment, when the processor executes the computer program, the following steps are also implemented:

[0159] S1071: If the first level signal, the second level signal, and the third level signal are all low level signals, identify first type hardware.

[0160] S1072: If the first level signal and the third level signal are both low level signals, and the second level signal is a high level signal, identify second type hardware.

[0161] S1073: If the first level signal and the second level signal are both high level signals, and the third level signal is a low level signal, identify third type hardware.

[0162] S1074: If the first level signal, the second level signal, and the third level signal are all high level signals, identify fourth type hardware.

[0163] In one embodiment, when the processor executes the computer program, the following steps are also implemented:

[0164] S201, determining a target resistance range of the pull-up resistor and a target resistance range of the pull-down resistor according to the resistance value of the internal pull-up resistor, the resistance value of the internal pull-down resistor, and a level threshold range.

[0165] S203, determining a target resistance value of the pull-up resistor and a target resistance value of the pull-down resistor within the target resistance range.

[0166] S205 , based on the target resistance value of the pull-up resistor and / or the target value of the pull-down resistor and the corresponding relationship with the hardware type, set a pull-up resistor and / or a pull-down resistor with corresponding resistance value for different types of hardware.

[0167] In one embodiment, when the processor executes the computer program, the following steps are also implemented:

[0168] S2011, determining a first target resistance range of the pull-down resistor according to the resistance of the internal pull-up resistor and a high level threshold range.

[0169] S2012: Determine a second target resistance range of the pull-down resistor according to the resistance of the internal pull-up resistor and the low level threshold range.

[0170] S2013: Determine a third target resistance range of the pull-up resistor according to the resistance of the internal pull-down resistor and the high level threshold range.

[0171] S2014: Determine a fourth target resistance range of the pull-up resistor according to the resistance of the internal pull-down resistor and the low level threshold range.

[0172] In one embodiment, when the processor executes the computer program, the following steps are also implemented:

[0173] S301, determining the high level threshold range according to the high level judgment coefficient, system power supply and voltage parameters.

[0174] S303: Determine the low level threshold range according to the low level judgment coefficient, the system power supply and the voltage parameter.

[0175] In one embodiment, when the processor executes the computer program, the following steps are also implemented:

[0176] S3011, determining a first high level threshold value according to the product of the high level judgment coefficient and the system power supply.

[0177] S3012: Determine a second high level threshold according to the sum of the system power supply and the voltage parameter.

[0178] S3013: Determine a threshold range that is greater than or equal to the first high level threshold and less than or equal to the second high level threshold as the high level threshold range.

[0179] In one embodiment, when the processor executes the computer program, the following steps are also implemented:

[0180] S3031: Determine a first low level threshold according to the negative value of the voltage parameter.

[0181] S3032: Determine a second low level threshold value according to the product of the low level judgment coefficient and the system power supply.

[0182] S3033: Determine a threshold range that is greater than or equal to the first low level threshold and less than or equal to the second low level threshold as the low level threshold range.

[0183] In the technical solution provided by the present embodiment, when both the internal pull-up resistor and the internal pull-down resistor are in a suspended state, a first level signal received by the internal port is obtained; when the internal pull-up resistor is in an on state, a second level signal received by the internal port is obtained; when the internal pull-down resistor is in an on state, a third level signal received by the internal port is obtained; different types of hardware are identified according to the first level signal, the second level signal and the third level signal. Since each level signal may be a high level signal or a low level signal, the three level signals have eight possible results, each possibility being a different type of hardware. Therefore, a single IO can identify multiple different types of hardware, which can increase the number of hardware types identified by a single IO, thereby releasing IO interface resources.

[0184] The embodiment of the present invention further provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the following steps are implemented:

[0185] S101, when both the internal pull-up resistor and the internal pull-down resistor are in a suspended state, obtaining a first level signal received by the internal port.

[0186] S103, when the internal pull-up resistor is in an on state, obtaining a second level signal received by the internal port.

[0187] S105 , when the internal pull-down resistor is in the on state, obtaining a third level signal received by the internal port.

[0188] S107 , identifying different types of hardware according to the first level signal, the second level signal, and the third level signal.

[0189] In one embodiment, when the processor executes the computer program, the following steps are also implemented:

[0190] S1071: If the first level signal, the second level signal, and the third level signal are all low level signals, identify first type hardware.

[0191] S1072: If the first level signal and the third level signal are both low level signals, and the second level signal is a high level signal, identify second type hardware.

[0192] S1073: If the first level signal and the second level signal are both high level signals, and the third level signal is a low level signal, identify third type hardware.

[0193] S1074: If the first level signal, the second level signal, and the third level signal are all high level signals, identify fourth type hardware.

[0194] In one embodiment, when the processor executes the computer program, the following steps are also implemented:

[0195] S201, determining a target resistance range of the pull-up resistor and a target resistance range of the pull-down resistor according to the resistance value of the internal pull-up resistor, the resistance value of the internal pull-down resistor, and a level threshold range.

[0196] S203, determining a target resistance value of the pull-up resistor and a target resistance value of the pull-down resistor within the target resistance range.

[0197] S205 , based on the target resistance value of the pull-up resistor and / or the target value of the pull-down resistor and the corresponding relationship with the hardware type, set a pull-up resistor and / or a pull-down resistor with corresponding resistance value for different types of hardware.

[0198] In one embodiment, when the processor executes the computer program, the following steps are also implemented:

[0199] S2011, determining a first target resistance range of the pull-down resistor according to the resistance of the internal pull-up resistor and a high level threshold range.

[0200] S2012: Determine a second target resistance range of the pull-down resistor according to the resistance of the internal pull-up resistor and the low level threshold range.

[0201] S2013: Determine a third target resistance range of the pull-up resistor according to the resistance of the internal pull-down resistor and the high level threshold range.

[0202] S2014: Determine a fourth target resistance range of the pull-up resistor according to the resistance of the internal pull-down resistor and the low level threshold range.

[0203] In one embodiment, when the processor executes the computer program, the following steps are also implemented:

[0204] S301, determining the high level threshold range according to the high level judgment coefficient, system power supply and voltage parameters.

[0205] S303: Determine the low level threshold range according to the low level judgment coefficient, the system power supply and the voltage parameter.

[0206] In one embodiment, when the processor executes the computer program, the following steps are also implemented:

[0207] S3011, determining a first high level threshold value according to the product of the high level judgment coefficient and the system power supply.

[0208] S3012: Determine a second high level threshold according to the sum of the system power supply and the voltage parameter.

[0209] S3013: Determine a threshold range that is greater than or equal to the first high level threshold and less than or equal to the second high level threshold as the high level threshold range.

[0210] In one embodiment, when the processor executes the computer program, the following steps are also implemented:

[0211] S3031: Determine a first low level threshold according to the negative value of the voltage parameter.

[0212] S3032: Determine a second low level threshold value according to the product of the low level judgment coefficient and the system power supply.

[0213] S3033: Determine a threshold range that is greater than or equal to the first low level threshold and less than or equal to the second low level threshold as the low level threshold range.

[0214] In the technical solution provided by the embodiment of the present invention, when both the internal pull-up resistor and the internal pull-down resistor are in a suspended state, a first level signal received by the internal port is obtained; when the internal pull-up resistor is in an on state, a second level signal received by the internal port is obtained; when the internal pull-down resistor is in an on state, a third level signal received by the internal port is obtained; different types of hardware are identified according to the first level signal, the second level signal and the third level signal. Since each level signal may be a high level signal or a low level signal, the three level signals have eight possible results, each possibility being a different type of hardware. Therefore, a single IO can identify multiple different types of hardware, and the number of hardware types identified by a single IO can be increased, thereby releasing IO interface resources.

[0215] Those of ordinary skill in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to the memory, database or other medium used in the embodiments provided in the present application may include at least one of non-volatile and volatile memory. Non-volatile memory may include read-only memory (ROM), magnetic tape, floppy disk, flash memory or optical memory, etc. Volatile memory may include random access memory (RAM) or external cache memory. As an illustration and not limitation, RAM is available in many forms, such as static random access memory (SRAM) and dynamic random access memory (DRAM).

[0216] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0217] The above-mentioned embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the attached claims.

[0218] It should be noted that, in this article, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0219] The above description is only a specific embodiment of the present disclosure, so that those skilled in the art can understand or implement the present disclosure. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present disclosure. Therefore, the present disclosure will not be limited to the embodiments described herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A hardware identification method, characterized in that: Applied to at least one input / output IO interface, the internal port of the IO interface is electrically connected to a high level through an internal pull-up resistor, and the internal port is also grounded through an internal pull-down resistor; The method comprises: Determine the high level threshold range according to the high level judgment coefficient, system power supply and voltage parameters; Determining a low level threshold range according to a low level judgment coefficient, the system power supply and the voltage parameter; Determine a first target resistance range of the pull-down resistor according to the resistance value of the internal pull-up resistor and the high level threshold range; Determining a second target resistance range of the pull-down resistor according to the resistance value of the internal pull-up resistor and the low level threshold range; Determining a third target resistance range of the pull-up resistor according to the resistance value of the internal pull-down resistor and the high level threshold range; Determining a fourth target resistance range of the pull-up resistor according to the resistance value of the internal pull-down resistor and the low level threshold range; Determine a target resistance value of the pull-up resistor and a target resistance value of the pull-down resistor from within the target resistance range; Based on the target resistance value of the pull-up resistor and / or the target value of the pull-down resistor and the corresponding relationship with the hardware type, setting the pull-up resistor and / or the pull-down resistor of corresponding resistance value for different types of hardware; When both the internal pull-up resistor and the internal pull-down resistor are in a suspended state, obtaining a first level signal received by the internal port; When the internal pull-up resistor is in an on state, obtaining a second level signal received by the internal port; When the internal pull-down resistor is in a conducting state, obtaining a third level signal received by the internal port; Different types of hardware are identified according to the first level signal, the second level signal, and the third level signal.

2. The method according to claim 1, characterized in that: The identifying different types of hardware according to the first level signal, the second level signal, and the third level signal comprises: If the first level signal, the second level signal and the third level signal are all low level signals, identifying a first type of hardware; If the first level signal and the third level signal are both low level signals, and the second level signal is a high level signal, identifying a second type of hardware; If the first level signal and the second level signal are both high level signals, and the third level signal is a low level signal, identifying a third type of hardware; If the first level signal, the second level signal and the third level signal are all high level signals, a fourth type of hardware is identified.

3. The method according to claim 1, characterized in that Determining the high level threshold range according to the high level judgment coefficient, system power supply and voltage parameters includes: Determining a first high level threshold value according to the product of the high level determination coefficient and the system power supply; Determining a second high level threshold value according to the sum of the system power supply and the voltage parameter; A threshold range that is greater than or equal to the first high level threshold and less than or equal to the second high level threshold is determined as the high level threshold range.

4. The method according to claim 1, characterized in that: Determining the low level threshold range according to the low level judgment coefficient, the system power supply and the voltage parameter comprises: Determining a first low level threshold value according to the negative value of the voltage parameter; Determining a second low level threshold value according to the product of the low level determination coefficient and the system power supply; A threshold range that is greater than or equal to the first low level threshold and less than or equal to the second low level threshold is determined as the low level threshold range.

5. A hardware identification device, characterized in that: Applied to at least one input / output IO interface, the internal port of the IO interface is electrically connected to a high level through an internal pull-up resistor, and the internal port is also grounded through an internal pull-down resistor; The identification device comprises: A determination module, used to determine a high level threshold range according to a high level judgment coefficient, a system power supply and a voltage parameter; determine a low level threshold range according to a low level judgment coefficient, the system power supply and the voltage parameter; determine a first target resistance range of a pull-down resistor according to the resistance value of an internal pull-up resistor and a high level threshold range; determine a second target resistance range of the pull-down resistor according to the resistance value of the internal pull-up resistor and the low level threshold range; determine a third target resistance range of the pull-up resistor according to the resistance value of the internal pull-down resistor and the high level threshold range; determine a fourth target resistance range of the pull-up resistor according to the resistance value of the internal pull-down resistor and the low level threshold range; and determine a target resistance value of the pull-up resistor and a target resistance value of the pull-down resistor from within the target resistance range; A setting module, configured to set a pull-up resistor and / or a pull-down resistor of corresponding resistance value for different types of hardware based on a corresponding relationship between a target resistance value of the pull-up resistor and / or a target value of the pull-down resistor and a hardware type; an acquisition module, configured to acquire a first level signal received by the internal port when both the internal pull-up resistor and the internal pull-down resistor are in a suspended state; acquire a second level signal received by the internal port when the internal pull-up resistor is in a conducting state; and acquire a third level signal received by the internal port when the internal pull-down resistor is in a conducting state; The identification module is used to identify different types of hardware according to the first level signal, the second level signal and the third level signal.

6. An electronic device comprising a memory and a processor, wherein the memory stores a computer program, wherein: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 4 are implemented.

7. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 4 are implemented.

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