Pixels of organic light-emitting display devices

Abstract

The present invention relates to a pixel of an organic light-emitting display device. The pixel of the organic light-emitting display device includes: a storage capacitor connected between a first node and a second node; a first switching transistor connecting a data line to the first node in response to a scan signal; a drive transistor generating a drive current based on a voltage at the first node; a second switching transistor connecting an initialization line to the second node in response to an initialization signal; and an organic light-emitting diode (OLED) emitting light based on the drive current. The pixel performs a first reset operation and a second reset operation. The first reset operation resets the first node to a first initialization voltage of the initialization line during a first interval of a previous horizontal time, and the second reset operation resets the first node to a second initialization voltage different from the first initialization voltage during a second interval of the previous horizontal time.

Description

Technical Field

[0001] The present invention relates to a display device, and in particular to a pixel of an organic light-emitting display device and the organic light-emitting display device. Background Art

[0002] Each pixel of the organic light-emitting display device stores the data voltage in the storage capacitor during the gate-on time (or scan-on time) or 1 horizontal (1H) time. However, as the resolution, driving frequency, etc. of the display panel increase, the gate-on time (i.e., 1 horizontal time) may decrease. For example, the 1 horizontal time of a display panel with a resolution of about 8K and a driving frequency of about 120Hz can be reduced to half of the 1 horizontal time of about 3.7μs of a display panel with a resolution of about 8K and a driving frequency of about 60Hz, i.e., about 1.85μs. When the gate-on time (i.e., 1 horizontal time) is reduced, the charging rate of the storage capacitor may not be sufficient to store the data voltage. In this case, the data voltage with the desired voltage level cannot be stored in the storage capacitor, and the pixel cannot emit light with the desired brightness. Summary of the Invention

[0003] An object of the present invention is to provide a pixel of an organic light emitting display device capable of improving the charging rate of the pixel.

[0004] Another object of the present invention is to provide an organic light emitting display device capable of improving the charging rate of pixels.

[0005] However, the technical problems to be solved by the present invention are not limited to the above-mentioned technical problems, and the present invention can be expanded in many ways without departing from the idea and concept of the present invention.

[0006] To achieve an objective of the present invention, a pixel of an organic light-emitting display device according to an embodiment of the present invention includes: a storage capacitor connected between a first node and a second node; a first switching transistor connecting a data line to the first node in response to a scan signal; a drive transistor generating a drive current based on a voltage at the first node; a second switching transistor connecting an initialization line to the second node in response to an initialization signal; and an organic light-emitting diode emitting light based on the drive current. The pixel performs a first reset operation and a second reset operation, wherein the first reset operation resets the first node to a first initialization voltage of the initialization line during a first interval of a previous horizontal time, and the second reset operation resets the first node to a second initialization voltage different from the first initialization voltage during a second interval of the previous horizontal time.

[0007] In one embodiment, the second initialization voltage may be lower than the first initialization voltage.

[0008] In one embodiment, the second initialization voltage may be lower than the lowest data voltage.

[0009] In one embodiment, the scanning signal may have a cutoff voltage in the first interval and the second interval of the previous horizontal time, the initialization signal may have a turn-on voltage in the first interval and the second interval of the previous horizontal time, the first switching transistor may be turned off in the first interval and the second interval of the previous horizontal time in response to the scanning signal having the cutoff voltage, and the second switching transistor may be turned on in the first interval and the second interval of the previous horizontal time in response to the initialization signal having the turn-on voltage.

[0010] In one embodiment, the scan signal and the initialization signal may have a turn-on voltage in a first interval of a current horizontal time, and have a turn-off voltage in a second interval of the current horizontal time.

[0011] In one embodiment, the first switching transistor can transmit the data voltage of the data line to the first node in response to the scanning signal having the turn-on voltage in the first interval of the current horizontal time, and the second switching transistor can transmit the first initialization voltage of the initialization line to the second node in response to the initialization signal having the turn-on voltage in the first interval of the current horizontal time.

[0012] In one embodiment, the initial gate-source voltage of the first switch transistor at the start time point of the first interval of the current horizontal time may be a constant voltage.

[0013] In one embodiment, the initial gate-source voltage of the first switch transistor may be a voltage obtained by subtracting the second initialization voltage from the turn-on voltage of the scan signal.

[0014] In one embodiment, the final gate-source voltage of the first switching transistor at the end time point of the first interval of the current horizontal time may be changed according to the data voltage.

[0015] In one embodiment, the final gate-source voltage of the first switching transistor may be a voltage obtained by subtracting the data voltage from the turn-on voltage of the scan signal.

[0016] In one embodiment, in the first interval of the current horizontal time, the direction of the current path formed between the data line and the first node may be constant regardless of the voltage level of the data voltage.

[0017] In one embodiment, during the first interval of the current horizontal time, the current path may be formed to have a direction from the data line toward the first node.

[0018] In one embodiment, the storage capacitor may include a first electrode connected to the first node and a second electrode connected to the second node, the first switching transistor includes a gate for receiving the scan signal, a first terminal connected to the data line, and a second terminal connected to the first node, the driving transistor includes a gate connected to the first node, a first terminal for receiving a first power supply voltage, and a second terminal connected to the second node, the second switching transistor includes a gate for receiving the initialization signal, a first terminal connected to the second node, and a second terminal connected to the initialization line, and the organic light emitting diode includes an anode connected to the second node and a cathode for receiving a second power supply voltage.

[0019] In one embodiment, the first switch transistor, the driving transistor, and the second switch transistor may be NMOS transistors.

[0020] To achieve another object of the present invention, a pixel of an organic light-emitting display device according to an embodiment of the present invention includes: a storage capacitor including a first electrode connected to a first node and a second electrode connected to a second node; a first switching transistor including a gate for receiving a scan signal, a first terminal connected to a data line, and a second terminal connected to the first node; a driving transistor including a gate connected to the first node, a first terminal for receiving a first power supply voltage, and a second terminal connected to the second node; a second switching transistor including a gate for receiving an initialization signal, a first terminal connected to the second node, and a second terminal connected to an initialization line; and an organic light-emitting diode including an anode connected to the second node and a cathode for receiving a second power supply voltage. The pixel performs a first reset operation and a second reset operation, wherein the first reset operation resets the first node to a first initialization voltage of the initialization line during a first interval of a previous horizontal time, and the second reset operation resets the first node to a second initialization voltage different from the first initialization voltage during a second interval of the previous horizontal time.

[0021] To achieve another object of the present invention, an organic light-emitting display device according to an embodiment of the present invention includes: a display panel including a plurality of pixels; a data driver providing a data voltage to each of the plurality of pixels; a scan driver providing a scan signal and an initialization signal to each of the plurality of pixels; a power management circuit providing an initialization voltage to each of the plurality of pixels; and a controller controlling the data driver, the scan driver, and the power management circuit. Each of the plurality of pixels includes: a storage capacitor connected between a first node and a second node; a first switching transistor connecting a data line to the first node in response to a scan signal; a drive transistor generating a drive current based on a voltage at the first node; a second switching transistor connecting the initialization line to the second node in response to an initialization signal; and an organic light-emitting diode emitting light based on the drive current. Each frame interval includes a plurality of horizontal times. The power management circuit generates a first initialization voltage as the initialization voltage in a first interval of each of the plurality of horizontal times, and generates a second initialization voltage, different from the first initialization voltage, as the initialization voltage in a second interval of each of the plurality of horizontal times.

[0022] In one embodiment, each of the multiple pixels performs a first reset operation and a second reset operation, wherein the first reset operation resets the first node to the first initialization voltage in the first interval of the previous horizontal time among the multiple horizontal times, and the second reset operation resets the first node to the second initialization voltage in the second interval of the previous horizontal time.

[0023] In one embodiment, the second initialization voltage may be lower than the first initialization voltage.

[0024] In one embodiment, the second initialization voltage may be lower than the lowest data voltage.

[0025] In one embodiment, in the first interval of a current horizontal time among the plurality of horizontal times, a direction of a current path formed between the data line and the first node may be constant regardless of a voltage level of the data voltage.

[0026] In an organic light-emitting display device according to an embodiment of the present invention, each pixel can perform a first reset operation and a second reset operation. The first reset operation resets a first node (e.g., the gate node of a drive transistor) to a first initialization voltage during a first interval of a previous horizontal time, and the second reset operation resets the first node to a second initialization voltage different from the first initialization voltage during a second interval of the previous horizontal time. Therefore, the current path of the first switching transistor of each pixel can have a constant direction from the data line to the first node, regardless of the voltage level of the data voltage. Furthermore, compared to a case where the reset operation is not performed, the gate-source voltage of the first switching transistor can be increased, and the charging rate of the pixel can be improved.

[0027] However, the effects of the present invention are not limited to the above-mentioned effects, and various extensions can be achieved without departing from the spirit and concept of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 is a circuit diagram illustrating a pixel of an organic light emitting display device according to an embodiment of the present invention.

[0029] Figure 2 FIG. 1 is a timing diagram for explaining an example of operation of a pixel of an organic light emitting display device according to an embodiment of the present invention.

[0030] Figure 3 is a circuit diagram for explaining a first reset operation of pixels in a first interval of a previous horizontal time.

[0031] Figure 4 is a circuit diagram for explaining a second reset operation of pixels in a second interval of the previous horizontal time.

[0032] Figure 5 1 is a circuit diagram for explaining a data writing operation for a pixel in the first interval of the current horizontal time.

[0033] Figure 6 is a diagram for explaining an example of the gate-source voltage of the first switching transistor in a case where a reset operation is not performed.

[0034] Figure 7 is a diagram for explaining an example of a gate-source voltage of a first switching transistor in a pixel performing a two-step reset operation according to an embodiment of the present invention.

[0035] Figure 8 is a block diagram illustrating an organic light emitting display device according to an embodiment of the present invention.

[0036] Figure 9FIG. 1 is a timing diagram for illustrating an example of an initialization voltage during one frame period of an organic light emitting display device according to an embodiment of the present invention.

[0037] Figure 10 is a block diagram illustrating an electronic device including an organic light emitting display device according to an embodiment of the present invention.

[0038] Description of Reference Numerals

[0039] 100: Pixel CST: Storage capacitor

[0040] ST1: First switching transistor DT: Driving transistor

[0041] ST2: second switch transistor 300: organic light emitting display device

[0042] 310: Display panel 330: Data driver

[0043] 350: Scan driver 370: Power management circuit

[0044] 390: Controller DETAILED DESCRIPTION

[0045] Hereinafter, preferred embodiments of the present invention will be described in more detail with reference to the accompanying drawings. The same reference numerals are used for the same components in the drawings, and repeated descriptions of the same components are omitted.

[0046] Figure 1 is a circuit diagram illustrating a pixel of an organic light emitting display device according to an embodiment of the present invention.

[0047] Reference Figure 1 , the pixel 100 of the organic light emitting display device may include a storage capacitor CST, a first switching transistor ST1, a driving transistor DT, a second switching transistor ST2 and an organic light emitting diode EL. Figure 1 As shown, the pixel 100 may have a 3T1C structure including only three transistors, namely, a first switching transistor ST1 , a driving transistor DT, and a second switching transistor ST2 , and one capacitor, namely, a storage capacitor CST.

[0048] The storage capacitor CST may be connected between the first node N1 and the second node N2. The storage capacitor CST may store the data voltage VDAT transmitted from the data line DL through the first switching transistor ST1. In one embodiment, the storage capacitor CST may include a first electrode connected to the first node N1 and a second electrode connected to the second node N2.

[0049] The first switching transistor ST1 can connect the data line DL to the first node N1 in response to the scan signal SC. The first switching transistor ST1 can transmit the data voltage VDAT of the data line DL to the first node N1 (i.e., the first electrode of the storage capacitor CST) during a period in which the scan signal SC has a turn-on voltage (e.g., approximately 20V). In one embodiment, the first switching transistor ST1 may include a gate for receiving the scan signal SC, a first terminal connected to the data line DL, and a second terminal connected to the first node N1.

[0050] The driving transistor DT may generate a driving current based on the voltage of the first node N1 (i.e., the data voltage VDAT stored in the storage capacitor CST). In one embodiment, the driving transistor DT may include a gate connected to the first node N1, a first terminal receiving a first power supply voltage ELVDD (e.g., a high power supply voltage), and a second terminal connected to the second node N2.

[0051] The second switching transistor ST2 can connect the initialization line IL to the second node N2 in response to the initialization signal SI. The second switching transistor ST2 can transmit the initialization voltage VINT of the initialization line IL to the second node N2 (i.e., the second electrode of the storage capacitor CST) during a period in which the initialization signal SI has a turn-on voltage (e.g., approximately 20V). In one embodiment, the second switching transistor ST2 may include a gate for receiving the initialization signal SI, a first terminal connected to the second node N2, and a second terminal connected to the initialization line IL.

[0052] The organic light emitting diode EL may emit light based on the driving current generated by the driving transistor DT. In one embodiment, the organic light emitting diode EL may include an anode connected to the second node N2 and a cathode receiving a second power voltage ELVSS (eg, a low power voltage).

[0053] In one embodiment, the first switch transistor ST1 , the driving transistor DT, and the second switch transistor ST2 may be NMOS transistors, but the present invention is not limited thereto.

[0054] According to an embodiment of the present invention, the pixel 100 can perform a first reset operation and a second reset operation. The first reset operation resets the first node N1 to the first initialization voltage VINT1 of the initialization line IL in a first interval of a horizontal time (i.e., a previous horizontal time) of a pixel in a previous row (e.g., an immediately preceding row) with respect to the row in which the pixel 100 is located. The second reset operation resets the first node N1 to a second initialization voltage VINT2 different from the first initialization voltage VINT1 in a second interval of the previous horizontal time. That is, the pixel 100 can perform a two-step reset operation including the first reset operation and the second reset operation using different initialization voltages VINT1 and VINT2.

[0055] In one embodiment, the second initialization voltage VINT2 may be lower than the first initialization voltage VINT1. For example, the first initialization voltage VINT1 may be approximately 1V, and the second initialization voltage VINT2 may be approximately -5V, but the present invention is not limited thereto. Furthermore, in one embodiment, the second initialization voltage VINT2 may be lower than the lowest data voltage. For example, the data voltage VDAT may have a data voltage range from approximately 1V corresponding to 0-grayscale to approximately 11V corresponding to 255-grayscale, and the second initialization voltage VINT2 may be approximately -5V, which is lower than the lowest data voltage of approximately 1V, but the present invention is not limited thereto.

[0056] Furthermore, when the data voltage VDAT is written into the storage capacitor CST without a reset operation, the current path of the first switching transistor ST1 can be directed from the data line DL toward the first node N1, or from the first node N1 toward the data line DL, depending on the previous data voltage at the first node N1 (the data voltage VDAT of the previous frame interval) and the current data voltage VDAT of the data line DL (the data voltage VDAT of the current frame interval). Furthermore, the gate-source voltage of the first switching transistor ST1 can be determined by the difference between the on-state voltage of the scan signal SC and the current data voltage VDAT, or by the difference between the on-state voltage of the scan signal SC and the voltage of the first node N1 (or the previous data voltage at the start time of the data write operation), depending on the direction of the current path. Accordingly, the gate-source voltage of the first switching transistor ST1 can be altered by the previous data voltage and / or the current data voltage VDAT.

[0057] However, in the pixel 100 according to an embodiment of the present invention, the first node N1 can be reset to the first initialization voltage VINT1 by the first reset operation in the first interval of the previous horizontal time, and reset to the second initialization voltage VINT2 by the second reset operation in the second interval of the previous horizontal time. Accordingly, in the first interval of the horizontal time (i.e., the current horizontal time) of the row in which the pixel 100 is located, the data voltage VDAT of the data line DL can be higher than the voltage of the first node N1 (i.e., the second initialization voltage VINT2), and the current path of the first switching transistor ST1 has a constant direction from the data line DL to the first node N1 regardless of the voltage level of the data voltage VDAT. Furthermore, the initial gate-source voltage of the first switching transistor ST1 at the start time of the first interval of the current horizontal time may be a constant voltage (e.g., approximately 25V) obtained by subtracting the voltage of the first node N1 at the start time (i.e., the second initialization voltage VINT2 (e.g., approximately -5V)) from the turn-on voltage of the scan signal SC (e.g., approximately 20V), regardless of the voltage level of the data voltage VDAT. Furthermore, the initial gate-source voltage may be increased compared to a case where the reset operation is not performed. Accordingly, the gate-source voltage of the first switching transistor ST1 increases, thereby increasing the current carrying capacity of the first switching transistor ST1 and improving the charging rate of the pixel 100 (e.g., the charging rate of the storage capacitor CST).

[0058] Below, refer to Figures 2 to 7 An example of the operation of the pixel 100 of the organic light emitting display device will be described.

[0059] Figure 2 is a timing diagram for explaining an example of the operation of a pixel of an organic light emitting display device according to an embodiment of the present invention. Figure 3 is a circuit diagram for explaining a first reset operation of pixels in a first interval of a previous horizontal time, Figure 4 is a circuit diagram for explaining a second reset operation of pixels in a second interval of a previous horizontal time, Figure 5 is a circuit diagram for explaining a data writing operation for a pixel in the first interval of the current horizontal time. Figure 6 is a diagram for explaining an example of the gate-source voltage of the first switching transistor in a case where the reset operation is not performed, Figure 7 is a diagram for explaining an example of a gate-source voltage of a first switching transistor in a pixel performing a two-step reset operation according to an embodiment of the present invention.

[0060] Reference Figure 1 and Figure 2Each frame interval of the organic light-emitting display device including the pixel 100 may include a plurality of horizontal times HTN-1, HTN, and HTN+1 corresponding to a plurality of pixel rows, respectively. For example, when the organic light-emitting display device includes M pixel rows (M is an integer greater than or equal to 2), each frame interval may include M (or M+1) horizontal times HTN-1, HTN, and HTN+1. Figure 2 The diagram shows an example in which the Nth horizontal time HTN (N is an integer greater than 2 and less than M) is a horizontal time for a pixel row including pixel 100 (i.e., a current horizontal time), and the N-1th horizontal time HTN-1 is a horizontal time for a previous pixel row (i.e., a previous horizontal time). Furthermore, each horizontal time HTN-1, HTN, and HTN+1 can be divided into a first interval P1 and a second interval P2. The initialization voltage VINT of the initialization line IL is a first initialization voltage VINT1 in the first interval P1 of each horizontal time HTN-1, HTN, and HTN+1, and a second initialization voltage VINT2 different from the first initialization voltage VINT1 in the second interval P2 of each horizontal time HTN-1, HTN, and HTN+1. For example, the first initialization voltage VINT1 can be approximately 1V, and the second initialization voltage VINT2 can be approximately -5V, but this is not limited to this.

[0061] Reference Figure 2 and Figure 3 During the first interval P1 of the previous horizontal time HTN-1, the scan signal SC may have a cut-off voltage VOFF, and the initialization signal SI may have an on-voltage VON. The first switching transistor ST1 may be turned off in response to the scan signal SC having the cut-off voltage VOFF, and the second switching transistor ST2 may be turned on in response to the initialization signal SI having the on-voltage VON. At the start time of the first interval P1 of the previous horizontal time HTN-1, the first node N1 (i.e., the first electrode of the storage capacitor CST) may have the data voltage VDAT of the previous frame interval (i.e., the previous data voltage PVDAT). However, during the first interval P1 of the previous horizontal time HTN-1, the second node N2 (i.e., the second electrode of the storage capacitor CST) may be applied with the first initialization voltage VINT1. Accordingly, the second node N2 may have the first initialization voltage VINT1 during the first interval P1 of the previous horizontal time HTN-1, and the first node N1 may change from the previous data voltage PVDAT to the first initialization voltage VINT1 (or close to the first initialization voltage VINT1) (e.g., due to leakage current of the storage capacitor CST). In addition, such an operation of changing the first node N1 to the first initialization voltage VINT1 (or close to the first initialization voltage VINT1) may be referred to as a first reset operation using the first initialization voltage VINT1.

[0062] Reference Figure 2 and Figure 4 , in the second interval P2 of the previous horizontal time HTN-1, the scan signal SC can be maintained at the off voltage VOFF, the initialization signal SI is maintained at the on voltage VON, and the initialization voltage VINT of the initialization line IL is changed from the first initialization voltage VINT1 to the second initialization voltage VINT2. In one embodiment, the second initialization voltage VINT2 can be lower than the first initialization voltage VINT1. For example, the first initialization voltage VINT1 can be approximately 1V, and the second initialization voltage VINT2 can be approximately -5V, but it is not limited to this. In addition, in one embodiment, the second initialization voltage VINT2 can be lower than the lowest data voltage. For example, the data voltage VDAT can have a data voltage range from approximately 1V corresponding to 0-grayscale to approximately 11V corresponding to 255-grayscale, and the second initialization voltage VINT2 can be approximately -5V, which is lower than the lowest data voltage of approximately 1V, but it is not limited to this. Accordingly, during the second interval P2 of the previous horizontal time HTN-1, the second node N2 may have the second initialization voltage VINT2 of approximately -5V, and the first node N1 may change from the first initialization voltage VINT1 of approximately 1V to the second initialization voltage VINT2 of approximately -5V (or, close to the second initialization voltage VINT2 of approximately -5V). Furthermore, this operation in which the first node N1 is changed to the second initialization voltage VINT2 of approximately -5V may be referred to as a second reset operation using the second initialization voltage VINT2. Furthermore, the first and second reset operations using different initialization voltages VINT1 and VINT2 may be referred to as a two-step reset operation.

[0063] Reference Figure 2 and Figure 5During the first interval P1 of the current horizontal time HTN, the scan signal SC may be changed to the on-voltage VON, the initialization signal SI may be maintained at the on-voltage VON, and the initialization voltage VINT of the initialization line IL may be changed from the second initialization voltage VINT2 to the first initialization voltage VINT1. During the first interval P1 of the current horizontal time HTN, the first switching transistor ST1 may transmit the data voltage VDAT of the data line DL to the first node N1 in response to the scan signal SC having the on-voltage VON, and the second switching transistor ST2 may transmit the first initialization voltage VINT1 of the initialization line IL to the second node N2 in response to the initialization signal SI having the on-voltage VON. Accordingly, during the first interval P1 of the current horizontal time HTN, a data write operation may be performed on the pixel 100. That is, during the first interval P1 of the current horizontal time HTN, the storage capacitor CST may store the voltage difference between the data voltage VDAT and the first initialization voltage VINT1, and store the data voltage VDAT at the first node N1 (i.e., the first electrode).

[0064] In addition, when the reset operation is not performed, the direction of the current path and the gate-source voltage of the first switching transistor ST1 may not be constant when the data writing operation is performed. Figure 6 As shown in the first column of , when the previous data voltage PVDAT is approximately 11V corresponding to 255-grayscale 255G, the current data voltage VDAT is approximately 6V corresponding to 128-grayscale 128G, and the turn-on voltage of the scan signal SC is approximately 20V, when the data write operation starts, the first node N1 may have a previous data voltage PVDAT of approximately 11V, and the data line DL has a current data voltage VDAT of approximately 6V. In this case, the first current path IDAT1 of the first switching transistor ST1 may have a direction from the first node N1 to the data line DL, and the first terminal of the first switching transistor ST1 connected to the data line DL may serve as the source of the first switching transistor ST1. Accordingly, during the execution of the data write operation, the gate-source voltage VGS of the first switching transistor ST1 may be constant at approximately 14V obtained by subtracting the current data voltage VDAT of approximately 6V from the turn-on voltage of approximately 20V. In another example, as Figure 6As shown in the second column of FIG, when the previous data voltage PVDAT is approximately 1V corresponding to 0-grayscale 0G, the current data voltage VDAT is approximately 6V corresponding to 128-grayscale 128G, and the turn-on voltage of the scan signal SC is approximately 20V, when the data write operation begins, the first node N1 may have a previous data voltage PVDAT of approximately 1V, and the data line DL may have a current data voltage VDAT of approximately 6V. In this case, the second current path IDAT2 of the first switching transistor ST1 may extend from the data line DL toward the first node N1, and the second terminal of the first switching transistor ST1 connected to the first node N1 may function as the source of the first switching transistor ST1. Furthermore, when the data write operation ends, the voltage of the first node N1 may have a current data voltage VDAT of approximately 6V. Accordingly, during the data write operation, the gate-source voltage VGS of the first switching transistor ST1 can gradually change from approximately 19V obtained by subtracting the previous data voltage PVDAT of approximately 1V from the turn-on voltage of approximately 20V to approximately 14V obtained by subtracting the current data voltage VDAT of approximately 6V from the turn-on voltage of approximately 20V.

[0065] However, in the pixel 100 according to an embodiment of the present invention, since the first node N1 is reset by the two-step reset operation using the first initialization voltage VINT1 and the second initialization voltage VINT2 during the previous horizontal time HTN-1 before the current horizontal time HTN, the direction of the current path IDAT formed between the data line DL and the first node N1 during the first interval P1 of the current horizontal time HTN can be constant regardless of the voltage levels of the previous data voltage PVDAT and the current data voltage VDAT. That is, at the start time point of the first interval P1 of the current horizontal time HTN, the first node N1 has the second initialization voltage VINT2 that is lower than the data voltage range of approximately 1V to approximately 11V (i.e., lower than the lowest data voltage of approximately 1V). Therefore, as shown in FIG. Figure 7 As shown, regardless of whether the current data voltage VDAT is about 1V for 0-grayscale 0G, about 6V for 128-grayscale 128G, or about 11V for 255-grayscale 255G, the current path IDAT of the first switching transistor ST1 can have a constant direction from the data line DL to the first node N1.

[0066] Furthermore, in the pixel 100 according to an embodiment of the present invention, the initial gate-source voltage of the first switching transistor ST1 at the start time point of the first interval P1 of the current horizontal time HTN can be constant regardless of the voltage levels of the previous data voltage PVDAT and the current data voltage VDAT. Furthermore, the final gate-source voltage of the first switching transistor T1 at the end time point of the first interval P1 of the current horizontal time HTN can be determined based on the current data voltage VDAT.

[0067] For example, Figure 7 As shown in the first column of FIG, when the data voltage VDAT is approximately 11V corresponding to 255-grayscale 255G and the turn-on voltage of the scan signal SC is approximately 20V, the first node N1 may have a second initialization voltage VINT2 of approximately -5V at the start time of the first interval P1 of the current horizontal time HTN, and a data voltage VDAT of approximately 11V at the end time of the first interval P1 of the current horizontal time HTN. Accordingly, the initial gate-source voltage of the first switching transistor ST1 may be determined to be approximately 25V, which is obtained by subtracting the second initialization voltage VINT2 of approximately -5V from the turn-on voltage of approximately 20V. The final gate-source voltage of the first switching transistor ST1 may be determined to be approximately 9V, which is obtained by subtracting the data voltage VDAT of approximately 11V from the turn-on voltage of approximately 20V. The gate-source voltage VGS of the first switching transistor ST1 changes from approximately 25V to approximately 9V during the first interval P1 of the current horizontal time HTN.

[0068] In another example, Figure 7 As shown in the second column of FIG, when the data voltage VDAT is approximately 6V corresponding to 128-grayscale 128G and the turn-on voltage of the scan signal SC is approximately 20V, the first node N1 may have a second initialization voltage VINT2 of approximately -5V at the start time of the first interval P1 of the current horizontal time HTN, and have a data voltage VDAT of approximately 6V at the end time of the first interval P1 of the current horizontal time HTN. Accordingly, the initial gate-source voltage of the first switching transistor ST1 may be determined to be approximately 25V, which is obtained by subtracting the second initialization voltage VINT2 of approximately -5V from the turn-on voltage of approximately 20V. The final gate-source voltage of the first switching transistor ST1 may be determined to be approximately 14V, which is obtained by subtracting the data voltage VDAT of approximately 6V from the turn-on voltage of approximately 20V. The gate-source voltage VGS of the first switching transistor ST1 changes from approximately 25V to approximately 14V during the first interval P1 of the current horizontal time HTN.

[0069] In yet another example, Figure 7As shown in the third column of FIG, when the data voltage VDAT is approximately 1V corresponding to 0-grayscale 0G and the turn-on voltage of the scan signal SC is approximately 20V, the first node N1 may have a second initialization voltage VINT2 of approximately -5V at the start time of the first interval P1 of the current horizontal time HTN, and may have a data voltage VDAT of approximately 1V at the end time of the first interval P1 of the current horizontal time HTN. Accordingly, the initial gate-source voltage of the first switching transistor ST1 may be determined to be approximately 25V, which is obtained by subtracting the second initialization voltage VINT2 of approximately -5V from the turn-on voltage of approximately 20V. The final gate-source voltage of the first switching transistor ST1 may be determined to be approximately 19V, which is obtained by subtracting the data voltage VDAT of approximately 1V from the turn-on voltage of approximately 20V. The gate-source voltage VGS of the first switching transistor ST1 changes from approximately 25V to approximately 19V during the first interval P1 of the current horizontal time HTN.

[0070] As described above, in the pixel 100 according to an embodiment of the present invention, in the first interval P1 of the current horizontal time HTN, the data voltage VDAT of the data line DL can be higher than the voltage of the first node N1 (i.e., the second initialization voltage VINT2), and the current path IDAT of the first switching transistor ST1 has a constant direction from the data line DL to the first node N1 regardless of the voltage level of the data voltage VDAT. Furthermore, the initial gate-source voltage of the first switching transistor ST1 at the starting time point of the first interval P1 of the current horizontal time HTN can be a constant voltage (e.g., approximately 25V) obtained by subtracting the second initialization voltage VINT2 (e.g., approximately -5V) from the turn-on voltage of the scan signal SC (e.g., approximately 20V), regardless of the voltage level of the data voltage VDAT. Furthermore, as Figure 6 and Figure 7 As shown in FIG. 1 , the gate-source voltage VGS of the first switching transistor ST1 of the pixel 100 performing the two-step reset operation can be increased compared to the case where the reset operation is not performed. Accordingly, since the gate-source voltage VGS of the first switching transistor ST1 is increased, the current carrying capacity of the first switching transistor ST1 can be improved, and the charging rate of the pixel 100 can be improved.

[0071] And, as Figure 1 and Figure 2 As shown, the scan signal SC and the initialization signal SI may be changed to the cut-off voltage in the second interval P2 of the current horizontal time HTN, and the pixel 100 may emit light based on the data voltage VDAT of the first node N1.

[0072] Figure 8 is a block diagram illustrating an organic light emitting display device according to an embodiment of the present invention, Figure 9FIG. 1 is a timing diagram for illustrating an example of an initialization voltage during one frame period of an organic light emitting display device according to an embodiment of the present invention.

[0073] Reference Figure 8 According to an embodiment of the present invention, the organic light-emitting display device 300 may include: a display panel 310 including a plurality of pixels PX; a data driver 330 providing a data voltage VDAT to each of the plurality of pixels PX; a scan driver 350 providing a scan signal SC and an initialization signal SI to each of the plurality of pixels PX; a power management circuit 370 providing an initialization voltage VINT to each of the plurality of pixels PX; and a controller 390 controlling the data driver 330, the scan driver 350, and the power management circuit 370.

[0074] The display panel 310 may include a plurality of data lines DL, a plurality of initialization lines IL, a plurality of scan signal lines, a plurality of initialization signal lines, and a plurality of pixels PX connected thereto. Figure 1 The 3T1C structure pixel 100 shown, or a pixel with a different structure, can receive an initialization voltage VINT alternating between a first initialization voltage VINT1 and a second initialization voltage VINT2 from the power management circuit 370, and perform a first reset operation and a second reset operation. The first reset operation resets the first node (or the gate node of the drive transistor) to the first initialization voltage VINT1 during a first interval of a previous horizontal time, and the second reset operation resets the first node to the second initialization voltage VINT2 during a second interval of the previous horizontal time. Accordingly, the current path of the first switching transistor of each pixel PX can have a constant direction from the data line DL to the first node, regardless of the voltage level of the data voltage VDAT. Furthermore, compared to a case where no reset operation is performed, the gate-source voltage of the first switching transistor of each pixel PX can be increased, and the charging rate of the pixel PX can be improved.

[0075] The data driver 330 can generate a data voltage VDAT based on a data control signal DCTRL and output image data ODAT received from the controller 390, and provide the data voltage VDAT to a plurality of pixels PX via a plurality of data lines DL. In one embodiment, the data control signal DCTRL may include a transfer pulse signal TP for controlling the output timing of the data voltage VDAT from the data driver 330. For example, the data driver 330 may output the data voltage VDAT for a row of pixels PX to the plurality of data lines DL at the rising edge of the transfer pulse signal TP. In another embodiment, the data driver 330 may further include a horizontal start signal and a load signal, but is not limited thereto. In one embodiment, the data driver 330 may be implemented using one or more data driver integrated circuits (ICs). In another embodiment, the data driver 330 and the controller 390 may be implemented using a single integrated circuit, which may be referred to as a timing controller embedded data driver (TED).

[0076] The scan driver 350 can generate a scan signal SC and an initialization signal SI based on a scan control signal SCTRL received from the controller 390, and sequentially provide the scan signal SC to the plurality of pixels PX in rows via the plurality of scan signal lines, and sequentially provide the initialization signal SI to the plurality of pixels PX in rows via the plurality of initialization signal lines. In one embodiment, the scan control signal SCTRL can include a scan start signal, a scan clock signal, an initialization start signal, and an initialization clock signal, but is not limited thereto. In one embodiment, the scan driver 350 can be integrated or formed in the periphery of the display panel 310. In another embodiment, the scan driver 350 can be implemented using one or more scan driver ICs.

[0077] The power management circuit 370 can provide a first power supply voltage ELVDD, a second power supply voltage ELVSS, and an initialization voltage VINT to a plurality of pixels PX. The power management circuit 370 can generate a first initialization voltage VINT1 as the initialization voltage VINT in a first interval of each horizontal time, and generate a second initialization voltage VINT2, which is different from the first initialization voltage VINT1, as the initialization voltage VINT in a second interval of each horizontal time. To perform such an operation, the power management circuit 370 can include a switch SW configured to receive an initialization voltage control signal VINTCTRL from the controller 390 and selectively output the first initialization voltage VINT1 or the second initialization voltage VINT2 to a plurality of initialization lines IL (e.g., connected to each other) in response to the initialization voltage control signal VINTCTRL. For example, the switch SW can output the first initialization voltage VINT1 to the plurality of initialization lines IL in response to the initialization voltage control signal VINTCTRL having a low level, and output the second initialization voltage VINT2 to the plurality of initialization lines IL in response to the initialization voltage control signal VINTCTRL having a high level. In one embodiment, the power management circuit 370 may be implemented as a separate integrated circuit, and such an integrated circuit may be referred to as a power management integrated circuit (PMIC). In another embodiment, the power management circuit 370 may be included in the controller 390 .

[0078] The controller 390 (e.g., a timing controller (T-CON)) can receive input image data IMDAT and a control signal CTRL from an external host processor (e.g., a graphics processing unit (GPU), an application processor (AP), or a graphics card). In one embodiment, the control signal CTRL may include a vertical synchronization signal, a horizontal synchronization signal, an input data enable signal, a master clock signal, etc., but is not limited thereto. Based on the input image data IMDAT and the control signal CTRL, the controller 390 can generate output image data ODAT, a data control signal DCTRL, a scan control signal SCTRL, and an initialization voltage control signal VINTCTRL. The controller 390 can also provide the output image data ODAT and the data control signal DCTRL to the data driver 330 to control the data driver 330, provide the scan control signal SCTRL to the scan driver 350 to control the scan driver 350, and provide the initialization voltage control signal VINTCTRL to the power management circuit 370 to control the power management circuit 370.

[0079] In one embodiment, if Figure 9 As shown, each frame interval FP of the organic light emitting display device 300 may include an active interval and a blank interval BP, wherein the active interval includes a plurality of horizontal times HT0, HT1, HT2, ..., HTM-1, and HTM corresponding to a plurality of pixel rows. For example, when the display panel 310 includes the first pixel row to the M-th pixel row (M is an integer greater than 2), as shown in FIG. Figure 9 As shown, each frame interval FP may include the previous horizontal time HT0 of the first pixel row and the first horizontal time to the M-th horizontal time HT1, HT2, ..., HTM-1, HTM, which are the M current horizontal times of the first pixel row to the M-th pixel row. Each horizontal time HT0, HT1, HT2, ..., HTM-1, HTM may include a first interval P1 and a second interval P2. The power management circuit 370 may generate a first initialization voltage VINT1 as the initialization voltage VINT in response to the initialization voltage control signal VINTCTRL having a low level in the first interval P1 of each horizontal time HT0, HT1, HT2, ..., HTM-1, HTM, and generate a second initialization voltage VINT2 as the initialization voltage VINT in response to the initialization voltage control signal VINTCTRL having a high level in the second interval P2 of each horizontal time HT0, HT1, HT2, ..., HTM-1, HTM.

[0080] During the first interval P1 and the second interval P2 of the previous horizontal time HT0 of the first pixel row, the first initialization signal SI1 for the first pixel row may have a turn-on voltage. In response to the first initialization signal SI1 having the turn-on voltage, the pixels PX of the first pixel row may perform the first reset operation using the first initialization voltage VINT1 in the first interval P1 of the previous horizontal time HT0, and perform the second reset operation using the second initialization voltage VINT2 in the second interval P2 of the previous horizontal time HT0. During the first interval P1 of the first horizontal time HT1, the first scan signal SC1 and the first initialization signal SI1 for the first pixel row may have the turn-on voltage, and the pixels PX of the first pixel row may perform a data write operation in response to the first scan signal SC1 and the first initialization signal SI1 having the turn-on voltage. Furthermore, the first and second reset operations during the previous horizontal time HT0 may increase the charging rate of the pixels PX of the first pixel row, and the pixels PX of the first pixel row may store data voltages VDAT having a desired voltage level. In the second interval P2 of the first horizontal time HT1 , the first scan signal SC1 and the first initialization signal SI1 associated with the first pixel row may be changed to a cut-off voltage.

[0081] Furthermore, during the first interval P1 and the second interval P2 of the first horizontal time HT1, the second initialization signal SI2 for the second pixel row may have a turn-on voltage, and the pixels PX of the second pixel row may perform the first reset operation using the first initialization voltage VINT1 during the first interval P1 of the first horizontal time HT1, and perform the second reset operation using the second initialization voltage VINT2 during the second interval P2 of the first horizontal time HT1. During the first interval P1 of the second horizontal time HT2, the second scan signal SC2 and the second initialization signal SI2 for the second pixel row may have the turn-on voltage, and the pixels PX of the second pixel row may perform a data write operation in response to the second scan signal SC2 and the second initialization signal SI2 having the turn-on voltage.

[0082] Similarly, in the first interval P1 and the second interval P2 of the M-1st horizontal time HTM-1, the M-th initialization signal SIM for the M-th pixel row may have a turn-on voltage, and the pixels PX of the M-th pixel row may perform the first reset operation using the first initialization voltage VINT1 in the first interval P1 of the M-1st horizontal time HTM-1, and perform the second reset operation using the second initialization voltage VINT2 in the second interval P2 of the M-1st horizontal time HTM-1. In the first interval P1 of the M-th horizontal time HTM, the M-th scan signal SCM and the M-th initialization signal SIM for the M-th pixel row may have the turn-on voltage, and the pixels PX of the M-th pixel row may perform a data write operation in response to the M-th scan signal SCM and the M-th initialization signal SIM having the turn-on voltage.

[0083] In this manner, during each frame period FP, the plurality of pixels PX can sequentially perform a two-step reset operation and a data write operation on a pixel row basis in response to the first to M-th scan signals SC1, SC2, ..., SCM and the first to M-th initialization signals SI1, SI2, ..., SIM sequentially applied on a pixel row basis. Furthermore, since each pixel PX performs the two-step reset operation, the charging rate of the pixel PX can be improved.

[0084] Figure 10 is a block diagram illustrating an electronic device including an organic light emitting display device according to an embodiment of the present invention.

[0085] Reference Figure 10The electronic device 1100 may include a processor 1110, a memory device 1120, a storage device 1130, an input / output device 1140, a power supply 1150, and an organic light-emitting display device 1160. The electronic device 1100 may also include a plurality of ports capable of communicating with a video card, a sound card, a memory card, a USB device, or other systems.

[0086] The processor 1110 can perform specific calculations or tasks. Depending on the embodiment, the processor 1110 can be a microprocessor, a central processing unit (CPU), etc. The processor 1110 can be connected to other components via an address bus, a control bus, and a data bus. Depending on the embodiment, the processor 1110 can also be connected to an expansion bus such as a Peripheral Component Interconnect (PCI) bus.

[0087] The memory device 1120 may store data required for the operation of the electronic device 1100 . For example, the memory device 1120 may include non-volatile memory devices such as erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), flash memory, phase change random access memory (PRAM), resistance random access memory (RRAM), nano floating gate memory (NFGM), polymer random access memory (PoRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), and / or volatile memory devices such as dynamic random access memory (DRAM), static random access memory (SRAM), mobile DRAM, and the like.

[0088] The storage device 1130 may include a solid-state drive (SSD), a hard disk drive (HDD), a compact disk read-only memory (CD-ROM), etc. The input / output device 1140 may include input structures such as a keyboard, a keypad, a touchpad, a touch screen, a mouse, etc., and output structures such as a speaker, a printer, etc. The power supply 1150 may supply the power required for the operation of the electronic device 1100. The organic light-emitting display device 1160 may be connected to other components via the bus or other communication links.

[0089] In the organic light-emitting display device 1160, each pixel can perform a first reset operation and a second reset operation. The first reset operation resets a first node (e.g., the gate node of a drive transistor) to a first initialization voltage during a first interval of a previous horizontal time, and the second reset operation resets the first node to a second initialization voltage different from the first initialization voltage during a second interval of the previous horizontal time. Accordingly, the current path of the first switching transistor of each pixel can have a constant direction from the data line to the first node, regardless of the voltage level of the data voltage. Furthermore, compared to a case where the reset operation is not performed, the gate-source voltage of the first switching transistor can be increased, and the charging rate of the pixel can be improved.

[0090] According to an embodiment, the electronic device 1100 can be any electronic device including an organic light-emitting display device 1160, such as a mobile phone, a smart phone, a tablet computer, a digital television, a 3D TV, a personal computer (PC), a home electronic device, a laptop computer, a personal digital assistant (PDA), a portable multimedia player (PMP), a digital camera, a music player, a portable game console, a navigation system, etc.

[0091] Industrial applicability

[0092] The present invention can be applied to any organic light-emitting display device and electronic devices including the same. For example, the present invention can be applied to mobile phones, smart phones, tablet computers, TVs, digital TVs, 3D TVs, PCs, home electronic devices, laptop computers, PDAs, PMPs, digital cameras, music players, portable game consoles, and navigation systems.

[0093] Although the present invention has been described above with reference to the embodiments, it will be understood by those skilled in the art that various modifications and changes may be made to the present invention without departing from the scope of the ideas and concepts of the present invention as described in the claims.

Claims

1. A pixel of an organic light-emitting display device, characterized in that: include: a storage capacitor connected between the first node and the second node; a first switching transistor, connecting the data line to the first node in response to a scan signal; a driving transistor that generates a driving current based on the voltage of the first node; a second switch transistor, connecting the initialization line to the second node in response to an initialization signal; as well as an organic light emitting diode that emits light based on the driving current, The pixel performs a first reset operation and a second reset operation, wherein the first reset operation resets the first node to the first initialization voltage of the initialization line in the first interval of the previous horizontal time, and the second reset operation resets the first node to a second initialization voltage lower than the first initialization voltage in the second interval of the previous horizontal time.

2. The pixel of the organic light emitting display device according to claim 1, wherein: The second initialization voltage is lower than the lowest data voltage.

3. The pixel of the organic light emitting display device according to claim 1, wherein: The scanning signal has a cutoff voltage in the first interval and the second interval of the previous horizontal time, The initialization signal has a conduction voltage in the first interval and the second interval of the previous horizontal time. The first switching transistor is turned off in the first interval and the second interval of the previous horizontal time in response to the scan signal having the turn-off voltage, The second switching transistor is turned on in response to the initialization signal having the turn-on voltage during the first interval and the second interval of the previous horizontal time.

4. The pixel of the organic light emitting display device according to claim 1, wherein: The scan signal and the initialization signal have an on-voltage in a first interval of a current horizontal time, and have an off-voltage in a second interval of the current horizontal time.

5. The pixel of the organic light emitting display device according to claim 4, wherein: The first switching transistor transmits the data voltage of the data line to the first node in response to the scan signal having the turn-on voltage in the first interval of the current horizontal time. The second switching transistor transmits the first initialization voltage of the initialization line to the second node in response to the initialization signal having the turn-on voltage during the first interval of the current horizontal time.

6. The pixel of the organic light emitting display device according to claim 5, wherein: An initial gate-source voltage of the first switching transistor at a start time point of the first interval of the current horizontal time is a constant voltage.

7. The pixel of the organic light emitting display device according to claim 6, wherein: The initial gate-source voltage of the first switching transistor is a voltage obtained by subtracting the second initialization voltage from the turn-on voltage of the scan signal.

8. The pixel of the organic light emitting display device according to claim 5, wherein: A final gate-source voltage of the first switching transistor at an end time point of the first interval of the current horizontal time is changed according to the data voltage.

9. The pixel of the organic light emitting display device according to claim 8, wherein: The final gate-source voltage of the first switching transistor is a voltage obtained by subtracting the data voltage from the turn-on voltage of the scan signal.

10. The pixel of the organic light emitting display device according to claim 5, wherein: In the first section of the current horizontal time, a direction of a current path formed between the data line and the first node is constant regardless of a voltage level of the data voltage.

11. The pixel of the organic light emitting display device according to claim 10, wherein: In the first interval of the current horizontal time, the current path is formed to have a direction from the data line to the first node.

12. The pixel of the organic light emitting display device according to claim 1, wherein: The storage capacitor includes a first electrode connected to the first node and a second electrode connected to the second node, The first switching transistor includes a gate for receiving the scan signal, a first terminal connected to the data line, and a second terminal connected to the first node. The driving transistor includes a gate connected to the first node, a first terminal receiving a first power supply voltage, and a second terminal connected to the second node. The second switch transistor includes a gate receiving the initialization signal, a first terminal connected to the second node, and a second terminal connected to the initialization line. The organic light emitting diode includes an anode connected to the second node and a cathode receiving a second power supply voltage.

13. The pixel of the organic light emitting display device according to claim 1, wherein: The first switch transistor, the driving transistor, and the second switch transistor are NMOS transistors.

14. A pixel of an organic light-emitting display device, characterized in that: include: a storage capacitor comprising a first electrode connected to the first node and a second electrode connected to the second node; a first switch transistor comprising a gate for receiving a scan signal, a first terminal connected to a data line, and a second terminal connected to the first node; a driving transistor comprising a gate connected to the first node, a first terminal receiving a first power supply voltage, and a second terminal connected to the second node; a second switch transistor comprising a gate for receiving an initialization signal, a first terminal connected to the second node, and a second terminal connected to an initialization line; as well as an organic light emitting diode comprising an anode connected to the second node and a cathode receiving a second power supply voltage, The pixel performs a first reset operation and a second reset operation, wherein the first reset operation resets the first node to the first initialization voltage of the initialization line in the first interval of the previous horizontal time, and the second reset operation resets the first node to a second initialization voltage lower than the first initialization voltage in the second interval of the previous horizontal time.

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