Data reading and writing method, device, computer equipment and storage medium

Abstract

The present invention relates to a data reading and writing method, apparatus, computer equipment, and storage medium. The data writing method comprises: in response to at least two write operation instructions, combining first data corresponding to the at least two write operation instructions in a time sequence to obtain second data; and writing the second data into a write cache based on corresponding write channels. In response to at least two write operation instructions, the present invention combines first data corresponding to the at least two write operation instructions in a time sequence to obtain second data, and writes the second data into the write cache based on corresponding write channels. Compared to the prior art, in which each write operation instruction corresponds to a write cache and a write channel, the write cache area and the number of write channels are reduced, the burden of write arbitration is reduced, and thus read and write efficiency is improved.

Description

Technical Field

[0001] The present application relates to the field of data storage, and in particular to a data reading and writing method, apparatus, computer equipment, and storage medium. Background Art

[0002] In data processing, processing modules often perform memory DDR operations in the middle of output processing. To ensure the real-time performance of algorithm processing and data conversion in different clock domains, read-write cache is needed. If a processing module needs to read and write memory DDR multiple times, it is necessary to match a read-write cache and a read-write channel for each read-write operation, and implement read and write through read-write arbitration, such as Figure 1 As shown, this will result in a larger area of ​​the entire read and write cache, and will also cause a higher burden on the DDR read and write arbitration, reducing the read and write efficiency. Summary of the Invention

[0003] Based on this, it is necessary to provide a data reading and writing method, device, computer equipment and storage medium to address the above technical problems.

[0004] In a first aspect, an embodiment of the present invention provides a data writing method, the method comprising:

[0005] In response to at least two write operation instructions, combining first data corresponding to the at least two write operation instructions in a time sequence to obtain second data;

[0006] The second data is written into the write cache based on the corresponding write channel.

[0007] The present invention responds to at least two write operation instructions, combines the first data corresponding to the at least two write operation instructions in a time sequence to obtain second data, and writes the second data into a write cache based on the corresponding write channel. Compared with the prior art, each write operation instruction corresponds to a write cache and a write channel, which reduces the area of ​​the write cache and the number of write channels, reduces the burden of write arbitration, and thus improves read and write efficiency.

[0008] In one embodiment, in response to at least two write operation instructions, combining first data corresponding to the at least two write operation instructions in a time sequence to obtain second data includes:

[0009] Determining whether a bit splicing operation is required based on the first data respectively corresponding to the at least two write operation instructions;

[0010] If so, performing a bit splicing operation on the first data corresponding to the at least two write operation instructions respectively to obtain second data; if not, combining the first data corresponding to the at least two write operation instructions respectively according to a preset first timing rule to obtain second data.

[0011] In one embodiment, determining whether a bit splicing operation is required based on the first data respectively corresponding to the at least two write operation instructions includes:

[0012] Determine whether the bit width of the first data is an integer multiple of the number of bytes written to the write cache each time. If so, no bit splicing operation is required; if not, a bit splicing operation is required.

[0013] In one embodiment, performing a bit splicing operation on the first data corresponding to the at least two write operation instructions to obtain the second data includes:

[0014] Splitting the first data respectively corresponding to the at least two write operation instructions according to a preset second timing rule;

[0015] Performing bit-wise splicing on the split first data according to a preset third timing rule to obtain second data;

[0016] Wherein, the total amount of the first data corresponding to the at least two write operation instructions in M ​​clock cycles is equal to the total amount of the second data in N clock cycles;

[0017] Wherein, M and N are unequal integers.

[0018] In a second aspect, an embodiment of the present invention provides a data reading method, the method comprising:

[0019] In response to at least one read operation instruction, obtain corresponding second data from the read cache; wherein the second data is obtained from the write cache and is obtained by combining first data corresponding to at least two write operation instructions in a time sequence;

[0020] Splitting the second data according to time sequence to obtain at least two first data;

[0021] The first data corresponding to the at least one read operation instruction is read based on the corresponding read channel.

[0022] The present invention obtains corresponding second data from a read cache in response to at least one read operation instruction; wherein, the second data is obtained from a write cache and is obtained by combining the first data corresponding to at least two write operation instructions in a time sequence, the second data is split according to the time sequence to obtain at least two first data, and the first data corresponding to the at least one read operation instruction is read based on the corresponding read channel. Compared with the prior art, each read operation instruction corresponds to a read cache and a read channel, which reduces the area of ​​the read cache and the number of read channels, reduces the burden of read arbitration, and thus improves read and write efficiency.

[0023] In one embodiment, splitting the second data in time sequence to obtain at least two first data includes:

[0024] Determining whether a de-splicing operation is required based on the second data;

[0025] If so, performing a de-splicing operation on the second data to obtain at least two first data; if not, performing a corresponding splitting operation on the second data based on a preset first timing rule to obtain at least two first data.

[0026] In one embodiment, determining whether a de-splicing operation is required based on the second data includes:

[0027] Determine whether the bit width of the first data is an integer multiple of the number of bytes read each time by the read cache. If so, no de-splicing operation is required; if not, a de-splicing operation is required.

[0028] In one embodiment, the de-splicing operation on the second data includes:

[0029] De-splicing the second data accordingly based on a preset third time sequence rule;

[0030] Merging the de-joined second data based on a preset second time sequence rule;

[0031] The total amount of the second data in N clock cycles is equal to the total amount of the first data in M ​​clock cycles.

[0032] In a third aspect, an embodiment of the present invention provides a data writing device, the device comprising:

[0033] a timing combination module, configured to, in response to at least two write operation instructions, combine first data corresponding to the at least two write operation instructions according to a timing sequence to obtain second data;

[0034] A writing module is configured to write the second data into a write cache based on a corresponding writing channel.

[0035] In a fourth aspect, an embodiment of the present invention provides a data reading device, comprising:

[0036] an acquisition module, configured to acquire corresponding second data from a read cache in response to at least one read operation instruction; wherein the second data is acquired from a write cache and is obtained by combining first data corresponding to at least two write operation instructions in a time sequence;

[0037] a time sequence splitting module, configured to split the second data according to the time sequence to obtain at least two first data;

[0038] A reading module, configured to read the first data corresponding to the at least one read operation instruction

[0039] In a fifth aspect, an embodiment of the present invention provides a computer device, comprising a memory and a processor, wherein the memory stores a computer program, and when the processor executes the computer program, the following steps are implemented:

[0040] In response to at least two write operation instructions, combining first data corresponding to the at least two write operation instructions in a time sequence to obtain second data;

[0041] Writing the second data into a write cache based on a corresponding write channel; or

[0042] In response to at least one read operation instruction, obtain corresponding second data from the read cache; wherein the second data is obtained from the write cache and is obtained by combining first data corresponding to at least two write operation instructions in a time sequence;

[0043] Splitting the second data according to time sequence to obtain at least two first data;

[0044] The first data corresponding to the at least one read operation instruction is read based on the corresponding read channel.

[0045] In a sixth aspect, an embodiment of the present invention provides a computer-readable storage medium having a computer program stored thereon, wherein when the processor executes the computer program, the following steps are implemented:

[0046] In response to at least two write operation instructions, combining first data corresponding to the at least two write operation instructions in a time sequence to obtain second data;

[0047] Writing the second data into a write cache based on a corresponding write channel; or

[0048] In response to at least one read operation instruction, obtain corresponding second data from the read cache; wherein the second data is obtained from the write cache and is obtained by combining first data corresponding to at least two write operation instructions in a time sequence;

[0049] Splitting the second data according to time sequence to obtain at least two first data;

[0050] The first data corresponding to the at least one read operation instruction is read based on the corresponding read channel. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] Figure 1 Schematic diagram of the flow of read and write operations in the prior art;

[0052] Figure 2 This is an application environment diagram of a data reading and writing method in one embodiment;

[0053] Figure 3 1 is a flow chart of a data writing method according to an embodiment;

[0054] Figure 4 A schematic diagram of a flow chart of determining whether a bit splicing method is required in one embodiment;

[0055] Figure 5 1 is a flow chart of a method for mid-splicing according to an embodiment;

[0056] Figure 6 is a schematic diagram of a timing combination in an example embodiment;

[0057] Figure 7 is a schematic diagram of a timing combination in another exemplary embodiment;

[0058] Figure 8 1 is a flow chart of a data reading method according to an embodiment;

[0059] Figure 9 A schematic diagram of a flow chart of a method for determining whether de-splicing is required in one embodiment;

[0060] Figure 10 A schematic flow chart of a method for de-splicing in one embodiment;

[0061] Figure 11 is a structural diagram of a data writing device in one embodiment;

[0062] Figure 12 is a structural diagram of a data reading device in one embodiment;

[0063] Figure 13 FIG. 1 is a diagram showing the internal structure of a computer device in one embodiment. DETAILED DESCRIPTION

[0064] In order to make the purpose, technical solutions and advantages of this application more clear, the following further describes this application in detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain this application and are not intended to limit this application.

[0065] It should be noted that the terms "first", "second", etc. in the description and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0066] The method embodiments provided in the embodiments of the present application can be executed in a mobile terminal, a computer terminal or a similar computing device. Taking running on a mobile terminal as an example, Figure 2 FIG. 1 is a hardware structure diagram of a mobile terminal according to an embodiment of the present invention. Figure 2 As shown, the mobile terminal may include one or more ( Figure 2 Only one is shown in the figure) processor 102 (processor 102 may include but is not limited to a microprocessor MCU or a programmable logic device FPGA and other processing devices) and a memory 104 for storing data. Optionally, the mobile terminal may also include a transmission device 106 and an input and output device 108 for communication functions. It will be understood by those skilled in the art that Figure 2 The structure shown is only for illustration and does not limit the structure of the mobile terminal. Figure 2 More or fewer components than shown, or with Figure 1 Different configurations shown.

[0067] The memory 104 can be used to store computer programs, for example, software programs and modules of application software, such as the computer program corresponding to the data writing method in the embodiment of the present invention. The processor 102 executes various functional applications and data processing by running the computer program stored in the memory 104, that is, implementing the above-mentioned method. The memory 104 may include a high-speed random access memory and may also include a non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some examples, the memory 104 may further include a memory remotely located relative to the processor 102, and these remote memories may be connected to the mobile terminal via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0068] The transmission device 106 is used to receive or send data via a network. A specific example of the aforementioned network may include a wireless network provided by the mobile terminal's communications provider. In one embodiment, the transmission device 106 includes a network interface controller (NIC), which can be connected to other network devices via a base station to enable communication with the Internet. In one embodiment, the transmission device 106 may be a radio frequency (RF) module, which is used to communicate with the Internet wirelessly.

[0069] In one embodiment, if Figure 3 As shown, a data writing method is provided, which is applied to Figure 2 The following steps are used as an example to illustrate the terminal in the figure:

[0070] S202: In response to at least two write operation instructions, combine first data corresponding to the at least two write operation instructions in a time sequence to obtain second data.

[0071] S204: Writing the second data into the write cache based on the corresponding write channel.

[0072] In this embodiment, after the first data corresponding to at least two write operation instructions are combined in time sequence to obtain the second data, only one write channel and one write buffer are required to execute the at least two write operation instructions, thereby writing the second data into the write buffer based on the corresponding write channel. Compared to the prior art, each write operation instruction corresponds to a write buffer and a write channel, which reduces the write buffer area and the number of write channels, reduces the burden of write arbitration, and thus improves read and write efficiency.

[0073] Before the first data is combined in a time-sequential manner, valid data in the first data must be confirmed. This valid data confirmation is the minimum amount of data that needs to be written or read per unit time to ensure real-time data processing, measured in bits per second. For example, if the effective writing resolution is w*h (width * height), the frame rate is f, the data bit width is l, and the number of channels is n, then the effective data written per unit time is: T = w*h*f*l*n.

[0074] In one embodiment, if Figure 4 As shown, in response to at least two write operation instructions, the method for combining first data corresponding to the at least two write operation instructions in a time sequence to obtain second data includes the following steps:

[0075] S302: Determine whether a bit splicing operation is required based on first data respectively corresponding to the at least two write operation instructions;

[0076] S304: If yes, perform a bit splicing operation on the first data corresponding to the at least two write operation instructions to obtain second data; if no, combine the first data corresponding to the at least two write operation instructions according to a preset first timing rule to obtain second data.

[0077] Considering that the write cache is stored in bytes (8 bits), the minimum unit is 8 bits. If the bit width of the first data is an integer multiple of the number of bytes written to the write cache each time, that is, an integer multiple of 8, then the bit splicing operation is not required. If the bit width of the first data is not an integer multiple of the number of bytes written to the write cache each time, that is, not an integer multiple of 8, then the bit splicing operation is required.

[0078] For example, if the bit width of the first data is l = 10 bits, if the bit concatenation operation is not performed, a write buffer with a width of at least 16 bits is required to write the first data, and the extra 6 bits are left unused, resulting in wasted space. In this embodiment, multiple 10-bit data are concatenated to obtain multiple 8-bit integer multiples of the second data, that is, four 10-bit data are concatenated to obtain five 8-bit data, which does not waste bit width and thus reduces cache.

[0079] For another example, if the bit width of the first data is 8 bits, which is an integer multiple of the bytes written to the write cache, then no bit splicing operation is required. Instead, the first data is combined according to a preset first timing rule to obtain the second data, which is then written to the write cache in sequence. The preset first timing rule is based on the number and timing of write operation instructions. If there are three write operation instructions, and the timing is A, B, and C, then the first valid data among A, B, and C is arranged in sequence according to the timing, and the second data is obtained by combining them in this order.

[0080] In one embodiment, if Figure 5 As shown, the method of performing a bit splicing operation on the first data corresponding to the at least two write operation instructions to obtain the second data includes the following steps:

[0081] S402: Splitting the first data corresponding to the at least two write operation instructions according to a preset second timing rule;

[0082] S404: performing bit splicing on the split first data according to a preset third timing rule to obtain second data.

[0083] The total amount of first data corresponding to the at least two write operation instructions in M ​​clock cycles is equal to the total amount of second data in N clock cycles; wherein M and N are unequal integers.

[0084] In this embodiment, the preset second timing rule can be set according to actual needs, and only needs to meet the condition that the total amount of first data within M clock cycles corresponding to at least two write operation instructions is equal to the total amount of second data within N clock cycles. The preset third timing rule corresponds to the preset second timing rule.

[0085] In this embodiment, the total amount of first data corresponding to at least two write operation instructions in M ​​clock cycles is equal to the total amount of second data in N clock cycles. That is, by adjusting the operating frequency of the write cache, the write cache is ensured to have a total data throughput in a single clock cycle equal to the throughput of the processing module in a single clock cycle at the minimum operating frequency.

[0086] Assume a processing module p, running at a clock frequency c, with m read channels and n write channels. The data bit width of each channel is l, and the effective storage resolution is w*h (width*height). Then, the data throughput per unit clock of the processing module, i.e., one clock cycle, is (m+n)*l. If, using the existing solution, each cache module also runs at a clock frequency of c, the write cache bit width is b, where b is a multiple of 8 of the nearest neighbor greater than l (for example, if l=10, then the multiple of 8 of the nearest neighbor greater than 10 is 16, so b=16). To ensure real-time performance, it is necessary to ensure that the total data throughput of the write cache in a single clock cycle is greater than or equal to the throughput of the processing module in a single clock cycle, i.e., (m+n)*b. The depth of the write cache is generally one row, i.e., the effective resolution width w (the cache depth is generally selected optimally based on the system and is not strictly limited, but it must be ensured that the write cache cannot be filled or read empty). The total required cache size is (m+n)*w*b.

[0087] The method in this embodiment is to reduce the write cache through timing combination. When performing timing combination, it is also necessary to follow that the total effective data throughput of the cache in a single clock cycle is greater than or equal to the effective throughput of the module in a single clock cycle, where equal throughput is the lowest cost solution. In this embodiment, the design is based on equality. Only one write channel is retained through the timing combination. According to the principle that the read throughput and the write throughput are equal, the calculation identity m*l=1*b (the effective throughput of the processing module in a single clock cycle) normalized to the read in a single clock cycle = (only one channel is retained after the timing combination, and the effective throughput of the cache with a bit width of b in a single clock cycle); it can be obtained that b=m*l; but b is an integer multiple of 8, and m*l may not necessarily be satisfied. In order to ensure that the above equation is satisfied, the operating clock frequency of the cache module needs to be changed. After rewriting, it is b*f br =m*l*f c ; where f br Represents the working frequency of the read cache, f c represents the operating frequency of the processing module p; then f br =(m*l / b)*f c , using cycle representation: Where T br f br The reciprocal of fc is the clock cycle of the read cache. Tc is the reciprocal of fc, which is the clock cycle of the processing module. Since m*l / b may not be an integer, multiple clock cycles need to be used when using bit splicing operations. Let c be the greatest common divisor of m*l and b. m, l, c, x are all positive integers, y, b, c are also positive integers. Substituting them into the equation we get:

[0088] From the above equation, it can be seen that the total data used in the processing module takes y clock cycles, and the write cache takes x clock cycles to read. The method used in this embodiment requires a total cache size of (m+n)*w*l, which is smaller than the cache size required by the existing solution (m+n)*w*b.

[0089] In an example embodiment, Figure 6 As shown, the first data corresponding to each write operation instruction has one valid data every three clock cycles. Assuming that the valid data bit width l = 16 bits is an integer multiple of byte (8 bits), and the write cache bit width b = 16 bits, no bit splicing operation is required. The effective data throughput of the processing module in a single clock cycle is m*l / 3 = 3 (number of channels) * 16 (bit width) / 3 (only one valid data every three clock cycles) = 16 bits. m*l / 3*b = 1, it can be obtained that the clock cycle of the write cache is equal to the clock cycle of the processing module, that is, f b =f c That is, the processing module has only 16 bits of valid data in one clock cycle. By combining the timing and rearranging the timing according to the preset first timing rule, there are 16 bits of valid data in each clock cycle. Each clock cycle corresponds to the data of one channel, and the cache depth remains unchanged, thus saving 2 / 3 of the write channels and cache area.

[0090] In another example embodiment, Figure 7 As shown, the bit width of the first data corresponding to n (n=4) write operation instructions is l=10 bits, and the working clock frequency is f c The cycle is Tc. The write bit width of the write cache is b = 64 bits. According to the above calculation formula m*l = n*l = 40, b = 64. The greatest common divisor of 40 and 64 is c = 8. Assume that the cache cycle is Tb and the operating frequency is fb, then according to x*T b =y*T c →5*T b =8*T c The data volume of the processing module in 8 clock cycles is 8*m*l=320 bits. The write cache uses 5 clock cycles to process 5*64=320 bits. The cache operating frequency fb=fc*5 / 8=0.625fc.

[0091] The 320-bit first data of 8 clocks in the processing module is regarded as a completed unit, and then a bit splicing operation is performed to obtain the second data. The 320 bits are allocated to the corresponding 5 clock cycles with each 64 bits as a unit. Only one write channel and one write cache are required, thereby saving 3 channels and 3 caches.

[0092] In one embodiment, if Figure 8 As shown, a data reading method is provided, which is applied to Figure 2 The following steps are used as an example to illustrate the terminal in the figure:

[0093] S502: Retrieve corresponding second data from a read cache in response to at least one read operation instruction; wherein the second data is retrieved from a write cache and is obtained by combining first data corresponding to at least two write operation instructions in a time sequence;

[0094] S504: Split the second data according to the time sequence to obtain at least two first data;

[0095] S506: Read first data corresponding to the at least one read operation instruction based on the corresponding read channel.

[0096] In this embodiment, the second data is obtained by combining the first data corresponding to at least two write operation instructions in a time sequence, and is output from the write cache to the memory, and is output from the memory to the read cache.

[0097] In this embodiment, the first data corresponding to at least two write operation instructions are combined in time sequence to generate the second data. Only one read channel and one read buffer are required to read the data. Compared to the prior art, each read operation instruction corresponds to a read buffer and a read channel. This reduces the read buffer area and the number of read channels, reduces the burden of read arbitration, and thus improves read and write efficiency.

[0098] In one embodiment, if Figure 9 As shown, the method of splitting the second data according to the time sequence to obtain at least two first data includes the following steps:

[0099] S602: Determine whether a de-splicing operation is required based on the second data;

[0100] S604: If yes, perform a de-joining operation on the second data to obtain at least two first data; if no, perform a corresponding splitting operation on the second data based on a preset first time sequence rule to obtain at least two first data.

[0101] It is understood that if the second data is obtained through a bit-splicing operation, a corresponding de-splicing operation is required, and if the second data is not obtained through a bit-splicing operation, a de-splicing operation is not required. In other words, it is determined whether the bit width of the first data is an integer multiple of the number of bytes read per read buffer. If so, a de-splicing operation is not required; if not, a de-splicing operation is required.

[0102] In one embodiment, if Figure 10As shown, the method for performing a de-splicing operation on the second data includes the following steps:

[0103] S702: De-splicing the second data based on a preset third time sequence rule;

[0104] S704: Merging the de-joined second data based on a preset second time sequence rule;

[0105] The total amount of the second data in N clock cycles is equal to the total amount of the first data in M ​​clock cycles.

[0106] It can be understood that de-splicing is the reverse operation of bit splicing, and merging the de-splicing second data is also the reverse operation of splitting the second data according to time sequence. Therefore, the second data is de-splicing based on the preset third time sequence rule, and the de-splicing second data is merged based on the preset second time sequence rule.

[0107] It can be understood that the requirements met in bit splicing also need to be met accordingly in de-splicing, that is, the total amount of data of the second data in N clock cycles is equal to the total amount of data of the first data in M ​​clock cycles, that is, by adjusting the operating frequency of the read cache, the read cache is ensured to have a total data throughput of the read cache in a single clock cycle at the minimum operating frequency, which is equal to the throughput of the processing module in a single clock cycle.

[0108] It should be understood that although Figure 1-10 The steps in the flowchart are shown in sequence as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. In addition, Figure 1-10 At least part of the steps may include multiple steps or multiple stages. These steps or stages are not necessarily performed at the same time, but can be performed at different times. The order of execution of these steps or stages is not necessarily one by one, but can be performed in turn or alternately with other steps or at least part of the steps or stages in other steps.

[0109] In one embodiment, if Figure 11 As shown, the present invention provides a data writing device, the device comprising:

[0110] A timing combination module 802 is configured to, in response to at least two write operation instructions, combine first data corresponding to the at least two write operation instructions according to a timing sequence to obtain second data;

[0111] The writing module 804 is configured to write the second data into the write cache based on the corresponding writing channel.

[0112] In one embodiment, the timing combination module is specifically configured to:

[0113] Determining whether a bit splicing operation is required based on the first data respectively corresponding to the at least two write operation instructions;

[0114] If so, performing a bit splicing operation on the first data corresponding to the at least two write operation instructions respectively to obtain second data; if not, combining the first data corresponding to the at least two write operation instructions respectively according to a preset first timing rule to obtain second data.

[0115] In one embodiment, determining whether a bit splicing operation is required based on the first data respectively corresponding to the at least two write operation instructions includes:

[0116] Determine whether the bit width of the first data is an integer multiple of the number of bytes written to the write cache each time. If so, no bit splicing operation is required; if not, a bit splicing operation is required.

[0117] In one embodiment, performing a bit splicing operation on the first data corresponding to the at least two write operation instructions to obtain the second data includes:

[0118] Splitting the first data respectively corresponding to the at least two write operation instructions according to a preset second timing rule;

[0119] Performing bit-wise splicing on the split first data according to a preset third timing rule to obtain second data;

[0120] Wherein, the total amount of the first data corresponding to the at least two write operation instructions in M ​​clock cycles is equal to the total amount of the second data in N clock cycles;

[0121] Wherein, M and N are unequal integers.

[0122] In one embodiment, if Figure 11 As shown, the present invention provides a data reading device, the device comprising:

[0123] An acquisition module 902 is configured to acquire corresponding second data from a read cache in response to at least one read operation instruction; wherein the second data is acquired from a write cache and is obtained by combining first data corresponding to at least two write operation instructions in a time sequence;

[0124] A time sequence splitting module 904 is configured to split the second data according to the time sequence to obtain at least two first data;

[0125] The reading module 906 is configured to read the first data corresponding to the at least one read operation instruction.

[0126] In one embodiment, the timing splitting module is specifically configured to:

[0127] Determining whether a de-splicing operation is required based on the second data;

[0128] If so, performing a de-splicing operation on the second data to obtain at least two first data; if not, performing a corresponding splitting operation on the second data based on a preset first timing rule to obtain at least two first data.

[0129] In one embodiment, determining whether a de-splicing operation is required based on the second data includes:

[0130] Determine whether the bit width of the first data is an integer multiple of the number of bytes read each time by the read cache. If so, no de-splicing operation is required; if not, a de-splicing operation is required.

[0131] In one embodiment, the de-splicing operation on the second data includes:

[0132] De-splicing the second data accordingly based on a preset third time sequence rule;

[0133] Merging the de-joined second data based on a preset second time sequence rule;

[0134] The total amount of the second data in N clock cycles is equal to the total amount of the first data in M ​​clock cycles.

[0135] For the specific definition of the data writing device, please refer to the definition of the data writing method above and will not be repeated here. Each module in the above-mentioned data writing device can be implemented in whole or in part by software, hardware, or a combination thereof. Each of the above-mentioned modules can be embedded in or independent of the processor in the computer device in hardware form, or can be stored in the memory of the computer device in software form, so that the processor can call and execute the corresponding operations of each of the above modules.

[0136] In one embodiment, a computer device is provided. The computer device may be a server, and its internal structure diagram may be as shown in FIG. Figure 12As shown. The computer device includes a processor, a memory, and a network interface connected via a system bus. The processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program, and a database. The internal memory provides an environment for the operation of the operating system and computer program in the non-volatile storage medium. The database of the computer device is used to store motion detection data. The network interface of the computer device is used to communicate with an external terminal via a network connection. When the computer program is executed by the processor, the steps of any of the above-mentioned data writing or reading method embodiments are implemented.

[0137] Those skilled in the art will understand that Figure 12 The structure shown in the figure is only a block diagram of a part of the structure related to the solution of the present application, and does not constitute a limitation on the computer device to which the solution of the present application is applied. The specific computer device may include more or fewer components than shown in the figure, or combine certain components, or have a different component arrangement.

[0138] In one embodiment, a computer device is provided, including a memory and a processor, wherein a computer program is stored in the memory, and when the processor executes the computer program, the steps of any of the above-mentioned data writing or reading method embodiments are implemented.

[0139] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the steps of any of the above-mentioned data writing or reading method embodiments are implemented.

[0140] Those skilled in the art will appreciate that all or part of the processes in the above-mentioned embodiment methods can be implemented by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to memory, storage, database or other media used in the embodiments provided in this application may include at least one of non-volatile and volatile memory. Non-volatile memory may include read-only memory (ROM), magnetic tape, floppy disk, flash memory or optical memory, etc. Volatile memory may include random access memory (RAM) or external cache memory. As an illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM).

[0141] The technical features of the above embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0142] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that a person skilled in the art could make various modifications and improvements without departing from the spirit of the present application, all of which fall within the scope of protection of the present application. Therefore, the scope of protection of the present patent application shall be determined by the appended claims.

Claims

1. A data writing method, characterized in that: The method comprises: In response to at least two write operation instructions, combining first data corresponding to the at least two write operation instructions in a time sequence to obtain second data; Writing the second data into a unique write cache based on a unique write channel; In response to at least two write operation instructions, combining first data corresponding to the at least two write operation instructions in a time sequence to obtain second data includes: determining, based on first data respectively corresponding to the at least two write operation instructions, whether a bit width of the first data is an integer multiple of a number of bytes written to the write cache each time; If not, performing a bit splicing operation on the first data corresponding to the at least two write operation instructions to obtain second data; if so, combining the first data corresponding to the at least two write operation instructions according to a preset first timing rule to obtain second data; The first data corresponding to the at least two write operation instructions are respectively in M The total amount of data in a clock cycle is equal to the second data N The total amount of data in each clock cycle is equal; in, M 、 N Are not equal integers.

2. The method according to claim 1, characterized in that The performing a bit splicing operation on the first data respectively corresponding to the at least two write operation instructions to obtain the second data includes: Splitting the first data respectively corresponding to the at least two write operation instructions according to a preset second timing rule; The split first data is bit-joined according to a preset third timing rule to obtain second data.

3. A data reading method, characterized in that: The method comprises: In response to at least one read operation instruction, obtain corresponding second data from a unique read cache; wherein the second data is obtained from the write cache and is obtained by combining first data corresponding to at least two write operation instructions in a time sequence; Splitting the second data according to time sequence to obtain at least two first data; Reading first data corresponding to the at least one read operation instruction based on a unique read channel; The step of splitting the second data according to the time sequence to obtain at least two first data includes: Based on the second data, determining whether a bit width of the first data is an integer multiple of a number of bytes read each time from the read cache; If not, performing a de-joining operation on the second data to obtain at least two first data; if yes, performing a corresponding splitting operation on the second data based on a preset first time sequence rule to obtain at least two first data; Wherein, the second data is N The total amount of data in a clock cycle is equal to the first data M The total amount of data in each clock cycle is equal; in, M 、 N Are not equal integers.

4. The method according to claim 3, characterized in that The de-splicing operation on the second data includes: De-splicing the second data accordingly based on a preset third time sequence rule; The de-joined second data are merged based on a preset second timing rule.

5. A data writing device, characterized in that: The device comprises: a timing combination module, configured to, in response to at least two write operation instructions, combine first data corresponding to the at least two write operation instructions in a timing sequence to obtain second data; A writing module, configured to write the second data into a unique write cache based on a unique write channel; The timing combination module is specifically used for: determining, based on first data respectively corresponding to the at least two write operation instructions, whether a bit width of the first data is an integer multiple of a number of bytes written to the write cache each time; If not, performing a bit splicing operation on the first data corresponding to the at least two write operation instructions to obtain second data; if so, combining the first data corresponding to the at least two write operation instructions according to a preset first timing rule to obtain second data; The first data corresponding to the at least two write operation instructions are respectively in M The total amount of data in a clock cycle is equal to the second data N The total amount of data in each clock cycle is equal; in, M 、 N Are not equal integers.

6. A data reading device, characterized in that: The device comprises: an acquisition module, configured to acquire corresponding second data from a unique read cache in response to at least one read operation instruction; wherein the second data is acquired from the write cache and is obtained by combining first data corresponding to at least two write operation instructions in a time sequence; a time sequence splitting module, configured to split the second data according to the time sequence to obtain at least two first data; a reading module, configured to read first data corresponding to the at least one read operation instruction based on a unique read channel; The timing splitting module is specifically used for: Based on the second data, determining whether a bit width of the first data is an integer multiple of a number of bytes read each time from the read cache; If not, performing a de-joining operation on the second data to obtain at least two first data; if yes, performing a corresponding splitting operation on the second data based on a preset first time sequence rule to obtain at least two first data; Wherein, the second data is N The total amount of data in a clock cycle is equal to the first data M The total amount of data in each clock cycle is equal; in, M 、 N Are not equal integers.

7. A computer device comprising a memory and a processor, wherein the memory stores a computer program, wherein: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 2 or any one of claims 3 to 4 are implemented.

8. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 2 or claims 3 to 4 are implemented.

Images