Display substrate and display device

Abstract

A display substrate and a display device. The display substrate has a first side for display and a second side opposite to the first side, and includes: a base substrate, a display area, at least one connecting wire and at least one switching electrode. Each of the at least one connecting wire at least partially extends along the first direction, and is connected to the first power line respectively connected to the first pixel unit group of the adjacent first display area in the first direction; each of the at least one switching electrode at least partially extends along the first direction, and is connected to the first signal line respectively connected to the first pixel unit group of the adjacent first display area in the first direction; wherein, the film layer where at least part of the at least one switching electrode is located is different from the film layer where each of the at least one connecting wire is located, and the orthographic projection of the at least one switching electrode on the base substrate at least partially overlaps with the orthographic projection of the at least one connecting wire on the base substrate.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a display substrate and a display device. Background Art

[0002] The market demand for display panels with high screen-to-body ratio is becoming more and more urgent to provide users with a better visual experience. Taking mobile phones, tablets and other electronic products as an example, since these electronic devices need to be combined with components such as cameras and light sensors, the existing "notch screen" and "water drop screen" designs are gradually unable to meet user needs. In this context, under-screen camera technology came into being. It does not require punching holes in the screen to place the camera, making true full-screen possible. Summary of the invention

[0003] At least one embodiment of the present disclosure provides a display substrate, which has a first side for display and a second side opposite to the first side, and includes: a base substrate, a display area, at least one connecting wiring, and at least one switching electrode. The display area is arranged on the base substrate, including a first display area, the first display area allows light from the first side of the display substrate to be at least partially transmitted to the second side of the display substrate, wherein the first display area includes a first sub-pixel array, the first sub-pixel array includes a plurality of first pixel unit groups arranged in a first direction and a second direction intersecting the first direction, a plurality of first signal lines, and a plurality of first power lines, the first pixel unit group includes at least one first pixel unit, each of the plurality of first signal lines at least partially extends along the first direction, and is configured to provide a first display signal to the plurality of first pixel units, the plurality of first signal lines are connected to the first pixel units of the plurality of first pixel unit groups, the plurality of first power lines at least partially extend along the first direction, and are configured In order to provide a first power supply voltage to the multiple first pixel units, the multiple first power lines are connected to the first pixel units of the multiple first pixel unit groups; each of the at least one connecting line at least partially extends along the first direction, and is connected to the first power lines respectively connected to the adjacent first pixel unit groups in the first direction; each of the at least one switching electrode at least partially extends along the first direction, and is connected to the first signal lines respectively connected to the adjacent first pixel unit groups in the first direction; wherein, the film layer where at least part of the at least one switching electrode is located is different from the film layer where each of the at least one connecting line is located, and the orthographic projection of the at least one switching electrode on the substrate substrate at least partially overlaps with the orthographic projection of the at least one connecting line on the substrate substrate.

[0004] For example, in the display substrate provided in at least one embodiment of the present disclosure, the at least one connecting route includes a first connecting route, the first connecting route extends along the first direction, the first connecting route is connected to the first power lines respectively connected to the first pixel units adjacent in the first direction and belonging to different first pixel unit groups, and the first connecting route is arranged on the same layer as the first power line and is formed integrally.

[0005] For example, in the display substrate provided by at least one embodiment of the present disclosure, at least one first pixel unit of the first pixel unit group includes a plurality of first pixel units, and the at least one switching electrode includes a plurality of switching electrodes, and the plurality of switching electrodes are connected one-to-one with a plurality of first pixel units that are adjacent in the first direction and belong to different first pixel unit groups, and the plurality of switching electrodes are respectively located in different film layers.

[0006] For example, in the display substrate provided by at least one embodiment of the present disclosure, the plurality of first pixel units of the first pixel unit group are arranged into at least two columns parallel to each other along the second direction, the plurality of switching electrodes include a first switching electrode and a second switching electrode, the first switching electrode and the second switching electrode are arranged in parallel, the first switching electrode and the second switching electrode are connected to first signal lines respectively connected to first pixel units adjacent to each other in the first direction and belonging to different first pixel unit groups, the first switching electrode and the second switching electrode are located in different film layers, and the orthographic projections of the first switching electrode and the second switching electrode on the base substrate at least partially overlap with the orthographic projection of the first connecting line on the base substrate.

[0007] For example, in the display substrate provided in at least one embodiment of the present disclosure, the orthographic projections of the portion of the first switching electrode extending along the first direction and the portion of the second switching electrode extending along the first direction on the base substrate overlap with the orthographic projections of the portion of the first connecting trace extending along the first direction on the base substrate.

[0008] For example, in the display substrate provided in at least one embodiment of the present disclosure, there is a gap allowing light transmission between the first direction and the first pixel unit group adjacent to the second direction, and a portion of the first connecting line and a portion of each of the at least one switching electrode extend along the second direction and bypass the gap allowing light transmission.

[0009] For example, in the display substrate provided in at least one embodiment of the present disclosure, the first connecting line is a bent line and includes a first part, a second part and a third part, the first end of the first part and the first end of the second part are respectively connected to the two ends of the third part and extend along a second direction different from the first direction, the third part extends along the first direction, and the second end of the first part and the second end of the second part are respectively connected to the first power lines connected to the adjacent first pixel units in the first direction.

[0010] For example, in the display substrate provided in at least one embodiment of the present disclosure, the orthographic projections of the first switching electrode and the second switching electrode on the base substrate overlap with the orthographic projections of at least one of the first part, the second part and the third part of the first connecting trace on the base substrate.

[0011] For example, in the display substrate provided by at least one embodiment of the present disclosure, the plurality of first pixel units of the first pixel unit group include at least three columns arranged in parallel along the second direction, the at least one switching electrode includes a first switching electrode, a second switching electrode and a third switching electrode, the first switching electrode, the second switching electrode and the third switching electrode are arranged in parallel, the third switching electrode is located between the first switching electrode and the second switching electrode, the first switching electrode, the second switching electrode and the third switching electrode are respectively connected to the first signal lines connected to the first pixel units adjacent to each other in the first direction, the first switching electrode, the second switching electrode and the third switching electrode are located in different film layers, the orthographic projection of the first connecting line on the base substrate at least partially overlaps with the orthographic projection of at least one of the first switching electrode and the second switching electrode on the base substrate, and the third switching electrode is arranged on the same layer as the first connecting line.

[0012] For example, in the display substrate provided in at least one embodiment of the present disclosure, the orthographic projection of the third switching electrode on the base substrate at least partially overlaps with the orthographic projection of the first switching electrode or the second switching electrode on the base substrate.

[0013] For example, the display substrate provided by at least one embodiment of the present disclosure also includes: a first insulating layer, a second insulating layer and a third insulating layer, the first insulating layer is located on the base substrate, the second insulating layer is located on the side of the first insulating layer away from the base substrate, the third insulating layer is located on the side of the second insulating layer away from the base substrate, the multiple first signal lines, the multiple first power lines and the first connecting lines are located on the side of the third insulating layer away from the base substrate, the second transfer electrode is located on the side of the first insulating layer away from the base substrate, and is connected to the first signal line connecting the first pixel units adjacent in the first direction through a via hole passing through the second insulating layer and the third insulating layer, the first transfer electrode is located on the side of the second insulating layer away from the base substrate, and is connected to the first signal line connecting the first pixel units adjacent in the first direction through a via hole passing through the third insulating layer, and the third transfer electrode is located on the side of the third insulating layer away from the base substrate.

[0014] For example, in the display substrate provided by at least one embodiment of the present disclosure, a plurality of first pixel units of the first pixel unit group are arranged into at least one row along the second direction, and in the same row, the first pixel unit group includes at least two first pixel units, each first pixel unit of the first pixel unit group includes a first pixel driving circuit and a first light-emitting device, the first pixel driving circuit is connected to the first light-emitting device and drives the first light-emitting device to emit light, the first pixel driving circuit includes a storage capacitor, the storage capacitor includes a first electrode plate and a second electrode plate at least partially overlapping with the first electrode plate, the first electrode plate is located on a side of the second insulating layer away from the substrate, the second electrode plate is located on a side of the first insulating layer away from the substrate, the plurality of first power lines connected to each of the first pixel units are connected to the first electrode plate through a via hole penetrating the third insulating layer, and the first electrodes of at least two first pixel units of the first pixel unit group located in the same row are interconnected and formed as one.

[0015] For example, the display substrate provided by at least one embodiment of the present disclosure further includes a fourth conversion electrode, wherein the fourth conversion electrode at least partially extends along the second direction, and the fourth conversion electrode is connected to the first power lines respectively connected to the first pixel units that are staggered and adjacent to the second direction and belong to different first pixel unit groups.

[0016] For example, the display substrate provided by at least one embodiment of the present disclosure further includes a fourth conversion electrode, wherein the fourth conversion electrode extends along the second direction, and the fourth conversion electrode is connected to the first power lines respectively connected to two first pixel units that are adjacent to the second direction and belong to different first pixel unit groups.

[0017] For example, in the display substrate provided in at least one embodiment of the present disclosure, the two ends of the fourth switching electrode are respectively connected to the first electrode plates of the two adjacent first pixel units belonging to different first pixel unit groups, so as to connect the first power lines located in the different first pixel unit groups.

[0018] For example, in the display substrate provided in at least one embodiment of the present disclosure, the fourth transfer electrode is located on a side of the third insulating layer away from the base substrate, and the fourth transfer electrode is connected to the first plates of the two adjacent first pixel units that belong to different first pixel unit groups through a via hole penetrating the third insulating layer.

[0019] For example, in the display substrate provided in at least one embodiment of the present disclosure, the fourth transfer electrode is located on the side of the second insulating layer away from the base substrate, and the fourth transfer electrode is arranged in the same layer as the first plates of the two adjacent first pixel units belonging to different first pixel unit groups and formed as one.

[0020] For example, in the display substrate provided by at least one embodiment of the present disclosure, the fourth switching electrode includes a first sub-switching electrode, a second sub-switching electrode and a third sub-switching electrode, the first end of the first sub-switching electrode and the first end of the second sub-switching electrode are respectively connected to the two ends of the third sub-switching electrode, the second end of the first sub-switching electrode and the second end of the second sub-switching electrode are respectively connected to the first electrode plates of the two first pixel units that are adjacently arranged and belong to different first pixel unit groups, the first sub-switching electrode and the second sub-switching electrode are arranged in the same layer as the first electrode plates of the two first pixel units that are adjacently arranged and belong to different first pixel unit groups and are formed as one piece, the third sub-switching electrode is located on the side of the third insulating layer away from the base substrate, and the third sub-switching electrode is connected to the first sub-switching electrode and the second sub-switching electrode through a via hole that penetrates the third insulating layer.

[0021] For example, in the display substrate provided by at least one embodiment of the present disclosure, the multiple first pixel units of the first pixel unit group are arranged in multiple rows and columns, and in the same first pixel unit group, the first signal lines connected to the first pixel units in the same column are interconnected and formed as one body, and the first power lines connected to the first pixel units in the same column are also interconnected and formed as one body.

[0022] For example, in the display substrate provided in at least one embodiment of the present disclosure, the display area also includes a second display area, the second display area at least partially surrounds the first display area, the second display area includes a second sub-pixel array, the second sub-pixel array includes a plurality of second pixel units, each of the plurality of second pixel units includes a second light-emitting device and a second pixel driving circuit, the second pixel driving circuit is configured to drive the second light-emitting device to emit light, a first signal line connected to a first pixel unit close to the second display area extends to the second display area to be connected to a second pixel unit located in the first direction relative to the first pixel unit, and a first power line connected to the first pixel unit close to the second display area extends to the second display area to be connected to a second pixel unit located in the first direction relative to the first pixel unit.

[0023] For example, in the display substrate provided in at least one embodiment of the present disclosure, the pixel density of the second display area is greater than the pixel density of the first display area.

[0024] For example, the display substrate provided by at least one embodiment of the present disclosure further includes a plurality of second signal lines and a plurality of second power lines located in the second display area, wherein the plurality of second pixel units are arranged as a plurality of columns parallel to each other in the second direction, the plurality of second signal lines extend along the first direction, each of the plurality of second signal lines passes through the plurality of second pixel units arranged in a column in the first direction to provide a second display signal to the plurality of second pixel units, and the plurality of second power lines extend along the first direction, each of the plurality of second power lines passes through the plurality of second pixel units arranged in a column in the first direction to provide a second power supply voltage to the plurality of second pixel units.

[0025] At least one embodiment of the present disclosure further provides a display device, which includes any display substrate as described above.

[0026] For example, the display device provided by at least one embodiment of the present disclosure further includes a sensor, wherein the sensor is disposed on the second side of the display substrate, and the sensor is configured to receive light from the first side of the display substrate.

[0027] For example, in the display device provided in at least one embodiment of the present disclosure, the orthographic projection of the sensor on the base substrate at least partially overlaps with the first display area. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, but are not intended to limit the present disclosure.

[0029] Figure 1A A schematic plan view of a display substrate provided by at least one embodiment of the present disclosure;

[0030] Figure 1B A partially enlarged schematic diagram of a display substrate provided by at least one embodiment of the present disclosure;

[0031] Figure 1C A partially enlarged schematic diagram of a display substrate provided by at least another embodiment of the present disclosure;

[0032] Figure 1D For along Figure 1A Schematic diagram of the cross section along the midline B1-B2;

[0033] Figure 2 A schematic diagram of a planar layout of wiring in a first display area of ​​a display substrate provided by at least one embodiment of the present disclosure;

[0034] Figure 3A for Figure 2 Enlarged view of the middle A1 area;

[0035] Figure 3B for Figure 2 Enlarged view of the middle A2 area;

[0036] Figure 4A for Figure 3A A schematic cross-sectional view along line C1-C2;

[0037] Figure 4B for Figure 3A A schematic cross-sectional view along line C3-C4;

[0038] Figure 4C for Figure 3A A schematic cross-sectional view along line C5-C6;

[0039] Figure 4D for Figure 3B A schematic cross-sectional view along line C7-C8;

[0040] Figure 5A-Figure 5C for Figure 2 A plan view of each layer of wiring in the first display area shown;

[0041] Figure 5D for Figure 2 A schematic diagram of sub-pixel arrangement in the first display area is shown;

[0042] Figure 6 A schematic diagram of a planar layout of wiring in a first display area of ​​a display substrate provided in at least another embodiment of the present disclosure;

[0043] Fig. 7A for Figure 6Enlarged view of the middle A11 area;

[0044] Figure 7B for Figure 6 Enlarged view of the middle A12 area;

[0045] Figure 8 for Fig. 7A A schematic cross-sectional view along line C11-C12;

[0046] Figure 9A-9C for Figure 6 A plan view of each layer of wiring in the first display area shown;

[0047] Fig.9D for Figure 6 A schematic diagram of sub-pixel arrangement in the first display area is shown;

[0048] Fig.10 A schematic diagram of a planar layout of wiring in a first display area of ​​a display substrate provided in at least one further embodiment of the present disclosure;

[0049] Fig.11 for Fig.10 Enlarged view of the middle A21 area;

[0050] Fig.12 for Fig.11 A schematic cross-sectional view along line C21-C22;

[0051] Figure 13A-13C for Fig.10 A plan view of each layer of wiring in the first display area shown;

[0052] Fig.13D for Fig.10 A schematic diagram of sub-pixel arrangement in the first display area is shown;

[0053] Fig.14 A schematic diagram of a planar layout of wiring in a first display area of ​​a display substrate provided in at least one further embodiment of the present disclosure;

[0054] Fig.15 for Fig.14 A magnified view of the middle A31 area;

[0055] Fig.16A for Fig.15 A schematic cross-sectional view along line C31-C32;

[0056] Fig. 16B for Fig.15 A schematic cross-sectional view along line C33-C34;

[0057] Figure 17A-17C for Fig.14 A plan view of each layer of wiring in the first display area shown;

[0058] Fig.17D for Fig.14 A schematic diagram of sub-pixel arrangement in the first display area is shown;

[0059] Fig.18 A schematic diagram of a planar layout of wiring in a second display area of ​​a display substrate provided by at least one embodiment of the present disclosure;

[0060] Fig.19 An equivalent circuit diagram of a first pixel driving circuit in a first display area of ​​a display substrate provided by at least one embodiment of the present disclosure;

[0061] Fig. 20A A schematic diagram of a planar layout of a first pixel driving circuit in a first display area of ​​a display substrate provided by at least one embodiment of the present disclosure;

[0062] Figures 20B-20E A schematic diagram of various layers of a first pixel driving circuit in a first display area of ​​a display substrate provided by at least one embodiment of the present disclosure;

[0063] Fig.21 A schematic cross-sectional view of a first display area in a display substrate provided in at least one embodiment of the present disclosure;

[0064] Fig. 22 A schematic cross-sectional view of a second display area in a display substrate provided by at least one embodiment of the present disclosure;

[0065] Fig.23 A schematic diagram of a display device provided by at least one embodiment of the present disclosure. DETAILED DESCRIPTION

[0066] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0067] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, similar words such as "one", "one" or "the" do not indicate a quantitative limitation, but indicate that there is at least one. Similar words such as "include" or "comprise" mean that the elements or objects appearing in front of the word cover the elements or objects listed after the word and their equivalents. For the convenience of description, in some drawings, "up", "down", "front" and "back" are given. In the embodiment of the present disclosure, the vertical direction is the direction from top to bottom, the vertical direction is the direction of gravity, the horizontal direction is the direction perpendicular to the vertical direction, and the horizontal direction from right to left is the direction from front to back.

[0068] In recent years, mobile display technology has developed rapidly, and a new generation of display technology represented by flexible active-matrix organic light-emitting diodes (AMOLED) is being used more and more widely. AMOLED has the characteristics of being thinner and lighter, actively emitting light (no backlight is required), no viewing angle problem, high definition, high brightness, fast response, low energy consumption, wide operating temperature range, strong shock resistance, and flexible display. Since these display devices need to be combined with components such as cameras and light sensors, and these components usually occupy the display area of ​​the display screen, it is difficult to achieve a full-screen design for the display screen. In order to increase the transmittance of the camera area in the display screen and ensure the camera's photo effect, usually only the light-emitting device of the pixel circuit is retained in the camera area. However, the above technology still needs to dig out part of the display area, and the overall effect is still to form a special-shaped display area, which affects the visual experience, and the technology of placing the camera to improve the transmittance.

[0069] In order to avoid sacrificing the display area, a technology has emerged that reduces the pixel resolution PPI (Pixels Per Inch) in local areas and improves the transmittance, thereby placing a camera on the back side of the display substrate to image the display side of the display substrate. This technology places the camera in an area with low resolution PPI. In this area, due to the low resolution PPI and high light transmittance, the light on the display side of the display substrate can pass through the low PPI area to the camera on the back side of the display substrate. The horizontal and vertical cross-wiring of the pixel drive circuit forms a grating, which will still have an adverse effect on camera imaging and will also reduce the aperture ratio and transmittance of the PPI area.

[0070] At least one embodiment of the present disclosure provides a display substrate, which has a first side for display and a second side opposite to the first side, and includes: a substrate substrate, a display area, at least one connecting line and at least one switching electrode. The display area is arranged on the substrate substrate and includes a first display area, and the first display area allows light from the first side of the display substrate to be at least partially transmitted to the second side of the display substrate. The first display area includes a first sub-pixel array, and the first sub-pixel array includes a plurality of first pixel unit groups arranged in a first direction and a second direction intersecting the first direction, a plurality of first signal lines and a plurality of first power lines. The first pixel unit group includes at least one first pixel unit. Each of the plurality of first signal lines extends at least partially along the first direction, and is configured to provide a first display signal to the plurality of first pixel units, and the plurality of first signal lines are connected to the first pixel units of the plurality of first pixel unit groups. Each of the plurality of first power lines extends at least partially along the first direction, and is configured to provide a first power supply voltage to the plurality of first pixel units, and the plurality of first power lines are connected to the first pixel units of the plurality of first pixel unit groups. Each of the at least one connecting wire at least partially extends along the first direction and is connected to the first power lines respectively connected to the adjacent first pixel unit groups in the first direction. Each of the at least one switching electrode at least partially extends along the first direction and is connected to the first signal lines respectively connected to the adjacent first pixel unit groups in the first direction. The film layer where at least part of the at least one switching electrode is located is different from the film layer where the at least one connecting wire is located, and the orthographic projection of the at least one switching electrode on the substrate substrate at least partially overlaps with the orthographic projection of the at least one connecting wire on the substrate substrate.

[0071] In the display substrate provided by the above embodiment, the orthographic projection of at least one switching electrode on the base substrate at least partially overlaps with the orthographic projection of at least one connecting wire on the base substrate, thereby reducing the wiring space occupied by the switching electrodes and the connecting wires in the first display area, which is beneficial to reducing the grating effect caused by the switching electrodes and the connecting wires in the first display area, and improving the aperture ratio and transmittance of the first display area, allowing, for example, a sensor to be set in the first display area and on the second side of the display substrate for sensing (for example, imaging), and improving the sensing effect (imaging quality) of the sensor.

[0072] The embodiments and examples of the present disclosure are described in detail below with reference to the accompanying drawings.

[0073] Figure 1A A schematic plan view of a display substrate provided by at least one embodiment of the present disclosure; Figure 1B A partially enlarged schematic diagram of a display substrate provided by at least one embodiment of the present disclosure; Figure 1C A partially enlarged schematic diagram of a display substrate provided by at least another embodiment of the present disclosure; Figure 1D For along Figure 1A Schematic diagram of the cross section along the midline B1-B2.

[0074] For example, Figure 1A As shown, at least one embodiment of the present disclosure provides a display substrate 1 including a base substrate 100 and a display area. The display area is disposed on the base substrate 100, and the display area includes a first display area 10 (e.g., a light-transmitting display area) and a second display area 20 (e.g., a normal display area). The display substrate 1 may further include a peripheral area 30, and the peripheral area 30 surrounds (e.g., partially surrounds) the display area. The second display area 20 surrounds (e.g., partially surrounds) the first display area 10.

[0075] For example, the display substrate 1 provided in at least one embodiment of the present disclosure may be an organic light emitting diode (OLED) display substrate or a quantum dot light emitting diode (QLED) display substrate or other display substrates. The embodiments of the present disclosure do not limit the specific type of the display substrate.

[0076] For example, Figure 1D As shown, the first display area 10 is a light-transmitting display area, that is, light from the first side S1 (e.g., the display side) of the display substrate 1 is allowed to at least partially transmit to the second side S2 (e.g., the non-display side) of the display substrate 1, that is, the incident light from the display side is transmitted through the first display area 10 to reach the non-display side of the display substrate 1. A sensor 192 may also be provided on the second side S2 of the display substrate 1 to receive the transmitted light, thereby realizing corresponding functions (e.g., imaging, infrared sensing, distance sensing, etc.). For example, the sensor 192 is provided on the second side S2 of the display substrate 1, and the orthographic projection of the sensor 192 on the base substrate 100 at least partially overlaps with the first display area 10, and is configured to receive and process light from the first side S1 of the display substrate 1. The light from the first side S1 of the display substrate 1 may be collimated light along the normal direction of the display substrate 1 (e.g., the Z1 direction), or non-collimated light.

[0077] For example, the sensor 192 is an image sensor, an infrared sensor, a distance sensor, etc., and the sensor 192 can be implemented in the form of a chip, etc. The sensor 192 is arranged on the second side S2 (the side facing away from the user) of the display substrate 1. The sensor 192 at least partially overlaps with the first display area 10 in the normal direction of the display surface of the display substrate.

[0078] For example, the sensor 192 may be an image sensor, and may be used to collect an image of the external environment facing the light-collecting surface of the sensor 192, such as a CMOS image sensor or a CCD image sensor; the sensor 192 may also be an infrared sensor, a distance sensor, etc. The sensor 192 may be used to implement a camera of a mobile terminal such as a mobile phone or a notebook, and may further include optical devices such as a lens, a reflector, or an optical waveguide to modulate the optical path as required. The embodiments of the present disclosure do not limit the type, function, and configuration of the sensor 192.

[0079] The sensor 192 is disposed on the first side S2 of the display substrate by means of double-sided adhesive or the like, and the orthographic projection of the sensor 192 on the base substrate 100 at least partially overlaps with the first display area 10, and is configured to receive light from the first side S1. Thus, the first display area 10 facilitates the arrangement of the sensor 192 while realizing display.

[0080] For example, Figure 1B as well as Figure 1C As shown, the first display area 10 includes a first sub-pixel array (composed of gray boxes in the first display area 10), and the first sub-pixel array includes a plurality of first pixel unit groups P0 (gray boxes in the first display area 10) arranged in a first direction Y1 and a second direction X1 intersecting the first direction Y1. Each of the plurality of first pixel unit groups P0 may also include at least one first pixel unit (e.g., a plurality of first pixel units) (described in detail later). The first pixel unit includes a first light-emitting device and a first pixel driving circuit directly connected to each other, and the first pixel driving circuit is configured to drive the first light-emitting device to emit light. The first light-emitting device and the first pixel driving circuit are located in the same pixel area and are not separated from each other in position.

[0081] It should be noted that the first direction Y1 and the second direction X1 may or may not intersect each other perpendicularly. For example, the acute angle at which the first direction Y1 and the second direction X1 intersect each other may be less than or equal to 10° and greater than or equal to 45°. The drawings of the embodiments of the present disclosure take the example of the first direction Y1 and the second direction X1 intersecting perpendicularly.

[0082] Gaps allowing light to pass therethrough are provided between the plurality of first pixel unit groups P0 , ie, blank areas in the first display area 10 , so as to allow incident light from the first side S1 to be transmitted through the gaps between adjacent first pixel unit groups P0 , thereby ensuring light transmittance of the first display area 10 .

[0083] For example, Figure 1BAs shown, a plurality of first pixel unit groups P0 are arranged in a staggered arrangement between two adjacent columns, that is, the first pixel unit group P0 in the first column in the figure is staggered in the second direction X1 with the first pixel unit group P0 in the second column and distributed in different rows. For example, the first pixel unit groups P0 in adjacent columns are in different rows.

[0084] For example, Figure 1C As shown, a plurality of first pixel unit groups P0 are arranged in multiple rows and columns, that is, the first pixel unit group P0 in the first column in the figure is spaced and adjacent to the first pixel unit group P0 in the second column in the second direction X1.

[0085] For example, Figure 1B as well as Figure 1C As shown, the second display area 20 includes a second sub-pixel array (composed of white boxes in the second display area 20), and the second sub-pixel array includes a plurality of second pixel units C (white boxes in the second display area 20). Each of the plurality of second pixel units C includes a second light-emitting device and a second pixel driving circuit directly connected to each other, and the second pixel driving circuit is configured to drive the second light-emitting device to emit light. The second light-emitting device and the second pixel driving circuit are located in the same pixel area and are not separated from each other in position.

[0086] For example, the pixel density of the second display area is greater than the pixel density of the first display area. Figure 1B as well as Figure 1C As shown, the arrangement density of the first pixel unit group P0 in the first display area 10 is less than the arrangement density of the second pixel unit C in the second display area 20. That is, the resolution of the first display area 10 is set lower than the resolution of the second display area 20 to leave space for light to pass through, that is, the pixel density arranged in the first display area 10 for display is less than the sub-pixel density of the second display area 20.

[0087] For example, Figure 2 A schematic diagram of a planar layout of wiring in a first display area of ​​a display substrate provided in at least one embodiment of the present disclosure. Figure 3A for Figure 2 Magnified view of area A1 in the middle. Figure 3B for Figure 2 Magnified view of area A2 in the middle. Figure 5A-Figure 5C for Figure 2 A plan view of each layer of wiring in the first display area is shown. Figure 5A for Figure 2 The schematic plan view of the wiring in the first display area located in the first conductive layer GA1 is shown. Figure 5B for Figure 2 The schematic plan view of the wiring in the first display area located in the second conductive layer GA2 is shown. Figure 5C for Figure 2FIG. 1 is a plan view of the wiring in the first display area located in the third conductive layer SD1.

[0088] For example, Figure 2 as well as Figure 5C As shown, the first display area 10 includes a plurality of first signal lines DATA1 and a plurality of first power lines VDD1. The first pixel unit group P0 includes two first pixel units P1 arranged adjacent to each other along the first direction X1. The plurality of first signal lines DATA1 and the plurality of first power lines VDD1 extend along the first direction Y1. Each of the plurality of first signal lines DATA1 corresponds to and is connected to the first pixel units P1 of the plurality of first pixel unit groups P0 one by one. Each of the plurality of first power lines VDD1 corresponds to and is connected to the first pixel units P1 of the plurality of first pixel unit groups P0 one by one. That is, each first pixel unit P1 is respectively connected to a first signal line DATA1 and a first power line VDD1. The first signal line DATA1 is configured to provide a first display signal to the first pixel unit P1. The first power line VDD1 is configured to provide a first power supply voltage to the plurality of first pixel units P1.

[0089] It should be noted that the “connection” in the embodiments of the present disclosure includes direct connection of a wiring or a circuit, and “electrical connection”, “signal connection”, etc. of a wiring or a circuit. The embodiments of the present disclosure are not limited thereto.

[0090] For example, Figure 5C As shown, the first power line VDD1 and the first signal line DATA1 in the same first pixel unit P1 are arranged in parallel. The lower part of the first signal line DATA1 on the left side in the same first pixel unit group P0 (the part used to connect the switching electrode) is bent to the right (that is, bent toward the first voltage line VDD1 connected to the connecting line).

[0091] For example, the display substrate 1 further includes at least one connecting wire, at least part of which extends along the first direction and is connected to the first power lines respectively connected to the adjacent first pixel unit groups in the first direction. Figure 2 , Figure 3A as well as Figure 5CAs shown, the display substrate 1 also includes a plurality of connecting wires (e.g., a plurality of first connecting wires LS1), each of which extends along the first direction Y1 and is connected to the first power line VDD1 respectively connected to the first pixel unit group P0 adjacent in the first direction Y1. That is, the first power line VDD1 in two corresponding first pixel units P1 of the first pixel unit group P0 adjacent in the first direction Y1 is connected to the connecting wire (e.g., the first connecting wire LS1). For example, the first power line VDD1 connected to the first pixel unit group P0 adjacent in the first direction Y1 is connected via a connecting wire (e.g., the first connecting wire LS1). That is, the first power line VDD1 in one of the two first pixel units P1 of the first pixel unit group P0 is connected to the connecting wire (e.g., the first connecting wire LS1) to reduce the number of wires and increase the aperture ratio and light transmittance of the first display area 10.

[0092] For example, the display substrate further includes at least one switching electrode, at least a portion of which extends along the first direction and is connected to first signal lines respectively connected to adjacent first pixel unit groups in the first direction. Figure 2 as well as Figure 3A As shown, the display substrate 1 further includes a plurality of switching electrodes, for example, the switching electrodes include a first switching electrode TS1 and a second switching electrode TS2. The main part of each of the plurality of switching electrodes (that is, most of the switching electrodes) extends along the first direction Y1, and is respectively connected to the first signal lines DATA1 respectively connected to the first pixel unit groups P0 adjacent to each other in the first direction Y1. That is, the first signal lines DATA1 in two corresponding first pixel units P1 of the first pixel unit groups P0 adjacent to each other in the first direction Y1 are connected to one of the plurality of switching electrodes (the first switching electrode TS1 or the second switching electrode TS2). For example, the first signal line DATA1 connected to two first pixel units P1 adjacent to each other in the first direction Y1 is connected via a switching electrode (the first switching electrode TS1 or the second switching electrode TS2). The plurality of switching electrodes are connected one-to-one to a plurality of first pixel units P1 adjacent to each other in the first direction Y1 and belonging to different first pixel unit groups P0. That is, the first signal line DATA1 in one of the two first pixel units P1 of the first pixel unit group P0 (for example, located near the left side of a pixel unit P0) is connected to a switching electrode (for example, the first switching electrode TS1), and the first signal line DATA1 in the other of the two first pixel units P1 of the first pixel unit group P0 (for example, located near the right side of a pixel unit P0) is connected to a switching electrode (for example, the second switching electrode TS2).

[0093] For example, with respect to the base substrate 1, at least a portion of at least one switching electrode is located in a different film layer from that of at least one connecting wire, and the orthographic projection of at least one switching electrode on the base substrate overlaps at least partially with the orthographic projection of at least one connecting wire on the base substrate. Figure 2 as well as Figure 3A As shown, a plurality of first connection traces (eg, first connection traces LS1) are located on a side of a plurality of transfer electrodes (eg, first transfer electrodes TS1 or second transfer electrodes TS2) away from the base substrate 100. Figure 3A As shown, the orthographic projection of the connecting trace (e.g., the first connecting trace LS1) on the base substrate 100 partially overlaps with the orthographic projection of the switching electrode (e.g., the first switching electrode TS1 or the second switching electrode TS2) on the base substrate 100. For example, the orthographic projection of the portion of the switching electrode (e.g., the first switching electrode TS1 or the second switching electrode TS2) extending along the first direction Y1 on the base substrate 100 overlaps with the orthographic projection of the connecting trace (e.g., the first connecting trace LS1) on the base substrate 100. For example, the orthographic projection of the portion of the switching electrode (for example, the first switching electrode TS1 or the second switching electrode TS2) extending along the first direction Y1 on the base substrate 100 is located in the orthographic projection of the connecting trace (for example, the first connecting trace LS1) on the base substrate 100, so that the connecting trace overlaps with the switching electrode and blocks the switching electrode, thereby reducing the wiring space of the switching electrode, improving the aperture ratio and transmittance of the first display area, and reducing the occurrence of light interference between different traces, thereby allowing, for example, a sensor to be set in the first display area and on the second side S2 of the display substrate 1 for sensing (for example, imaging), and improving the sensing effect (imaging quality) of the sensor.

[0094] It should be noted that the “different film layers” in the embodiment of the present disclosure includes that the two functional layers or structural layers are in different layers in the hierarchical structure of the display substrate and are formed of different materials, that is, in the preparation process, the two functional layers or structural layers can be formed by different material layers and the required patterns and structures can be formed through different composition processes.

[0095] For example, the at least one connecting line includes a first connecting line. Figure 2 , Figure 3A as well as Figure 5CAs shown, the first connection line LS1 extends along the first direction Y1, and the first connection line LS1 is connected to the first power line VDD1 respectively connected to the first pixel units P1 adjacent to each other in the first direction Y1 and belonging to different first pixel unit groups P0. The first connection line LS1 and the first power line VDD1 connected thereto are both substantially located in the first direction Y1. As shown in the figure, there is a gap between the first pixel unit groups P0 adjacent to each other in the first direction Y1 to allow light from the first side S1 of the display substrate 1 to pass through. One of the two first pixel units P1 of the first pixel unit group P0 adjacent to each other in the first direction Y1 is connected to the first connection line LS1 to reduce the number of lines and increase the aperture ratio and light transmittance of the first display area 10.

[0096] For example, the first connection line and the first power line are arranged in the same layer and are formed integrally. Figure 4A for Figure 3A The cross-sectional view along the line C1 - C2 in the figure. The line C1 - C2 passes through the first connection line LS1 , the first transfer electrode TS1 and the second transfer electrode TS2 along the second direction X1 .

[0097] like Figure 4A As shown, the display substrate 1 includes a first insulating layer 141 (e.g., a first gate insulating layer), a second insulating layer 142 (e.g., a second gate insulating layer), and a third insulating layer 143 (e.g., an interlayer insulating layer) sequentially arranged on a base substrate 100. The second insulating layer 142 is located on a side of the first insulating layer 141 away from the base substrate 100, and the third insulating layer 143 is located on a side of the second insulating layer 142 away from the base substrate 100. The first connecting wire LS1 is located on a side of the third insulating layer 143 away from the base substrate 100, and the first power line VDD1 is arranged on the same layer as the first connecting wire LS1 and is formed integrally through the same patterning process. For example, Figure 5C As shown, the first connection line LS1 and the first power line VDD1 are located in the third conductive layer SD1.

[0098] It should be noted that "integrated formation" in the embodiments of the present disclosure refers to a structure in which two (or more) film layers or structures are formed by the same deposition process and patterned by the same composition process to form a structure connected to each other, and their materials may be the same or different.

[0099] For example, the material of the first connection line LS1 and the first power line VDD1 (that is, the third conductive layer SD1) may include a metal material or an alloy material, such as a metal single layer or multilayer structure formed by molybdenum, aluminum and titanium, for example, the multilayer structure is a multi-metal layer stack (such as a titanium, aluminum and titanium three-layer metal stack (Ti / Al / Ti)). The embodiments of the present disclosure do not specifically limit the materials of each functional layer.

[0100] It should be noted that in the embodiments of the present disclosure, "same-layer arrangement" includes two functional layers or structural layers being formed of the same material in the hierarchical structure of the display substrate, that is, in the preparation process, the two functional layers or structural layers can be formed of the same material layer and can be formed into the required pattern and structure by the same composition process. A single composition process, for example, includes the formation of photoresist, exposure, development, etching and other processes.

[0101] For example, one or more materials of the first insulating layer 141, the second insulating layer 142 and the third insulating layer 143 may include insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, etc. The materials of the first insulating layer 141, the second insulating layer 142 and the third insulating layer 143 may be the same or different.

[0102] It should be noted that other film layers, such as a buffer layer, a barrier layer, etc., may be disposed between the base substrate 100 and the first insulating layer 141 , but the embodiments of the present disclosure are not limited thereto.

[0103] For example, Figure 3A , Figure 5A as well as Figure 5B As shown, the plurality of switching electrodes include a first switching electrode TS1 and a second switching electrode TS2, and the portions of the first switching electrode TS1 and the second switching electrode TS2 extending along the first direction Y1 are arranged in parallel. The two first pixel units P1 of the first pixel unit group P0 are arranged in two columns in parallel along the second direction Y1. The first switching electrode TS1 and the second switching electrode TS2 are connected to the first signal lines DATA1 respectively connected to the first pixel units P1 adjacent to each other in the first direction Y1 and belonging to different first pixel unit groups P0. That is, the two first pixel units P1 of the first pixel unit group P0 located in two columns are respectively connected to the first switching electrode TS1 and the second switching electrode TS2. The first switching electrode TS1 and the second switching electrode TS2 first extend in the second direction X1 close to the first connection wiring LS1, then extend in the first direction Y1, and finally extend in the second direction X1 to connect the first signal lines DATA1 adjacent to each other in the first direction Y1 and belonging to different first pixel unit groups P0. The portions of the first switching electrode TS1 and the second switching electrode TS2 extending along the second direction X1 are shorter, and the main portions of the first switching electrode TS1 and the second switching electrode TS2 extend along the first direction Y1.

[0104] For example, Figure 5A As shown in FIG. 1 , the second transfer electrode TS2 is in a concave shape or a “]” shape that opens to the right side (away from the first connection trace LS1 ) in the figure. Figure 5BAs shown, the first transfer electrode TS1 is in a "concave" shape or "[" shape that opens to the left side (away from the first connection line LS1) in the figure. The second transfer electrode TS2 and the second transfer electrode TS1 have opposite directions and both converge to the position where the first connection line LS1 is located to overlap with the first connection line LS1.

[0105] For example, relative to the base substrate, the film layers where the plurality of transfer electrodes are located are different. Figure 4B for Figure 3A A schematic cross-sectional view along line C3-C4; Figure 4C for Figure 3A A schematic cross-sectional view of the line C5-C6 in Figure 1. Figure 3A , 4B as well as Figure 4C As shown, the first transfer electrode TS1 and the second transfer electrode TS2 are located in different film layers relative to the base substrate 100. The first transfer electrode TS1 is located between the second insulating layer 142 and the third insulating layer 143. Figure 5B As shown, the first switching electrode TS1 is located on the second conductive layer GA2. The second switching electrode TS2 is located between the first insulating layer 141 and the second insulating layer 142. Figure 5A As shown, the second transfer electrode TS2 is located in the first conductive layer GA1. The second insulating layer 142 insulates the first transfer electrode TS1 from the second transfer electrode TS2. The first transfer electrode TS1 and the second transfer electrode TS2 are located in different film layers, which can reduce the size of the interval between the first transfer electrode TS1 and the second transfer electrode TS2, thereby reducing the space occupied by the first transfer electrode TS1 and the second transfer electrode TS2.

[0106] For example, the material of the first transfer electrode TS1 and the second transfer electrode TS2 (i.e., the first conductive layer GA1 and the second conductive layer GA2) may include a metal material or an alloy material, such as a metal single layer or multilayer structure formed by molybdenum, aluminum, and titanium, for example, the multilayer structure is a multi-metal layer stack (such as a titanium, aluminum, and titanium three-layer metal stack (Ti / Al / Ti)). The embodiments of the present disclosure do not specifically limit the materials of each functional layer.

[0107] For example, the orthographic projections of the first switching electrode and the second switching electrode on the substrate at least partially overlap with the orthographic projection of the first connecting trace on the substrate. Figure 3A and Figure 4AAs shown, the orthographic projection of the first connecting line LS1 on the base substrate overlaps with the orthographic projection of the first switching electrode TS1 (the portion extending along the first direction Y1) and the second switching electrode TS2 (the portion extending along the first direction Y1) on the base substrate. That is, the orthographic projection of the first connecting line LS1 on the base substrate covers the orthographic projection of the first switching electrode TS1 (the portion extending along the first direction Y1) and the second switching electrode TS2 (the portion extending along the first direction Y1) on the base substrate, so that the first switching electrode TS1 shields the first connecting line LS1 and the second switching electrode TS2, thereby reducing the wiring space of the connecting lines, improving the aperture ratio and light transmittance of the first display area, and reducing the occurrence of light interference between different lines.

[0108] For example, Figure 4A As shown, the value range of the width W1 of the cross section of the first connecting trace LS1 along the second direction X1 is, for example, about 5-6 microns, and the value of the width W1 is, for example, about 5.55 microns. The value range of the width W2 of the cross section of the first switching electrode TS1 along the second direction X1 is, for example, about 2-3 microns, and the value of the width W2 is, for example, about 2.5 microns. The value range of the width W3 of the cross section of the second switching electrode TS2 along the second direction X1 is, for example, about 2-3 microns, and the value of the width W3 is, for example, about 2.5 microns. The value range of the width W4 of the gap between the first switching electrode TS1 and the second switching electrode TS2 along the second direction X1 is, for example, about 0.2-1.5 microns, and the value of the width W3 is, for example, about 0.55 microns.

[0109] It should be noted that, in the embodiments of the present disclosure, the word “about” indicates that the numerical range or the value of the numerical value may fluctuate within a range of, for example, ±5%, or ±10%.

[0110] For example, Figure 3A The cut line C3-C4 in the embodiment passes through the first signal line DATA1, the first via hole GH1 and the first switching electrode TS1. Figure 3A The cut line C5-C6 in FIG. 1 passes through the first signal line DATA1, the second via hole GH2 and the second switching electrode TS2. The two first signal lines DATA1 respectively connected to the first switching electrode TS1 and the second switching electrode TS2 are located at two first pixel units P1 belonging to the first pixel unit group P0. Figure 4B as well as Figure 4C As shown, the first signal line DATA1 is located on the side of the third insulating layer 143 away from the base substrate 100. The film layer where the first signal line DATA1 is located is different from the film layer where the first transfer electrode TS1 and the second transfer electrode TS2 are located. For example, as shown in FIG5C, the first signal line DATA1 is located in the third conductive layer SD1.

[0111] like Figure 4B As shown, the first via hole GH1 is a via hole penetrating the third insulating layer 143 , and the first signal line DATA1 is connected to the first switching electrode TS1 through the first via hole GH1 .

[0112] like Figure 4C As shown, the second via hole GH2 is a via hole penetrating the third insulating layer 143 and the second insulating layer 142 , and the first signal line DATA1 is connected to the second switching electrode TS2 through the second via hole GH2 .

[0113] For example, Fig.21 FIG. 1 is a cross-sectional schematic diagram of a first display area in a display substrate provided in at least one embodiment of the present disclosure. Figure 2 As shown, the two first pixel units P0 of the first pixel unit group P0 are arranged in at least one row along the first direction Y1, that is, in the same row, the first pixel unit group P0 includes two first pixel units P0. Fig.21 As shown, each first pixel unit P1 of the first pixel unit group P0 includes a first pixel driving circuit 12 and a first light-emitting device 11, and the first pixel driving circuit 12 is connected to the first light-emitting device 11 and drives the first light-emitting device 11 to emit light. The first pixel driving circuit 12 includes a storage capacitor 13, and the storage capacitor 13 includes a first plate CE1 and a second plate CE2 that overlaps (for example, partially overlaps) with the first plate CE1. The first plate CE1 is located on a side of the second insulating layer 142 away from the substrate 100. The second plate CE2 is located on a side of the first insulating layer 141 away from the substrate 100. For example, as Figure 5B As shown, the second electrode plate CE2 is located on the second conductive layer GA2.

[0114] For example, Fig. 20A The schematic diagram of the planar layout of a first pixel driving circuit in a first display area of ​​a display substrate provided by at least one embodiment of the present disclosure is shown in FIG. Figure 2 as well as Fig. 20A As shown, a plurality of first power lines VDD1 connected to each first pixel unit P0 in one-to-one correspondence are connected to the first electrode plate CE1 through via holes VH9 and VH3 penetrating the third insulating layer 143. The first power line VDD1 can also be connected to the first electrode plate CE1 through one of the via holes VH9 and VH3, which is not limited in the embodiment of the present disclosure.

[0115] It should be noted that Fig. 20A The first pixel driving circuit shown in FIG. 1 is a 7T1C type (i.e., 7 transistors and 1 capacitor) pixel driving circuit. Fig. 20AAs only an example of the first pixel driving circuit, the embodiment of the present disclosure does not limit the first pixel driving circuit. For example, it can also be a 2T1C (i.e., 2 transistors and 1 capacitor) type pixel driving circuit, where the two transistors are respectively a data writing transistor and a driving transistor, and the one capacitor is a signal storage capacitor (e.g. Fig. 20A The storage capacitor 13 in the first pixel driving circuit can generate a driving current for driving the light-emitting element to emit light according to the received scanning signal and data signal, and the light-emitting element generates light of different intensities according to the magnitude of the driving current. The pixel circuit can also be other types of pixel circuits, for example, it can further have a compensation function, a reset function, a sensing function, etc., and thus can include more than two thin film transistors.

[0116] For example, Figure 2 as well as Figure 5B As shown, the first electrodes CE1 of the two first pixel units P1 in the same row of the first pixel unit group P0 are interconnected and formed in one piece, so as to save the manufacturing process and reduce the cost. That is to say, the first power line VDD1 in each first pixel unit P1 is connected to the first electrode CE1 of the storage capacitor 13 of the first pixel unit P1 corresponding to it, so as to be connected to the first pixel unit P1, and the first power lines VDD1 in the two first pixel units P1 are connected by interconnecting the first electrodes CE1 of the two first pixel units P1 in the same row of the first pixel unit group P0. As mentioned above, when the first power lines VDD1 in the two first pixel units P1 belonging to the same first pixel unit group P0 are connected, the first power line VDD1 in one of the two first pixel units P1 can be connected by setting a first connecting wire LS1 to reduce the number of wires.

[0117] For example, Figure 2 as well as Figure 3B As shown, the display substrate 1 further includes a fourth switching electrode TS4, and a portion (most portion) of the fourth switching electrode TS4 extends along the second direction X1. The fourth switching electrode TS is connected to the first power line VDD1 to which the first pixel units P1 that are staggered and adjacently arranged in the second direction X1 and belong to different first pixel unit groups P0 are respectively connected. Figure 2 As shown in FIG. 1 , a plurality of first pixel unit groups P0 (four first pixel unit groups P0 are shown in the figure) are arranged as follows: Figure 1B That is, the plurality of first pixel unit groups P0 in two adjacent columns are staggered and arranged in different rows, so as to leave more gaps in the first pixel unit groups P0, thereby allowing light from the first side S1 of the display substrate 1 to pass through.

[0118] For example, Figure 2 as well as Figure 5CAs shown, both ends of the fourth transfer electrode TS4 are respectively connected to the first electrode plates CE1 of two first pixel units P1 that are adjacently arranged and belong to different first pixel unit groups P0, so as to connect the first power supply line VDD1 located in different first pixel unit groups P1. Since the two first pixel units P1 that are adjacently arranged and belong to different first pixel unit groups P0 are misaligned and are not located in a row along the second direction X1, the fourth transfer electrode TS4 first extends along the first direction Y1, then extends along the second direction X1, and finally extends along the first direction Y1, that is, the fourth transfer electrode TS4 includes a portion extending along the first direction Y1. Most of the fourth transfer electrode TS4 extends along the second direction X1.

[0119] For example, Figure 3B The section line C7 - C8 in FIG. 1 passes through a portion of the first electrode plate CE1 , the third via hole GH3 , and the fourth switching electrode TS4 . Figure 4D for Figure 3B As shown in FIG4C , the fourth transfer electrode TS4 is located on the side of the third insulating layer 143 away from the base substrate 100, and the third via hole GH3 is a via hole penetrating the third insulating layer 143. The fourth transfer electrode TS4 is connected to the first electrode plate CE1 of the first pixel unit P1 through the third via hole 143.

[0120] For example, Figure 3B As shown, the value range of the width W5 of the fourth switching electrode TS4 (for example, perpendicular to the wiring direction of the fourth switching electrode TS4) is, for example, about 2-3 microns, and the value of the width W5 is, for example, about 2.5 microns.

[0121] For example, Figure 5D for Figure 2 The schematic diagram of the sub-pixel arrangement of the first display area is shown; Figure 5DAs shown, the two first pixel units P1 of the first pixel unit group P0 may include a red sub-pixel (R) and a green sub-pixel (G) or a blue sub-pixel (B) and a green sub-pixel (G), respectively. For example, as shown in the figure, the first pixel unit group P0 in the first row in the first column includes a red sub-pixel (R) and a green sub-pixel (G1), that is, the light-emitting device 11 of the first pixel unit P1 on the left side of the first pixel unit group P0 emits red light, and the light-emitting device 11 of the first pixel unit P1 on the right side of the first pixel unit group P0 emits green light. It should be noted that the first pixel unit group P0 in the figure is regarded as a whole and divided into rows and columns, that is, the first pixel unit group P0 arranged in the first column includes two rows of first pixel unit groups P0, and the first pixel unit group P0 arranged in the second column includes two rows of first pixel unit groups P0. The first pixel unit group P0 in the second row in the first column includes a red sub-pixel (R) and a green sub-pixel (G1), the first pixel unit group P0 in the first row in the second column includes a blue sub-pixel (B) and a green sub-pixel (G2), and the first pixel unit group P0 in the second row in the second column includes a blue sub-pixel (B) and a green sub-pixel (G2). The first pixel unit groups P0 adjacent to each other in the second direction X1 share a red sub-pixel (R) and a blue sub-pixel (B), that is, the first pixel unit group P0 in the first row in the first column and the first pixel unit group P0 in the first row in the second column share a red sub-pixel (R) and a blue sub-pixel (B), and the first pixel unit group P0 in the second row in the first column and the first pixel unit group P0 in the second row in the second column share a red sub-pixel (R) and a blue sub-pixel (B) to realize the display of the picture. The luminous color of the first pixel unit P1 of the first pixel unit group P0 can be selected according to the actual display needs, and the embodiments of the present disclosure are not limited thereto.

[0122] In another embodiment of the present disclosure, for example, Figure 6 A schematic diagram of a planar layout of wiring in a first display area of ​​a display substrate provided in at least another embodiment of the present disclosure. Fig. 7A for Figure 6 Magnified view of region A11. Figure 7B for Figure 6 Magnified view of the middle A12 area. Figure 9A-9C for Figure 6 A plan view of each layer of wiring in the first display area is shown. Fig.9A for Figure 6 The schematic plan view of the wiring in the first display area located on the first conductive layer GA11 is shown. Fig. 9B for Figure 6 A schematic plan view of wiring in the first display area located in the second conductive layer GA12 is shown. Fig. 9C for Figure 6A schematic plan view of the wiring in the first display area located in the third conductive layer SD11 is shown.

[0123] For example, Figure 6 as well as Fig. 9C As shown, the first display area 10 includes a plurality of first pixel unit groups P10, a plurality of first signal lines DATA1 and a plurality of first power lines VDD1. The plurality of first pixel unit groups P10 are arranged in a plurality of rows and columns, that is, according to Figure 1C The arrangement shown. The first pixel unit group P10 includes three first pixel units P11 arranged adjacent to each other along the first direction X1 (that is, arranged in a row). A plurality of first signal lines DATA1 and a plurality of first power lines VDD1 extend along the first direction Y1. Each of the plurality of first signal lines DATA1 corresponds to and is connected to a plurality of first pixel units P11 of the first pixel unit group P10. Each of the plurality of first power lines VDD1 corresponds to and is connected to a plurality of first pixel units P11 of the first pixel unit group P10. In other words, a first signal line DATA1 and a first power line VDD1 are respectively connected to each first pixel unit P11. The first signal line DATA1 is configured to provide a first display signal to the first pixel unit P11. The first power line VDD1 is configured to provide a first power supply voltage to the plurality of first pixel units P11.

[0124] For example, Fig. 9C As shown, the first power line VDD1 and the first signal line DATA1 in the same first pixel unit P11 are arranged in parallel. The lower portion of the first signal line DATA1 on the left side in the same first pixel unit group P0 (the portion used to connect to the switching electrode) is bent toward the direction close to the first power line VDD1 in the middle (for connecting to the connecting wire). The lower portion of the first signal line DATA1 on the right side in the same first pixel unit group P10 (the portion used to connect to the switching electrode) is bent toward the direction close to the first power line VDD1 in the middle (for connecting to the connecting wire). Fig. 9C In the figure, the upper portion of the first signal line DATA1 on the right side of the first pixel unit group P10 in the second row (the portion for connecting to the switching electrode) is bent toward the first power line VDD1 in the middle (for connecting to the connecting wire).

[0125] For example, the display substrate 1 further includes at least one connecting wire, at least part of which extends along the first direction and is connected to the first power lines respectively connected to the adjacent first pixel unit groups in the first direction. Figure 6 , Fig. 7A as well as Fig. 9CAs shown, the display substrate 1 also includes a plurality of connecting wires (e.g., a plurality of first connecting wires LS11), each of which extends along the first direction Y1 and is connected to the first power line VDD1 respectively connected to the first pixel unit group P10 adjacent to the first direction Y1. That is, the first power line VDD1 in two corresponding first pixel units P11 of the first pixel unit group P10 adjacent to the first direction Y1 is connected to the connecting wire (e.g., the first connecting wire LS11). For example, the first power line VDD1 connected to the first pixel unit group P10 adjacent to the first direction Y1 is connected through a connecting wire (e.g., the first connecting wire LS11). That is, the first power line VDD1 in one of the three first pixel units P11 of the first pixel unit group P10 is connected to the connecting wire (e.g., the first connecting wire LS11) to reduce the number of wires and increase the aperture ratio and light transmittance of the first display area 10.

[0126] For example, the display substrate 1 further includes at least one switching electrode, at least part of which extends along the first direction and is connected to the first signal lines respectively connected to the adjacent first pixel unit groups in the first direction. Figure 6 as well as Fig. 7AAs shown, the display substrate 1 further includes a plurality of switching electrodes, for example, the switching electrodes include a first switching electrode TS11, a second switching electrode TS12, and a third switching electrode TS3. The main part of each of the plurality of switching electrodes (that is, most of the switching electrodes) extends along the first direction Y1, and is respectively connected to the first signal lines DATA1 respectively connected to the first pixel unit groups P10 adjacent to each other in the first direction Y1. That is, the first signal lines DATA1 in two corresponding first pixel units P11 of the first pixel unit groups P10 adjacent to each other in the first direction Y1 are connected to one of the plurality of switching electrodes (the first switching electrode TS11, the second switching electrode TS12, or the third switching electrode TS3). For example, the first signal line DATA1 connected to two first pixel units P11 adjacent to each other in the first direction Y1 is connected via a switching electrode (the first switching electrode TS11, the second switching electrode TS12, or the third switching electrode TS3). The plurality of switching electrodes are connected one-to-one to the plurality of first pixel units P11 that are adjacent in the first direction Y1 and belong to different first pixel unit groups P10. That is, the first signal line DATA1 in one of the three first pixel units P1 of the first pixel unit group P10 (for example, located near the left side of a pixel unit P10) is connected to a switching electrode (for example, the first switching electrode TS11). The first signal line DATA1 in another of the three first pixel units P11 of the first pixel unit group P10 (for example, located near the middle of a pixel unit P10) is connected to a switching electrode (for example, the third switching electrode TS3). The first signal line DATA1 in another of the three first pixel units P1 of the first pixel unit group P10 (for example, located near the right side of a pixel unit P10) is connected to a switching electrode (for example, the second switching electrode TS12).

[0127] For example, Figure 6 as well as Fig. 7A As shown, a plurality of connection traces (eg, first connection traces LS11) are located on a side of a plurality of transfer electrodes (eg, first transfer electrodes TS11 or second transfer electrodes TS12) away from the substrate. Fig. 7AAs shown, the orthographic projection of the connecting trace (e.g., the first connecting trace LS11) on the base substrate 100 partially overlaps with the orthographic projection of the switching electrode (e.g., the first switching electrode TS11 or the second switching electrode TS12) on the base substrate 100. For example, the orthographic projection of the portion of the switching electrode (e.g., the first switching electrode TS11) extending along the first direction Y1 on the base substrate 100 overlaps with the orthographic projection of the connecting trace (e.g., the first connecting trace LS11) on the base substrate 100. For example, the orthographic projection of the portion of the transfer electrode (for example, the first transfer electrode TS11) extending along the first direction Y1 on the base substrate 100 is located in the orthographic projection of the connecting trace (for example, the first connecting trace LS11) on the base substrate 100, so that the connecting trace overlaps with the transfer electrode and blocks the transfer electrode, thereby reducing the wiring space of the trace, improving the aperture ratio and transmittance of the first display area, and reducing the occurrence of light interference between different traces, thereby allowing, for example, a sensor to be set in the first display area and on the second side S2 of the display substrate 1 for sensing (for example, imaging), and improving the sensing effect (imaging quality) of the sensor.

[0128] For example, the at least one connecting line includes a first connecting line. Figure 6 , Fig. 7A as well as Fig. 9C As shown, the first connection line LS11 extends along the first direction Y1, and the first connection line LS11 is connected to the first power line VDD1 respectively connected to the first pixel units P11 adjacent in the first direction Y1 and belonging to different first pixel unit groups P10. The first connection line LS11 and the first power line VDD1 connected thereto are both substantially located in the first direction Y1. As shown in the figure, there is a gap between the first pixel unit groups P10 adjacent in the first direction Y1 to allow light from the first side S1 of the display substrate 1 to pass through. One of the three first pixel units P1 of the first pixel unit group P10 adjacent in the first direction Y1 (for example, a pixel unit P1 located in the middle) is connected to the first connection line LS11 to reduce the number of lines and increase the aperture ratio and light transmittance of the first display area 10.

[0129] For example, the first connection line and the first power line are arranged in the same layer and are formed integrally. Figure 8 for Fig. 7A Schematic diagram of a cross section along line C11-C12 in FIG. Line C11-C12 passes through the first transfer electrode TS11, the first connection trace LS11, the third transfer electrode TS3 and the second transfer electrode TS12 along the second direction X1. Figure 8 As shown, the first connection line LS11 is located on the side of the third insulating layer 143 away from the base substrate 100, and the first power line VDD1 and the first connection line LS11 are arranged in the same layer and are formed integrally through the same patterning process. Fig. 9C As shown, the first connection line LS11 and the first power line VDD1 are located in the third conductive layer SD11.

[0130] For example, Fig. 7A , Fig.9A as well as Fig. 9B As shown, the plurality of switching electrodes include a first switching electrode TS11, a second switching electrode TS12, and a third switching electrode TS3. The portions of the first switching electrode TS11, the second switching electrode TS12, and the third switching electrode TS3 extending along the first direction Y1 are arranged in parallel. The third switching electrode TS3 is located between the first switching electrode TS11 and the second switching electrode TS12. The three first pixel units P11 of the first pixel unit group P10 are arranged in three columns in parallel along the second direction Y1. The first switching electrode TS11, the third switching electrode TS3, and the second switching electrode TS12 are connected to the first signal lines DATA1 to which the first pixel units P11 adjacent to each other in the first direction Y1 and belonging to different first pixel unit groups P10 are respectively connected. That is, the three first pixel units P11 belonging to the same first pixel unit group P10 located in three columns are respectively connected to the first switching electrode TS11, the third switching electrode TS3, and the second switching electrode TS12. The third switching electrode TS3 extends along the first direction Y1. The first transfer electrode TS11 and the second transfer electrode TS12 first extend in the second direction X1 close to the first connection line LS11, then extend in the first direction Y1, and then extend in the second direction X1 to connect the first signal line DATA1 of the first pixel unit P11 belonging to different first pixel unit groups P10 adjacent in the first direction Y1. The portions of the first transfer electrode TS11 and the second transfer electrode TS12 extending in the second direction X1 are shorter, and the main parts of the first transfer electrode TS11 and the second transfer electrode TS12 extend in the first direction Y1. The third transfer electrode TS3 extends in the first direction Y1, and the first signal line DATA1 connected thereto is basically located in a straight line (that is, both are located in the first direction Y1). The third transfer electrode TS3 can be formed integrally with the first signal line DATA1 connected to the third transfer electrode TS3.

[0131] For example, Fig.9A As shown in FIG. 1 , the second transfer electrode TS12 is in a concave shape or a “]” shape that opens to the right side (away from the first connection trace LS11 ). Fig. 9B As shown, the first transfer electrode TS11 is in a "concave" shape or "[" shape that opens to the left side (away from the first connection line LS11) in the figure. The second transfer electrode TS12 is in the opposite direction to the second transfer electrode TS11, and both converge to the position where the first connection line LS11 is located to overlap with the first connection line LS11. Fig. 9C As shown, the third switching electrode TS3 is located in the third conductive layer SD11 and is disposed in the same layer as the first signal line DATA1. The third switching electrode TS3 and the first signal line DATA1 connected thereto are both located in the first direction Y1.

[0132] For example, the film layers where the plurality of transfer electrodes are located are different from the base substrate. Figure 8 As shown, the first transfer electrode TS11, the second transfer electrode TS12 and the third transfer electrode TS3 are located in different film layers relative to the base substrate 100. The first transfer electrode TS11 is located between the second insulating layer 142 and the third insulating layer 143. Fig. 9B As shown, the first switching electrode TS11 is located on the second conductive layer GA12. The second switching electrode TS12 is located between the first insulating layer 141 and the second insulating layer 142. Figure 5A As shown, the second transfer electrode TS12 is located in the first conductive layer GA11. The second insulating layer 142 insulates the first transfer electrode TS11 and the second transfer electrode TS12. The first transfer electrode TS11 and the second transfer electrode TS12 are located in different film layers, which can reduce the size of the interval between the first transfer electrode TS11 and the second transfer electrode TS12, thereby reducing the space occupied by the first transfer electrode TS11 and the second transfer electrode TS12.

[0133] For example, Fig. 9C As shown, the third transfer electrode TS3 is located on the third conductive layer SD11, that is, the side of the third insulating layer 143 away from the base substrate 100, that is, it is arranged in the same layer as the first connection line LS11 to reduce the wiring space. The first signal line DATA1 is located in the third conductive layer SD11, that is, the side of the third insulating layer 143 away from the base substrate 100. The film layer where the first signal line DATA1 is located is different from the film layer where the first transfer electrode TS11 and the second transfer electrode TS12 are located, but is the same as the film layer where the third transfer electrode TS3 is located. The third transfer electrode TS3 is arranged in the same layer as the first signal line DATA1 connected to it and is formed integrally.

[0134] For example, the orthographic projection of the third switching electrode on the substrate at least partially overlaps with the orthographic projection of the first switching electrode or the second switching electrode on the substrate. Fig. 7A as well as Figure 8 As shown, the orthographic projection of the third switching electrode TS3 on the base substrate 100 partially overlaps with the orthographic projection of the second switching electrode TS12 on the base substrate 100 to reduce wiring space.

[0135] For example, the orthographic projection of the first connecting trace on the substrate at least partially overlaps with the orthographic projection of at least one of the first switching electrode and the second switching electrode on the substrate. Fig. 7A and Figure 8 As shown, the orthographic projection of the first connecting line LS11 on the base substrate 100 overlaps with the orthographic projection of the first transfer electrode TS11 (the portion extending along the first direction Y1) on the base substrate 100. That is, the orthographic projection of the first connecting line LS11 on the base substrate 100 covers the orthographic projection of the first transfer electrode TS11 (the portion extending along the first direction Y1) on the base substrate 100, so that the first connecting line LS11 blocks the first transfer electrode TS11, thereby reducing the wiring space of the connecting line, improving the aperture ratio and light transmittance of the first display area, and reducing the generation of light interference between different lines.

[0136] The orthographic projection of the first connection line LS11 on the base substrate 100 overlaps with the orthographic projection of the second transfer electrode TS21 (the portion extending along the first direction Y1) on the base substrate 100 to reduce the wiring space. The orthographic projection of the second transfer electrode TS21 (the portion extending along the first direction Y1) on the base substrate 100 partially overlaps with the orthographic projections of the first connection line LS11 and the third transfer electrode TS3 on the base substrate 100, that is, the second transfer electrode TS21 blocks the gap between the first connection line LS11 and the third transfer electrode TS3 to prevent the occurrence of light interference.

[0137] For example, Figure 8 As shown, the value range of the width W11 of the cross section of the first connection trace LS11 along the second direction X1 is, for example, about 5-6 microns, and the value of the width W1 is, for example, about 5.55 microns. The value range of the width W12 of the cross section of the first transfer electrode TS11 along the second direction X1 is, for example, about 2-3 microns, and the value of the width W12 is, for example, about 2.5 microns. The value range of the width W13 of the cross section of the second transfer electrode TS12 along the second direction X1 is, for example, about 3-4 microns, and the value of the width W13 is, for example, about 3.5 microns. The value range of the width W14 of the gap between the first transfer electrode TS1 and the second transfer electrode TS2 along the second direction X1 is, for example, about 2-3 microns, and the value of the width W13 is, for example, about 2.65 microns. The value range of the width W16 of the cross section of the third transfer electrode TS3 along the second direction X1 is, for example, about 1.5-2.5 microns, and the value of the width W16 is, for example, about 2 microns. The value range of the width W17 of the gap between the first connection trace LS11 and the third transfer electrode TS3 along the second direction X1 is, for example, approximately 2-3 micrometers, and the value of the width W17 is, for example, approximately 2.7 micrometers.

[0138] For example, Fig. 7AAs shown, the first signal line DATA1 (located on the left side of the figure) is connected to the first switching electrode TS11 through the first via hole GH11. The first signal line DATA1 (located on the right side of the figure) is connected to the second switching electrode TS12 through the second via hole GH12. Figure 4B as well as Figure 4C The first via hole GH11 and the first via hole GH1 are both via holes penetrating the third insulating layer 143 , and the second via hole GH12 and the second via hole GH2 are both via holes penetrating the third insulating layer 143 and the second insulating layer 142 .

[0139] For example, Figure 6 as well as Fig.21 As shown, the three first pixel units P10 of the first pixel unit group P0 are arranged in a row along the first direction Y1, that is, in the same row, the first pixel unit group P10 includes three first pixel units P10. Each first pixel unit P1 of the first pixel unit group P10 includes a first pixel driving circuit 12 and a first light-emitting device 11, and the first pixel driving circuit 12 is electrically connected to the first light-emitting device 11 and drives the first light-emitting device 11 to emit light. The first pixel driving circuit 12 includes a storage capacitor 13, and the storage capacitor 13 includes a first electrode plate CE1 and a second electrode plate CE2 that is overlapped (for example, partially overlapped) with the first electrode plate CE1. The first electrode plate CE1 is located on a side of the second insulating layer 142 away from the substrate 100. The second electrode plate CE2 is located on a side of the first insulating layer 141 away from the substrate 100. For example, as Fig. 9B As shown, the first electrode plate CE1 is located on the second conductive layer GA12.

[0140] For example, Figure 6 as well as Fig. 20A As shown, a plurality of first power lines VDD1 correspondingly connected to each first pixel unit P10 are connected to the first electrode plate CE1 through via holes VH9 and VH3 penetrating the third insulating layer 143. The first power line VDD1 may also be connected to the first electrode plate CE1 through one of the via holes VH9 and VH3.

[0141] For example, Figure 6 ,as well as Fig. 9BAs shown, the first electrodes CE1 of the three first pixel units P11 in the same row of the first pixel unit group P10 are interconnected and formed in one piece, so as to save the manufacturing process and reduce the cost. That is to say, the first power line VDD1 in each first pixel unit P11 is connected to the first electrode CE1 of the storage capacitor 13 of the first pixel unit P11 corresponding to it, so as to be electrically connected to the first pixel unit P11, and the first power lines VDD1 in the two first pixel units P11 are electrically connected by interconnecting the first electrodes CE1 of the two first pixel units P11 in the same row of the first pixel unit group P10. As mentioned above, when the first power lines VDD1 in the three first pixel units P11 belonging to a first pixel unit group P10 are electrically connected, the first power line VDD1 in one of the three first pixel units P11 can be connected by setting a first connecting wire LS11 to reduce the number of wires.

[0142] For example, Figure 6 as well as Figure 7B As shown, the display substrate 1 further includes a fourth transfer electrode TS14, which extends along the second direction X1. The fourth transfer electrode TS14 is electrically connected to the first power line VDD1 to which the first pixel units P1 adjacent to the second direction X1 and belonging to different first pixel unit groups P0 are respectively connected. Figure 2 As shown in FIG. 6 , a plurality of first pixel unit groups P10 (four first pixel unit groups P10 are shown in FIG. 6 ) are arranged as follows: Figure 1C That is, the plurality of first pixel unit groups P10 in two adjacent columns are located in the same row, so as to leave more gaps between the first pixel unit groups P10, thereby allowing light from the first side S1 of the display substrate 1 to pass through.

[0143] For example, Figure 6 as well as Fig. 9C As shown, both ends of the fourth switching electrode TS14 are respectively connected to the first electrode plates CE1 of two first pixel units P11 that are adjacently arranged and belong to different first pixel unit groups P10, so as to electrically connect the first power lines VDD1 located in different first pixel units P11. Since the two first pixel units P11 that are adjacently arranged and belong to different first pixel unit groups P10 are located in a row along the second direction X1, the fourth switching electrode TS14 extends along the first direction Y1.

[0144] For example, Figure 7B As shown in FIG. 9B , the fourth transfer electrode TS14 is located on the second conductive layer GA12 and is connected to the first electrode plate CE1 of the first pixel unit P11 and can be formed integrally.

[0145] For example, Figure 7BAs shown, the value range of the width W15 of the fourth transfer electrode TS14 (for example, perpendicular to the routing direction of the fourth transfer electrode TS14) is, for example, about 14-15 microns, and the value of the width W15 is, for example, about 14.5 microns. The width W15 of the fourth transfer electrode TS14 is relatively large, so that other routing lines (for example, light emitting control signal lines, gate scanning signal lines, etc.) between two first pixel units P11 that are adjacently arranged and belong to different first pixel unit groups P10 can be shielded to reduce the generation of light interference.

[0146] For example, Fig.9D for Figure 6 The schematic diagram of the sub-pixel arrangement of the first display area is shown in FIG. Fig.9D As shown, the three first pixel units P11 of the first pixel unit group P10 can include a red sub-pixel (R), a green sub-pixel (G1) and a blue sub-pixel (B), that is, the light-emitting device 11 of the first pixel unit P1 on the left side of the first pixel unit group P10 emits red light, the light-emitting device 11 of the first pixel unit P1 in the middle of the first pixel unit group P10 emits green light, and the light-emitting device 11 of the first pixel unit P1 on the right side of the first pixel unit group P10 emits blue light to display the picture. The light-emitting color of the first pixel unit P11 of the first pixel unit group P10 can be selected according to actual display needs, and the embodiments of the present disclosure are not limited thereto.

[0147] In another embodiment of the present disclosure, for example, Fig.10 A schematic diagram of a planar layout of wiring in a first display area of ​​a display substrate provided in at least one further embodiment of the present disclosure. Fig.11 for Fig.10 Magnified view of the A21 region in the middle. Figure 13A-13C for Fig.10 A plan view of each layer of wiring in the first display area is shown. Fig.13A for Fig.10 The schematic plan view of the wiring in the first display area located in the first conductive layer GA21 is shown. Fig. 13B for Fig.10 The schematic plan view of the wiring in the first display area located in the second conductive layer GA22 is shown. Fig. 13C for Fig.10 FIG. 1 is a schematic plan view of wiring in the first display area located in the third conductive layer SD21 .

[0148] For example, Fig.10 as well as Fig. 13C As shown, the first display area 10 includes a plurality of first pixel unit groups P20, a plurality of first signal lines DATA1 and a plurality of first power lines VDD1. The plurality of first pixel unit groups P20 are arranged in a plurality of rows and columns in a staggered manner, that is, according to Figure 1BThe arrangement shown in the figure, that is, the first pixel unit group P20 in the first column and the first pixel unit group P20 in the second column are staggered. The first pixel unit group P20 includes four first pixel units P21 arranged in two rows and two columns along the second direction X1 and the first direction Y1. A plurality of first signal lines DATA1 and a plurality of first power lines VDD1 extend along the first direction Y1. Each of the plurality of first signal lines DATA1 corresponds to and is electrically connected to the first pixel units P21 of the plurality of first pixel unit groups P20. Each of the plurality of first power lines VDD1 corresponds to and is electrically connected to the first pixel units P21 of the plurality of first pixel unit groups P20. In other words, a first signal line DATA1 and a first power line VDD1 are respectively connected to each first pixel unit P21. The first signal line DATA1 is configured to provide a first display signal to the first pixel unit P21. The first power line VDD1 is configured to provide a first power supply voltage to the plurality of first pixel units P21.

[0149] For example, in the same first pixel unit group P20 (eg Fig. 13C In the first pixel unit group P20 located on the right side, the first signal lines DATA1 connected to the first pixel units P21 in the same column are connected to each other and formed as one body, and the first power lines VDD1 connected to the first pixel units P21 in the same column are also connected to each other and formed as one body. Fig. 13C The two first pixel unit groups P20 on the left side only show two first pixel units P21, and the complete structure of the two first pixel unit groups P20 on the left side is the same as that of the first pixel unit groups P21. Fig. 13C The first pixel unit group P20 located on the right side is the same.

[0150] For example, Fig. 13C As shown, the first power line VDD1 and the first signal line DATA1 in the same first pixel unit P21 are arranged in parallel. The lower portion of the first signal line DATA1 on the left side in the same first pixel unit group P20 (the portion used to connect to the switching electrode) is bent in a direction close to the first power line VDD1 on the right side (for connecting to the connecting wiring). The lower portion of the first signal line DATA1 on the right side in the same first pixel unit group P20 (the portion used to connect to the switching electrode) is bent in a direction away from the first power line VDD1 on the right side (for connecting to the connecting wiring). The lower portion of the first power line VDD1 on the right side in the same first pixel unit group P20 (the portion used to connect the wiring) is bent to the right side (the same bending direction as the lower portion of the first signal line DATA1 on the right side in the same first pixel unit group P20). Fig. 13C In the same first pixel unit group P20, the upper portion of the first signal line DATA1 on the right side (the portion used for switching electrodes) is bent to the right side.

[0151] For example, the display substrate 1 further includes at least one connecting wire, at least part of which extends along the first direction and is connected to the first power lines respectively connected to the adjacent first pixel unit groups in the first direction. Fig.10 , Fig.11 as well as Fig. 13C As shown, the display substrate 1 also includes a plurality of connecting wires (e.g., a plurality of first connecting wires LS21), each of the plurality of connecting wires includes a portion extending along the first direction Y1 and a portion extending along the second direction X1, and is connected to the first power line VDD1 respectively connected to the first pixel unit group P20 adjacent in the first direction Y1. That is, the first power line VDD1 in two corresponding first pixel units P21 of the first pixel unit group P20 adjacent in the first direction Y1 is connected to the connecting wire (e.g., the first connecting wire LS21). For example, the first power line VDD1 connected to the first pixel unit group P20 adjacent in the first direction Y1 is connected through a connecting wire (e.g., the first connecting wire LS21). That is, the first power line VDD1 in one of the two first pixel units P21 of the first pixel unit group P20 is connected to the connecting wire (e.g., the first connecting wire LS21) to reduce the number of wires and increase the aperture ratio and light transmittance of the first display area 10.

[0152] For example, the display substrate 1 further includes at least one switching electrode, at least part of which extends along the first direction and is connected to the first signal lines respectively connected to the adjacent first pixel unit groups in the first direction. Fig.10 as well as Fig.11As shown, the display substrate 1 further includes a plurality of switching electrodes, for example, the switching electrodes include a first switching electrode TS21 and a second switching electrode TS22. The main part of each of the plurality of switching electrodes (that is, most of the switching electrodes) extends along the first direction Y1, and is respectively connected to the first signal lines DATA1 respectively connected to the first pixel unit groups P20 adjacent to each other in the first direction Y1. That is, the first signal lines DATA1 in two corresponding first pixel units P21 of the first pixel unit groups P20 adjacent to each other in the first direction Y1 are connected to one of the plurality of switching electrodes (the first switching electrode TS21 or the second switching electrode TS22). For example, the first signal line DATA1 connected to two first pixel units P21 adjacent to each other in the first direction Y1 is connected through a switching electrode (the first switching electrode TS21 or the second switching electrode TS22). The plurality of switching electrodes are connected one-to-one to a plurality of first pixel units P21 adjacent to each other in the first direction Y1 and belonging to different first pixel unit groups P20. That is, the first signal line DATA1 in one of the two first pixel units P21 in the same row of the first pixel unit group P20 (for example, located near the left side of one pixel unit P20) is connected to a switching electrode (for example, the first switching electrode TS21). The first signal line DATA1 in the other of the two first pixel units P21 in the same row of the first pixel unit group P20 (for example, located near the right side of one pixel unit P20) is connected to a switching electrode (for example, the second switching electrode TS22).

[0153] For example, a plurality of connection traces (such as the first connection trace LS21) are located on a side of a plurality of transfer electrodes (such as the first transfer electrode TS21 or the second transfer electrode TS22) away from the base substrate. Fig.11As shown, the orthographic projection of the connecting trace (e.g., the first connecting trace LS21) on the base substrate 100 overlaps with the orthographic projection of the switching electrode (e.g., the first switching electrode TS21 and the second switching electrode TS22) on the base substrate 100. For example, the orthographic projection of the switching electrode (e.g., the first switching electrode TS21 and the second switching electrode TS22) on the base substrate 100 overlaps with the orthographic projection of the connecting trace (e.g., the first connecting trace LS21) on the base substrate 100. For example, the orthographic projection of the portion of the transfer electrode (for example, the first transfer electrode TS21 and the second transfer electrode TS22) extending along the first direction Y1 on the base substrate 100 is located in the orthographic projection of the connecting trace (for example, the first connecting trace LS21) on the base substrate, so that the connecting trace overlaps with the transfer electrode and blocks the transfer electrode, thereby reducing the wiring space of the transfer electrode, improving the aperture ratio and transmittance of the first display area, and reducing the occurrence of light interference between different traces, thereby allowing, for example, a sensor to be set in the first display area and on the second side S2 of the display substrate 1 for sensing (for example, imaging), and improving the sensing effect (imaging quality) of the sensor.

[0154] For example, Fig.10 as well as Fig. 13C As shown, there is a gap allowing light transmission between the first pixel unit group P20 adjacent to each other in the first direction Y1 and the second direction X1. Portions of the connecting wire (e.g., the first connecting wire LS21) and the switching electrode (e.g., the first switching electrode TS21 and the second switching electrode TS22) extend along the second direction X1 and bypass the gap allowing light transmission. Fig.10 As shown in , the connecting line (e.g., the first connecting line LS21) and the transfer electrode (e.g., the first transfer electrode TS21 and the second transfer electrode TS22) first extend in the direction close to the first pixel unit group P20 on the right side along the second direction X1, then extend in the first direction Y1, and then extend in the direction away from the first pixel unit group P20 on the right side, so that the connecting line (e.g., the first connecting line LS21) and the transfer electrode (e.g., the first transfer electrode TS21 and the second transfer electrode TS22) are connected to two adjacent first pixel unit groups P20 in the first direction Y1. That is to say, the connecting line (e.g., the first connecting line LS21) and the transfer electrode (e.g., the first transfer electrode TS21 and the second transfer electrode TS22) are "three-segment folded line" to leave a larger gap between the first pixel unit groups P20, thereby preventing light interference.

[0155] For example, the at least one connecting line includes a first connecting line. Fig. 13CAs shown, the first connecting line LS21 is a meandering line, and includes a first part LSP1, a second part LSP2 and a third part LSP3. The first part LSP1 and the second part LSP2 extend along the second direction X1, and the third part LSP3 extends along the first direction Y1. The first end LSP11 of the first part LSP1 and the first end LSP21 of the second part LSP2 are respectively connected to the two ends of the third part LSP3, so that the first connecting line LS21 is set as a meandering line composed of three sections. The second end LSP12 of the first part LSP1 and the second end LSP22 of the second part LSP2 are respectively connected to the first power line VDD1 connected to the adjacent first pixel units P21 in the first direction Y1. That is, the first connecting line LS21 is connected to the first power line VDD1 connected to the adjacent first pixel units P21 in the first direction Y1 and belonging to different first pixel unit groups P20. As shown in the figure, there is a gap between the adjacent first pixel unit groups P20 in the first direction Y1 to allow light from the first side S1 of the display substrate 1 to pass through. One of the two first pixel units P21 of the first pixel unit group P20 adjacent to each other in the first direction Y1 (eg, the middle pixel unit P31 ) is connected to the first connection line LS21 to reduce the number of lines and increase the aperture ratio and transmittance of the first display area 10 .

[0156] For example, the first connection line and the first power line are arranged in the same layer and are formed integrally. Fig.12 for Fig.11 The line C11-C12 passes through the first transfer electrode TS21, the first connection line LS21 and the second transfer electrode TS22 along the second direction Y1. Fig.12 As shown, the first connection line LS21 is located on the side of the third insulating layer 143 away from the base substrate 100, and the first power line VDD1 and the first connection line LS21 are arranged in the same layer and are formed integrally through the same patterning process. Fig. 13C As shown, the first connection line LS21 and the first power line VDD1 are located in the third conductive layer SD21.

[0157] For example, Fig.11 , Fig.13A as well as Fig. 13BAs shown, the plurality of transfer electrodes include a first transfer electrode TS21 and a second transfer electrode TS12. The shapes of the first transfer electrode TS21 and the second transfer electrode TS22 are the same as the shape of the first connection line LS21, that is, a bent line formed by connecting three sections of lines. The first transfer electrode TS21 and the second transfer electrode TS12 are arranged in parallel, and first extend in the second direction X1 toward the direction close to the first pixel unit group P20 on the right side, then extend in the first direction Y1, and then extend in the direction away from the first pixel unit group P20 on the right side, so as to leave a larger gap between the first pixel unit groups P20, thereby preventing light interference.

[0158] For example, the orthographic projections of the first switching electrode and the second switching electrode on the substrate overlap with the orthographic projections of at least one of the first part, the second part, and the third part of the first connecting trace on the substrate. Fig.11 as well as Fig.12 As shown, the orthographic projections of the first switching electrode TS21 and the second switching electrode TS22 on the substrate substrate overlap (for example, partially overlap) with the orthographic projections of the first part LSP1, the second part LSP2 and the third part LSP3 of the first connecting line LS21 on the substrate substrate. For example, the orthographic projection of the first switching electrode TS21 on the substrate substrate 100 is located in the orthographic projections of the first part LSP1, the second part LSP2 and the third part LSP3 of the first connecting line LS21 on the substrate substrate 100, that is, the first switching electrode TS2 is completely blocked by the first connecting line LS21. The orthographic projection of the second switching electrode TS22 on the substrate substrate 100 is not completely located in the overlapped orthographic projections of the first part LSP1, the second part LSP2 and the third part LSP3 of the first connecting line LS21 on the substrate substrate, and the orthographic projection of the part of the second switching electrode TS22 that is routed along the second direction X1 on the substrate substrate 100 partially overlaps with the orthographic projection of the first part LSP1 of the first connecting line LS21 on the substrate substrate 100. For example, the first connection line LS21 may be increased in width so that the first connection line LS21 completely blocks the portion of the second transfer electrode TS22 that is routed along the second direction X1. In the above case, the space occupied by the first transfer electrode TS11 and the second transfer electrode TS12 may be reduced, the aperture ratio and light transmittance of the first display area may be increased, and the generation of light interference between different routes may be reduced.

[0159] For example, Fig.13A as well as Fig. 13BAs shown, the first switching electrode TS21 and the second switching electrode TS22 are connected to the first signal line DATA1 respectively connected to the first pixel units P21 adjacent to each other in the first direction Y1 and belonging to different first pixel unit groups P20. That is, the two first pixel units P21 located in two columns and belonging to the same first pixel unit group P20 are respectively connected to the first switching electrode TS2 and the second switching electrode TS22. The portions of the first switching electrode TS11 and the second switching electrode TS12 extending along the first direction Y1 are close to the first pixel unit group P20 on the right side of the figure to reduce light interference.

[0160] For example, Fig.13A As shown in FIG. 1 , the second transfer electrode TS22 is in a concave shape and opens to the right side (away from the first connection trace LS21 ) in the figure. Fig. 13B As shown, the first transfer electrode TS21 is in a concave shape opening to the left (away from the first connection line LS21). The second transfer electrode TS22 and the second transfer electrode TS21 have opposite directions and converge to the position of the first connection line LS21 to overlap with the first connection line LS21.

[0161] For example, the film layers where the plurality of transfer electrodes are located are different from the base substrate. Fig.12 As shown, the first transfer electrode TS21 and the second transfer electrode TS22 are located in different film layers relative to the base substrate 100. The first transfer electrode TS21 is located between the second insulating layer 142 and the third insulating layer 143. Fig. 13B As shown, the first switching electrode TS21 is located on the second conductive layer GA22. The second switching electrode TS22 is located between the first insulating layer 141 and the second insulating layer 142. Fig.13A As shown, the second transfer electrode TS22 is located in the first conductive layer GA21. The second insulating layer 142 insulates the first transfer electrode TS21 and the second transfer electrode TS22. The first transfer electrode TS21 and the second transfer electrode TS22 are located in different film layers, which can reduce the size of the interval between the first transfer electrode TS21 and the second transfer electrode TS22, thereby reducing the space occupied by the first transfer electrode TS21 and the second transfer electrode TS22.

[0162] For example, Fig.12As shown, the value range of the width W21 of the cross section of the first connection trace LS21 along the second direction X1 is, for example, about 4.5-5.5 microns, and the value of the width W21 is, for example, about 5 microns. The value range of the width W22 of the cross section of the first transfer electrode TS21 along the second direction Y1 is, for example, about 2-3 microns, and the value of the width W22 is, for example, about 2.5 microns. The value range of the width W23 of the cross section of the second transfer electrode TS22 along the second direction Y1 is, for example, about 2-3 microns, and the value of the width W23 is, for example, about 2.5 microns. The value range of the width W24 of the gap between the first transfer electrode TS21 and the second transfer electrode TS22 along the second direction Y1 is, for example, about 1-2 microns, and the value of the width W3 is, for example, about 0.8 microns.

[0163] For example, Fig.11 As shown, the first signal line DATA1 (located on the left side of the figure) is connected to the first switching electrode TS21 through the first via hole GH21. The first signal line DATA1 (located on the right side of the figure) is connected to the second switching electrode TS22 through the second via hole GH22. Figure 3A , Figure 4B As shown in FIG. 4C , the first via hole GH21 and the first via hole GH1 are both via holes penetrating the third insulating layer 143 , and the second via hole GH22 and the second via hole GH2 are both via holes penetrating the third insulating layer 143 and the second insulating layer 142 .

[0164] For example, Fig.10 as well as Fig.21 As shown, the four first pixel units P20 of the first pixel unit group P20 are arranged in two rows and two columns, that is, in the same row, the first pixel unit group P10 includes two first pixel units P20. Each first pixel unit P21 of the first pixel unit group P20 includes a first pixel driving circuit 12 and a first light-emitting device 11, and the first pixel driving circuit 12 is electrically connected to the first light-emitting device 11 and drives the first light-emitting device 11 to emit light. The first pixel driving circuit 12 includes a storage capacitor 13, and the storage capacitor 13 includes a first electrode plate CE1 and a second electrode plate CE2 that is overlapped (for example, partially overlapped) with the first electrode plate CE1. The first electrode plate CE1 is located on a side of the second insulating layer 142 away from the substrate 100. The second electrode plate CE2 is located on a side of the first insulating layer 141 away from the substrate 100. For example, as Fig. 13B As shown, the first electrode plate CE1 is located on the second conductive layer GA22.

[0165] For example, Fig.10 as well as Fig. 20AAs shown, a plurality of first power lines VDD1 correspondingly connected to each first pixel unit P20 are connected to the first electrode plate CE1 through via holes VH9 and VH3 penetrating the third insulating layer 143. The first power line VDD1 may also be connected to the first electrode plate CE1 through one of the via holes VH9 and VH3.

[0166] For example, Fig.10 ,as well as Fig. 13B As shown, the first electrodes CE11 of the two first pixel units P11 in the same row of the first pixel unit group P20 are interconnected and formed in one piece, so as to save the manufacturing process and reduce the cost. That is to say, the first power line VDD1 in each first pixel unit P21 is connected to the first electrode CE1 of the storage capacitor 13 of the first pixel unit P11 corresponding to it, so as to be electrically connected to the first pixel unit P21, and the first power lines VDD1 in the two first pixel units P21 are electrically connected by interconnecting the first electrodes CE1 of the two first pixel units P11 in the same row of the first pixel unit group P20. The first power lines VDD1 in different rows are connected to each other and formed in one piece. As mentioned above, when the first power lines VDD1 in the two first pixel units P21 in the same row of a first pixel unit group P20 are electrically connected, the first power line VDD1 in one of the two first pixel units P21 can be connected by setting a first connecting wire LS21 to reduce the number of wires.

[0167] For example, Fig.10 as well as Fig. 13B As shown, the display substrate 1 further includes a fourth transfer electrode TS24, which extends along the second direction X1. The fourth transfer electrode TS24 is electrically connected to the first power line VDD1 to which the first pixel units P21 adjacent to the second direction X1 and belonging to different first pixel unit groups P20 are respectively connected. Fig.10 As shown in FIG. , a plurality of first pixel unit groups P20 ( Figure 6 3 first pixel unit groups P20 are shown, arranged as follows Figure 1B That is, the plurality of first pixel unit groups P10 in two adjacent columns are located in different rows, so as to leave more gaps between the first pixel unit groups P20, thereby allowing light from the first side S1 of the display substrate 1 to pass through.

[0168] For example, Fig.10 as well as Fig. 13BAs shown, both ends of the fourth switching electrode TS24 are respectively connected to the first electrode plates CE1 of two first pixel units P21 that are adjacently arranged and belong to different first pixel unit groups P20, so as to electrically connect the first power lines VDD1 located in the different first pixel units P21. Since the two first pixel units P21 that are adjacently arranged and belong to different first pixel unit groups P20 are located in different rows along the second direction X1, the fourth switching electrode TS24 includes a portion extending along the first direction Y1.

[0169] For example, Fig. 13B As shown, the fourth transfer electrode TS24 is located in the second conductive layer GA22 and is connected to the first electrode plate CE1 of the first pixel unit P21 and can be formed integrally.

[0170] For example, Fig. 13B As shown, when the four first pixel units P20 of the first pixel unit group P20 are arranged in two rows and two columns, the first pixel unit P21 located in the first row and the first pixel unit P21 located in the second row of the first pixel unit group P20 are connected to different fourth switching electrodes TS24. Fig. 13B Taking the first pixel unit group P20 on the right side shown in the figure (four first pixel units P21 are shown in the figure) as an example, the first electrode plate CE1 of the first pixel unit P21 in the first column of the first row (i.e., the left side) of the first pixel unit group P20 is connected to the fourth switching electrode TS24 at the upper left, and the fourth switching electrode TS24 at the upper left is also connected to the first electrode plate CE1 of the first pixel unit P21 in the second column of the second row (i.e., the right side) of the first pixel unit group P20 located at the upper left. The first electrode plate CE1 of the first pixel unit P21 in the second column of the first row (i.e., the right side) of the first pixel unit group P20 is connected to the fourth switching electrode TS24 at the upper right, and the fourth switching electrode TS24 at the upper right is also connected to the first electrode plate CE1 (not shown in the figure) of the first pixel unit P21 in the first column of the second row (i.e., the left side) of the first pixel unit group P20 located at the upper right. The first electrode plate CE1 of the first pixel unit P21 in the first column of the second row (i.e., the left side) of the first pixel unit group P20 is connected to the fourth switching electrode TS24 at the lower left, and the fourth switching electrode TS24 at the lower left is also connected to the first electrode plate CE1 of the first pixel unit P21 in the second column of the first row (i.e., the right side) of the first pixel unit group P20 located at the lower left. The first electrode plate CE1 of the first pixel unit P21 in the second column of the second row (i.e., the right side) of the first pixel unit group P20 is connected to the fourth switching electrode TS24 at the lower right, and the fourth switching electrode TS24 at the upper right is also connected to the first electrode plate CE1 (not shown in the figure) of the first pixel unit P21 in the first column of the first row (i.e., the left side) of the first pixel unit group P20 located at the lower right.

[0171] For example, Fig.11 As shown, the value range of the width W25 of the fourth transfer electrode TS24 (eg, perpendicular to the wiring direction of the fourth transfer electrode TS24 ) is, for example, approximately 2-3 microns, and the value of the width W15 is, for example, approximately 2.5 microns.

[0172] For example, Fig.13D for Fig.10 The schematic diagram of the sub-pixel arrangement of the first display area is shown in FIG. Fig.13D As shown, the four first pixel units P21 arranged in two rows and two columns of the first pixel unit group P20 may respectively include a red sub-pixel (R), a blue sub-pixel (B), a green sub-pixel (G1) and a green sub-pixel (G2) (that is, two green sub-pixels), that is, in a first pixel unit group P20 (taking the four first pixel units P21 on the right side of the figure as an example), the two first pixel units P21 located in the first row include a blue sub-pixel (B) and a green sub-pixel (G2), and the two first pixel units P21 located in the second row include a red sub-pixel (R) and a green sub-pixel (G2). (G1), that is, in a first pixel unit group P20 (taking the four first pixel units P21 on the right side of the figure as an example), the light-emitting device 11 of the first pixel unit P21 in the first column of the first row (i.e., the upper left corner) emits blue light, the light-emitting device 11 of the first pixel unit P21 in the second column of the first row (i.e., the upper right corner) emits green light, the light-emitting device 11 of the first pixel unit P21 in the first column of the second row (i.e., the lower left corner) emits red light, and the light-emitting device 11 of the first pixel unit P21 in the second column of the second row (i.e., the lower right corner) emits green light to display the picture. The light-emitting color of the first pixel unit P21 of the first pixel unit group P20 can be selected according to actual display needs, and the embodiments of the present disclosure are not limited thereto.

[0173] In another embodiment of the present disclosure, for example, Fig.14 A schematic diagram of a planar layout of wiring in a first display area of ​​a display substrate provided in at least one further embodiment of the present disclosure. Fig.15 for Fig.14 Magnified view of the A31 region in the middle. Figure 17A-17C for Fig.14 A plan view of each layer of wiring in the first display area is shown. Fig.17A for Fig.14 The schematic plan view of the wiring in the first display area located on the first conductive layer GA31 is shown. Fig. 17B for Fig.14 The schematic plan view of the wiring in the first display area located in the second conductive layer GA32 is shown. Fig. 17C for Fig.14 FIG. 1 is a schematic plan view of wiring in the first display area located in the third conductive layer SD31 .

[0174] For example, Fig.14 as well as Fig. 17C As shown, the first display area 10 includes a plurality of first pixel unit groups P30, a plurality of first signal lines DATA1 and a plurality of first power lines VDD1. The plurality of first pixel unit groups P30 are arranged in a plurality of rows and columns in a staggered manner, that is, according to Figure 1B The arrangement shown, that is, the first pixel unit group P30 in the first column and the first pixel unit group P30 in the second column are staggered with each other (that is, located in two adjacent rows). The first pixel unit group P30 includes four first pixel units P31 arranged in two rows and two columns along the second direction X1 and the first direction Y1. A plurality of first signal lines DATA1 and a plurality of first power lines VDD1 extend along the first direction Y1. Each of the plurality of first signal lines DATA1 corresponds to and is electrically connected to the first pixel units P31 of the plurality of first pixel unit groups P30. Each of the plurality of first power lines VDD1 corresponds to and is electrically connected to the first pixel units P31 of the plurality of first pixel unit groups P30. In other words, a first signal line DATA1 and a first power line VDD1 are respectively connected to each first pixel unit P31. The first signal line DATA1 is configured to provide a first display signal to the first pixel unit P31. The first power line VDD1 is configured to provide a first power supply voltage to the plurality of first pixel units P31.

[0175] For example, in the same first pixel unit group P30, the first signal lines DATA1 connected to the first pixel units P31 in the same column are connected to each other and formed as one body, and the first power lines VDD1 connected to the first pixel units P31 in the same column are also connected to each other and formed as one body. It should be noted that FIG. 14 only shows two first pixel unit groups P30.

[0176] For example, Fig. 17C As shown, the first power line VDD1 and the first signal line DATA1 in the same first pixel unit P31 are arranged in parallel. The lower part of the first signal line DATA1 on the left side in the same first pixel unit group P30 (the part used to connect the switching electrode) is bent to the right side (for example, bent toward the first power line VDD1 connected to the connecting line).

[0177] For example, the display substrate 1 further includes at least one connecting wire, at least part of which extends along the first direction and is connected to the first power lines respectively connected to the adjacent first pixel unit groups in the first direction. Fig.14 , Fig.15 as well as Fig. 17CAs shown, the display substrate 1 also includes a plurality of connecting wires (e.g., a plurality of first connecting wires LS31), each of which extends along the first direction Y1 and is connected to the first power line VDD1 respectively connected to the first pixel unit group P30 adjacent to the first direction Y1. That is, the first power line VDD1 in two corresponding first pixel units P31 of the first pixel unit group P30 adjacent to the first direction Y1 is connected to the connecting wire (e.g., the first connecting wire LS31). For example, the first power line VDD1 connected to the first pixel unit group P30 adjacent to the first direction Y1 is connected through a connecting wire (e.g., the first connecting wire LS31). That is, the first power line VDD1 in one of the two first pixel units P31 of the first pixel unit group P30 is connected to the connecting wire (e.g., the first connecting wire LS31) to reduce the number of wires and increase the aperture ratio and light transmittance of the first display area 10.

[0178] For example, the display substrate 1 further includes at least one switching electrode, at least part of which extends along the first direction and is connected to the first signal lines respectively connected to the adjacent first pixel unit groups in the first direction. Fig.14 as well as Fig.15 As shown, the display substrate 1 further includes a plurality of switching electrodes, for example, the switching electrodes include a first switching electrode TS31 and a second switching electrode TS32. The main part of each of the plurality of switching electrodes (that is, most of the switching electrodes) extends along the first direction Y1, and is respectively connected to the first signal lines DATA1 respectively connected to the first pixel unit groups P30 adjacent to each other in the first direction Y1. That is, the first signal lines DATA1 in two corresponding first pixel units P31 of the first pixel unit groups P30 adjacent to each other in the first direction Y1 are connected to one of the plurality of switching electrodes (the first switching electrode TS31 or the second switching electrode TS32). For example, the first signal line DATA1 connected to two first pixel units P31 adjacent to each other in the first direction Y1 is connected through a switching electrode (the first switching electrode TS31 or the second switching electrode TS32). The plurality of switching electrodes are connected one-to-one to a plurality of first pixel units P31 adjacent to each other in the first direction Y1 and belonging to different first pixel unit groups P30. That is, the first signal line DATA1 in one of the two first pixel units P31 in the same row of the first pixel unit group P30 (for example, located near the left side of one pixel unit P30) is connected to a switching electrode (for example, the first switching electrode TS31). The first signal line DATA1 in the other of the two first pixel units P31 in the same row of the first pixel unit group P30 (for example, located near the right side of one pixel unit P30) is connected to a switching electrode (for example, the second switching electrode TS32).

[0179] For example, Fig.14 as well as Fig.15 As shown, a plurality of connection lines (eg, first connection lines LS31) are located on a side of a plurality of transfer electrodes (eg, first transfer electrodes TS31 or second transfer electrodes TS32) away from the substrate. Fig.15 As shown, the orthographic projection of the connecting trace (e.g., the first connecting trace LS31) on the base substrate 100 overlaps with the orthographic projection of the switching electrode (e.g., the first switching electrode TS31 and the second switching electrode TS32) on the base substrate 100. For example, the orthographic projection of the switching electrode (e.g., the first switching electrode TS31 and the second switching electrode TS32) on the base substrate 100 overlaps with the orthographic projection of the connecting trace (e.g., the first connecting trace LS31) on the base substrate 100. For example, the orthographic projection of the portion of the transfer electrode (such as the first transfer electrode TS31 and the second transfer electrode TS32) extending along the first direction Y1 on the base substrate 100 is located in the orthographic projection of the connecting trace (such as the first connecting trace LS31) on the base substrate 100, so that the connecting trace overlaps with the transfer electrode and blocks the transfer electrode, thereby reducing the wiring space of the transfer electrode, improving the aperture ratio and transmittance of the first display area, and reducing the occurrence of light interference between different traces, thereby allowing, for example, a sensor to be set in the first display area and on the second side S2 of the display substrate 1 for sensing (such as imaging), and improving the sensing effect (imaging quality) of the sensor.

[0180] For example, the at least one connecting line includes a first connecting line. Fig. 17C As shown, the first connection line LS31 is respectively connected to the first power line VDD1 connected to the adjacent first pixel units P31 in the first direction Y1 (that is, the first pixel units P31 located in the second column (that is, the right side) of the adjacent first pixel unit group P30 in the first direction Y1). That is, the first connection line LS31 is connected to the first power line VDD1 connected to the first pixel units P31 adjacent in the first direction Y1 and belonging to different first pixel unit groups P30. As shown in the figure, there is a gap between the adjacent first pixel unit groups P30 in the first direction Y1 to allow light from the first side S1 of the display substrate 1 to pass through. One of the two first pixel units P31 of the adjacent first pixel unit group P30 in the first direction Y1 (for example, a pixel unit P31 located in the middle) is connected to the first connection line LS31 to reduce the number of lines and increase the aperture ratio and light transmittance of the first display area 10.

[0181] For example, the first connection line and the first power line are arranged in the same layer and are formed integrally. Fig.16A15 is a schematic cross-sectional view along line C31-C32. Line C31-C32 passes through the first transfer electrode TS31, the first connection trace LS31 and the second transfer electrode TS32 along the second direction X1. Fig.16A As shown, the first connection line LS31 is located on the side of the third insulating layer 143 away from the base substrate 100, and the first power line VDD1 and the first connection line LS21 are arranged in the same layer and are formed integrally through the same patterning process. Fig. 17C As shown, the first connection line LS31 and the first power line VDD1 are located in the third conductive layer SD31. The first connection line LS31 and the first power line VDD1 connected to the first connection line LS31 are located in the first direction Y1.

[0182] For example, Fig.17A as well as Fig. 17B As shown, the plurality of switching electrodes include a first switching electrode TS31 and a second switching electrode TS32, and the portions of the first switching electrode TS31 and the second switching electrode TS32 extending along the first direction YS are arranged in parallel. The first switching electrode TS31 and the second switching electrode TS32 are connected to the first signal line DATA1 respectively connected to the first pixel units P31 adjacent to each other in the first direction Y1 and belonging to different first pixel unit groups P30. That is, the two first pixel units P31 belonging to the same first pixel unit group P30 located in two columns are respectively connected to the first switching electrode TS31 and the second switching electrode TS32. That is, the two first pixel units P31 of the first pixel unit group P30 located in two columns are respectively connected to the first switching electrode TS31 and the second switching electrode TS32. The first switching electrode TS31 and the second switching electrode TS32 first extend along the second direction X1 close to the first switching electrode LS31, and then extend along the first direction Y1. The portions of the first transfer electrode TS31 and the second transfer electrode TS32 extending along the second direction X1 are shorter, and the main portions of the first transfer electrode TS31 and the second transfer electrode TS32 extend along the first direction Y1.

[0183] For example, Fig.17A As shown in FIG. 1 , the second transfer electrode TS32 is in a concave shape or a “]” shape that opens to the right side (away from the first connection trace LS21 ) in the figure. Fig. 17B As shown, the first transfer electrode TS31 is in a "concave" shape or "[" shape that opens to the left side (away from the first connection line LS21) in the figure. The second transfer electrode TS32 and the second transfer electrode TS31 have opposite directions and both converge to the position where the first connection line LS31 is located to overlap with the first connection line LS31.

[0184] For example, the film layers where the plurality of transfer electrodes are located are different from the base substrate. Fig.16A As shown, relative to the base substrate 100, the first transfer electrode TS31 and the second transfer electrode TS32 are located in different film layers. The first transfer electrode TS31 is located between the second insulating layer 142 and the third insulating layer 143. Fig. 17B As shown, the first transfer electrode TS31 is located in the second conductive layer GA32. The second transfer electrode TS32 is located between the first insulating layer 141 and the second insulating layer 142. For example, as shown in FIG. 17A , the second transfer electrode TS32 is located in the first conductive layer GA31. The second insulating layer 142 insulates the first transfer electrode TS31 and the second transfer electrode TS32. The first transfer electrode TS31 and the second transfer electrode TS32 are located in different film layers, which can reduce the size of the interval between the first transfer electrode TS31 and the second transfer electrode TS32, thereby reducing the space occupied by the first transfer electrode TS31 and the second transfer electrode TS32.

[0185] For example, Fig.16A As shown, the value range of the width W31 of the cross section of the first connection trace LS31 along the second direction X1 is, for example, about 5-6 microns, and the value of the width W31 is, for example, about 5.5 microns. The value range of the width W32 of the cross section of the first transfer electrode TS31 along the second direction X1 is, for example, about 2-3 microns, and the value of the width W32 is, for example, about 2.5 microns. The value range of the width W33 of the cross section of the second transfer electrode TS32 along the second direction X1 is, for example, about 2-3 microns, and the value of the width W33 is, for example, about 2.5 microns. The value range of the width W34 of the gap between the first transfer electrode TS31 and the second transfer electrode TS32 along the second direction X1 is, for example, about 0.2-1.5 microns, and the value of the width W34 is, for example, about 0.5 microns.

[0186] For example, Fig.15 As shown, the first signal line DATA1 (located on the left side of the figure) is connected to the first switching electrode TS31 through the first via hole GH31. The first signal line DATA1 (located on the right side of the figure) is connected to the second switching electrode TS32 through the second via hole GH32. Figure 3A , Figure 4B As shown in FIG. 4C , the first via hole GH31 and the first via hole GH1 are both via holes penetrating the third insulating layer 143 , and the second via hole GH32 and the second via hole GH2 are both via holes penetrating the third insulating layer 143 and the second insulating layer 142 .

[0187] For example, Fig.14 as well as Fig.21As shown, the four first pixel units P30 of the first pixel unit group P30 are arranged in two rows and two columns, that is, in the same row, the first pixel unit group P30 includes two first pixel units P30. Each first pixel unit P31 of the first pixel unit group P30 includes a first pixel driving circuit 12 and a first light-emitting device 11, and the first pixel driving circuit 12 is electrically connected to the first light-emitting device 11 and drives the first light-emitting device 11 to emit light. The first pixel driving circuit 12 includes a storage capacitor 13, and the storage capacitor 13 includes a first electrode plate CE1 and a second electrode plate CE2 that is overlapped (for example, partially overlapped) with the first electrode plate CE1. The first electrode plate CE1 is located on a side of the second insulating layer 142 away from the substrate substrate 100. The second electrode plate CE2 is located on a side of the first insulating layer 141 away from the substrate substrate 100. For example, as Fig. 17B As shown, the first electrode plate CE1 is located on the second conductive layer GA22.

[0188] For example, Fig.14 as well as Fig. 20A As shown, a plurality of first power lines VDD1 correspondingly connected to each first pixel unit P30 are connected to the first electrode plate CE1 through via holes VH9 and VH3 penetrating the third insulating layer 143. The first power line VDD1 may also be connected to the first electrode plate CE1 through one of the via holes VH9 and VH3.

[0189] For example, Fig.14 as well as Fig. 17B As shown, the first electrodes CE1 of the two first pixel units P31 in the same row of the first pixel unit group P30 are interconnected and formed in one piece to save the manufacturing process and reduce the cost. That is to say, the first power line VDD1 in each first pixel unit P31 is connected to the first electrode CE1 of the storage capacitor 13 of the first pixel unit P31 corresponding to it, so as to be electrically connected to the first pixel unit P31, and the first power lines VDD1 in the two first pixel units P31 are electrically connected by interconnecting the first electrodes CE1 of the two first pixel units P31 in the same row of the first pixel unit group P30. The first power lines VDD1 in different rows are connected to each other and formed in one piece. As mentioned above, when the first power lines VDD1 in the two first pixel units P31 in the same row of a first pixel unit group P30 are electrically connected, the first power line VDD1 in one of the two first pixel units P31 can be connected by setting a first connecting wire LS31 to reduce the number of wires.

[0190] For example, Fig.10 as well as Fig. 13BAs shown, the display substrate 1 further includes a fourth transfer electrode TS34, and the fourth transfer electrode TS24 (for example, a majority of the fourth transfer electrode TS24) extends along the second direction X1. The fourth transfer electrode TS34 is electrically connected to the first power line VDD1 to which the first pixel units P31 adjacent to the second direction X1 and belonging to different first pixel unit groups P30 are respectively connected. As shown in FIG. 14, a plurality of first pixel unit groups P30 ( Figure 6 Two first pixel unit groups P30 are shown, arranged as follows Figure 1B That is, the plurality of first pixel unit groups P30 in two adjacent columns are located in different rows, so as to leave more gaps between the first pixel unit groups P30, thereby allowing light from the first side S1 of the display substrate 1 to pass through.

[0191] For example, Fig.14 as well as Fig. 17B As shown, both ends of the fourth transfer electrode TS34 are respectively connected to the first electrode plates CE1 of two first pixel units P31 that are adjacently arranged and belong to different first pixel unit groups P30, so as to electrically connect the first power lines VDD1 located in different first pixel units P31. Since the two first pixel units P11 that are adjacently arranged and belong to different first pixel unit groups P30 are misaligned with each other, the fourth transfer electrode TS24 also includes a portion extending along the first direction Y1. That is, the fourth transfer electrode TS34 first extends along the first direction Y1 and then along the second direction X1, and then along the first direction Y1.

[0192] like Fig.15 , Fig. 17B as well as Fig. 17C As shown, the fourth transfer electrode TS34 includes a first sub-transfer electrode TSP1, a second sub-transfer electrode TSP2 and a third sub-transfer electrode TSP3. The first sub-transfer electrode TSP1 is connected to the first pixel unit group P30 located on the left side in the figure, and is in an "L" shape. The second sub-transfer electrode TSP2 is connected to the first pixel unit group P30 located on the right side in the figure, and is in an "L" shape. The first end TSP11 of the first sub-transfer electrode TSP1 and the first end TSP21 of the second sub-transfer electrode TSP2 are respectively connected to the two ends of the third sub-transfer electrode TSP3. The third sub-transfer electrode TSP3 extends along the second direction X1. The second end TSP2 of the first sub-transfer electrode TSP1 and the second end TSP21 of the second sub-transfer electrode TSP2 are respectively connected to the first electrode plates CE1 of two first pixel units P31 that are adjacently arranged and belong to different first pixel unit groups P30. The third sub-transfer electrode TSP3 can reduce the interference of electrical signals of other routings on the fourth transfer electrode TS34.

[0193] For example, Fig. 16B for Fig.15Schematic diagram of a cross section along line C33-C34. Line C33-C34 passes through the first sub-switching electrode TSP1, the second sub-switching electrode TSP2 and the third sub-switching electrode TSP3. Fig. 16B as well as Fig. 17B As shown, the first sub-transfer electrode TSP1 and the second sub-transfer electrode TSP2 are located between the second insulating layer 142 and the third insulating layer 143, that is, the first sub-transfer electrode TSP1 and the second sub-transfer electrode TSP2 are located in the second conductive layer GA32. The first sub-transfer electrode TSP1 and the second sub-transfer electrode TSP2 are connected to the first electrode plate CE1 of the first pixel unit P31 that is adjacently arranged and belongs to a different first pixel unit group P30, and can be formed integrally.

[0194] For example, Fig. 16B as well as Fig. 17C As shown, the third sub-switching electrode TSP3 is located on the side of the third insulating layer 143 away from the base substrate 100, that is, located on the third conductive layer SD31. The fourth via hole GH33 is a via hole penetrating the third insulating layer, and the fifth via hole GH34 is also a via hole penetrating the third insulating layer. The third sub-switching electrode TSP3 is connected to the first end TSP11 of the first sub-switching electrode TSP1 through the fourth via hole GH33, and the third sub-switching electrode TSP3 is connected to the first end TSP21 of the second sub-switching electrode TSP2 through the fifth via hole GH34.

[0195] For example, Fig.14 As shown in FIG. 1 , when the four first pixel units P20 of the first pixel unit group P30 are arranged in two rows and two columns, the first pixel unit P21 located in the first row of the first pixel unit group P30 is connected to different fourth switching electrodes TS24. Fig.14 Taking the first pixel unit group P30 on the right side shown in the figure (four first pixel units P31 are shown in the figure) as an example, the first electrode plate CE1 of the first pixel unit P31 in the first column of the first row (i.e., the left side) of the first pixel unit group P30 is connected to the fourth switching electrode TS34 in the upper left, and the fourth switching electrode TS34 in the upper left is also connected to the first electrode plate CE1 of the first pixel unit P31 in the second column of the second row (i.e., the right side) of the first pixel unit group P30 located in the upper left. The first electrode plate CE1 of the first pixel unit P31 in the second column of the first row (i.e., the right side) of the first pixel unit group P30 is connected to the fourth switching electrode TS34 in the upper right, and the fourth switching electrode TS34 in the upper right is also connected to the first electrode plate CE1 (not shown in the figure) of the first pixel unit P21 in the first column of the second row (i.e., the left side) of the first pixel unit group P30 located in the upper right.

[0196] In other embodiments, the first electrode plate CE1 of the first pixel unit P31 in the first column of the second row (i.e., the left side) of the first pixel unit group P30 may also be connected to the fourth switching electrode TS34 at the lower left, and the fourth switching electrode TS34 at the lower left is also connected to the first electrode plate CE1 of the first pixel unit P31 in the second column (i.e., the right side) of the first row of the first pixel unit group P30 located at the lower left. The first electrode plate CE1 of the first pixel unit P31 in the second column (i.e., the right side) of the second row of the first pixel unit group P30 is connected to the fourth switching electrode TS34 at the lower right, and the fourth switching electrode TS34 at the upper right is also connected to the first electrode plate CE1 (not shown in the figure) of the first pixel unit P31 in the first column (i.e., the left side) of the first row of the first pixel unit group P30 located at the lower right.

[0197] For example, Fig.15 As shown, the value range of the width W35 of the fourth transfer electrode TS34 (eg, perpendicular to the routing direction of the fourth transfer electrode TS34 ) is, for example, approximately 2-3 microns, and the value of the width W35 is, for example, approximately 2.5 microns.

[0198] For example, Fig.17D for Fig.14 The schematic diagram of the sub-pixel arrangement of the first display area is shown in FIG. Fig.17D As shown, the four first pixel units P31 arranged in two rows and two columns of the first pixel unit group P30 may respectively include a red sub-pixel (R), a blue sub-pixel (B), a green sub-pixel (G1) and a green sub-pixel (G2) (that is, two green sub-pixels), that is, in a first pixel unit group P30, the two first pixel units P31 located in the first row include a red sub-pixel (R) and a green sub-pixel (G1), and the two first pixel units P31 located in the second row include a blue sub-pixel (B) and a green sub-pixel (G2), that is, in a first pixel unit group P30, the light-emitting device 11 of the first pixel unit P31 in the first column of the first row (that is, the upper left corner) emits red light, the light-emitting device 11 of the first pixel unit P31 in the second column of the first row (that is, the upper right corner) emits green light, the light-emitting device 11 of the first pixel unit P31 in the first column of the second row (that is, the lower left corner) emits blue light, and the light-emitting device 11 of the first pixel unit P31 in the second column of the second row (that is, the lower right corner) emits The light emitting color of the first pixel unit P31 of the first pixel unit group P30 can be selected according to actual display needs, and the embodiment of the present disclosure is not limited thereto.

[0199] For example, Figure 2 , Figure 6 , Fig.10 as well as Fig.14The arrangement of the first pixel units and the wiring in the first display area of ​​the display substrate shown respectively are different. In terms of the transmittance of the first display area 10, Fig.10 The embodiment shown is smaller than Figure 6 The embodiment shown is smaller than Fig.14 The embodiment shown is smaller than Figure 2 In terms of the display effect of the first display area 10, Figure 2 The embodiment shown is smaller than Figure 6 The embodiment shown is smaller than Fig.10 The embodiment shown, while Fig.10 The embodiment shown is equivalent to Fig.14 In the embodiment shown, the arrangement of the first pixel units and the wiring in the first display area 10 can be flexibly selected according to the requirements of the product in terms of light transmittance and display effect.

[0200] For example, Figure 1B as well as Figure 1C As shown, the first signal line DATA1 and the first power line VDD1 connected to the first pixel unit of the first pixel unit group P0 (P10 / P20 / P30) close to the second display area 20 extend to the second display area 20 to connect to the second pixel unit C located in the first direction Y1 relative to the first pixel unit P0 (P10 / P20 / P30). That is, the first signal line DATA1 and the first power line VDD1 connected to a row of first pixel units in the first display area 10 located closest to the second display area 20 (for example, the bottom or top of the first display area 10) can be extended to the second display area 20, so as to connect to the second pixel unit C in the second display area 20. Therefore, relative to the first pixel unit in the first display area 10, the second pixel unit C in the first direction Y1 (that is, located in the same column as the first pixel unit in the first display area 10) is connected by a first signal line DATA1 and a first power line VDD1 to provide the same first display signal and first power voltage.

[0201] For example, Fig.18 A schematic diagram of a planar layout of wiring in a second display area of ​​a display substrate provided by at least one embodiment of the present disclosure. Fig.18 As shown, the display substrate further includes a plurality of second signal lines DATA2 and a plurality of second power lines VDD2 located in the second display area 20. The plurality of second pixel units C of the second display area 20 are arranged as a plurality of columns parallel to each other in the second direction X1, that is, arranged as a plurality of rows and columns arranged in an array, and there is no gap between adjacent rows and adjacent columns where the plurality of second pixel units C are arranged. The pixel density of the second display area 20 is greater than that of the first display area 10.

[0202] The second signal line DATA2 extends along the first direction Y1, and each of the plurality of second signal lines DATA2 passes through the plurality of second pixel units C arranged in a column in the first direction Y1, and is electrically connected to the plurality of second pixel units C arranged in a column, so as to provide a second display signal to the plurality of second pixel units C. The second power line VDD2 extends along the first direction Y1, and each of the plurality of second power lines VDD2 passes through the plurality of second pixel units C arranged in a column in the first direction Y1, and is electrically connected to the plurality of second pixel units C arranged in a column, so as to provide a second power supply voltage to the plurality of second pixel units C.

[0203] For example, the structure of the second pixel driving circuit of the second pixel unit C may be the same as the structure of the first pixel driving circuit of the first pixel unit P1 (P11 / P21 / P31), for example, Fig. 20A The structure shown. The electrical connection mode of the second power line VDD2 and the second pixel unit C can be the same as the electrical connection mode of the second power line VDD1 and the first pixel unit P1 (P11 / P21 / P31), that is, the second power line VDD2 is connected to the first electrode plate CE21 of the storage capacitor of the second pixel driving circuit of the second pixel unit C. The first electrodes CE0 of the second pixel units C located in the same row are interconnected and formed as one body, so that the second power supply voltages of the plurality of second pixel units C in the second display area 20 are the same.

[0204] It should be noted that the second pixel driving circuit of the second pixel unit C can select the same circuit structure as the first pixel driving circuit of the first pixel unit P1 (P11 / P21 / P31). For the sake of brevity, the structure of the first pixel driving circuit will be introduced in detail taking the 7T1C circuit as an example, and the first pixel driving circuit will not be repeated.

[0205] For example, Fig.19 An equivalent circuit diagram of a first pixel driving circuit in a first display area of ​​a display substrate provided by at least one embodiment of the present disclosure. Figures 20B-20E A schematic diagram of various layers of a first pixel driving circuit in a first display area of ​​a display substrate provided by at least one embodiment of the present disclosure.

[0206] For example, Fig.19As shown, the first pixel driving circuit includes a plurality of thin film transistors: a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6 and a seventh transistor T7, a plurality of signal lines connected to the plurality of thin film transistors T1, T2, T3, T4, T5, T6 and T7 and a storage capacitor 13, that is, the pixel circuit in this embodiment is a 7T1C structure. Accordingly, the plurality of signal lines include a gate line GLn / GLn-1 (i.e., a scanning signal line), a light emitting control line EM, an initialization line RL, a first signal line DATA1 and a first power line VDD1. The gate line GLn / GLn-1 may include a first gate line GLn and a second gate line GLn-1. For example, the first gate line GLn is used to transmit a gate scanning signal, and the second gate line GLn-1 is used to transmit a reset voltage signal. The light emitting control line EM is used to transmit a light emitting control signal, for example, connected to a first light emitting control terminal EM1 and a second light emitting control terminal EM2. The gate of the fifth transistor T5 is connected to the first light-emitting control terminal EM1, or serves as the first light-emitting control terminal EM1, to receive the first light-emitting control signal; the gate of the sixth transistor T6 is connected to the second light-emitting control terminal EM2, or serves as the second light-emitting control terminal EM2, to receive the second light-emitting control signal.

[0207] It should be noted that the embodiments of the present disclosure include but are not limited to the above-mentioned pixel circuit of the 7T1C structure. The pixel circuit may also adopt other types of circuit structures, such as a 7T2C structure or a 9T2C structure, etc., and the embodiments of the present disclosure are not limited to this.

[0208] For example, Fig.19 As shown, the first gate of the first thin film transistor T1 is electrically connected to the third drain D3 of the third thin film transistor T3 and the fourth drain D4 of the fourth thin film transistor T4. The first source S1 of the first thin film transistor T1 is electrically connected to the second drain D2 of the second thin film transistor T2 and the fifth drain D5 of the fifth thin film transistor T5. The first drain D1 of the first thin film transistor T1 is electrically connected to the third source S3 of the third thin film transistor T3 and the sixth source S6 of the sixth thin film transistor T6.

[0209] For example, Fig.19 As shown, the second gate electrode of the second thin film transistor T2 is configured to be electrically connected to the first gate line GLn to receive the gate scanning signal; the second source electrode S2 of the second thin film transistor T2 is configured to be electrically connected to the first signal line DATA1 to receive the data signal. The second drain electrode D2 of the second thin film transistor T2 is electrically connected to the first source electrode S1 of the first thin film transistor T1.

[0210] For example, Fig.19As shown, the third gate of the third thin film transistor T3 is configured to be electrically connected to the first gate line GLn, the third source S3 of the third thin film transistor T3 is electrically connected to the first drain electrode D1 of the first thin film transistor T1, and the third drain D3 of the third thin film transistor T3 is electrically connected to the first gate of the first thin film transistor T1.

[0211] For example, Fig.19 As shown, the fourth gate of the fourth thin film transistor T4 is configured to be electrically connected to the second gate line GLn-1 to receive the reset voltage signal, the fourth source S4 of the fourth thin film transistor T4 is configured to be electrically connected to the initialization line RL to receive the initialization voltage signal, and the fourth drain D4 of the fourth thin film transistor T4 is electrically connected to the first gate of the first thin film transistor T1.

[0212] For example, Fig.19 As shown, the fifth gate of the fifth thin film transistor T5 is configured to be electrically connected to the light emitting control line EM to receive the light emitting control signal, the fifth source S5 of the fifth thin film transistor T5 is configured to be electrically connected to the first power line VDD1 to receive the first power signal, and the fifth drain D5 of the fifth thin film transistor T5 is electrically connected to the first source S1 of the first thin film transistor T1.

[0213] For example, Fig.19 As shown, the sixth gate of the sixth thin film transistor T6 is configured to be electrically connected to the light emitting control line EM to receive a light emitting control signal, the sixth source S6 of the sixth thin film transistor T6 is electrically connected to the first drain D1 of the first thin film transistor T1, and the sixth drain D6 of the sixth thin film transistor T6 is electrically connected to the first electrode (e.g., the anode 211) of the light emitting element 11. Fig. 22 The thin film transistor T6 in FIG. 1 is the sixth thin film transistor T6.

[0214] For example, Fig.19 As shown, the seventh gate electrode of the seventh thin film transistor T7 is configured to be electrically connected to the second gate line GLn-1 to receive the reset voltage signal, the seventh source electrode S7 of the seventh thin film transistor T7 is electrically connected to the first electrode (e.g., the anode 111) of the light emitting element 11, and the seventh drain electrode D7 of the seventh thin film transistor T7 is configured to be electrically connected to the initialization line RL to receive the initialization voltage signal. For example, the seventh drain electrode D7 of the seventh thin film transistor T7 can be electrically connected to the initialization line RL by being connected to the fourth source electrode S4 of the fourth thin film transistor T4.

[0215] For example, Fig.19 and Fig. 20AAs shown, the storage capacitor 13 includes a first plate CE1 and a second plate CE2. The first plate CE1 is electrically connected to the first power line VDD1, and the second plate CE2 is electrically connected to the first gate electrode of the first thin film transistor T1 and the third drain electrode D3 of the third thin film transistor T3. For example, the first power line VDD1 is connected to the first plate CE1 of the storage capacitor 13 through the third via hole VH3 and the ninth via hole VH9, and the first plate CE1 of the storage capacitor 13 is connected to the first plate CE1 adjacent to the second direction X1 through the first sub-wire 2422.

[0216] For example, Fig.19 As shown, the second electrode (eg, cathode 113) of the light emitting element 11 is electrically connected to the second power line VSS.

[0217] For example, the first power line VDD1 is a power line for providing a high voltage to the first pixel driving circuit, and the second power line VSS is a power line for providing a low voltage (lower than the aforementioned high voltage) to the first pixel driving circuit. Fig.19 In the illustrated embodiment, the first power line VDD1 provides a constant first power voltage, which is a positive voltage; the second power line VSS provides a constant second power voltage, which may be a negative voltage, etc. For example, in some examples, the second power voltage may be a ground voltage.

[0218] It should be noted that the reset voltage signal and the initialization voltage signal may be the same signal.

[0219] It should be noted that the transistors used in the embodiments of the present disclosure may be thin film transistors or field effect transistors or other switching devices with the same characteristics, and the thin film transistors may include oxide semiconductor thin film transistors, amorphous silicon thin film transistors or polycrystalline silicon thin film transistors, etc. The source and drain of the transistor may be symmetrical in structure, so the source and drain may be indistinguishable in physical structure, and the source and drain of all or part of the transistors in the embodiments of the present disclosure may be interchangeable as needed.

[0220] In some embodiments, as shown in 20A, the pixel circuit includes the above-mentioned thin film transistors T1, T2, T3, T4, T5, T6 and T7, a storage capacitor 13, a first gate line GLn connected to multiple thin film transistors T1, T2, T3, T4, T5, T6 and T7, a second gate line GLn-1, a light emitting control line EM, an initialization line RL, a first signal line DATA1 and a first power line VDD1.

[0221] Next, combine Fig.19 and Figures 20A-20E The structure of the pixel circuit is described.

[0222] For example, Fig. 20A It is a schematic layout diagram of the stacking position relationship of the semiconductor layer, the first conductive layer, the second conductive layer and the third conductive layer of the pixel circuit.

[0223] Fig. 20B The semiconductor layers of the pixel circuit are shown. For example, Fig. 20B The semiconductor layer shown includes Fig.21 The active layer 121 shown in FIG. 1 is, for example, the active layer of the sixth thin film transistor T6. Fig. 20B As shown, the semiconductor layer can be formed by a semiconductor material layer through a patterning process. The semiconductor layer can be used to make the active layers of the first thin film transistor T1, the second thin film transistor T2, the third thin film transistor T3, the fourth thin film transistor T4, the fifth thin film transistor T5, the sixth thin film transistor T6 and the seventh thin film transistor T7, and each active layer may include a source region, a drain region and a channel region between the source region and the drain region. For example, the semiconductor layer can be made of amorphous silicon, polycrystalline silicon, oxide semiconductor materials (for example, indium gallium tin oxide (IGZO)), etc. It should be noted that the above-mentioned source region and drain region may be regions doped with n-type impurities or p-type impurities.

[0224] In the display substrate provided in some embodiments of the present disclosure, one or more other insulating layers are formed on the above-mentioned semiconductor layer, and the insulating layer includes Fig.21 For clarity, the first insulating layer 141 is shown in FIG. Figures 20A-20E The insulating layer is not shown in the following Fig.21 as well as Fig. 22 It is shown in the figure and described in detail later.

[0225] Fig. 20C FIG. 4 shows a first conductive layer of a first pixel driving circuit. Fig. 20C As shown, the first conductive layer may include the second electrode CE2 of the storage capacitor 13, the first gate line GLn, the second gate line GLn-1, the light emitting control line EM, and the gates of the first thin film transistor T1, the second thin film transistor T2, the third thin film transistor T3, the fourth thin film transistor T4, the fifth thin film transistor T5, the sixth thin film transistor T6 and the seventh thin film transistor T7.

[0226] like Fig. 20BAs shown, the gates of the second thin film transistor T2, the fourth thin film transistor T4, the fifth thin film transistor T5, the sixth thin film transistor T6 and the seventh thin film transistor T7 are the portions where the first gate line GLn, the second gate line GLn-1 overlap with the semiconductor layer. The third thin film transistor T3 may be a thin film transistor with a dual-gate structure, one gate of the third thin film transistor T3 may be the portion where the first gate line GLn overlaps with the semiconductor layer, and the other gate of the third thin film transistor T3 may be a protrusion protruding from the first gate line GLn; the gate of the first thin film transistor T1 may be the first electrode CE1. The fourth thin film transistor T4 may be a thin film transistor with a dual-gate structure, and the two gates are the portions where the second gate line GLn-1 overlaps with the semiconductor layer.

[0227] For example, the gates of the above-mentioned thin film transistors are respectively formed integrally with the corresponding first gate line GLn or the second gate line GLn-1.

[0228] In the display substrate provided in some embodiments of the present disclosure, one or more other insulating layers are formed on the first conductive layer. For example, the insulating layer includes Fig.21 The second insulating layer 142 is shown in FIG.

[0229] Fig.20D The second conductive layer of the first pixel driving circuit is shown. Fig. 20A and Fig.20D The second conductive layer of the first pixel driving circuit includes the first plate CE1 of the storage capacitor 13, the initialization line RL and the second sub-wire 2422, that is, the second sub-wire 2422 is arranged in the same layer as the first plate CE1 of the storage capacitor 13 and is formed integrally. For example, the second sub-wire 2422 can also be regarded as a part of the extension of the first plate CE1. The second plate CE2 at least partially overlaps with the first plate CE1 to form the storage capacitor 13.

[0230] For example, in some embodiments, the second conductive layer may further include a first light shielding portion 791 and a second light shielding portion 792. The orthographic projection of the first light shielding portion 791 on the base substrate 100 covers the active layer of the second thin film transistor T2, the drain of the third thin film transistor T3, and the active layer between the drain of the fourth thin film transistor T4, thereby preventing external light from affecting the active layer of the second thin film transistor T2, the third thin film transistor T3, and the fourth thin film transistor T4. The orthographic projection of the second light shielding portion 792 on the base substrate 100 covers the active layer between the two gates of the third thin film transistor T3, thereby preventing external light from affecting the active layer of the third thin film transistor T3. The first light shielding portion 791 may be an integral structure with the second light shielding portion 792 of the adjacent pixel circuit, and be electrically connected to the first power line VDD1 through the tenth via hole VH9' penetrating the insulating layer, as shown in FIG. Fig. 20A shown.

[0231] In the display substrate provided in some embodiments of the present disclosure, one or more other insulating layers are formed on the second conductive layer. For example, the insulating layer includes Fig.21 The third insulating layer 143 is shown in FIG.

[0232] Fig.20E The third conductive layer of the pixel circuit is shown. Fig.20E As shown, the third conductive layer of the first pixel driving circuit includes a first signal DATA1 and a first power line VDD1. As shown in combination with Figures 20A-20E, the first signal line DATA1 is connected to the source region of the second thin film transistor T2 in the semiconductor layer through at least one via (e.g., via VH1) in the first insulating layer, the second insulating layer, and the third insulating layer. The first power line VDD1 is connected to the source region of the corresponding fifth thin film transistor T5 in the semiconductor layer through at least one via (e.g., via VH2) in the first insulating layer, the second insulating layer, and the third insulating layer. The first power line VDD1 is connected to the first electrode CE1 in the second conductive layer through at least one via (e.g., via VH3) in the third insulating layer.

[0233] For example, combined with Fig. 20A and Fig.20E , the third conductive layer further includes a first connection portion CP1, a second connection portion CP2, and a third connection portion CP3. One end of the first connection portion CP1 is connected to the drain region of the corresponding third thin film transistor T3 in the semiconductor layer through at least one via hole (e.g., via hole VH4) in the first insulating layer, the second insulating layer, and the third insulating layer, and the other end of the first connection portion CP1 is connected to the gate of the first thin film transistor T1 in the first conductive layer through at least one via hole (e.g., via hole VH5) in the second insulating layer and the third insulating layer. One end of the second connection portion CP2 is connected to the initialization line RL through a via hole (e.g., via hole VH6) in the third insulating layer, and the other end of the second connection portion CP2 is connected to the source region of the seventh thin film transistor T7 and the source region of the fourth thin film transistor T4 in the semiconductor layer through at least one via hole (e.g., via hole VH7) in the first insulating layer, the second insulating layer, and the third insulating layer. The third connection portion CP3 is connected to the drain region of the sixth thin film transistor T6 in the semiconductor layer through at least one via hole (e.g., via hole VH8) in the first gate insulating layer, the second gate insulating layer, and the interlayer insulating layer.

[0234] For example, Fig.21 FIG. 1 is a cross-sectional schematic diagram of a first display area in a display substrate provided in at least one embodiment of the present disclosure. Fig.21 As shown, the display substrate 1 further includes a first planarization layer 144 and a pixel defining layer 145. The first pixel unit includes a first light emitting device 11 and a first pixel driving circuit 12.

[0235] For example, the first planarization layer 144 is located on the side of the first pixel driving circuit 12 away from the base substrate 100 to provide a planarized surface, and the first planarization layer 144 provides a planarized surface and includes a via 144A. The sixth transistor T6 includes an active layer 121, a gate 122, and a source-drain electrode (a source 123 and a drain 124). The storage capacitor 13 includes a first plate CE1 and a second plate CE2. The active layer 121 is disposed on the base substrate 100, the first insulating layer 141 is disposed on the side of the active layer 121 away from the base substrate 100, the gate 122 and the second plate CE2 are disposed in the same layer on the side of the first insulating layer 141 away from the base substrate 100, and the second insulating layer 142 is disposed on the side of the gate 122 and the second plate CE2 away from the base substrate 100. The first plate CE1 is disposed on the side of the second insulating layer 142 away from the base substrate 100, and the third insulating layer 143 is disposed on the side of the first plate CE1 away from the base substrate 100. The source electrode 123 and the drain electrode 124 are disposed on a side of the third insulating layer 143 away from the base substrate 100 , and are electrically connected to the active layer 121 through via holes in the first insulating layer 141 , the second insulating layer 142 , and the third insulating layer 143 .

[0236] For example, the material of the first planarization layer 144 includes inorganic insulating materials such as silicon oxide, silicon nitride, and silicon oxynitride, and may also include organic insulating materials such as polyimide, polyphthalimide, polyphthalamide, acrylic resin, benzocyclobutene, or phenolic resin, which is not limited in the embodiments of the present disclosure.

[0237] For example, the material of the active layer 121 may include polysilicon or an oxide semiconductor (e.g., indium gallium zinc oxide). The material of the gate 122 may include a metal material or an alloy material, such as a metal single layer or multilayer structure formed by molybdenum, aluminum, and titanium, for example, the multilayer structure is a multi-metal layer stack (e.g., a titanium, aluminum, and titanium three-layer metal stack (Ti / Al / Ti)). The material of the source 123 and the drain 124 may include a metal material or an alloy material, such as a metal single layer or multilayer structure formed by molybdenum, aluminum, and titanium, for example, the multilayer structure is a multi-metal layer stack (e.g., a titanium, aluminum, and titanium three-layer metal stack (Ti / Al / Ti)). The embodiments of the present disclosure do not specifically limit the materials of each functional layer.

[0238] For example, Fig.21As shown, the first light emitting device 11 includes a first electrode 111 (for example, an anode), a first light emitting layer 112, and a second electrode 113 (for example, a cathode). The first electrode 111 is located on a side of the first planarization layer 144 away from the substrate 100 and is connected to the source 123 (or drain 124) of the sixth transistor T6 through a via 144A of the first planarization layer 144. The pixel defining layer 145 is located on a side of the first electrode 111 of the first light emitting device 11 away from the substrate 100, and includes a first pixel opening 145A. The first pixel opening 145A corresponds to the first light emitting device 11 to form a light emitting area of ​​the first light emitting device 11. The second electrode 113 is located on a side of the pixel defining layer 145 away from the substrate 100. The light emitting layer 112 is located in the first pixel opening 145A and between the first electrode 111 and the second electrode 112. A portion of the light emitting layer 112 directly sandwiched between the first electrode 111 and the second electrode 112 will emit light when powered on, so that the area occupied by this portion corresponds to the light emitting region.

[0239] For example, the material of the pixel defining layer 145 may include an organic insulating material such as polyimide, polyphthalimide, polyphthalamide, acrylic resin, benzocyclobutene or phenolic resin, or an inorganic insulating material such as silicon oxide or silicon nitride, which is not limited in the embodiments of the present disclosure.

[0240] For example, the material of the first electrode 111 may include at least one transparent conductive oxide material including indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), etc. In addition, the first electrode 111 may include a metal with high reflectivity as a reflective layer, such as silver (Ag).

[0241] For example, for OLED, the first light-emitting layer 112 may include small molecule organic materials or polymer molecule organic materials, and may be fluorescent luminescent materials or phosphorescent luminescent materials, and may emit red light, green light, blue light, or white light; and, as required, the light-emitting layer may further include functional layers such as an electron injection layer, an electron transport layer, a hole injection layer, and a hole transport layer. For QLED, the light-emitting layer may include quantum dot materials, such as silicon quantum dots, germanium quantum dots, cadmium sulfide quantum dots, cadmium selenide quantum dots, cadmium telluride quantum dots, zinc selenide quantum dots, lead sulfide quantum dots, lead selenide quantum dots, indium phosphide quantum dots, and indium arsenide quantum dots, and the particle size of the quantum dots is 2-20 nm.

[0242] For example, the second electrode 113 may include various conductive materials, such as lithium (Li), aluminum (Al), magnesium (Mg), silver (Ag), and the like.

[0243] For example, a passivation layer may be further provided between the first planarization layer and the source electrode 123 and the drain electrode 124. The passivation layer may be provided to include a via hole to expose one of the source electrode 123 and the drain electrode 124, for example, to expose the drain electrode 124. The passivation layer may protect the source electrode 123 and the drain electrode 124 from being corroded by water vapor. For example, the material of the passivation layer may include an organic insulating material or an inorganic insulating material, for example, a silicon nitride material, which has a high dielectric constant and good hydrophobicity, and can well protect the first pixel circuit 12 from being corroded by water vapor.

[0244] For example, a switching electrode may be provided between the first electrode 111 and the first pixel circuit 12, and the switching electrode is connected to the first electrode 111 and the first pixel circuit 12 to electrically connect the first electrode 111 to the first pixel circuit 12. The embodiment of the disclosure is not limited to the specific structure of the first pixel unit.

[0245] For example, Fig.21 As shown, the display substrate 1 further includes an encapsulation layer 146. The encapsulation layer 146 is located on the side of the second electrode 113 away from the base substrate 100. The encapsulation layer 146 seals the first light-emitting device 11, thereby reducing or preventing the degradation of the first light-emitting device 11 caused by moisture and / or oxygen included in the environment. The encapsulation layer 146 can be a single-layer structure or a composite layer structure, and the composite layer structure includes a structure in which an inorganic layer and an organic layer are stacked. The encapsulation layer 146 includes at least one encapsulation sublayer. For example, the encapsulation layer 146 may include a first inorganic encapsulation layer, a first organic encapsulation layer, and a second inorganic encapsulation layer arranged in sequence.

[0246] For example, the material of the encapsulation layer 146 may include insulating materials such as silicon nitride, silicon oxide, silicon oxynitride, and polymer resin. Inorganic materials such as silicon nitride, silicon oxide, and silicon oxynitride have high density and can prevent the intrusion of water, oxygen, etc.; the material of the organic encapsulation layer may be a polymer material containing a desiccant or a polymer material that can block water vapor, such as a polymer resin, etc., to planarize the surface of the display substrate, and to relieve the stress of the first inorganic encapsulation layer and the second inorganic encapsulation layer, and may also include a desiccant and other water-absorbing materials to absorb water, oxygen, and other substances that intrude into the interior.

[0247] For example, Fig. 22 A cross-sectional schematic diagram of a second display area in a display substrate provided in at least one embodiment of the present disclosure. Each of the plurality of second pixel units C in the second display area 20 of the display substrate 1 includes a second light emitting device 21 and a second pixel driving circuit 22, and the second pixel driving circuit 22 is electrically connected to the second light emitting device 21 to drive the second light emitting device 21.

[0248] For example, the second pixel driving circuit 22 includes a sixth transistor T6' and a storage capacitor 23 and other structures. The second light-emitting device 21 includes a third electrode 211, a fourth electrode 213, and a second light-emitting layer 212 between the third electrode 211 and the fourth electrode 213. The first planarization layer 144 is located on the side of the second pixel driving circuit 22 away from the substrate 100 to provide a planarized surface, and the first planarization layer 144 provides a planarized surface and includes a via 144A. The third electrode 211 is electrically connected to the second pixel driving circuit 22 through the via 144A. For example, the third electrode 211 is an anode of the second light-emitting device 21, and the fourth electrode 213 is a cathode of the second light-emitting device 21. The pixel defining layer 145 is disposed on the side of the third electrode 211 away from the substrate 100, and includes a plurality of openings. The second light layer 212 is disposed in the plurality of openings of the pixel defining layer 145. The fourth electrode 213 is disposed on the side of the second light-emitting layer 212 and the pixel defining layer 145 away from the substrate 100. The third electrode 211 is disposed in the same layer and made of the same material as the first electrode 111, and the fourth electrode 213 is disposed in the same layer and made of the same material as the second electrode 113. The second light emitting layer 212 is disposed in the same layer and made of the same material as the first light emitting layer 112.

[0249] For example, the sixth transistor T6 ′ includes an active layer 221 , a gate 222 , source-drain electrodes (ie, a source 223 and a drain 224 ) and other structures, and the storage capacitor 23 includes a first electrode plate CE21 and a second electrode plate CE22 . The active layer 321 is arranged on the base substrate 100, the first insulating layer 141 is arranged on the side of the active layer 221 away from the base substrate 100, the gate 222 and the second electrode CE22 are arranged in the same layer on the side of the first insulating layer 141 away from the base substrate 100, the second insulating layer 142 is arranged on the side of the gate 222 and the first capacitor electrode 231 away from the base substrate 14, the first electrode CE21 is arranged on the side of the second insulating layer 142 away from the base substrate 100, the third insulating layer 143 is arranged on the side of the first electrode CE21 away from the base substrate 100, the source and drain electrodes are arranged on the side of the third insulating layer 143 away from the base substrate 14, and are electrically connected to the active layer 221 through vias in the first insulating layer 141, the second insulating layer 142 and the third insulating layer 143, and the first planarization layer 144 is arranged on the side of the source and drain electrodes away from the base substrate 100 to provide a first planarization surface to planarize the third pixel circuit.

[0250] For example, the active layer 221, the gate 222, and the source-drain electrode (i.e., the source 223 and the drain 224) of the sixth transistor T6' are respectively arranged in the same layer and made of the same material as the source layer 121, the gate 122, and the source-drain electrode (the source 123 and the drain 124) of the sixth transistor T6. The first plate CE21 and the second plate CE22 of the storage capacitor 23 are respectively arranged in the same layer and made of the same material as the first plate CE1 and the second plate CE2 of the storage capacitor 13.

[0251] It should be noted that the second pixel driving circuit 22 in the second display area 20 has the same structure as the first pixel driving circuit 12 in the first display area 10, and therefore can be formed by the same patterning process in the preparation process. For example, the first insulating layer 141, the second insulating layer 142, the third insulating layer 143, the first planarization layer 144, the pixel defining layer 145, and the encapsulation layer 146 are arranged in the same layer in the second display area 20 and the first display area 10, and in some embodiments, they are integrated, such as the same insulating layer, and therefore the same reference numerals are used in the drawings.

[0252] For example, the base substrate 100 in at least one embodiment of the present disclosure may be a glass plate, a quartz plate, a metal plate or a resin plate, etc. For example, the material of the base substrate may include an organic material, such as a resin material such as polyimide, polycarbonate, polyacrylate, polyetherimide, polyethersulfone, polyethylene terephthalate and polyethylene naphthalate; for example, the base substrate 100 may be a flexible substrate or a non-flexible substrate, which is not limited in the embodiments of the present disclosure.

[0253] Fig.23 A schematic diagram of a display device provided by at least one embodiment of the present disclosure. At least one embodiment of the present disclosure provides a display device 2, and the display device 20 may include a display substrate 1 of any of the above embodiments.

[0254] For example, Fig.23 As shown, the display device 2 may further include a flexible circuit board and a control chip. For example, the flexible circuit board is bonded to the bonding area of ​​the display substrate 1, and the control chip is mounted on the flexible circuit board, thereby being electrically connected to the display area; or the control chip is directly bonded to the bonding area, thereby being electrically connected to the display area.

[0255] For example, the control chip may be a central processing unit, a digital signal processor, a system-on-chip (SoC), etc. For example, the control chip may also include a memory, a power module, etc., and realize power supply and signal input and output functions through additionally provided wires, signal lines, etc. For example, the control chip may also include hardware circuits and computer executable codes, etc. The hardware circuit may include conventional very large scale integration (VLSI) circuits or gate arrays and existing semiconductors or other discrete components such as logic chips and transistors; the hardware circuit may also include field programmable gate arrays, programmable array logic, programmable logic devices, etc.

[0256] For example, the display device 2 provided in at least one embodiment of the present disclosure may be any product or component with a display function, such as an OLED panel, an OLED TV, a QLED panel, a QLED TV, a mobile phone, a tablet computer, a laptop computer, a digital photo frame, a navigator, etc. The display device 2 may also include other components, such as a data drive circuit, a timing controller, etc., which are not limited in the embodiments of the present disclosure.

[0257] For example, Fig.23 as well as Figure 1D As shown, the display device 2 further includes a sensor 192. The sensor 192 is disposed on the second side S2 (e.g., the non-display side) of the display substrate 1. The sensor 192 is configured to receive light (e.g., collimated light or collimated light) from the first side S1 (e.g., the display side of the display substrate) of the display substrate 1. The orthographic projection of the sensor 192 on the base substrate 100 at least partially overlaps with the first display area 10.

[0258] For example, the sensor 192 is an image sensor, an infrared sensor, a distance sensor, etc. The sensor 192 can be implemented in the form of a chip, etc. The sensor 192 is disposed on the non-display side S2 (the side away from the user) of the display substrate.

[0259] For example, the sensor 192 and the first display area 10 at least partially overlap in the normal direction of the display surface of the display substrate.

[0260] For example, the sensor 192 may be an image sensor, and may be used to collect an image of the external environment facing the light-collecting surface of the sensor 192, such as a CMOS image sensor or a CCD image sensor; the sensor 192 may also be an infrared sensor, a distance sensor, etc. The sensor 192 may be used to implement a camera of a mobile terminal such as a mobile phone or a notebook, and may further include optical devices such as a lens, a reflector, or an optical waveguide to modulate the optical path as required. The embodiments of the present disclosure do not limit the type, function, and configuration of the sensor 192.

[0261] The sensor 192 is arranged on the non-display side S2 of the display panel by means of double-sided adhesive or the like, and the orthographic projection of the sensor 192 on the base substrate 100 at least partially overlaps with the first display area 10, and is configured to receive light from the first side S1. Thus, the first display area 10 facilitates the arrangement of the sensor 192 while realizing display.

[0262] It should be noted that, for the sake of clarity and simplicity, the embodiments of the present disclosure do not provide all the components of the display device. To realize the substrate function of the display device, those skilled in the art may provide and set other structures not shown according to specific needs, and the embodiments of the present disclosure are not limited to this.

[0263] Regarding the technical effects of the display device provided in the above embodiments, reference may be made to the technical effects of the display substrate provided in the embodiments of the present disclosure, which will not be described in detail here.

[0264] There are a few points to note:

[0265] (1) The drawings of the embodiments of the present disclosure only relate to the structures related to the embodiments of the present disclosure, and other structures may refer to the general design.

[0266] (2) In the absence of conflict, the embodiments of the present disclosure and the features therein may be combined with each other to obtain new embodiments.

[0267] The above are only specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A display substrate having a first side for display and a second side opposite to the first side, comprising: Substrate substrate, A display area is provided on the base substrate, comprising a first display area, wherein the first display area allows light from a first side of the display substrate to be at least partially transmitted to a second side of the display substrate, The first display area includes a first sub-pixel array, and the first sub-pixel array includes a plurality of first pixel unit groups, a plurality of first signal lines, and a plurality of first power lines arranged in a first direction and a second direction intersecting the first direction. The first pixel unit group includes at least one first pixel unit, Each of the plurality of first signal lines at least partially extends along the first direction and is configured to provide a first display signal to the plurality of first pixel units, and the plurality of first signal lines are connected to the first pixel units of the plurality of first pixel unit groups, The plurality of first power lines at least partially extend along the first direction and are configured to provide a first power supply voltage to the plurality of first pixel units, and the plurality of first power lines are connected to the first pixel units of the plurality of first pixel unit groups; At least one connecting wire, wherein each of the at least one connecting wire at least partially extends along the first direction and is connected to first power lines respectively connected to adjacent first pixel unit groups in the first direction; and At least one switching electrode, wherein each of the at least one switching electrode at least partially extends along the first direction and is connected to first signal lines respectively connected to adjacent first pixel unit groups in the first direction; The film layer where at least part of the at least one switching electrode is located is different from the film layer where each of the at least one connecting wire is located, and The orthographic projection of the at least one switching electrode on the base substrate at least partially overlaps with the orthographic projection of the at least one connecting trace on the base substrate, The at least one connecting wire includes a first connecting wire, the at least one first pixel unit of the first pixel unit group includes a plurality of first pixel units, the at least one switching electrode includes a plurality of switching electrodes, the plurality of first pixel units of the first pixel unit group are arranged in at least two columns parallel to each other along the second direction, the plurality of switching electrodes include a first switching electrode and a second switching electrode, the first switching electrode and the second switching electrode are arranged in parallel, The first switching electrode and the second switching electrode are connected to first signal lines respectively connected to first pixel units adjacent to each other in the first direction and belonging to different first pixel unit groups. The first transfer electrode and the second transfer electrode are located in different film layers, and the orthographic projections of the first transfer electrode and the second transfer electrode on the base substrate at least partially overlap with the orthographic projection of the first connection trace on the base substrate.

2. The display substrate according to claim 1, wherein: The first connecting wire extends along the first direction, and the first connecting wire is connected to first power lines respectively connected to first pixel units adjacent to each other in the first direction and belonging to different first pixel unit groups. The first connection line is arranged in the same layer as the first power line and is formed integrally.

3. The display substrate according to claim 2, wherein: The plurality of switching electrodes are connected one-to-one to a plurality of first pixel units that are adjacent in the first direction and belong to different first pixel unit groups, The plurality of switching electrodes are located in different film layers.

4. The display substrate according to claim 1, wherein: The orthographic projections of a portion of the first switching electrode extending along the first direction and a portion of the second switching electrode extending along the first direction on the base substrate overlap with the orthographic projections of a portion of the first connecting trace extending along the first direction on the base substrate.

5. The display substrate according to claim 1, wherein: There is a gap allowing light transmission between the first pixel unit group adjacent to the first direction and the second direction, A portion of the first connection line and a portion of each of the at least one switching electrode extend along the second direction and bypass the gap allowing light transmission.

6. The display substrate according to claim 5, wherein: The first connecting line is a meandering line and includes a first portion, a second portion and a third portion. The first end of the first part and the first end of the second part are respectively connected to two ends of the third part and extend along a second direction different from the first direction. The third portion extends along the first direction, The second end of the first portion and the second end of the second portion are respectively connected to first power lines to which adjacent first pixel units in the first direction are respectively connected.

7. The display substrate according to claim 6, wherein: The orthographic projections of the first switching electrode and the second switching electrode on the base substrate overlap with the orthographic projections of at least one of the first portion, the second portion, and the third portion of the first connecting trace on the base substrate.

8. The display substrate according to claim 3, wherein: The plurality of first pixel units of the first pixel unit group include at least three columns arranged in parallel along the second direction, The at least one switching electrode includes a first switching electrode, a second switching electrode and a third switching electrode, the first switching electrode, the second switching electrode and the third switching electrode are arranged in parallel, and the third switching electrode is located between the first switching electrode and the second switching electrode. The first switching electrode, the second switching electrode and the third switching electrode are respectively connected to first signal lines respectively connected to first pixel units adjacent to each other in the first direction. The first switching electrode, the second switching electrode and the third switching electrode are located in different film layers. The orthographic projection of the first connecting trace on the substrate at least partially overlaps with the orthographic projection of at least one of the first switching electrode and the second switching electrode on the substrate, The third transfer electrode and the first connecting line are arranged in the same layer.

9. The display substrate according to claim 8, wherein: An orthographic projection of the third switching electrode on the base substrate at least partially overlaps with an orthographic projection of the first switching electrode or the second switching electrode on the base substrate.

10. The display substrate according to claim 8, further comprising: a first insulating layer, a second insulating layer and a third insulating layer, The first insulating layer is located on the base substrate, the second insulating layer is located on a side of the first insulating layer away from the base substrate, and the third insulating layer is located on a side of the second insulating layer away from the base substrate. The plurality of first signal lines, the plurality of first power lines and the first connecting line are located on a side of the third insulating layer away from the base substrate. The second transfer electrode is located on a side of the first insulating layer away from the base substrate, and is connected to the first signal line connected to the first pixel units adjacent to each other in the first direction through a via hole penetrating the second insulating layer and the third insulating layer. The first transfer electrode is located on a side of the second insulating layer away from the base substrate, and is connected to the first signal line connected to the first pixel units adjacent to each other in the first direction through a via hole penetrating the third insulating layer. The third transfer electrode is located at a side of the third insulating layer away from the base substrate.

11. The display substrate according to claim 10, wherein: The plurality of first pixel units of the first pixel unit group are arranged in at least one row along the second direction, and in the same row, the first pixel unit group includes at least two first pixel units. Each first pixel unit of the first pixel unit group includes a first pixel driving circuit and a first light emitting device, wherein the first pixel driving circuit is connected to the first light emitting device and drives the first light emitting device to emit light. The first pixel driving circuit includes a storage capacitor, and the storage capacitor includes a first electrode plate and a second electrode plate at least partially overlapping the first electrode plate. The first electrode plate is located on a side of the second insulating layer away from the substrate, and the second electrode plate is located on a side of the first insulating layer away from the substrate. The plurality of first power lines connected to each of the first pixel units are connected to the first electrode plate through via holes penetrating the third insulating layer. The first electrodes of at least two first pixel units in the first pixel unit group located in the same row are connected to each other and formed as one.

12. The display substrate according to claim 11, further comprising a fourth transfer electrode, in, The fourth switching electrode at least partially extends along the second direction, and the fourth switching electrode is connected to first power lines respectively connected to first pixel units that are offset and adjacently arranged in the second direction and belong to different first pixel unit groups.

13. The display substrate according to claim 11, further comprising a fourth transfer electrode, wherein: The fourth switching electrode extends along the second direction, and the fourth switching electrode is connected to first power lines respectively connected to two first pixel units that are adjacently arranged in the second direction and belong to different first pixel unit groups.

14. The display substrate according to claim 12 or 13, wherein: Two ends of the fourth switching electrode are respectively connected to the first electrode plates of the two first pixel units that are adjacently arranged and belong to different first pixel unit groups, so as to connect the first power lines located in the different first pixel unit groups.

15. The display substrate according to claim 14, wherein: The fourth switching electrode is located on a side of the third insulating layer away from the base substrate, and is connected to the first electrodes of the two adjacent first pixel units belonging to different first pixel unit groups through a via hole penetrating the third insulating layer.

16. The display substrate according to claim 14, wherein: The fourth switching electrode is located on a side of the second insulating layer away from the base substrate, and the fourth switching electrode is arranged in the same layer as the first electrodes of the two adjacent first pixel units belonging to different first pixel unit groups and formed integrally.

17. The display substrate according to claim 14, wherein: The fourth switching electrode includes a first sub-switching electrode, a second sub-switching electrode and a third sub-switching electrode. The first end of the first switching sub-electrode and the first end of the second switching sub-electrode are respectively connected to two ends of the third switching sub-electrode. The second end of the first sub-switching electrode and the second end of the second sub-switching electrode are respectively connected to the first electrode plates of the two first pixel units that are adjacently arranged and belong to different first pixel unit groups. The first sub-switching electrode and the second sub-switching electrode are arranged in the same layer and integrally formed with the first electrode plates of the two first pixel units that are adjacently arranged and belong to different first pixel unit groups, The third sub-switching electrode is located on a side of the third insulating layer away from the base substrate, and the third sub-switching electrode is connected to the first sub-switching electrode and the second sub-switching electrode through a via hole penetrating the third insulating layer.

18. The display substrate according to claim 3, wherein: The plurality of first pixel units of the first pixel unit group are arranged in a plurality of rows and columns, In the same first pixel unit group, the first signal lines connected to the first pixel units in the same column are interconnected and formed as one body, and the first power lines connected to the first pixel units in the same column are also interconnected and formed as one body.

19. The display substrate according to claim 1, wherein: The display area further includes a second display area, the second display area at least partially surrounding the first display area, The second display area includes a second sub-pixel array, and the second sub-pixel array includes a plurality of second pixel units. Each of the plurality of second pixel units comprises a second light emitting device and a second pixel driving circuit, wherein the second pixel driving circuit is configured to drive the second light emitting device to emit light. A first signal line connected to a first pixel unit close to the second display area extends to the second display area to be connected to a second pixel unit located in the first direction relative to the first pixel unit, A first power line connected to a first pixel unit close to the second display area extends to the second display area to be connected to a second pixel unit located in the first direction relative to the first pixel unit.

20. The display substrate according to claim 19, wherein: The pixel density of the second display area is greater than the pixel density of the first display area.

21. The display substrate according to claim 19, further comprising a plurality of second signal lines and a plurality of second power lines located in the second display area, in, The plurality of second pixel units are arranged in a plurality of rows parallel to each other in the second direction, The plurality of second signal lines extend along the first direction, and each of the plurality of second signal lines passes through the plurality of second pixel units arranged in a column in the first direction to provide a second display signal to the plurality of second pixel units. The plurality of second power lines extend along the first direction, and each of the plurality of second power lines passes through the plurality of second pixel units arranged in a column in the first direction to provide a second power voltage to the plurality of second pixel units.

22. A display device, comprising the display substrate according to any one of claims 1-20.

23. The display device according to claim 22, further comprising a sensor, in, The sensor is disposed on the second side of the display substrate, and the sensor is configured to receive light from the first side of the display substrate.

24. The display device according to claim 23, wherein: The orthographic projection of the sensor on the base substrate at least partially overlaps with the first display area.

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