Display device

Abstract

A display device includes a substrate including a first region and a second region surrounded by the first region; a first gate drive circuit unit and a second gate drive circuit unit arranged adjacent to and spaced apart from each other in the first region; a 1-1 pixel circuit unit arranged between the first gate drive circuit unit and the second gate drive circuit unit; and a 1-1 display element arranged in the first region and electrically connected to the 1-1 pixel circuit unit.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2020-0074954, filed on June 19, 2020, and all benefits derived from that application, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0002] One or more embodiments relate to a display device. Background Technology

[0003] Display devices visually display data. They can be used as display units in small products such as mobile phones or as display units in large products such as televisions.

[0004] Such a display device includes a substrate divided into display and non-display areas, with gate lines and data lines formed insulated from each other in the display area. The gate lines and data lines intersect each other to define multiple pixel areas in the display area, and these pixel areas receive electrical signals and emit light to display an image externally. Thin-film transistors and pixel electrodes electrically connected to the thin-film transistors are provided corresponding to each pixel area, and counter electrodes are provided together in the pixel area. Various lines for transmitting electrical signals to the display area, gate drivers, data drivers, and controllers, etc., can be provided in the non-display area.

[0005] The use of display devices has diversified. Furthermore, as display devices have become thinner and lighter, their applications are expanding. With the increasing number of users, research is actively being conducted to improve visual satisfaction, for example, by increasing the display area of ​​display devices. Various studies have been explored to expand the display area of ​​display devices. Summary of the Invention

[0006] One or more embodiments include a display device in which the non-display area is reduced. However, the above description is merely illustrative, and the scope of this disclosure is not limited thereto.

[0007] Additional aspects will be set forth in part in the description which follows, and will be apparent in part from the description, or may be learned by practice of the embodiments presented in this disclosure.

[0008] According to one or more embodiments, a display device includes: a substrate including a first region and a second region surrounded by the first region; a first gate driving circuit unit and a second gate driving circuit unit arranged adjacent to and spaced apart from each other in the first region; a first-1 pixel circuit unit arranged between the first gate driving circuit unit and the second gate driving circuit unit; and a first-1 display element arranged in the first region and electrically connected to the first-1 pixel circuit unit.

[0009] The first-1 display element may at least partially overlap with the first gate drive circuit unit in the plan view.

[0010] The display device may further include: a second pixel circuit unit disposed in the second region and a second display element disposed in the second region and electrically connected to the second pixel circuit unit.

[0011] The display device may further include: a data line disposed on a substrate and extending in a first direction, wherein the sum of the length of the first gate driving circuit unit in the first direction and the length of the first-1 pixel circuit unit in the first direction may be less than or equal to the length of the second pixel circuit unit in the first direction.

[0012] The display device may further include: a first gate line connected to the first gate driving circuit unit and extending in a first region, and a second gate line connected to the first gate driving circuit unit and extending in a second region.

[0013] The display device may further include: a first-2 display element disposed in the first region and electrically connected to the first-1 pixel circuit unit.

[0014] The first-1 display element may at least partially overlap with the first gate drive circuit unit in the plan view, and the first-2 display element may at least partially overlap with the second gate drive circuit unit in the plan view.

[0015] The first-1 display element may at least partially overlap with the first gate drive circuit unit in the plan view, and the first-2 display element may at least partially overlap with the first-1 pixel circuit unit in the plan view.

[0016] Display element 1-1 and display element 1-2 can each emit light of the same wavelength.

[0017] The display device may further include: a first-2 pixel circuit unit disposed between the first-1 pixel circuit unit and the second gate driving circuit unit, and a first-3 display element electrically connected to the first-2 pixel circuit unit, wherein the first-1 display element may at least partially overlap with the first gate driving circuit unit in a plan view, and the first-3 display element may at least partially overlap with the second gate driving circuit unit in a plan view.

[0018] The display device may further include: a voltage line disposed between the first-1 pixel circuit unit and the first-2 pixel circuit unit, wherein the voltage line may be connected to each of the first-1 pixel circuit unit and the first-2 pixel circuit unit.

[0019] The first-1 display element may include a first-1 pixel electrode, a first-1 intermediate layer, and a counter electrode. The display device may further include a pixel defining layer between the first-1 pixel electrode and the counter electrode, and the pixel defining layer may define a first-1 opening, the first-1 opening defining a first-1 emission region of the first-1 display element by exposing a portion of the first-1 pixel electrode, and a first gate driving circuit unit may at least partially overlap with the first-1 emission region in a plan view.

[0020] The display device may further include: a first-2 display element disposed in the first region and electrically connected to the first-1 pixel circuit unit, wherein the pixel defining layer may define a first-2 opening, the first-2 opening defining a first-2 emission region of the first-2 display element by exposing a portion of the first-1 pixel electrode, and the first-2 emission region may at least partially overlap with one of the first-1 pixel circuit unit or the second gate driving circuit unit in a plan view.

[0021] The display device may further include: a second pixel circuit unit disposed on a substrate to correspond to a second region, and a second display element electrically connected to the second pixel circuit unit, wherein the second display element may include a second pixel electrode, a second intermediate layer, and a counter electrode in the second region. The pixel defining layer may further define a second opening that defines a second emission region of the second display element by exposing a portion of the second pixel electrode, and the size of the first-first opening may be smaller than the size of the second opening.

[0022] One or more embodiments include a display device comprising: a substrate including a first region and a second region surrounded by the first region; a first gate driving circuit unit disposed in the first region; a first-1 pixel circuit unit disposed in the first region and located in a second direction closer to the outside of the substrate than the first gate driving circuit unit; and a first-1 display element disposed in the first region and electrically connected to the first-1 pixel circuit unit.

[0023] The first-1 display element may at least partially overlap with the first gate drive circuit unit in the plan view.

[0024] The display device may further include: a second gate driving circuit unit disposed in the first region; a first-2 pixel circuit unit disposed in the first region and closer to the second region than the second gate driving circuit unit; and a first-2 display element disposed in the first region and electrically connected to the first-2 pixel circuit unit.

[0025] The first-1 display element may at least partially overlap with the first gate drive circuit unit in the plan view, and the first-2 display element may at least partially overlap with the second gate drive circuit unit in the plan view.

[0026] The display device may further include: a first gate line connected to the first gate driving circuit unit and extending toward the outside of the substrate in a second direction; and a second gate line connected to the first gate driving circuit unit and extending toward the second region in a second direction.

[0027] The sum of the length of the first gate driving circuit unit in the second direction and the length of the first-1 pixel circuit unit in the second direction can be equal to the sum of the length of the second gate driving circuit unit in the second direction and the length of the first-2 pixel circuit unit in the second direction.

[0028] These and / or other aspects, features, and advantages will become apparent and more readily understood from the following detailed description, claims, and drawings used to carry out the embodiments described below. Attached Figure Description

[0029] The above and other aspects, features, and advantages of specific embodiments of this disclosure will become more apparent from the following description taken in conjunction with the accompanying drawings, in which:

[0030] Figure 1 This is a schematic plan view of a display device according to an embodiment;

[0031] Figure 2 This is a schematic plan view of a display panel according to an embodiment;

[0032] Figure 3 This is an equivalent circuit diagram of pixels arranged on a display panel according to an embodiment;

[0033] Figure 4 This is an equivalent circuit diagram of pixels arranged on a display panel according to an embodiment;

[0034] Figure 5 It is a schematic diagram. Figure 2 An enlarged plan view of part A;

[0035] Figure 6 It is along Figure 5 The lines I-I' and II-II' in the middle are intercepted Figure 5 An exemplary cross-sectional view of the display panel;

[0036] Figure 7 It is along Figure 5 The lines I-I' and II-II' in the middle are intercepted Figure 5 Another exemplary cross-sectional view of the display panel;

[0037] Figure 8 It is a schematic diagram. Figure 5 Another exemplary enlarged plan view of part B;

[0038] Figure 9 It is along Figure 8 The line III-III' in the middle is intercepted Figure 8 An exemplary cross-sectional view of the display panel.

[0039] Figure 10 It is a schematic diagram. Figure 2 Another exemplary enlarged plan view of part A;

[0040] Figure 11 It is along Figure 10 The line IV-IV' in the middle is intercepted Figure 10 An exemplary cross-sectional view of the display panel;

[0041] Figure 12 It is a schematic diagram. Figure 5 Another exemplary enlarged plan view of part B;

[0042] Figure 13 It is along Figure 12 The line V-V' intercepted in the middle Figure 12 An exemplary cross-sectional view of the display panel;

[0043] Figure 14 It is a schematic diagram. Figure 5 Another enlarged plan view of part B; and

[0044] Figure 15 It is a schematic diagram. Figure 5 Another enlarged plan view of part B. Detailed Implementation

[0045] Reference will now be made in detail to embodiments exemplified in the accompanying drawings, in which the same reference numerals consistently refer to the same elements. In this regard, the embodiments may take different forms and should not be construed as limited to the description set forth herein. Therefore, the embodiments described below with reference to the accompanying drawings are merely for explaining aspects of this description. As used herein, the term “and / or” includes any and all combinations of one or more of the listed items. Throughout this disclosure, the expression “at least one of a, b, and c” indicates only a, only b, only c, both a and b, both a and c, both b and c, all or variations thereof of a, b, and c.

[0046] Because various modifications and numerous embodiments are permitted, exemplary embodiments will be illustrated in the accompanying drawings and described in detail in the written description. The effects and features of this disclosure, as well as methods of implementing them, will be apparent from the embodiments and drawings described below in detail. However, this disclosure may be embodied in many different forms and should not be construed as limited to the exemplary embodiments set forth herein.

[0047] In the following, embodiments of the present disclosure will now be described more fully with reference to the accompanying drawings. In the drawings, the same reference numerals refer to the same elements, and therefore their descriptions will be omitted.

[0048] It will be understood that although the terms “first,” “second,” etc., may be used in this document to describe various components, these components should not be limited by these terms. These terms are only used to distinguish one component from another.

[0049] As used herein, the singular forms “a” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0050] It will be further understood that the terms “comprising” and / or “including” as used herein specify the presence of the stated features or components, but do not exclude the presence or addition of one or more other features or components.

[0051] It will be understood that when a layer, area, or component is referred to as being "formed on" another layer, area, or component, that layer, area, or component may be formed directly or indirectly on the other layer, area, or component. That is, for example, intermediate layers, areas, or components may exist.

[0052] For ease of illustration, the dimensions of the components in the accompanying drawings may be exaggerated. In other words, since the dimensions and thicknesses of the components in the accompanying drawings are arbitrarily illustrated for ease of illustration, the following embodiments are not limited thereto.

[0053] When certain embodiments can be implemented differently, a particular process sequence can be performed in a different order than that described. For example, two consecutively described processes can be performed substantially simultaneously, or in the reverse order of their description.

[0054] In this embodiment, expressions such as "A and / or B" indicate A, B, or A and B. Additionally, expressions such as "at least one of A and B" indicate A, B, or A and B.

[0055] It will be understood that when a layer, area, or component is referred to as being connected to another layer, area, or component, that layer, area, or component can be directly or indirectly connected to the other layer, area, or component. That is, for example, intermediate layers, areas, or components may exist. It will also be understood that when a layer, area, or component is referred to as being electrically connected to another layer, area, or component, that layer, area, or component can be directly or indirectly electrically connected to the other layer, area, or component. That is, for example, intermediate layers, areas, or components may exist.

[0056] The x-axis, y-axis, and z-axis are not limited to the three axes of a Cartesian coordinate system and can be interpreted in a broader sense. For example, the x-axis, y-axis, and z-axis can be perpendicular to each other, or they can represent different directions that are not perpendicular to each other.

[0057] Figure 1 This is a schematic plan view of the display device 1 according to an embodiment.

[0058] refer to Figure 1 The display device 1 includes a first region AR1 and a second region AR2. The second region AR2 can be surrounded by the first region AR1. The display device 1 can provide an image to the outside by using light emitted from the first region AR1 and the second region AR2. Since the display device 1 includes a substrate 100, it can be said that the substrate 100 has such a first region AR1 and a second region AR2.

[0059] The substrate 100 may comprise or be made of various materials such as glass, metal, or plastic. According to an embodiment, the substrate 100 may comprise a flexible material. Here, a flexible material refers to a material that is sufficiently twistable, bendable, and foldable or rollable. The flexible material substrate 100 may comprise or be made of ultrathin glass, metal, or plastic.

[0060] Pixels PX having various display elements such as organic light-emitting diodes (“OLEDs”) can be arranged in a first region AR1 and a second region AR2 of the substrate 100. There can be multiple pixels PX, and multiple pixels PX can be arranged in various forms such as strip arrangement, five-grid arrangement and mosaic arrangement to realize an image.

[0061] Various lines, printed circuit boards, or pads with attached driver IC chips used to transmit electrical signals to be applied to the second region AR2 can be provided in the first region AR1 of the substrate 100.

[0062] When the second region AR2 of the substrate 100 is viewed in a planar shape (i.e., in a planar view), the second region AR2 may have the following characteristics: Figure 1 The rectangular shape shown is illustrated. In another embodiment, the second region AR2 may have a polygonal shape, circular shape, elliptical shape, or irregular shape, such as a triangular shape, a pentagonal shape, or a hexagonal shape.

[0063] As a comparative example, pixels may not be arranged in the outer area of ​​the display device where printed circuit boards or pads are disposed. In this case, the area surrounded only by the outer area of ​​the display device (i.e., the first area AR1) corresponds to the area used to display the image (i.e., the second area AR2).

[0064] However, according to embodiments of this disclosure, when multiple pixels PX are arranged in a first region AR1 where a printed circuit board or a driver IC chip is attached, the area for displaying the image can extend from a second region AR2 to the first region AR1 where the multiple pixels PX are arranged. The non-display area can be reduced by arranging the first region AR1 where the multiple pixels PX are arranged.

[0065] Figure 2 This is a schematic plan view of the display panel 10 according to an embodiment.

[0066] refer to Figure 2 The display panel 10 includes a first region AR1 and a second region AR2 surrounded by the first region AR1, and may include a plurality of first pixels PX1 in the first region AR1 and a plurality of second pixels PX2 in the second region AR2. Figure 2 The dashed line in the diagram represents the boundary between the first region AR1 and the second region AR2. The display panel 10 may include multiple data lines DL and multiple gate lines GL. The multiple data lines DL extend in a first direction (e.g., the y-direction) and are respectively connected to pixels PX arranged in the same column among the multiple pixels PX. The multiple gate lines GL extend in a second direction (e.g., the x-direction) that intersects the first direction and are respectively connected to pixels PX arranged in the same row among the multiple pixels PX.

[0067] A plurality of pixels PX, including a plurality of first pixels PX1 and a plurality of second pixels PX2, may each include a display element such as an organic light-emitting diode (OLED). Each of the pixels PX may emit light, for example, red, green, blue, or white, via an organic light-emitting diode (OLED). In the following description, each of the pixels PX means a sub-pixel that emits light of a different color, such as a red (R) sub-pixel, a green (G) sub-pixel, and a blue (B) sub-pixel. The first region AR1 and the second region AR2 may be covered with a sealing member (not shown) and protected from ambient air or moisture.

[0068] Pixels PX can be electrically connected to driving circuits arranged in the first region AR1. The first driving unit DU1, the second driving unit DU2, and the pad unit PU can be arranged in the first region AR1. Although in Figure 2 The power cord is not shown, but it can also be arranged in the first area AR1.

[0069] The first driving unit DU1 may include a plurality of gate driving circuit units GDC. The gate driving circuit units GDC may be arranged spaced apart from each other. A plurality of first pixels PX1 may be arranged in the region between the plurality of spaced-apart gate driving circuit units GDC. The plurality of gate driving circuit units GDC may be respectively connected to a plurality of gate lines GL extending in a second direction (e.g., the x-direction), and transmit electrical signals sequentially to the pixels PX arranged in the same row through the plurality of gate lines GL.

[0070] exist Figure 2 In a multi-gate line GL, each line is a single line. However, each line in a multi-gate line GL can consist of multiple lines. Each line in a multi-gate line GL can include emission control lines and scan lines, etc. Through the multi-gate line GL, emission control signals and scan signals can be sequentially transmitted to pixels PX placed in the same row.

[0071] Each of the multiple gate lines GL may include a first gate line GL1 and a second gate line GL2, wherein the first gate line GL1 extends to a first region AR1 and the second gate line GL2 extends to a second region AR2.

[0072] The first gate line GL1 and the second gate line GL2 can be connected to the gate drive circuit unit GDC. The first gate line GL1 and the second gate line GL2 can be integrally formed. The first gate line GL1 can be connected to a plurality of first pixels PX1 arranged in the same row. The second gate line GL2 can be connected to a plurality of second pixels PX2 arranged in the same row. In a planar view, the first gate line GL1 can at least partially overlap with a first region AR1, and the second gate line GL2 can at least partially overlap with a second region AR2.

[0073] The second driving unit DU2 may be parallel to the first driving unit DU1, and the second region AR2 may be located between the second driving unit DU2 and the first driving unit DU1. As in the first driving unit DU1, the second driving unit DU2 may include multiple gate driving circuit units GDC. The multiple gate driving circuit units GDC may be respectively connected to multiple gate lines GL extending in the second direction, and electrical signals are sequentially transmitted to pixels PX arranged in the same row through the multiple gate lines GL.

[0074] exist Figure 2In this configuration, one end of each of the multiple gate lines GL is connected to the gate drive circuit unit GDC of the first drive unit DU1 and the gate drive circuit unit GDC of the second drive unit DU2, respectively. However, each of the multiple gate lines GL can be connected to one of the gate drive circuit units GDC of the first drive unit DU1 and the second drive unit DU2. For example, the odd-numbered gate lines GL can be connected to the gate drive circuit unit GDC of the first drive unit DU1, and the even-numbered gate lines GL can be connected to the gate drive circuit unit GDC of the second drive unit DU2. As another example, the second drive unit DU2 can be omitted.

[0075] The pad unit PU can be disposed on one end of the substrate 100. The pad unit PU can be exposed without being covered by an insulating layer and can be electrically connected to the printed circuit board PCB. The terminal unit PCB-P of the printed circuit board PCB can be electrically connected to the pad unit PU of the display panel 10. The pad unit PU may include a first clock pad CLP1, a second clock pad CLP2, a first scan pad SP1, a second scan pad SP2, and multiple data pads DP. Figure 2 In this configuration, each of the first clock pad CLP1, the second clock pad CLP2, the first scan pad SP1, and the second scan pad SP2 is a single pad. However, each of the first clock pad CLP1, the second clock pad CLP2, the first scan pad SP1, and the second scan pad SP2 can be multiple pads.

[0076] The first clock pad CLP1 is connected to multiple gate drive circuit units GDC included in the first drive unit DU1, and transmits a first clock signal to the multiple gate drive circuit units GDC. The multiple gate drive circuit units GDC sequentially transmit the first gate signal to multiple gate lines GL based on the first clock signal received from the first clock pad CLP1. Although in Figure 2 Not shown, but each of the plurality of gate drive circuit units (GDCs) is connected to a previous gate line and receives a previous gate signal from the previous gate line. According to another example, each of the plurality of gate drive circuit units (GDCs) may be connected to a previous gate drive circuit unit and may receive a previous control signal from the previous gate drive circuit unit.

[0077] An embodiment has been described based on the first clock pad CLP1, but this can also be applied to the second clock pad CLP2. The second clock pad CLP2 can be arranged spaced apart from the first clock pad CLP1, with a first scan pad SP1, a second scan pad SP2, a plurality of first data pads DP1, and a plurality of second data pads DP2 located between the second clock pad CLP2 and the first clock pad CLP1. The second clock pad CLP2 is connected to a plurality of gate drive circuit units GDC included in the second drive unit DU2 and transmits a second clock signal to the plurality of gate drive circuit units GDC. The plurality of gate drive circuit units GDC sequentially transmit second gate signals to a plurality of gate lines GL based on the second clock signal received from the second clock pad CLP2. In this case, the first clock signal and the second clock signal can be synchronized with each other, and the first gate signal and the second gate signal can be synchronized with each other.

[0078] The first scan pad SP1 can be connected to multiple gate drive circuit units GDC included in the first drive unit DU1. The second scan pad SP2 can be connected to multiple gate drive circuit units GDC included in the second drive unit DU2.

[0079] Multiple data lines DL extend in a first direction (e.g., the y-direction) and may include multiple first data lines DL1 and multiple second data lines DL2, wherein the multiple first data lines DL1 are disposed in a first region AR1 and the multiple second data lines DL2 are disposed in a second region AR2. The multiple first data lines DL1 may be connected to each of a plurality of first pixels PX1 disposed in the same column, and the multiple second data lines DL2 may be connected to each of a plurality of second pixels PX2 disposed in the same column.

[0080] Multiple data pads DP can be arranged between the first scan pad SP1 and the second scan pad SP2. The multiple data pads DP can include multiple first data pads DP1 and multiple second data pads DP2. Each of the multiple first data pads DP1 is connected to a corresponding first data line DL1 among multiple first data lines DL1, and each of the multiple second data pads DP2 is connected to a corresponding second data line DL2 among multiple second data lines DL2. Figure 2 In a given set of data pads (DPs), each data pad corresponds to a different data line (DL) among multiple data lines (DLs), but each data line (DL) may not correspond to a different data pad (DP) among multiple data pads (DPs). For example, some of the multiple data lines (DLs) can be connected to the same data pad (DP) among multiple data pads (DPs) via a multiplexer.

[0081] Display device 1 (see) Figure 1This may include a printed circuit board (PCB) on which a display driver circuit (DDC) is mounted. The display driver circuit (DDC) may include a timing controller (“TCON”) and data driver circuits, etc.

[0082] A printed circuit board (PCB) is mounted on pad units (PU), and the terminal units (PCB-P) of the PCB can be electrically connected to the pad units (PU) of the display panel 10. The PCB includes lines to be connected to each of the first clock pad (CLP1), the second clock pad (CLP2), the first scan pad (SP1), the second scan pad (SP2), and a plurality of data pads (DP), and can transmit signals or power from the controller to the display panel 10.

[0083] Figure 3 This is an equivalent circuit diagram of a pixel arranged on a display panel according to an embodiment.

[0084] refer to Figure 3 Each pixel PX includes a pixel circuit PC and an organic light-emitting diode (OLED), wherein the pixel circuit PC is connected to the scan line SL and the data line DL, and the organic light-emitting diode OLED is connected to the pixel circuit PC. The cathode of the organic light-emitting diode OLED can be a common electrode to which a common voltage ELVSS is applied.

[0085] The pixel circuit PC includes a driving thin-film transistor T1, a scanning thin-film transistor T2, and a storage capacitor Cst. The scanning thin-film transistor T2 is connected to the scan line SL and the data line DL, and transmits the data voltage Dm input through the data line DL according to the scan signal Sn received through the scan line SL.

[0086] The storage capacitor Cst is connected to the scanning thin-film transistor T2 and the drive voltage line PL, and stores a voltage corresponding to the difference between the voltage received from the scanning thin-film transistor T2 and the drive voltage ELVDD applied to the drive voltage line PL.

[0087] The driving thin-film transistor T1 is connected to the driving voltage line PL and the storage capacitor Cst, and can control the driving current flowing from the driving voltage line PL to the organic light-emitting diode (OLED). This driving current corresponds to the value of the voltage stored in the storage capacitor Cst. The OLED can emit light with a certain brightness according to the driving current.

[0088] exist Figure 3In the original description, the pixel circuit PC includes two thin-film transistors T1 and T2 and a storage capacitor Cst, but this disclosure is not limited thereto. For example, the pixel circuit PC may include three or more thin-film transistors and / or two or more storage capacitors. In an embodiment, the pixel circuit PC may include seven thin-film transistors and one storage capacitor. This will be referenced below. Figure 4 Described.

[0089] Figure 4 This is an equivalent circuit diagram of pixels arranged on a display panel according to an embodiment.

[0090] refer to Figure 4 Each of the pixels PX may include a pixel circuit PC and an organic light-emitting diode (OLED), wherein the OLED is electrically connected to the pixel circuit PC.

[0091] As an example, such as Figure 4 As shown, the pixel circuit PC may include a first thin-film transistor T1 to a seventh thin-film transistor T7 and a storage capacitor Cst. The first thin-film transistor T1 to the seventh thin-film transistor T7 and the storage capacitor Cst are connected to the first to third scan lines SL, SL-1 and SL+1 for transmitting the first to third scan signals Sn, Sn-1 and Sn+1, respectively; the data line DL for transmitting the data voltage Dm; the transmit control line EL for transmitting the transmit control signal En; the drive voltage line PL for transmitting the drive voltage ELVDD; the initialization voltage line VL for transmitting the initialization voltage Vint; and a common electrode to which a common voltage ELVSS is applied.

[0092] The first thin-film transistor T1 can be a driving transistor in which the magnitude of the leakage current is determined according to the gate-source voltage, and the second thin-film transistors T2 to the seventh thin-film transistors T7 can be switching transistors that are turned on and off according to the gate-source voltage (basically the gate voltage).

[0093] The first thin-film transistor T1 can be called a driving thin-film transistor, the second thin-film transistor T2 can be called a scanning thin-film transistor, the third thin-film transistor T3 can be called a compensation thin-film transistor, the fourth thin-film transistor T4 can be called a gate initialization thin-film transistor, the fifth thin-film transistor T5 can be called a first emitter control thin-film transistor, the sixth thin-film transistor T6 can be called a second emitter control thin-film transistor, and the seventh thin-film transistor T7 can be called an anode initialization thin-film transistor.

[0094] Between the driving voltage line PL and the driving gate G1 of the driving thin-film transistor T1, a storage capacitor Cst is connected to the driving voltage line PL. The storage capacitor Cst may have an upper electrode CE2 connected to the driving voltage line PL and a lower electrode CE1 connected to the driving gate G1 of the driving thin-film transistor T1.

[0095] The driving thin-film transistor T1 can control the driving current I flowing from the driving voltage line PL to the organic light-emitting diode (OLED) based on the gate-source voltage. OLED The size of the driving thin-film transistor T1 can include a driving gate G1, a driving source S1, and a driving drain D1, wherein the driving gate G1 is connected to the lower electrode CE1 of the storage capacitor Cst, the driving source S1 is connected to the driving voltage line PL through the first emission control thin-film transistor T5, and the driving drain D1 is connected to the organic light-emitting diode OLED through the second emission control thin-film transistor T6.

[0096] The driving thin-film transistor T1 can control the driving current I based on the gate-source voltage. OLED Output to an organic light-emitting diode (OLED). Drive current I OLED The magnitude is determined based on the difference between the gate-source voltage and the threshold voltage of the driving thin-film transistor T1. The organic light-emitting diode (OLED) can receive a driving current I from the driving thin-film transistor T1. OLED And can emit according to the drive current I OLED The size and brightness of the light.

[0097] The scanning thin-film transistor T2 transmits the data voltage Dm to the driving source S1 of the driving thin-film transistor T1 in response to the first scan signal Sn. The scanning thin-film transistor T2 includes a scan gate G2, a scan source S2, and a scan drain D2, wherein the scan gate G2 is connected to the first scan line SL, the scan source S2 is connected to the data line DL, and the scan drain D2 is connected to the driving source S1 of the driving thin-film transistor T1.

[0098] A compensation thin-film transistor T3 is connected in series between the driving drain D1 and the driving gate G1 of the driving thin-film transistor T1, and in response to the first scan signal Sn, the driving drain D1 of the driving thin-film transistor T1 is connected to the driving gate G1. The compensation thin-film transistor T3 includes a compensation gate G3, a compensation source S3, and a compensation drain D3, wherein the compensation gate G3 is connected to the first scan line SL, the compensation source S3 is connected to the driving drain D1 of the driving thin-film transistor T1, and the compensation drain D3 is connected to the driving gate G1 of the driving thin-film transistor T1. Figure 4 In the above, the compensation thin film transistor T3 includes two thin film transistors connected in series with each other, but the compensation thin film transistor T3 can also be composed of a single thin film transistor.

[0099] The gate-initialized thin-film transistor T4 applies an initialization voltage Vint to the driving gate G1 of the driving thin-film transistor T1 in response to the second scan signal Sn-1. The gate-initialized thin-film transistor T4 may include a first initialization gate G4 connected to the second scan line SL-1, a first initialization source S4 connected to the driving gate G1 of the driving thin-film transistor T1, and a first initialization drain D4 connected to the initialization voltage line VL. Figure 4 In the diagram, the gate-initialized thin-film transistor T4 comprises two thin-film transistors connected in series with each other, but the gate-initialized thin-film transistor T4 can also consist of a single thin-film transistor.

[0100] The anode initialization thin-film transistor T7 applies an initialization voltage Vint to the anode of the organic light-emitting diode (OLED) in response to the third scan signal Sn+1. The anode initialization thin-film transistor T7 may include a second initialization gate G7 connected to the third scan line SL+1, a second initialization source S7 connected to the anode of the OLED, and a second initialization drain D7 connected to the initialization voltage line VL.

[0101] The first emitter control thin-film transistor T5 can connect the drive voltage line PL and the drive source S1 of the drive thin-film transistor T1 to each other in response to the emitter control signal En. The first emitter control thin-film transistor T5 may include a first emitter control gate G5 connected to the emitter control line EL, a first emitter control source S5 connected to the drive voltage line PL, and a first emitter control drain D5 connected to the drive source S1 of the drive thin-film transistor T1.

[0102] The second emission control thin-film transistor T6 can connect the driving drain D1 of the driving thin-film transistor T1 to the anode of the organic light-emitting diode (OLED) in response to the emission control signal En. The second emission control thin-film transistor T6 may include a second emission control gate G6 connected to the emission control line EL, a second emission control source S6 connected to the driving drain D1 of the driving thin-film transistor T1, and a second emission control drain D6 connected to the anode of the organic light-emitting diode (OLED).

[0103] The second scan signal Sn-1 can be substantially synchronized with the first scan signal Sn in the previous row. The third scan signal Sn+1 can be substantially synchronized with the first scan signal Sn. According to another example, the third scan signal Sn+1 can be substantially synchronized with the first scan signal Sn in the next row.

[0104] In this embodiment, the first thin-film transistor T1 to the seventh thin-film transistor T7 may include a semiconductor layer comprising silicon. For example, the first thin-film transistor T1 to the seventh thin-film transistor T7 may include a semiconductor layer comprising low-temperature polycrystalline silicon (“LTPS”). Polycrystalline silicon material has a high electron mobility (100 square centimeters per volt-second). 2 ( / Vs or higher), low power consumption, and excellent reliability. As another example, the semiconductor layers of the first thin-film transistor T1 to the seventh thin-film transistor T7 include oxides of at least one material selected from the group consisting of indium (In), gallium (Ga), tin (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), aluminum (Al), cesium (Cs), cerium (Ce), and zinc (Zn). For example, the semiconductor layers of the first thin-film transistor T1 to the seventh thin-film transistor T7 may be In-Sn-Zn-O (“ITZO”) semiconductor layers or In-Ga-Zn-O (“IGZO”) semiconductor layers, etc. As another example, some semiconductor layers of the first thin-film transistor T1 to the seventh thin-film transistor T7 may be formed by LTPS, and other semiconductor layers may be formed by oxide semiconductors (e.g., IGZO).

[0105] The detailed operation process of each of the pixels PX in the display panel 10 according to the embodiment will now be described in detail. Figure 4 As illustrated in the diagram, it is assumed that the first thin-film transistor T1 to the seventh thin-film transistor T7 are p-type metal-oxide-semiconductor field-effect transistors (“MOSFETs”).

[0106] First, when a high-level transmit control signal En is received, the first transmit control thin-film transistor T5 and the second transmit control thin-film transistor T6 are turned off, and the driving thin-film transistor T1 stops driving current I. OLED The output of the OLED is reduced, and the OLED stops emitting light.

[0107] Subsequently, during the gate initialization period when the low-level second scan signal Sn-1 is received, the gate initialization thin-film transistor T4 is turned on, and the initialization voltage Vint is applied to the driving gate G1 of the driving thin-film transistor T1, i.e., the lower electrode CE1 of the storage capacitor Cst. The difference (ELVDD-Vint) between the driving voltage ELVDD and the initialization voltage Vint is stored in the storage capacitor Cst.

[0108] Subsequently, during the data writing period when the low-level first scan signal Sn is received, scan TFT T2 and compensation TFT T3 are turned on, and the data voltage Dm is received in the drive source S1 of drive TFT T1. Drive TFT T1 is connected to a diode using compensation TFT T3 and is forward biased. The gate voltage of drive TFT T1 rises from the initialization voltage Vint. When the gate voltage of drive TFT T1 equals the data compensation voltage (Dm-|Vth|) obtained by subtracting the threshold voltage Vth of drive TFT T1 from the data voltage Dm, drive TFT T1 is turned off, and the gate voltage of drive TFT T1 stops rising. Therefore, the difference (ELVDD-Dm+|Vth|) between the drive voltage ELVDD and the data compensation voltage (Dm-|Vth|) is stored in the storage capacitor Cst.

[0109] Furthermore, during the anode initialization period when the low-level third scan signal Sn+1 is received, the anode initialization thin-film transistor T7 is turned on, and an initialization voltage Vint is applied to the anode of the OLED. By applying the initialization voltage Vint to the anode of the OLED, the OLED does not emit any light at all, and therefore, in the next frame, pixel PX receives the data voltage Dm corresponding to the black grayscale, but the phenomenon of the OLED emitting light is eliminated.

[0110] The first scan signal Sn and the third scan signal Sn+1 can be basically synchronized, and in this case, the data writing period and the anode initialization period can be the same period.

[0111] Then, when a low-level transmit control signal En is received, the first transmit control thin-film transistor T5 and the second transmit control thin-film transistor T6 are turned on, and the driving thin-film transistor T1 can output a drive current I corresponding to the voltage stored in the storage capacitor Cst (i.e., the voltage obtained by subtracting the threshold voltage (|Vth|) of the driving thin-film transistor T1 from the source-gate voltage (ELVDD-Dm+|Vth|) of the driving thin-film transistor T1). OLED Furthermore, organic light-emitting diodes (OLEDs) can emit light with a frequency response similar to the driving current I. OLED The size of the light corresponds to its brightness.

[0112] The operation of a pixel PX of the display panel 10 is described based on the assumption that the first thin-film transistors T1 to the seventh thin-film transistors T7 are p-type MOSFETs. However, in another example, some of the thin-film transistors T1 to T7 may be formed by p-type MOSFETs, and the other thin-film transistors may be formed by n-type MOSFETs.

[0113] Figure 5 It is a schematic diagram. Figure 2 An enlarged plan view of part A, and Figure 6 and Figure 7 It is along Figure 5 The lines I-I' and II-II' in the middle are intercepted Figure 5 An exemplary cross-sectional view of the display panel.

[0114] refer to Figure 5 Display device 1 (see Figure 1 It may include a first gate driving circuit unit GDC1, a second gate driving circuit unit GDC2, a first pixel circuit unit PC1, a second pixel circuit unit PC2, a first data line DL1, a second data line DL2, a first gate line GL1, and a second gate line GL2.

[0115] The first gate driving circuit unit GDC1, the second gate driving circuit unit GDC2, the first pixel circuit unit PC1, the first data line DL1, and the first gate line GL1 can be disposed in the first region AR1, and the second pixel circuit unit PC2, the second data line DL2, and the second gate line GL2 can be disposed in the second region AR2.

[0116] The first gate driving circuit unit GDC1 and the second gate driving circuit unit GDC2 can be disposed on one side of the first region AR1. The first gate driving circuit unit GDC1 and the second gate driving circuit unit GDC2 can be arranged to be spaced apart from each other. The first gate driving circuit unit GDC1 and the second gate driving circuit unit GDC2 can be adjacent to each other. The first pixel circuit unit PC1 can be disposed in the region between the first gate driving circuit unit GDC1 and the second gate driving circuit unit GDC2.

[0117] Despite Figure 5Not shown in the diagram, but a gate driving circuit unit can be further arranged, spaced apart from the second gate driving circuit unit GDC2 in a manner that the first gate driving circuit unit GDC1 and the second gate driving circuit unit GDC2 are spaced apart from each other. The first pixel circuit unit PC1 can also be arranged in the region between the second gate driving circuit unit GDC2 and the gate driving circuit unit, wherein the gate driving circuit unit and the second gate driving circuit unit GDC2 are spaced apart in this region. That is, multiple gate driving circuit units GDC can be arranged spaced apart from each other, and the first pixel circuit unit PC1 can be arranged between the multiple gate driving circuit units GDC. There can be multiple first pixel circuit units PC1, and the multiple first pixel circuit units PC1 can be arranged side-by-side in the x-direction.

[0118] The second pixel circuit unit PC2 can be arranged in the second region AR2, and there can be multiple second pixel circuit units PC2. The multiple second pixel circuit units PC2 can be arranged in the row direction (e.g., the x direction) and the column direction (e.g., the y direction), respectively.

[0119] The first data line DL1 and the second data line DL2 may each extend in a first direction (e.g., the y direction).

[0120] A first data line DL1 is disposed in a first region AR1 and may overlap with a gate drive circuit unit GDC and a first pixel circuit unit PC1 in a plan view. There may be multiple first data lines DL1, and each of the multiple first data lines DL1 may overlap with a first pixel circuit unit PC1 arranged in the same column. Each of the multiple first data lines DL1 may be connected to a first pixel circuit unit PC1 arranged in the same column.

[0121] A second data line DL2 is disposed in a second region AR2 and may overlap with a second pixel circuit unit PC2 in a planar view. There may be multiple second data lines DL2, and each of the multiple second data lines DL2 may overlap with a second pixel circuit unit PC2 arranged in the same column in a planar view. Each of the multiple second data lines DL2 may be connected to a second pixel circuit unit PC2 arranged in the same column.

[0122] In an embodiment, such as Figure 5 As shown, the sum of the length l1 of the first direction of the first gate driving circuit unit GDC1 and the length l2 of the first direction of the first pixel circuit unit PC1 can be less than or equal to the length l3 of the first direction (e.g., the y-direction) of the second pixel circuit unit PC2. The area in which the first pixel circuit unit PC1 is disposed can be smaller than the area in which the second pixel circuit unit PC2 is disposed.

[0123] For example, the length l1 of the first gate driving circuit unit GDC1 can be the distance between the metal patterns that are most spaced apart in the first direction among the metal patterns constituting the first gate driving circuit unit GDC1. Although it has been described based on the first gate driving circuit unit GDC1, the first pixel circuit unit PC1 and the second pixel circuit unit PC2 can be applied equivalently.

[0124] The number of thin-film transistors included in the first pixel circuit unit PC1 can be less than or equal to the number of thin-film transistors included in the second pixel circuit unit PC2. For example, the first pixel circuit unit PC1 can be and Figure 3 The pixel circuit PC shown is the same, including two thin-film transistors, and the second pixel circuit unit PC2 can be connected to... Figure 4 The pixel circuit PC shown includes seven thin-film transistors, just like the one illustrated. As another example, the first pixel circuit unit PC1 may include three thin-film transistors. As yet another example, the first pixel circuit unit PC1 and the second pixel circuit unit PC2 both include seven thin-film transistors, but the configuration and arrangement of the seven thin-film transistors may differ from the configuration and arrangement of the seven thin-film transistors included in the second pixel circuit unit PC2.

[0125] First gate line GL1 and second gate line GL2 can be connected to first gate drive circuit unit GDC1 and can be synchronized. First gate line GL1 and second gate line GL2 can each include an emission control line and a scan line. First gate line GL1 extends to a first region AR1 and can overlap with first pixel circuit unit PC1 in a planar view. Second gate line GL2 extends to a second region AR2 and can overlap with second pixel circuit unit PC2 in a planar view. While it has been described that first gate line GL1 and second gate line GL2 are each connected to first gate drive circuit unit GDC1, embodiments can be similarly applied to first gate line GL1 and second gate line GL2, wherein first gate line GL1 and second gate line GL2 are each connected to second gate drive circuit unit GDC2.

[0126] Display device 1 may include a first display element DE1 electrically connected to a first pixel circuit unit PC1 and a second display element DE2 electrically connected to a second pixel circuit unit PC2. The first display element DE1 may at least partially overlap with the gate drive circuit unit GDC in a plan view.

[0127] The first display element DE1 can be connected to the first pixel circuit unit PC1 through the first contact hole CNT1, and the second display element DE2 can be connected to the second pixel circuit unit PC2 through the second contact hole CNT2.

[0128] like Figure 6As illustrated in the diagram, the first display element DE1 may include a first pixel electrode PXL1, a first intermediate layer IML1, and a counter electrode OE. The first pixel electrode PXL1 may extend from a first contact hole CNT1 in the +y direction. A first opening OP1 defined in the pixel defining layer PDL to expose a portion of the first pixel electrode PXL1 may define a first emission region EA1. The first emission region EA1 defined by the first opening OP1 may be disposed in the +y direction relative to the first contact hole CNT1. The first emission region EA1 may overlap with the gate drive circuit unit GDC in the planar view.

[0129] exist Figure 6 In this example, the first pixel electrode PXL1 extends from the first contact hole CNT1 in the +y direction. However, as another example, the first pixel electrode PXL1 can extend from the first contact hole CNT1 in the -y direction. The first emission region EA1 defined by the first opening OP1 can be positioned relative to the first contact hole CNT1 in the -y direction.

[0130] like Figure 6 As shown, the second display element DE2 may include a second pixel electrode PXL2, a second intermediate layer IML2, and a counter electrode OE. The second pixel electrode PXL2 can be accessed from the second contact hole CNT2 in the +y direction (i.e., Figure 6 (in the left direction) or -y direction (i.e., Figure 6 Extending upwards (to the right of the image). A second opening OP2, defined in the pixel definition layer PDL to expose a portion of the second pixel electrode PXL2, can define a second emission region EA2. The second emission region EA2 defined by the second opening OP2 can be set in the +y or -y direction based on the second contact hole CNT2.

[0131] exist Figure 5 In this configuration, the first pixel PX1 and the second pixel PX2 are arranged in a five-cell array. The first pixel PX1 includes a first pixel circuit unit PC1 and a first display element DE1, and the second pixel PX2 includes a second pixel circuit unit PC2 and a second display element DE2. However, the first pixel PX1 and the second pixel PX2 can have various forms, such as a strip arrangement and a mosaic arrangement.

[0132] In the following text, the stacked structure reference will be used. Figure 6 and Figure 7 The configuration included in the display device 1 will be described in more detail, and the positional relationship between the first data line DL1 and the second data line DL2 will be described.

[0133] Substrate 100 may comprise glass or polymer resin. Polymer resins include polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, or cellulose acetate propionate, etc. Substrate 100 comprising polymer resin may have flexible, rollable, or bendable properties. Substrate 100 may be a multilayer structure comprising a layer containing the polymer resin described above and an inorganic layer (not shown).

[0134] The buffer layer 111 can reduce or prevent the penetration of foreign matter, moisture, or ambient air from the bottom of the substrate 100 and can provide a flat surface on the substrate 100. The buffer layer 111 may include inorganic materials such as oxides or nitrides, organic materials, or organic-inorganic composites, and may be formed from a single layer or multiple layers of inorganic and organic materials.

[0135] A barrier layer (not shown) may be further included between the substrate 100 and the buffer layer 111. The barrier layer can be used to prevent or significantly reduce the penetration of impurities from the substrate 100, etc., into the semiconductor layer A. The barrier layer may include inorganic materials such as oxides or nitrides, organic materials, or organic-inorganic composites, and may be formed from a single layer or multiple layers of inorganic and organic materials.

[0136] Semiconductor layer A may be disposed on buffer layer 111. Semiconductor layer A may comprise amorphous silicon or polycrystalline silicon. In another embodiment, semiconductor layer A may comprise an oxide of at least one material selected from the group consisting of indium (In), gallium (Ga), tin (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), aluminum (Al), cesium (Cs), cerium (Ce), and zinc (Zn).

[0137] Semiconductor layer A may include a channel region, a source region, and a drain region, wherein the source region and the drain region are disposed on either side of the channel region. Semiconductor layer A may consist of a single layer or multiple layers.

[0138] A first gate insulating layer GI1 and a second gate insulating layer GI2 can be stacked on the substrate 100 to cover the semiconductor layer A. The first gate insulating layer GI1 and the second gate insulating layer GI2 may comprise silicon oxide (SiO2) or silicon nitride (SiN). X Examples of silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc oxide (ZnO) are included.

[0139] The gate electrode G can be arranged on the first gate insulating layer GI1 to at least partially overlap with the semiconductor layer A in a planar view. Figure 6In this embodiment, the gate electrode G is disposed on the first gate insulating layer GI1. However, in another embodiment, the gate electrode G may be disposed on the front side of the second gate insulating layer GI2.

[0140] The gate electrode G can be formed from a single layer or multiple layers of at least one metal selected from the group consisting of aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu).

[0141] The first pixel circuit unit PC1 and the second pixel circuit unit PC2 may each include a storage capacitor Cst. The storage capacitor Cst is provided with a lower electrode CE1 and an upper electrode CE2, and as follows: Figure 6 As shown, it can overlap with the thin-film transistor (TFT). For example, the gate electrode G of the TFT can be used as the lower electrode CE1 of the storage capacitor Cst. Alternatively, the storage capacitor Cst can not overlap with the TFT in the planar view and can exist independently.

[0142] The upper electrode CE2 of the storage capacitor Cst overlaps with the lower electrode CE1 to form a capacitor, and the second gate insulating layer GI2 is located between the upper electrode CE2 and the lower electrode CE1. In this case, the second gate insulating layer GI2 can be used as the dielectric layer of the storage capacitor Cst.

[0143] A first insulating layer IL1 may be provided on the second gate insulating layer GI2 to cover the upper electrode CE2 of the storage capacitor Cst. The first insulating layer IL1 may include SiO2, SiN X Materials such as SiON, Al2O3, TiO2, Ta2O5, HfO2, or ZnO. Additionally, the first insulating layer IL1 may include organic materials. Examples include general polymers such as benzocyclobutene (“BCB”), polyimide, hexamethyldisiloxane (“HMDSO”), poly(methyl methacrylate”) (“PMMA”), or polystyrene (“PS”), polymer derivatives having phenolic groups, acrylic polymers, imide polymers, aryl ether polymers, amide polymers, fluorinated polymers, p-xylene polymers, vinyl alcohol polymers, and blends thereof.

[0144] The source electrode, drain electrode, and second data line DL2 can be arranged on the first insulating layer IL1. In an embodiment, as shown... Figure 7 As shown, the clock line CWL can also be arranged on the first insulating layer IL1. The clock line CWL can be connected from... Figure 2The clock signal transmitted from the first clock pad CLP1 and the second clock pad CLP2 is sent to the gate drive circuit unit GDC. There can be multiple clock lines CWL.

[0145] The source electrode, drain electrode, second data line DL2, and clock line CWL may comprise conductive materials such as Mo, Al, Cu, or Ti, and may be formed from multiple layers or a single layer comprising these materials. For example, the source electrode, drain electrode, second data line DL2, and clock line CWL may be formed from a Ti / Al / Ti multilayer structure. The source electrode and drain electrode may be connected to the source or drain region of semiconductor layer A via contact holes.

[0146] The source electrode, drain electrode, second data line DL2, and clock line CWL can be covered with an inorganic protective layer (not shown). The inorganic protective layer can be SiN. X and silicon dioxide (SiO) X (A single or multilayer film.) An inorganic protective layer may be introduced to cover and protect some of the wires arranged on the first insulating layer IL1.

[0147] The second insulating layer IL2 and the third insulating layer IL3 are arranged sequentially to cover the source electrode, the drain electrode, the second data line DL2 and the clock line CWL, and each of the second insulating layer IL2 and the third insulating layer IL3 defines a contact hole for connecting the thin film transistor TFT to the pixel electrode PXL.

[0148] The second insulating layer IL2 and the third insulating layer IL3 may comprise films made of single or multiple layers of organic materials and may provide a flat front surface. The second insulating layer IL2 and the third insulating layer IL3 may comprise general polymers such as BCB, polyimide, HMDSO, PMMA, or PS, polymers having phenolic groups, acrylic polymers, imide polymers, aryl ether polymers, amide polymers, fluorinated polymers, p-xylene polymers, vinyl alcohol polymers, and blends thereof.

[0149] The first data line DL1, the first electrode layer E1, and the second electrode layer E2 can be disposed on the second insulating layer IL2. The first electrode layer E1 and the second electrode layer E2 can be connected to the thin-film transistor TFT of the first pixel circuit unit PC1 and the thin-film transistor TFT of the second pixel circuit unit PC2, respectively, through contact holes defined in the second insulating layer IL2.

[0150] like Figure 6 and Figure 7 As shown, the first data line DL1 can be arranged on different layers from the second data line DL2 and the clock line CWL, and the first data line DL1 can overlap with the clock line CWL in the plan view. The first data line DL1 and the second data line DL2 can be arranged on different layers.

[0151] The first display element DE1 and the second display element DE2 can be disposed on the third insulating layer IL3. The first display element DE1 may include a first pixel electrode PXL1, a first intermediate layer IML1 and a counter electrode OE, and the second display element DE2 may include a second pixel electrode PXL2, a second intermediate layer IML2 and a counter electrode OE.

[0152] like Figure 6 As illustrated, a first display element DE1 can be arranged in a first region AR1 and can overlap with a first gate drive circuit unit GDC1 in a plan view. The first display element DE1 can be connected to a thin-film transistor TFT of a first pixel circuit unit PC1 via a first contact hole CNT1 defined in a third insulating layer IL3. For example, a first pixel electrode PXL1 of the first display element DE1 can be connected to a first electrode layer E1 via a first contact hole CNT1 defined in a third insulating layer IL3, and the first electrode layer E1 can be connected to a thin-film transistor TFT of the first pixel circuit unit PC1 via a contact hole defined in a second insulating layer IL2.

[0153] The second display element DE2 can be disposed in the second region AR2. The second display element DE2 can be connected to the thin-film transistor TFT of the second pixel circuit unit PC2 through the second contact hole CNT2 defined in the third insulating layer IL3. For example, the second pixel electrode PXL2 of the second display element DE2 can be connected to the second electrode layer E2 through the second contact hole CNT2 defined in the third insulating layer IL3, and the second electrode layer E2 can be connected to the thin-film transistor TFT of the second pixel circuit unit PC2 through the contact hole defined in the second insulating layer IL2.

[0154] The pixel electrode PXL can be a translucent electrode or a reflective electrode. In some embodiments, the pixel electrode PXL may include a reflective layer formed of Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr and their compounds, and a transparent or translucent electrode layer formed on the reflective layer. The transparent or translucent electrode layer may include at least one selected from the group consisting of indium tin oxide (“ITO”), indium zinc oxide (“IZO”), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (“IGO”), and zinc aluminum oxide (“AZO”). In some embodiments, the pixel electrode PXL may be provided with ITO / Ag / ITO.

[0155] A pixel defining layer (PDL) can be disposed on a third insulating layer (IL3). The PDL increases the distance between the edge of the pixel electrode PXL and the counter electrode OE above the pixel electrode PXL, thereby preventing arcing at the edge of the pixel electrode PXL. The PDL may include a first opening OP1 exposing a portion of the first pixel electrode PXL1 and a second opening OP2 exposing a portion of the second pixel electrode PXL2. The first opening OP1 may define a first emission region EA1 of the first display element DE1, and the second opening OP2 may define a second emission region EA2 of the second display element DE2.

[0156] The pixel-limiting layer (PDL) may be composed of one or more organic insulating materials selected from the group consisting of polyimide, polyamide, acrylic resin, BCB, and phenolic resin.

[0157] The first intermediate layer IML1 and the second intermediate layer IML2 can be disposed in the first opening OP1 and the second opening OP2 defined by the pixel-defining layer PDL, respectively, and can include an organic emitting layer. The organic emitting layer can include an organic material, including fluorescent or phosphorescent materials that emit red, green, blue, or white light. The organic emitting layer can be a low-molecular-weight organic material or a high-molecular-weight organic material, and the hole transport layer (“HTL”), hole injection layer (“HIL”), electron transport layer (“ETL”), and electron injection layer (“EIL”) can be selectively disposed below and / or above the organic emitting layer.

[0158] The counter electrode OE can be a transmissive electrode or a reflective electrode. In some embodiments, the counter electrode OE can be a transparent or translucent electrode and can be formed from a metal thin film with a low work function, including Li, Ca, LiF, Al, Ag, Mg, and their compounds. Additionally, a transparent conductive oxide (“TCO”) film, such as ITO, IZO, ZnO, or In2O3, can be further disposed above the metal thin film. The counter electrode OE can be disposed on top of the first intermediate layer IML1 and the pixel defining layer PDL. The counter electrode OE can be integrally formed with multiple organic light-emitting diodes (OLEDs) and can correspond to multiple pixel electrodes PXL.

[0159] Since organic light-emitting devices (OLEDs) are susceptible to damage from external moisture or oxygen, an encapsulation layer (not shown) can cover and protect the OLEDs. The encapsulation layer may include a first inorganic encapsulation layer, an organic encapsulation layer, and / or a second inorganic encapsulation layer.

[0160] Figure 8 It is a schematic diagram. Figure 5 Another exemplary enlarged plan view of part B, and Figure 9 It is along Figure 8The line III-III' in the middle is intercepted Figure 8 An exemplary cross-sectional view of the display panel. Figure 8 and Figure 9 In, with Figure 5 and Figure 6 In the accompanying drawings, the same reference numerals refer to the same components, and repeated descriptions of them will be omitted.

[0161] Figure 8 yes Figure 5 A magnified view of the first region AR1 in the image. (Reference) Figure 8 Display device 1 (see Figure 1 It may include a first gate driving circuit unit GDC1, a second gate driving circuit unit GDC2, a first pixel circuit unit PC1, a first data line DL1, and a first gate line GL1.

[0162] The first gate driving circuit unit GDC1 and the second gate driving circuit unit GDC2 can be arranged to be spaced apart from each other, and the first pixel circuit unit PC1 can be arranged between the first gate driving circuit unit GDC1 and the second gate driving circuit unit GDC2.

[0163] In an embodiment, such as Figure 8 and Figure 9 As illustrated, the display device 1 includes a first-1 display element DE1-1 and a first-2 display element DE1-2, each electrically connected to a first pixel circuit unit PC1. The first-1 display element DE1-1 may at least partially overlap with a first gate drive circuit unit GDC1 in a plan view, and the first-2 display element DE1-2 may at least partially overlap with a second gate drive circuit unit GDC2 in a plan view.

[0164] Display element DE1-1 (1-1) and display element DE1-2 (1-2) can be connected to the first pixel circuit unit PC1 via the third contact hole CNT3.

[0165] refer to Figure 9 Display element DE1-1 (first-first display element) may include a first-first pixel electrode PXL1-1, a first-first intermediate layer IML1-1, and a counter electrode OE. Display element DE1-2 (first-second display element) may also include a first-first pixel electrode PXL1-1, a first-second intermediate layer IML1-2, and a counter electrode OE. Display element DE1-1 and display element DE1-2 (first-second display element) may share the first-first pixel electrode PXL1-1. The first-first intermediate layer IML1-1 and the first-second intermediate layer IML1-2 may each emit light in the same wavelength band.

[0166] like Figure 8 and Figure 9 As shown, the first-1 pixel electrode PXL1-1 can be accessed from the third contact hole CNT3 in the +y direction (i.e., Figure 9 (in the left direction) and -y direction (i.e., Figure 9 Extending upwards in the right direction (in the planar view). In the planar view, the portion of the first-1 pixel electrode PXL1-1 extending in the +y direction can overlap with the first gate drive circuit unit GDC1, and the portion of the first-1 pixel electrode PXL1-1 extending in the -y direction can overlap with the second gate drive circuit unit GDC2.

[0167] The pixel definition layer (PDL) can define a first-1 opening OP1-1 in the planar view that exposes the portion of the first-1 pixel electrode PXL1-1 that overlaps with the first gate driving circuit unit GDC1, and a first-2 opening OP1-2 that exposes the portion of the first-1 pixel electrode PXL1-1 that overlaps with the second gate driving circuit unit GDC2. The first-1 opening OP1-1 and the first-2 opening OP1-2 can define the first-1 emission region EA1-1 of the first-1 display element DE1-1 and the first-2 emission region EA1-2 of the first-2 display element DE1-2, respectively.

[0168] The first-1 emission region EA1-1, defined by the first-1 opening OP1-1, can be positioned in the +y direction relative to the third contact hole CNT3, and can overlap with the first gate drive circuit unit GDC1 in a plan view. The first-2 emission region EA1-2, defined by the first-2 opening OP1-2, can be positioned in the -y direction relative to the third contact hole CNT3, and can overlap with the second gate drive circuit unit GDC2 in a plan view.

[0169] The dimensions of opening OP1-1 (first-first opening) and opening OP1-2 (first-second opening) can be the same. The area of ​​launch region EA1-1 (first-first launch region) and launch region EA1-2 (first-second launch region) can be the same.

[0170] Figure 10 It is a schematic diagram. Figure 2 Another exemplary enlarged plan view of part A, and Figure 11 It is along Figure 10 The line IV-IV' in the middle is intercepted Figure 10 An exemplary cross-sectional view of the display panel. Figure 10 and Figure 11 In, with Figure 5 and Figure 6 In the accompanying drawings, the same reference numerals refer to the same components, and repeated descriptions of them will be omitted.

[0171] refer to Figure 10 Display device 1 (see Figure 1 It may include a first gate driving circuit unit GDC1, a second gate driving circuit unit GDC2, a first pixel circuit unit PC1, a second pixel circuit unit PC2, a first data line DL1, a second data line DL2, a first gate line GL1, and a second gate line GL2.

[0172] The first gate driving circuit unit GDC1 and the second gate driving circuit unit GDC2 can be arranged to be spaced apart from each other, and the first pixel circuit unit PC1 can be arranged between the first gate driving circuit unit GDC1 and the second gate driving circuit unit GDC2.

[0173] In an embodiment, such as Figure 10 As illustrated in the diagram, display device 1 may include first-3 display elements DE1-3 and first-4 display elements DE1-4, each electrically connected to a first pixel circuit unit PC1. In the plan view, first-3 display element DE1-3 may at least partially overlap with a first gate driving circuit unit GDC1, and first-4 display element DE1-4 may at least partially overlap with the first pixel circuit unit PC1. A portion of first-4 display element DE1-4 may overlap with the first gate driving circuit unit GDC1. Display device 1 may include a second display element DE2 electrically connected to a second pixel circuit unit PC2.

[0174] Display elements DE1-3 (1-3) and DE1-4 (1-4) can be connected to the first pixel circuit unit PC1 via the fourth contact hole CNT4. The second display element DE2 can be connected to the second pixel circuit unit PC2 via the second contact hole CNT2.

[0175] refer to Figure 11 Display elements DE1-3 (1-3) may include pixel electrodes PXL1-2 (1-2), intermediate layers IML1-3 (1-3), and counter electrodes OE. Display elements DE1-4 (1-4) may also include pixel electrodes PXL1-2 (1-2), intermediate layers IML1-4 (1-4), and counter electrodes OE. Display elements DE1-3 (1-3) and DE1-4 (1-4) may share pixel electrode PXL1-2. Intermediate layers IML1-3 (1-3) and IML1-4 (1-4) may each emit light in the same wavelength band.

[0176] like Figure 10 and Figure 11As shown, the first-second pixel electrode PXL1-2 can extend from the fourth contact hole CNT4 in the +y direction. In the plan view, a portion of the first-second pixel electrode PXL1-2 extending in the +y direction can overlap with the first gate drive circuit unit GDC1, and the remaining portion of the first-second pixel electrode PXL1-2 can overlap with the first pixel circuit unit PC1.

[0177] As another example, the first-second pixel electrode PXL1-2 can extend from the fourth contact hole CNT4 in the -y direction. In the plan view, a portion of the first-second pixel electrode PXL1-2 extending in the -y direction can overlap with the second gate drive circuit unit GDC2, and the remaining portion of the first-second pixel electrode PXL1-2 can overlap with the first pixel circuit unit PC1.

[0178] The pixel definition layer (PDL) may include a first-third opening (OP1-3) and a fourth opening (OP1-4). In a plan view, the first-third opening (OP1-3) exposes the portion of the first-second pixel electrode (PXL1-2) that overlaps with the first gate drive circuit unit (GDC1), and the fourth opening (OP1-4) exposes the portion of the first-second pixel electrode (PXL1-2) that overlaps with the first pixel circuit unit (PC1). The first-third opening (OP1-3) and the fourth opening (OP1-4) may define the first-third emission region (EA1-3) of the first-third display element (DE1-3) and the first-fourth emission region (EA1-4) of the first-fourth display element (DE1-4), respectively.

[0179] Additionally, the pixel defining layer PDL may further include a second opening OP2 that exposes a portion of the second pixel electrode PXL2, and the second opening OP2 may define a second emission region EA2 of the second display element DE2.

[0180] Each of the first-3 emission region EA1-3 defined by the first-3 opening OP1-3 and the first-4 emission region EA1-4 defined by the first-4 opening OP1-4 can be positioned in the +y direction based on the fourth contact hole CNT4. As another example, the first-3 emission region EA1-3 and the first-4 emission region EA1-4 can be positioned in the -y direction based on the fourth contact hole CNT4.

[0181] The dimensions of opening OP1-3 (first-third opening) and opening OP1-4 (first-fourth opening) can be the same. The area of ​​launch region EA1-3 (first-third launch region) and launch region EA1-4 (first-fourth launch region) can be the same.

[0182] like Figure 10As shown in the diagram, the size of opening OP1-3 (first-third opening) can be smaller than the size of opening OP2 (second-third opening). The size of opening OP1-4 (first-fourth opening) can be smaller than the size of opening OP2 (second-third opening). The area of ​​emission region EA1-3 (first-third emission region) can be smaller than the area of ​​emission region EA2 (second-third emission region). The area of ​​emission region EA1-4 (first-fourth emission region) can be smaller than the area of ​​emission region EA2 (second-third emission region).

[0183] Figure 12 It is a schematic diagram. Figure 5 Another exemplary enlarged plan view of part B, and Figure 13 It is along Figure 12 The line V-V' intercepted in the middle Figure 12 An exemplary cross-sectional view of the display panel. Figure 12 and Figure 13 In, with Figure 5 and Figure 6 In the accompanying drawings, the same reference numerals refer to the same components, and repeated descriptions of them will be omitted.

[0184] Figure 12 yes Figure 5 A magnified view of the first region AR1 in the image. (Reference) Figure 12 Display device 1 (see Figure 1 It may include a first gate driving circuit unit GDC1, a second gate driving circuit unit GDC2, a first-1 pixel circuit unit PC1-1, a first-2 pixel circuit unit PC1-2, a voltage line VWL, a first data line DL1, and a first gate line GL1.

[0185] The first gate driving circuit unit GDC1 and the second gate driving circuit unit GDC2 can be arranged to be spaced apart from each other, and the first-1 pixel circuit unit PC1-1 can be arranged between the first gate driving circuit unit GDC1 and the second gate driving circuit unit GDC2. The first-2 pixel circuit unit PC1-2 can be arranged between the first-1 pixel circuit unit PC1-1 and the second gate driving circuit unit GDC2.

[0186] A voltage line VWL can be arranged between pixel circuit unit PC1-1 (first-first pixel) and pixel circuit unit PC1-2 (first-second pixel). The voltage line VWL can be connected to each of pixel circuit units PC1-1 and PC1-2. The voltage line VWL can be an initialization voltage line or a driving voltage line. When the voltage line VWL is arranged between pixel circuit unit PC1-1 and pixel circuit unit PC1-2 (first-second pixel), voltage can be applied to the two pixel circuit units PC1-1 and PC1-2 arranged in different rows through a single voltage line VWL. Therefore, the area occupied by the voltage line VWL used to apply voltage to pixel circuit units PC1-1 and PC1-2 can be significantly reduced.

[0187] In an embodiment, such as Figure 12 As shown, the display device 1 may include display elements DE1-5 (1-5) and DE1-6 (1-6), wherein display element DE1-5 is electrically connected to pixel circuit unit PC1-1 (1-1), and display element DE1-6 is electrically connected to pixel circuit unit PC1-2 (1-2). In the plan view, display element DE1-5 may at least partially overlap with first gate driving circuit unit GDC1, and display element DE1-6 may at least partially overlap with second gate driving circuit unit GDC2.

[0188] Display element DE1-5 (1-5) can be connected to pixel circuit unit PC1-1 (1-1) via fifth contact hole CNT5, and display element DE1-6 (1-6) can be connected to pixel circuit unit PC1-2 (1-2) via sixth contact hole CNT6.

[0189] refer to Figure 13 The first-5 display elements DE1-5 may include the first-3 pixel electrodes PXL1-3, the first-5 intermediate layer IML1-5 and the counter electrode OE, and the first-6 display elements DE1-6 may include the first-4 pixel electrodes PXL1-4, the first-6 intermediate layer IML1-6 and the counter electrode OE.

[0190] like Figure 12 and Figure 13 As shown, the first to third pixel electrodes PXL1-3 can extend from the fifth contact hole CNT5 in the +y direction. The portion of the first to third pixel electrodes PXL1-3 extending in the +y direction can overlap with the first gate drive circuit unit GDC1 in the planar view. The first to fourth pixel electrode PXL1-4 can extend from the sixth contact hole CNT6 in the -y direction. The portion of the first to fourth pixel electrodes PXL1-4 extending in the -y direction can overlap with the second gate drive circuit unit GDC2 in the planar view.

[0191] The pixel definition layer (PDL) may include openings OP1-5 (1-5) and OP1-6 (1-6). In a plan view, opening OP1-5 exposes the portion of pixel electrode PXL1-3 that overlaps with the first gate driving circuit unit GDC1, and opening OP1-6 exposes the portion of pixel electrode PXL1-4 that overlaps with the second gate driving circuit unit GDC2. Openings OP1-5 and OP1-6 may define the emission region EA1-5 of display element DE1-5 (1-5) and the emission region EA1-6 of display element DE1-6 (1-6), respectively.

[0192] The first-5 emission region EA1-5, defined by the first-5 opening OP1-5, can be positioned in the +y direction relative to the fifth contact hole CNT5, and can overlap with the first gate drive circuit unit GDC1 in a plan view. The first-6 emission region EA1-6, defined by the first-6 opening OP1-6, can be positioned in the -y direction relative to the sixth contact hole CNT6, and can overlap with the second gate drive circuit unit GDC2 in a plan view.

[0193] The dimensions of opening OP1-5 (1-5) and opening OP1-6 (1-6) can be the same. The area of ​​launch region EA1-5 (1-5) and launch region EA1-6 (1-6) can be the same.

[0194] Figure 14 and Figure 15 It is a schematic diagram. Figure 5 Another enlarged plan view of part B.

[0195] Figure 14 and Figure 15 yes Figure 5 A magnified view of the first region AR1 in the image. (Reference) Figure 14 and Figure 15 Display device 1 (see Figure 1 It may include a first gate driving circuit unit GDC1, a second gate driving circuit unit GDC2, a first-to-third pixel circuit unit PC1-3, a first-to-fourth pixel circuit unit PC1-4, a first gate line GL1, and a second gate line GL2.

[0196] The first gate line GL1 and the second gate line GL2 can be connected to the first gate drive circuit unit GDC1 and can be synchronized with each other. The first gate line GL1 and the second gate line GL2 can each include an emission control line and a scan line. The first gate line GL1 can extend in the -x direction, and the second gate line GL2 can extend in the +x direction.

[0197] In an embodiment, such as Figure 14 and Figure 15 As shown, the sum of the length l4 of the second direction (i.e., the x direction) of the first gate driving circuit unit GDC1 and the length l5 of the second direction of the first-3 pixel circuit units PC1-3 can be equal to the sum of the length l6 of the second direction of the second gate driving circuit unit GDC2 and the length l7 of the second direction of the first-4 pixel circuit units PC1-4.

[0198] Display device 1 may include display elements DE1-7 electrically connected to the first-3 pixel circuit units PC1-3 and display elements DE1-8 electrically connected to the first-4 pixel circuit units PC1-4. In a plan view, the first-7 display elements DE1-7 may at least partially overlap with the first gate driving circuit unit GDC1, and the first-8 display elements DE1-8 may at least partially overlap with the second gate driving circuit unit GDC2.

[0199] In an embodiment, such as Figure 14 As shown, the first-to-third pixel circuit units PC1-3 can be arranged to be closer to the outside of the substrate 100 than the first gate driving circuit unit GDC1 in the second direction (i.e., the x-direction). The first-to-fourth pixel circuit units PC1-4 can be arranged to be closer to the outside of the substrate 100 than the second gate driving circuit unit GDC2 in the second direction (i.e., the x-direction). The first-to-third pixel circuit units PC1-3 and the first-to-fourth pixel circuit units PC1-4 can be arranged side by side in the y-direction (i.e., the first direction).

[0200] As another example, such as Figure 15 As illustrated, the first-3 pixel circuit units PC1-3 and the first-4 pixel circuit units PC1-4 may not be arranged side-by-side in the y-direction. The first-3 pixel circuit unit PC1-3 may be positioned closer to the outside of the substrate 100 in the second direction (i.e., the x-direction) than the first gate driving circuit unit GDC1, but the first-4 pixel circuit unit PC1-4 may not be positioned closer to the outside of the substrate 100 in the second direction (i.e., the x-direction) than the second gate driving circuit unit GDC2. The second gate driving circuit unit GDC2 may be positioned closer to the outside of the substrate 100 than the first-4 pixel circuit units PC1-4. The first-4 pixel circuit units PC1-4 may be positioned closer to the second region AR2 of the substrate 100 in the second direction (i.e., the x-direction) than the second gate driving circuit unit GDC2.

[0201] In the display device 1 according to the embodiment, a plurality of first pixels PX1 can be arranged in a first region AR1 to correspond to the peripheral region of the substrate 100. As a result, the area for displaying an image can be increased from a second region AR2 in which a plurality of second pixels PX2 are arranged to a first region AR1 in which a plurality of first pixels PX1 are arranged.

[0202] So far, only display devices have been described in general, but the embodiments are not limited thereto. For example, it can be said that methods for manufacturing display devices also fall within the scope of this disclosure for manufacturing such display devices.

[0203] Based on the embodiments described above, a display device in which the non-display area is reduced can be realized. The scope of the embodiments is not limited by these effects.

[0204] It should be understood that the embodiments described herein are to be considered in a descriptive sense and are not intended for limiting purposes. The description of features or aspects within each embodiment should typically be considered as other similar features or aspects that may be used in other embodiments. Although one or more embodiments have been described with reference to the accompanying drawings, those skilled in the art will understand that various changes in form and detail may be made in one or more embodiments without departing from the spirit and scope as defined by the appended claims.

Claims

1. A display device, comprising: The substrate includes a first region and a second region surrounded by the first region; The first gate driving circuit unit and the second gate driving circuit unit are arranged adjacent to each other and spaced apart from each other in the first region, and both the first gate driving circuit unit and the second gate driving circuit unit are arranged on one side of the substrate in a plan view. The first-1 pixel circuit unit includes at least one transistor and is arranged in the first region, between the first gate driving circuit unit and the second gate driving circuit unit; as well as The first-1 display element is arranged in the first region and is electrically connected to the first-1 pixel circuit unit.

2. The display device according to claim 1, wherein, The first-1 display element at least partially overlaps with the first gate drive circuit unit in the plan view.

3. The display device according to claim 1, further comprising: The second pixel circuit unit is arranged in the second region; A second display element is disposed in the second region and electrically connected to the second pixel circuit unit; as well as Data lines are arranged on the substrate and extend in a first direction. The sum of the length of the first gate driving circuit unit in the first direction and the length of the first-1 pixel circuit unit in the first direction is less than or equal to the length of the second pixel circuit unit in the first direction.

4. The display device according to claim 1, further comprising: A first gate line is connected to the first gate drive circuit unit and extends in the first region; as well as The second gate line is connected to the first gate drive circuit unit and extends in the second region.

5. The display device according to claim 1, further comprising: The first and second display elements are arranged in the first region and electrically connected to the first and first pixel circuit units. The first-1 display element at least partially overlaps with the first gate drive circuit unit in the plan view, and The first and second display elements at least partially overlap with the second gate drive circuit unit in the plan view.

6. The display device according to claim 1, further comprising: The first and second display elements are arranged in the first region and electrically connected to the first and first pixel circuit units. The first-1 display element at least partially overlaps with the first gate drive circuit unit in the plan view, and The first-2 display elements at least partially overlap with the first-1 pixel circuit unit in the plan view.

7. The display device according to claim 1, further comprising: The first-second pixel circuit unit is arranged between the first-first pixel circuit unit and the second gate driving circuit unit; as well as The first to third display elements are electrically connected to the first to second pixel circuit units. The first-1 display element overlaps at least partially with the first gate driving circuit unit in the plan view, and the first-3 display elements overlap at least partially with the second gate driving circuit unit in the plan view.

8. The display device according to claim 7, further comprising: A voltage line is arranged between the first-1 pixel circuit unit and the first-2 pixel circuit unit. The voltage line is connected to each of the first-1 pixel circuit unit and the first-2 pixel circuit unit.

9. A display device, comprising: The substrate includes a first region and a second region surrounded by the first region; A first gate drive circuit unit is arranged in the first region; The first-1 pixel circuit unit includes at least one transistor, is arranged in the first region and is closer to the outside of the substrate in the second direction than the first gate drive circuit unit; as well as A first-1 display element is arranged in the first region and electrically connected to the first-1 pixel circuit unit, wherein the first-1 display element at least partially overlaps with the first gate drive circuit unit in a plan view.

10. The display device according to claim 9, further comprising: The second gate drive circuit unit is arranged in the first region; The first and second pixel circuit units are arranged in the first region and are closer to the second region than the second gate driving circuit unit; as well as The first and second display elements are arranged in the first region and are electrically connected to the first and second pixel circuit units.

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