R-SpiNNaker System

Abstract

An R-SpiNNaker system is provided. The R-SpiNNaker system provided includes a plurality of chips, one or more of which include a digital router, an analog signal router, and one or more network ports or point-to-point ports; the network port or point-to-point port of a first chip among the plurality of chips is coupled to the network port or point-to-point port of a second chip among the plurality of chips; the digital router of the first chip receives a data packet through the network port or point-to-point port of the chip where the digital router is located; and one or more switches of the analog signal router of the first chip are set according to data of a data packet carrying configuration information or programming information of the analog signal router.

Description

Technical Field

[0001] The present application relates to an R-SpiNNaker system, which includes multiple R-SpiNNaker chips, in which a distributed spiking neural network (SNN) is constructed and used for distributed capacitance measurement and object perception. Background Art

[0002] The original intention of the SpiNNaker project led by Professor Steve B. Furber of the University of Manchester (see "Overview of the SpiNNaker System architecture" in IEEE-Journals & Magazines Volume 62, Issue 12, Dec. 2013) was to try to understand and simulate how the human brain represents and processes information. SpiNNaker attempts to simulate the brain behavior of mammals, and does not involve simulating the sensory behavior of mammals. Therefore, SpiNNaker is a massively parallel multi-core pure digital computing system. It can contain up to 1,036,800 ARM9 cores and 7Tbytes of RAM, distributed in 57K nodes (chips) throughout the system, each node contains 18 cores, and can simulate the behavior of 1 billion neurons.

[0003] Figure 1A This is a schematic diagram of the SpiNNaker chip architecture.

[0004] The central idea of ​​SpiNNaker is that all computational information is represented by AER (Address Event Representation). The basic principle of AER has been well demonstrated in brain neuroscience, that is, when a neuron triggers a pulse, it is a purely asynchronous event. All information only needs to include the time when the pulse was generated and the identity address of the neuron that sent the pulse. In the SpiNNaker system, each node (chip) has its own independent clock, and the neuron that receives information only needs to know the source address of the received pulse and the relative time interval between the two pulses. Therefore, in the AER system, when a neuron sends a pulse, it only needs to pass its identity address, and the relative time interval information of the pulse generation is calculated by the node where the receiving neuron is located. Since SpiNNaker needs to simulate 1 billion neurons, it requires 4 bytes of 32-bit address space. The key to realizing the SpiNNaker idea is to set up an on-chip router for each node (chip), and AER information communication is implemented by multicast routing through the on-chip router. Each on-chip router has 24 routing channels, 18 of which are used for information communication between the 18 cores within the chip, and the remaining 6 are used for inter-chip communication. Since SpiNNaker's goal is to use 57,000 18-core chip clusters to form a million-core supercomputer to simulate human brain activity, its 6 inter-chip routing physical channels use 7-wire high-speed asynchronous links suitable for short-distance communication. Nodes are exchanged by data packets carrying AER information, and the data packets carrying AER information are called AER packets.

[0005] Capacitance-based sensors are widely used. Similar to ADC (Analog Digital Converter), CDC (Capacitance Digital Converter) measures capacitance and converts it into digital output.

[0006] Figure 1B A schematic diagram of a capacitance measurement unit for measuring capacitance using a CDC is shown. The capacitance measurement unit includes a CDC, a capacitor plate, and a connecting wire. The connecting wire connects the capacitor plate to the CDC so that the CDC can apply excitation to the capacitor plate or receive a response to measure capacitance.

[0007] The CDC includes an excitation signal line port (AEC) and a mutual capacitance input signal line port (ACC). Optionally, the CDC also includes a self-capacitance signal line port (SCA), an active shielding signal line port (SHD) and / or a synchronous clock port (CLK). EXC represents an excitation source, such as a square wave signal source.

[0008] In one working mode, the two plates of the measured capacitor (Cm) are respectively connected to the excitation signal line port (AEC) and the mutual capacitance input signal line port (ACC) to form a mutual capacitance measurement loop. The excitation source EXC is connected to the excitation signal line port (AEC), and the CDC applies an excitation signal to the plate of the capacitor (Cm) through its excitation signal line port (AEC), and collects the response to the excitation signal obtained from the plate of the capacitor (Cm) through its mutual capacitance input signal line port (ACC), and measures the capacitance value of the capacitor (Cm) based on the response. Since both plates of the capacitor (Cm) are connected to the CDC, the capacitor (Cm) is called a mutual capacitor.

[0009] In another working mode, one plate of the measured capacitor (Cs) is connected to the self-capacitance signal line port (SCA), and the earth is used as the other plate of the measured capacitor (Cs), and a self-capacitance measurement loop is formed through the ground terminal (AGND) of the CDC. The capacitor (Cs) is called self-capacitance. The excitation source EXC is connected to the self-capacitance signal line port (SCA), and the CDC applies excitation to the capacitor (Cs) through the self-capacitance signal line port (SCA) and obtains a response to measure its capacitance value.

[0010] CDC can apply a variety of capacitance measurement principles. As an example, for mutual capacitance (Cm), CDC charges the capacitor (Cm) through its excitation signal line port (AEC), obtains the voltage value of the capacitor (Cm) after charging through the mutual capacitance input signal line port (ACC), and connects to the Σ-Δ modulator, and outputs a digital value representing the voltage value of the capacitor (Cm) to be measured after low-pass filtering. As another example, the excitation signal source (denoted as EXC) inside the CDC is dynamically connected to the self-capacitance signal line port (SCA), and the connection from the self-capacitance signal line port (SCA) to the Σ-Δ modulator in the CDC is cut off to charge the self-capacitance (Cs), and at the next moment, the excitation signal source (EXC) is disconnected from the self-capacitance signal line port (SCA), and the self-capacitance signal line port (SCA) is turned on with the Σ-Δ modulator to convert the voltage value of the capacitor (Cs) into a digital value representing its capacitance value.

[0011] In some cases, the self-capacitance signal line port (SCA) of the CDC is replaced by the excitation signal line port (AEC) or the mutual capacitance input signal line port (ACC), so that the CDC does not provide an independent self-capacitance signal line port (SCA). In order to replace the self-capacitance signal line port (SCA) with the excitation signal line port (AEC) or the mutual capacitance input signal line port (ACC), a switch is set inside the CDC. When the excitation signal line port (AEC) and the mutual capacitance input signal line port (ACC) measure mutual capacitance, the excitation signal line port (AEC) and the mutual capacitance input signal line port (ACC) are disconnected from the circuit for measuring self-capacitance; and when the excitation signal line port (AEC) or the mutual capacitance input signal line port (ACC) is used to replace the self-capacitance signal line port (SCA) to measure self-capacitance, the circuit for measuring self-capacitance (including the excitation source EXC) is connected to the excitation signal line port (AEC) or the mutual capacitance input signal line port (ACC), and the excitation signal line port (AEC) and the mutual capacitance input signal line port (ACC) are disconnected from the circuit for measuring mutual capacitance.

[0012] In some other cases, the CDC includes an active shielding signal line port (SHD). For example, inside the CDC, the excitation signal provided to the excitation signal line port (AEC) is provided to the active shielding signal line port (SHD) through a follower. Thus, the output signal of the active shielding signal line port (SHD) follows the output of the excitation signal line port (AEC). The active shielding signal line port (SHD) is used to couple the shielding electrode, and the shielding electrode is adjacent to, covers or wraps the wire connecting the excitation signal line port (AEC) and the capacitor plate, so that the signal transmitted on the wire connecting the excitation signal line port (AEC) and the capacitor plate has the same amplitude as the signal transmitted by the active shielding signal line port (SHD) and has a greater driving capability and a lower internal impedance. The shielding electrode can reduce the parasitic capacitance interference generated by the leads connecting the capacitor plates, avoid excessive reference capacitance values, and reduce the resolution of capacitance measurement.

[0013] Still as an example, inside the CDC, the active shielding signal line port (SHD) is connected to the self-capacitance signal line port (SCA) through a follower, so that the output signal of the active shielding signal line port (SHD) follows the signal output by the self-capacitance signal line port (SCA). The active shielding signal provided by the active shielding signal line port (SHD) is used to couple the shielding electrode. The shielding electrode is adjacent to, covers or wraps the wire connecting the self-capacitance signal line port (SCA) and the capacitor plate, the electrode and the ground, or the electrode and the surrounding conductor, so that the signal transmitted on the wire connecting the self-capacitance signal line port (SCA) and the capacitor plate has the same amplitude as the signal transmitted by the active shielding signal line port (SHD) and has a greater driving capability and lower internal impedance. The shielding electrode reduces the parasitic capacitance interference generated by the leads connecting the capacitor plates and around the plates, avoiding or reducing the impact on the resolution of the capacitance measurement caused by the excessive reference capacitance value.

[0014] Optionally, the CDC also includes a synchronous clock port (CLK). In one example, the synchronous clock port (CLK) provides a clock signal to the CDC as an input port. The clock signal provided from the CDC port is used to indicate the timing of the switch switching within the CDC to achieve the measurement of mutual capacitance and / or self-capacitance through multiple stages. In another example, the synchronous clock port (CLK) provides a clock signal to the outside as an output port of the CDC. The CDC synchronizes its own working timing with other circuits by outputting a clock signal to the outside, for example, so that it can simultaneously implement the measurement process with one or more other CDCs. Summary of the invention

[0015] In contact and / or contactless touch applications such as capacitive robot electronic skin, geographic electronic skin, capacitive tomography, and various electrical appliances such as elevator buttons, nodes carrying capacitance measurement units or their components are required. In addition to measuring capacitance, in order to obtain contact and / or contactless "perception" capabilities, nodes are also required to have computing capabilities to comprehensively utilize the measured physical quantities and obtain "perception" results of the external world. In order to facilitate industrial manufacturing and deployment in IoT scenarios, it is also hoped that the nodes provided are easy to mass produce and deploy on site. Multiple nodes are each set at a specified position in space to measure and perceive the existence, movement, and changes of materials and objects on the surface, nearby, and inside the space.

[0016] In order to achieve the above-mentioned purpose, an R-SpiNNaker chip is provided according to an embodiment of the present application. The R-SpiNNaker chip is a hybrid analog-digital chip. The SpiNNaker chip architecture is used for reference in the digital part to build an SNN system suitable for contact and / or non-contact "perception". An analog quantity sensor is provided in the analog part, and a trigger pulse (also referred to as "pulse") for the neuron of the SNN is generated according to the measured analog quantity and provided to the SNN for "perception" processing.

[0017] The network system composed of R-SpiNNaker chips is called R-SpiNNaker system. The original intention of the design of R-SpiNNaker system is to solve the modular analog-to-digital conversion, transmission, and calculation of tactile characteristic signals of large-area electronic skin simulated tactile signals. For general electronic skins such as resistive or piezoelectric, only the analog signal problem of contact tactile needs to be considered, but for some electronic skins such as capacitive, it is necessary to consider the problem of contact tactile and non-contact tactile analog signals at the same time. Contact tactile mainly realizes single-point 3D force perception and multi-point collaborative shape, surface texture, softness and hardness perception, while non-contact tactile can realize proximity perception, material perception and structure perception.

[0018] An important technical reason why the development of machine touch lags far behind that of machine vision is that machine vision can use general-purpose CPU or GPU chips for centralized signal processing, while in machine touch scenarios, the sensor array needs to be spread all over the robot's electronic skin. Due to the crosstalk caused by the large number of leads and long-line transmission of a large number of weak analog signals, it is almost impossible to use general-purpose chips for centralized signal processing.

[0019] The most reasonable method is to use a dedicated tactile chip to convert analog signals into digital signals and perform distributed signal processing. In contrast to centralized signal processing chips that require CPUs or GPUs to have strong computing power, a single tactile chip core only needs limited computing power, but has strong network communication capabilities, and can form a powerful neural computing network with multiple tactile chips distributed on the electronic skin.

[0020] The industrial production of large-area electronic skin requires that the nodes of the electronic skin must be modular, standardized and spliced. Large-area electronic skin is made up of standardized electronic skin nodes. The splicing between nodes includes physical splicing, analog signal splicing and digital neural network splicing. The focus of the R-SpiNNaker system design is to achieve dynamic splicing of analog signals and digital neural networks. The splicing problems that the R-SpiNNaker system needs to solve include the connection problems of analog and digital signals between chips.

[0021] The R-SpiNNaker node needs to support time-sharing capacitance measurement on several to dozens of capacitance channels. The capacitance resolution reaches the femtofarad level (1F = 1e15 ff), which requires integrating CDC in the node and enabling CDC to measure capacitance on multiple capacitance channels in time. It is also necessary to solve the interference problem between multiple channels and reduce the chip area and cost.

[0022] Humans do not have the ability of non-contact touch, but machine touch can have the function of non-contact touch. The non-contact touch of capacitive tactile sensors can achieve the following two functions: sensing the approach, movement and material of external objects, and sensing the internal structure of the contacted objects.

[0023] By changing the capacitance of the electric field at different spatial positions, the speed of the object approaching and the classification of its material can be determined. Based on the principle that the capacitance value is proportional to the electrode area, the larger the area of ​​the capacitor plate, the farther the capacitive sensor can detect. Therefore, the R-SpiNNaker node or R-SpiNNaker system needs to be able to change the position and / or area of ​​the capacitor plate to sense the position change, movement and / or material of the object relative to the capacitor plate.

[0024] The internal structure of the object is analyzed and perceived through electrical capacitance tomography (ECT).

[0025] Based on the perception results, we also hope to perform corresponding actions. We also hope that the execution is distributed, and one or more nodes can make corresponding actions based on their own decisions. For example, when the robot touches a hot or sharp object, or accidentally touches the human body, it needs to retract its hand immediately to avoid it.

[0026] To meet one or more of the above requirements, an R-SpiNNaker chip and an R-SpiNNaker system are provided according to an embodiment of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0028] Figure 1A A schematic diagram of the SpiNNaker chip architecture is shown;

[0029] Figure 1B A schematic diagram of a capacitance measurement unit for measuring capacitance using CDC is shown;

[0030] Figure 2A schematic diagram of the R-SpiNNaker chip architecture according to an embodiment of the present application is shown;

[0031] Figure 3 A schematic diagram of the R-SpiNNaker chip architecture according to another embodiment of the present application is shown;

[0032] Figure 4A A schematic diagram of an R-SpiNNaker system according to an embodiment of the present application is shown;

[0033] Figure 4B A schematic diagram of an R-SpiNNaker system according to another embodiment of the present application is shown;

[0034] Figure 4C A schematic diagram of an R-SpiNNaker system according to another embodiment of the present application is shown;

[0035] Figure 5A A block diagram of an analog signal router according to an embodiment of the present application is shown;

[0036] Figure 5B A block diagram of an analog signal router according to another embodiment of the present application is shown;

[0037] Figure 5C A block diagram of an analog signal router according to another embodiment of the present application is shown;

[0038] Fig. 6A A block diagram of an analog signal router according to another embodiment of the present application is shown;

[0039] Figure 6B A block diagram of an analog signal router according to another embodiment of the present application is shown;

[0040] Figure 6C A block diagram of an analog signal router according to another embodiment of the present application is shown;

[0041] Fig. 7A A schematic diagram of a capacitor channel according to an embodiment of the present application is shown;

[0042] Figure 7B A schematic diagram of a capacitor channel according to another embodiment of the present application is shown;

[0043] Fig. 8A A block diagram of an analog signal router according to another embodiment of the present application is shown;

[0044] Figure 8B A block diagram of an analog signal router according to another embodiment of the present application is shown;

[0045] Fig. 9The R-SpiNNaker system according to an embodiment of the present application is demonstrated;

[0046] Fig.10 An R-SpiNNaker system according to another embodiment of the present application is shown;

[0047] Fig.11 An R-SpiNNaker system according to another embodiment of the present application is shown;

[0048] Fig. 12A A schematic diagram of the R-SpiNNaker chip architecture according to another embodiment of the present application is shown;

[0049] Fig. 12B A schematic diagram of the R-SpiNNaker chip architecture according to another embodiment of the present application is shown;

[0050] Fig.13A A schematic diagram of constructing an SNN according to an SNN unit of an embodiment of the present application is shown;

[0051] Fig. 13B A schematic diagram of constructing an SNN according to an SNN unit of another embodiment of the present application is shown;

[0052] Fig.14 A schematic diagram of the R-SpiNNaker chip architecture according to another embodiment of the present application is shown;

[0053] Fig.15 An R-SpiNNaker system according to another embodiment of the present application is shown;

[0054] Fig.16A A schematic diagram showing an SNN constructed in the R-SpiNNaker system according to an embodiment of the present application; and

[0055] Fig. 16B A schematic diagram of an SNN constructed in the R-SpiNNaker system according to another embodiment of the present application is shown. DETAILED DESCRIPTION

[0056] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0057] Figure 2 A schematic diagram of the R-SpiNNaker chip architecture according to an embodiment of the present application is shown.

[0058] Figure 2 The R-SpiNNaker chip on display includes a computing unit, a digital router and an SNN (spiking neural network) unit.

[0059] The computing unit generates an AER packet and provides it to a digital router, which then provides the AER packet to one or more neurons in the SNN. The computing unit is, for example, a CPU core or a hardware circuit. The computing unit generates an AER packet according to specified rules, for example, based on collected external data, sensor measurements, time, and results generated by other calculations. Optionally, the AER packet carries the address of the computing unit that generated the AER packet or the node to which the computing unit belongs. Still optionally or further, the computing unit generates an AER packet at a specified time or according to specified rules, for example, immediately generating an AER packet in response to receiving collected external data, or triggering the generation of the AER packet by the size of the accumulated value of the external data exceeding a threshold.

[0060] Optionally, the computing unit includes an activation function unit and an encoder. The activation function unit implements the activation function of the SNN neuron, the measured value of the analog quantity is used as the input of the activation function unit, and the output of the activation function unit represents the pulse output by the SNN neuron. The encoder encodes the pulse into an AER packet and provides it to the digital router.

[0061] The R-SpiNNaker chip also includes a point-to-point port or a network port. For the purpose of clarity, the port connected to a shared media network such as Ethernet is referred to as a network port, and the port connected to a point-to-point link such as I2C is referred to as a point-to-point port. In deployment, the use of point-to-point ports helps to reduce the cost of the R-SpiNNaker chip compared to the use of network ports. The implementation method of using point-to-point ports to connect adjacent R-SpiNNaker nodes and form an R-SpiNNaker system will be introduced later. Optionally, the digital routers of the R-SpiNNaker chip can communicate wirelessly (for example, via 5G's DTD (Device-To-Device), Bluetooth, etc.).

[0062] The digital router of the R-SpiNNaker node exchanges AER packets with other R-SpiNNaker nodes through point-to-point ports or network ports. The digital router receives AER packets from the computing unit but does not send AER packets to the computing unit. The digital router receives AER packets from the SNN unit and also sends AER packets to the SNN unit.

[0063] In one embodiment, the computing unit is directly connected to the digital router without passing through the on-chip bus, thereby further reducing the cost of the R-SpiNNaker chip. The SNN unit is also directly connected to the digital router. The digital router is directly connected to the point-to-point port or the network port. Optionally, the computing unit, the digital router and the SNN unit of R-SpiNNaker are connected to each other via an on-chip bus. The computing unit and the SNN unit are not directly connected to the point-to-point port or the network port, but only communicate with other R-SpiNNaker nodes by exchanging data packets through the digital router.

[0064] Optionally, the digital router unicasts, multicasts or broadcasts the AER packet. For example, the digital router determines the target of forwarding the AER packet based on the address carried by the received AER packet or the source of the received AER packet. The target of the AER packet forwarding is one or more SNN neurons, and / or a point-to-point port or a network port.

[0065] The SNN unit includes multiple SNN neurons. The SNN neuron receives neural pulses (pulses for short) and outputs pulses. AER packets represent pulses. The SNN neuron receives an AER packet, which represents the receipt of a pulse, and the SNN neuron outputs an AER packet, which represents the output of a pulse. The SNN neuron receives an AER packet from a digital router and outputs an AER packet to a digital router. The computational model of the SNN neuron belongs to the prior art, and the SNN neuron model that may appear in the future is also utilized according to the embodiments of the present application. For example, the SNN unit is a CPU core, and the SNN neuron is implemented by a program or thread running on the CPU core.

[0066] Multiple SNN neurons constitute SNN (Spiking Neural Network). In this specification, compared with SNN unit, SNN has a specified topological structure and meaningful functions, and each SNN neuron constituting SNN has specified parameters. SNN is created. The SNN in the SNN unit is created or adjusted by configuring or programming a digital router, for example, updating the routing table of the digital router. Thus, the SNN neurons of the SNN unit can be used to construct different SNNs at different times. Multiple SNNs can also exist simultaneously in the SNN unit.

[0067] For a specified application or processing function, the topology of the SNN and the number of SNN neurons are known. For example, the specified function is to identify one of multiple keys approached or touched by a user's finger from the capacitance value collected by the capacitive sensor. For another example, the specified function is to detect abnormal objects in space.

[0068] The SNN neurons in the SNN have a unidirectional connection relationship. The SNN neurons in the SNN receive AER packets sent by zero, one or more SNN neurons, and output AER packets to one SNN neuron. According to an embodiment of the present application, the connection relationship of the neurons of the SNN is reflected by the routing table for AER packets maintained by the digital router. The routing table of the digital router records one or more destination SNN neurons, or point-to-point ports or network ports to which the addresses in the received AER packets are to be routed.

[0069] Optionally, the SNN includes input layer neurons, middle layer neurons and output layer neurons. The input layer neurons receive input to the SNN, and the output of the input layer neurons is provided to the middle layer neurons. The output of the middle layer neurons is provided to the middle layer neurons or the output layer neurons. The output of the output layer neurons serves as the output of the SNN in which it is located. It can be understood that according to an embodiment of the present application, the input and output of the SNN neurons are both processed by a digital router. Physically, the output of the SNN neuron is an AER packet provided to the digital router, and the digital router determines the destination neuron to which it is to be forwarded based on the address of the SNN neuron that generates the AER packet carried in the AER packet. The SNN neuron determines the timing of outputting the AER packet based on its own parameters based on the AER packets it receives from one or more SNN neurons.

[0070] Optionally, the R-SpiNNaker chip further includes a ground port.

[0071] Figure 2 The R-SpiNNaker chip on display is a pure digital chip and may not include analog circuits such as CDC. Compared with mixed analog-digital circuits, pure digital capacitors are cheaper to manufacture and less sensitive to noise or interference.

[0072] Figure 3 A schematic diagram of the R-SpiNNaker chip architecture according to another embodiment of the present application is shown.

[0073] Figure 3 The R-SpiNNaker chip on display Figure 2 The R-SpiNNaker chip of the embodiment also integrates CDC and ADC (Analog Digital Converter). Therefore, a single R-SpiNNaker chip not only has the ability to build an SNN network and perceive, but also can collect and measure external analog quantities. Although the cost is increased, the integration of the chip is improved, and it has richer functions, and can independently complete the measurement and perception of analog signals.

[0074] See also Figure 3,The CDC and ADC of the R-SpiNNaker chip are respectively connected to a computing unit, and the respective inputs of the CDC and ADC are provided to the computing unit as inputs, and the computing unit generates an AER packet representing the neural pulse based on the measurement values ​​output by the CDC and / or ADC.

[0075] Figure 3 In the embodiment, the CDC includes an excitation signal line port (AEC) and a mutual capacitance input signal line port (ACC). The R-SpiNNaker chip also includes a capacitance port. The excitation signal line port (AEC) and the mutual capacitance input signal line port (ACC) are respectively coupled to the capacitance port of the R-SpiNNaker chip. Thus, the CDC measures the self-capacitance and / or mutual capacitance through the capacitance port. The ADC is used to convert analog signals such as voltage and current into digital quantities and provide them to the calculation unit. Optionally, the R-SpiNNaker chip also includes a port (not shown) for providing an analog signal to the ADC. Still optionally, the ADC is connected to the capacitance port to obtain an analog signal.

[0076] CDC / ADC measures capacitance or analog signals at any time, periodically or in response to an operation command and outputs them. SNN senses the characteristics of the measured object from the measured value, for example, recognizing that a finger intentionally approaches a button rather than an accidental approach of a bag / clothing, etc. Using existing technology or future technology, SNN can be trained or configured to provide the ability to sense the measured object.

[0077] Figure 4A A schematic diagram of an R-SpiNNaker system according to an embodiment of the present application is shown.

[0078] Figure 4A In the R-SpiNNaker system, there are two components: Figure 3 The R-SpiNNaker chips (410 and 420) are shown. R-SpiNNaker chip 410 is connected to the digital router of R-SpiNNaker chip 420 (via a network port or a point-to-point port) and exchanges AER packets. Thus, the AER packets (pulses) emitted by the SNN neurons of the SNN unit of R-SpiNNaker chip 410 can be forwarded by the digital routers of the two R-SpiNNaker chips (410 and 420) to the SNN neurons of the SNN unit of R-SpiNNaker chip 420. Thus, the SNN can be constructed using the SNN neurons of the two R-SpiNNaker chips. And multiple SNNs can exist simultaneously in the R-SpiNNaker chip composed of two R-SpiNNaker chips, and these SNNs can sense / process the analog quantities measured by the ADC / CDC individually and / or collaboratively.

[0079] In the digital router of the R-SpiNNaker chip, the AER packet is forwarded to the network port or point-to-point port by configuring the routing table to forward the AER packet between two R-SpiNNaker chips. The routing table also records the destination (e.g., one or more specified SNN neurons) to which the AER packet received from the network port or point-to-point port is forwarded. To support multicast or broadcast, multiple forwarding targets can be recorded in the routing table.

[0080] Figure 4B A schematic diagram of an R-SpiNNaker system according to yet another embodiment of the present application is shown.

[0081] Figure 4B In the embodiment, the R-SpiNNaker system includes two R-SpiNNaker chips (430 and 450). The R-SpiNNaker chip 430 is connected to the digital router of the R-SpiNNaker chip 450 (via a network port or a point-to-point port) and exchanges AER packets.

[0082] R-SpiNNaker chip 430 and R-SpiNNaker chip 450 each further include an analog signal router and a plurality of capacitor ports. The capacitor ports are connected to capacitor plates outside the R-SpiNNaker chip. The analog signal router connects the capacitor ports to the excitation signal line port (AEC) and the mutual capacitance input signal line port (ACC) of the CDC. Thus, the CDC can measure capacitance using any combination of capacitor plates connected to the plurality of capacitor ports.

[0083] The analog signal router is configured or programmed to form different capacitance channels. The capacitance channels couple the CDC with one or more capacitance plates that form the capacitance to be measured. Optionally, the analog signal router is also coupled to the ground port of the R-SpiNNaker chip, thereby configurably or programmably coupling the ground port to the CDC, and / or other components of the R-SpiNNaker chip.

[0084] exist Figure 4BIn an embodiment, the digital router of the R-SpiNNaker chip is also coupled to the analog signal router, and the digital router forwards a data packet carrying the configuration information or programming information of the analog signal router to the analog signal router, and the analog signal router obtains the configuration information or programming information from the data packet, and sets the opening or closing of one or more switches of the analog signal router to form a capacitor channel. Thus, the digital router exchanges at least two types of data packets, AER packets and data packets carrying the configuration information or programming information of the analog signal router. The data packet carrying the configuration information or programming information of the analog signal router includes, for example, an address indicating the destination R-SpiNNaker chip, so that the digital router forwards such data packets according to the address. One or both of the R-SpiNNaker chip 430 and the R-SpiNNaker chip 450 serve as configuration chips to provide data packets carrying the configuration information or programming information of the analog signal router to the analog signal routers of the two chips. Optionally, such data packets are provided to the R-SpiNNaker chips 430 and 450 through an external device. One or both of R-SpiNNaker chip 430 and R-SpiNNaker chip 450 serve as configuration chips to provide data packets carrying configuration information or programming information of the analog signal routers to the analog signal routers of the two chips. Optionally, such data packets are provided to R-SpiNNaker chips 430 and 450 by an external device.

[0085] The specific implementation of the analog signal router will be introduced below.

[0086] Optionally, R-SpiNNaker chip 430 and R-SpiNNaker chip 450 each further include an analog signal port. Figure 4B In the figure, the ports (432, 434, 452 and 454) connected by dotted lines between R-SpiNNaker chip 430 and R-SpiNNaker chip 450 are analog signal ports. The analog signal ports of R-SpiNNaker chip 430 and R-SpiNNaker chip 450 are connected correspondingly to transmit analog signals between R-SpiNNaker chip 430 and R-SpiNNaker chip 450, so that the CDC of chip 430 can measure capacitance using the capacitor plates of chip 450, and vice versa, the CDC of chip 450 can measure capacitance using the capacitor plates of chip 430.

[0087] Figure 4B In the embodiment of the present invention, R-SpiNNaker chip 430 is the same as R-SpiNNaker chip 450. Optionally, the R-SpiNNaker chips of the R-SpiNNaker system may be the same or different.

[0088] In an optional implementation, the ADC is also connected to the analog signal router and obtains the analog signal to be measured or converted from the analog signal router.

[0089] Figure 4C A schematic diagram of an R-SpiNNaker system according to yet another embodiment of the present application is shown.

[0090] Figure 4C In the R-SpiNNaker system, there are four R-SpiNNaker chips (460, 470, 480 and 490). The four R-SpiNNaker chips are different from each other.

[0091] Each R-SpiNNaker chip of the R-SpiNNaker system includes a digital router and point-to-point ports (462, 464, 466 and 468, 472, 474, 476 and 478, 482, 484, 486 and 488, 492, 494, 496 and 498) to exchange AER packets. The point-to-point port 464 of R-SpiNNaker chip 460 is connected to the point-to-point port 478 of R-SpiNNaker chip 470, the point-to-point port 466 of R-SpiNNaker chip 460 is connected to the point-to-point port 482 of R-SpiNNaker chip 480, the point-to-point port 484 of R-SpiNNaker chip 480 is connected to the point-to-point port 498 of R-SpiNNaker chip 490, and the point-to-point port 476 of R-SpiNNaker chip 470 is connected to the point-to-point port 492 of R-SpiNNaker chip 490, thereby realizing arbitrary forwarding of data packets between digital routers between the various R-SpiNNaker chips of the R-SpiNNaker system.

[0092] In order to facilitate the deployment of the R-SpiNNaker system and the configuration of the routing table of the digital router, the point-to-point ports of the R-SpiNNaker chip have direction attributes (for example, East (E), West (W), South (S) and North (S)). In the routing table, for example, the specified point-to-point port of the east side point-to-point port can be used as the destination address of the configured forwarded data packet. When deployed, the R-SpiNNaker chips in the R-SpiNNaker system are arranged in rows and / or columns. Adjacent R-SpiNNaker chips belonging to the same row are connected to each other through their respective east / west point-to-point ports; adjacent R-SpiNNaker chips belonging to the same column are connected to each other through their respective south / north point-to-point ports. Thus, each R-SpiNNaker chip only includes 4 point-to-point ports, which can realize any connection between the digital routers of each R-SpiNNaker chip of the R-SpiNNaker system. This also reduces the cost of the R-SpiNNaker chip. The cost of the point-to-point port is also significantly lower than that of a network port of a shared medium such as Ethernet.

[0093] Although Figure 4C The R-SpiNNaker system includes 4 R-SpiNNaker chips. It can be understood that the R-SpiNNaker system can include any number of R-SpiNNaker chips to cover different areas of the detection area and provide more SNN units to build SNNs of different scales and different computing capabilities.

[0094] The R-SpiNNaker chip 480 may optionally include a CDC to measure and output the measured capacitance value. The R-SpiNNaker chip 480 may also include a calculation unit to generate an AER packet according to the capacitance value output by the CDC and provide it to the digital router.

[0095] Each of the R-SpiNNaker chips 460, 480, and 490 includes an analog signal router, a capacitor port (not shown), and an analog signal port (not shown). The analog signal router forms a capacitor channel between the R-SpiNNaker chips 460, 480, and 490, so that the CDC of the R-SpiNNaker chip 460 can measure the capacitance using any one or more of the connected capacitor plates of the R-SpiNNaker chips 460, 480, and 490. The digital routers of the R-SpiNNaker chips 460, 480, and 490 forward data packets to the analog signal routers of the respective nodes to configure or program the analog signal routers.

[0096] R-SpiNNaker chips 470 and 490 each include an SNN unit. SNN is constructed by the SNN units of R-SpiNNaker chips 470 and 490 to sense external objects using, for example, the CDC of R-SpiNNaker chip 480.

[0097] Optionally, R-SpiNNaker chip 470 is a pure digital circuit without including an analog signal router and / or CDC, so that R-SpiNNaker chip 470 can have a lower cost.

[0098] Figure 5A A block diagram of an analog signal router according to an embodiment of the present application is shown.

[0099] The analog signal router is used to dynamically establish a capacitance channel between the CDC and the capacitor plate, so that the CDC can use one or more capacitor plates to measure capacitance. The capacitance measured by the CDC may include, for example, one capacitor electrode (self-capacitance) or two capacitor electrodes (mutual capacitance). The analog signal router also makes the capacitor electrode of the measured capacitance consist of one or more capacitor plates.

[0100] Figure 5A In the embodiment, the CDC includes a self-capacitance signal line port (SCA). Accordingly, the analog signal router includes, for example, a self-capacitance signal line ASC (511), a plurality of switches (KAS1-KAS4, also referred to as capacitor port coupling switches), and a plurality of capacitor ports (510, 512, 514, and 516) for connecting capacitor plates. The plurality of capacitor ports may be identical to each other.

[0101] As an example, the capacitor port coupling switch corresponds to the capacitor port one by one, and each capacitor port is connected to the self-capacitance signal line ASC (511) through the corresponding capacitor port coupling switch. Thus, by closing the capacitor port coupling switch (e.g., KAS1), the corresponding capacitor port (510) is coupled to the self-capacitance signal line ASC (511), and then coupled to the self-capacitance signal line port (SCA) of the CDC. It can be understood that the capacitor port to the self-capacitance signal line ASC (511) can be directly connected or indirectly connected via one or more elements and / or leads. The term "coupling" is used to express a variety of connection methods including direct connection and indirect connection, and the present application is not intended to limit its implementation. Thus, the signal applied by the CDC to its self-capacitance signal line port (SCA) is transmitted to the capacitor port (e.g., 510) corresponding to the capacitor port coupling switch (e.g., KAS1), and then acts on the capacitor plate coupled to the capacitor port (510). And optionally, the signal received from the capacitor port (e.g., 510) is also transmitted to the self-capacitance signal line port (SCA) of the CDC through the capacitor port coupling switch (e.g., KAS1) and then the self-capacitance signal line ASC (511). It can be understood that the capacitor plate and the CDC may not be components of the analog signal router according to the embodiment of the present application, but the capacitor plate is externally connected to the capacitor port of the analog signal router, and one or more ports of the CDC (e.g., the self-capacitance signal line port (SCA)) are externally connected to the analog signal router (e.g., through the CDC coupling switch KSC). Thus, the analog signal router is suitable for capacitor plates of various shapes, sizes and / or materials, and CDCs of various specifications.

[0102] Continue to view Figure 5A When multiple switches (e.g., KAS1-KAS4) are closed at the same time, the self-capacitance signal line ASC (511) is connected to multiple capacitor ports (510, 512, 514, and 516), so that the excitation signal provided by the self-capacitance signal line port (SCA) of the CDC is simultaneously provided to the capacitor plates coupled with the above-mentioned multiple capacitor ports (510, 512, 514, and 516). In this way, the capacitor plates coupled to the multiple capacitor ports are spliced ​​to form a capacitor plate with a larger area (or a different shape) as an electrode of the measured capacitance. A larger capacitor plate helps to measure the influence of an object farther away from the capacitor plate on the capacitance formed by the capacitor plate. In a similar manner, by closing a plurality of switches of different numbers, the capacitor plates coupled to different numbers of capacitor ports are spliced ​​to form capacitor plates of different areas (or different shapes).

[0103] According to an embodiment of the present application, the analog signal router is also used for CDC to measure the capacitance formed by the capacitor plates connected to the same or different capacitor ports in time-sharing. Thus, a single CDC forms multiple identical or different capacitance measurement units at different times with the capacitor plates coupled to multiple capacitor ports. For example, at time T1, switch KAS1 is closed, and the other switches (KAS2-KAS4) are all disconnected, and the capacitor plates coupled to the CDC and the capacitor port 510 form a capacitance measurement unit; and at time T2, switch KAS2 is closed, and the other switches (KAS1, KAS3, KAS4) are all disconnected, and the capacitor plates coupled to the CDC and the capacitor port 512 form a capacitance measurement unit. Optionally, at multiple continuous or discontinuous moments, the CDC forms capacitance measurement units with the same or different capacitor plates in sequence.

[0104] In some cases, the CDC measures the self-capacitance through its self-capacitance signal line port (SCA). By coupling the CDC's self-capacitance signal line port (SCA) to, for example, capacitor ports KAS3 and KAS4, the CDC measures the self-capacitance of the capacitor plates formed by the capacitor plates connected to the capacitor ports KAS3 and KAS4, relative to the ground.

[0105] For the purpose of simplicity, all switches (KAE1, KAE2, KAE3, KAE4, and optional KAEC) in the analog signal router are also referred to as an analog switch matrix.

[0106] exist Figure 5A In the example, the CDC includes a single port (self-capacitance signal line port (SCA)), so that the analog signal router only routes analog signals for the CDC through the single self-capacitance signal line ASC (511). Optionally, if the CDC includes an excitation signal line port (AEC), the analog signal router routes analog signals for the CDC through the excitation signal line accordingly. Still optionally or further, the CDC includes a mutual capacitance input signal line port (ACC), and accordingly, the analog signal router routes analog signals for the CDC through the mutual capacitance input signal line.

[0107] Optionally, the analog signal router also includes a ground port for connecting to the ground. The analog signal router also includes, for example, a ground signal line and a ground switch. The ground signal line is connected to the ground port and is also connected to each capacitor port through the ground switch. The ground switch is set one-to-one with the capacitor port, for example. Thus, one or more capacitor ports can be connected to the ground signal line. Thus, by configuring or programming the analog signal router, the capacitor port is connected to the ground port or disconnected. Still optionally, the analog signal router also includes a ground port coupling switch for connecting or disconnecting the ground port with the ground signal line, thereby making the analog signal router configurable or programmable to connect to the ground. The analog signal router optionally also configurably or programmably connects the ground port / ground signal line to, for example, a CDC.

[0108] Figure 5B A block diagram of an analog signal router according to another embodiment of the present application is shown.

[0109] Figure 5B The analog signal router of the embodiment includes an excitation signal line (AE), a mutual capacitance input signal line (AC), an optional self-capacitance signal line (ASC), a plurality of switches (KAE1-KAE5, KAC1-KAC5, KAS1-KAS5, also referred to as capacitor port coupling switches), and a plurality of capacitor ports (510, 512, 514, 516 and 518) for connecting capacitor plates. Figure 5B In the embodiment, a plurality of CDC coupling switches (KAEC, KACC and optional KSC) are further included. The CDC includes an excitation signal line port (AEC), a mutual capacitance input signal line port (ACC) and an optional self-capacitance signal line port (SCA).

[0110] The combination of the excitation signal line (AE), the mutual capacitance input signal line (AC), and the optional self-capacitance signal line (ASC) is called a connection line group. Each connection line in the connection line group (excitation signal line (AE), mutual capacitance input signal line (AC), and optional self-capacitance signal line (ASC)) has the same connection method with the capacitor port and the CDC. Each connection line of the connection line group is connected to the capacitor port through its own capacitor port coupling switch, and is connected to the CDC through the CDC coupling switch.

[0111] The connection lines of the connection line group are connected one-to-one with the ports of the CDC. The number of CDC coupling switches is the same as the number of connection lines of the connection line group, and is also the same as the number of ports of the CDC, so that each CDC coupling switch couples the connection lines of its corresponding connection line group to the corresponding port of the CDC. For example, the excitation signal line (AE) is connected to the excitation signal line port (AEC) through the CDC coupling switch (KAEC), the mutual capacitance input signal line (AC) is connected to the mutual capacitance input signal line port (ACC) through the CDC coupling switch KACC, and the self-capacitance signal line (ASC) is connected to the self-capacitance signal line port (SCA) through the CDC coupling switch KSC. Thus, the connection lines of the connection line group are only connected to the corresponding ports of the CDC, and are not connected to other ports of the CDC. Optionally, in order to adapt to CDCs with different port configurations, the number of connection lines of the connection line group of the analog signal router is not less than the number of ports of the CDC, so that each port of the CDC is connected to one of the connection lines of the connection line group, and two or more ports of the CDC are prevented from being connected to the same connection line.

[0112] Each connection line (excitation signal line (AE), mutual capacitance input signal line (AC) and optional self capacitance signal line (ASC)) of the connection line group is coupled to one of the capacitance ports through a group of capacitance port coupling switches (called sub-switch groups). These sub-switch groups also form part of the analog switch matrix. The number of switches in the sub-switch group is the same as the number of connection lines of the connection line group.

[0113] Figure 5B In the example, the connection line group includes three connection lines, and thus each sub-switch group includes three switches. For example, the capacitor port 510 is coupled to (each connection line of) the connection line group through the sub-switch group (KAE1, KAC1, KAS1), and the capacitor port 512 is coupled to the connection line group through the sub-switch group (KAE2, KAC2, KAS2). Through such a setting, each capacitor port can be connected to any connection line of the connection line group, and thus the capacitor port can be coupled to any port of the CDC (AEC, ACC or SCA).

[0114] According to an embodiment of the present application, among the multiple switches of the sub-switch group, at most only one switch is closed at any time, and the other switches of the sub-switch group are all opened, so that the capacitor port is at most coupled to only one connection line of the connection line group at any time. Thus, each sub-switch group also avoids coupling two or more connection lines of the connection line group. It is allowed that all switches of the sub-switch group are opened at a certain time.

[0115] At a certain moment, it is allowed for multiple sub-switch groups to couple their respective corresponding capacitor ports to one of the connection lines of the connection line group, so as to couple a certain connection line of the connection line group to multiple capacitor ports at the same time. By connecting multiple capacitor ports to the same connection line, these capacitor ports have equal potentials, so as to combine the capacitor plates connected to these capacitor ports into one or a whole capacitor plate. For example, the sub-switch group (KAE1, KAC1 and KAS1, KAC1 is closed) couples the capacitor port 510 to the mutual capacitance input signal line AC, and the sub-switch group (KAE2, KAC2, KAS2, KAC2 is closed) couples the capacitor port 512 to the mutual capacitance input signal line AC, thereby coupling the mutual capacitance input signal line AC to multiple capacitor ports (510 and 512) at this moment, and then simultaneously coupling the capacitor plates corresponding to each of the multiple capacitor ports (510 and 512). Then, the area of ​​the capacitor plate coupled to the mutual capacitance input signal line AC is enlarged or the shape of the capacitor plate is changed.

[0116] according to Figure 5B The analog signal router of the embodiment is also adapted to different working modes of the CDC. When the CDC works in the mode of measuring mutual capacitance, the CDC applies an excitation signal to the measured capacitance through its excitation signal line port (AEC), and obtains the response of the measured capacitance to the excitation signal through its mutual capacitance input signal port (ACC). As an example, one plate of the measured mutual capacitance is connected to the capacitance port 510, and the other plate is connected to the capacitance 512. When the CDC is working and outputs an excitation signal through the excitation signal line port (AEC), the excitation signal line port (AEC) of the CDC is connected to the excitation signal line AE of the connection line group by closing the CDC coupling switch KAEC, and the excitation signal line AE is connected to the capacitor port 510 by closing the switch KAE1 (and opening the switches KAC1 and KAS1), so that the excitation signal output by the excitation signal line port (AEC) of the CDC is applied to the capacitor plate coupled to the capacitor port 510; and the switches KACC and KAC2 are closed at the same time to couple the capacitor port 512 to the mutual capacitance input signal line port (ACC) of the CDC, and the switches KAE2, KAS2 and KSC are opened, so that the CDC receives the response of the capacitor plate coupled to the capacitor port 512 to the aforementioned excitation signal through its mutual capacitance input signal line port (ACC).

[0117] When the CDC is working in the self-capacitance measurement mode, the CDC applies an excitation to the measured capacitance through its self-capacitance signal line port (SCA) and obtains a response. As an example, the capacitor plate of the measured self-capacitance is connected to the capacitor port 516. The capacitor plate connected to the capacitor port 516 forms a self-capacitance Cs with the ground. When the CDC is working, the capacitor port coupling switch KAS4 is closed (the switch KAE4 is disconnected from the switch KAC4), and the switch KSC is closed to connect the self-capacitance signal line port (ASC) of the CDC to the self-capacitance signal line ASC, and then to the capacitor plate of the coupling capacitor port 216.

[0118] In a further optional working mode, the CDC measures the self-capacitance through its self-capacitance signal line port (SCA) while also measuring the mutual capacitance through its excitation signal line port (AEC) and the mutual capacitance input signal line port (ACC). For example, while closing the CDC coupling switches KAEC and KACC, and closing switches KAE1 and KAC2 (disconnecting switches KAC1, KAS1, KAE2 and KAS2), the CDC coupling switch KSC and switch KAS4 are closed (disconnecting switches KAE4 and KAC4), thereby simultaneously measuring the mutual capacitance formed by the capacitor plates connected to the capacitor ports 510 and 512, and the self-capacitance of the capacitor plates connected to the capacitor port 516.

[0119] According to another embodiment of the present application, the CDC includes only an excitation signal line port (AEC) and a mutual capacitance input signal line port (ACC), but does not include a self-capacitance signal line port (SCA), and the function of the self-capacitance signal line port (SCA) is replaced by the excitation signal line port (AEC) or the mutual capacitance input signal line port (ACC). In this case, the connection line group of the analog signal router according to the embodiment of the present application includes an excitation signal line (AE) and a mutual capacitance input signal line (AC), but may not include a self-capacitance signal line (ASC). Accordingly, the analog switch matrix also does not include switches (KAS1-KAS5, and KSC) for connecting the self-capacitance signal line (ASC).

[0120] As another example, by opening or closing a plurality of capacitor port coupling switches of the same connection line of the corresponding connection line group, the area, position and / or shape of the capacitor plate of the capacitance measurement unit formed by the CDC and the capacitor plate are adjusted. For example, a plurality of capacitor port coupling switches (KAE1-KAE5) corresponding to the excitation signal line (AE) are selectively opened and closed (forming a capacitor plate with a given area, position and / or shape), so that the excitation signal line port (AEC) of the CDC forms an excitation path with the capacitor plates coupled to the plurality of capacitor port coupling switches; a plurality of capacitor port coupling switches (KAC1-KAC5) corresponding to the mutual capacitance input signal line (AC) are selectively opened and closed (forming a capacitor plate with a given area, position and / or shape), so that the mutual capacitance input signal line port (ACC) of the CDC forms a response path with the capacitor plates coupled to the plurality of capacitor port coupling switches. Thus, two capacitor plates of a given area are connected to the CDC in this way, so as to form a complete mutual capacitance measurement unit for mutual capacitance measurement. And there are a variety of capacitor plate combinations, corresponding to a variety of mutual capacitance measurement units. By controlling the analog switch matrix in time-sharing mode, different mutual capacitance measurement units can be constructed at different times, and time-sharing mutual capacitance measurements can be performed. When measuring self-capacitance, self-capacitance plates of different areas are formed through different combinations of self-capacitance signal lines (ASC) and switches KAS1-KAS5, etc. These self-capacitance plates are connected to the CDC through the opening and closing of the self-capacitance signal line (ASC) and the CDC coupling switch KSC, thereby forming different self-capacitance measurement units for self-capacitance measurement. By controlling the analog switch matrix in time-sharing mode, different self-capacitance measurement units can be constructed at different times, and time-sharing self-capacitance measurements can be performed.

[0121] As another example, the capacitor unit for the circular touch button includes four sector plates forming a circle, which are respectively connected to capacitor ports 510, 512, 514 and 516, and the capacitor unit also includes the same plate A, which is arranged opposite to the four sector plates, and the plate A is connected to the capacitor port 518. Plate A forms a mutual capacitance (denoted as A1, A2, A3 and A4) with each of the four sector plates. According to the analog signal router of the embodiment of the present application, at different times, CDC is connected to each of the four mutual capacitors (A1, A2, A3 and A4) to measure each mutual capacitance. At another moment, switches KAE1-KAE4 are all closed to connect capacitor ports 510, 512, 514 and 516 to the excitation signal line AE, and the equipotential surface is formed by the excitation signal line to combine the four sector electrodes into an integral plate, and the four sector electrodes of the combination form a mutual capacitance with the plate A, and the mutual capacitance is measured by the CDC. Therefore, through the analog signal router, it is possible to measure multiple capacitances in time-sharing manner using a single CDC and multiple fixed capacitance ports.

[0122] Figure 5C A block diagram of an analog signal router according to another embodiment of the present application is shown.

[0123] As another example, the CDC further includes a synchronous clock signal line port (CLK) and an active shield signal line port (SHD). Figure 5C The analog signal router of the embodiment, Figure 5B Compared to the analog signal router shown, it also includes an active shield signal line (ASH) and a synchronous clock signal line (ACLK).

[0124] Optionally, the active shielding signal line (ASH) is coupled to the capacitor port in the same manner as other connecting lines of the connecting line group, that is, through the switch coupling of the sub-switch group, one capacitor port is only coupled to one connecting line of the connecting line group at the same time, while the active shielding signal line (ASH) can be coupled to multiple capacitor ports at the same time. At this time, the active shielding signal line (ASH) becomes one of the connecting lines of the connecting line group. In the example where the connecting line group includes 4 connecting lines (excitation signal line (AE), mutual capacitance input signal line (AC), self-capacitance signal line (ASC) and active shielding signal line (ASH)), each sub-switch group includes corresponding 4 switches. Figure 5C The example also includes a capacitor port coupling switch (KASH1-KASH4) for coupling the capacitor port with the active shielding signal line (ASH).

[0125] During operation, if the active shielding signal line (ASH) is connected to the shielding electrode (230) through the capacitor port (e.g., 514), and the excitation signal line (AE) is connected to the capacitor plate through the capacitor port (516), the switch (KASH3) and the switch KAE4 are closed simultaneously accordingly, so as to provide the active shielding signal to the shielding electrode (530) while providing the excitation signal to the capacitor plate connected to the capacitor port (516).

[0126] Optionally or further, the analog signal router further includes an active shielding signal port (560), and the active shielding signal line (ASH) is connected to the active shielding signal port (560). The active shielding signal port (560) is dedicated to connecting the active shielding signal line (ASH) and is not connected to other connecting lines of the connecting line group. In this case, the analog switch matrix of the analog signal router may not include switches (KASH1-KASH4). In some cases, the active shielding signal provided by the CDC has a larger amplitude (voltage and / or current) than the excitation signal, and accordingly the active shielding signal line ASH and / or the active shielding signal port (560) are adapted to transmit the active shielding signal. Since the active shielding signal port (560) does not need to be connected to other connecting lines of the connecting line group, the active shielding signal port is only connected to the active shielding signal line (ASH) through a switch (not shown) or is directly connected to the active shielding signal line (ASH) without a switch. During operation, if the active shielding signal line is connected to the shielding electrode (532) via the active shielding signal port (560), and the excitation signal line AE is connected to the capacitor plate via the capacitor port (510), the switch (KAE1) is closed accordingly to provide the excitation signal to the capacitor plate connected to the capacitor port (510) while providing the active shielding signal to the shielding electrode (532).

[0127] Optionally, the CDC does not provide an active shielding signal port, and an analog signal router according to an embodiment of the present application generates an active shielding signal. For this purpose, the analog signal router includes a follower ( Figure 5C (not shown) to apply the excitation signal obtained by the excitation signal line from the CDC to the active shielding signal line (ASH). Still optionally, a switch is also set between the excitation signal line (AE) and the active shielding signal line (ASH) to disconnect or close the connection between the two.

[0128] Optionally, the analog signal router further includes a synchronous clock signal line (ACLK) and a synchronous clock port (562). The synchronous clock port 562 is optionally the same as or different from the capacitor port. The synchronous clock signal line (ACLK) does not belong to the connection line group. An optional switch is included between the synchronous clock signal line (ACLK) and the synchronous clock port (562) to disconnect or close the connection between the two. The synchronous clock signal line (ACLK) is coupled to the synchronous clock signal line port (CLK) of the CDC.

[0129] The CDC coupling switch of the analog signal router also includes a switch KSH and a switch KCL, which are respectively used to connect the active shield signal line (ASH) to the active shield signal port (SHD) of the CDC, and the synchronous clock signal line (ACLK) to the synchronous clock signal line port (CLK) of the CDC.

[0130] In one embodiment, the synchronous clock port (562) receives a synchronous clock signal from outside the analog signal router, and the synchronous clock signal line (ACLK) provides the synchronous clock signal obtained from the synchronous clock port (562) to the synchronous clock signal line port (CLK) of the CDC through the CDC coupling switch KCL. The synchronous clock signal indicates when the CDC starts the capacitance measurement. Optionally, the synchronous clock signal also indicates multiple working stages of the CDC measuring the capacitance.

[0131] Fig. 6A A block diagram of an analog signal router according to another embodiment of the present application is shown.

[0132] exist Fig. 6A In the example of FIG. 1 , the capacitance measuring unit includes a plurality of CDCs (CDC1 and CDC2 are shown). The plurality of CDCs can work simultaneously to measure a plurality of capacitances simultaneously.

[0133] See also Fig. 6A , the connection line group of the analog signal router includes an excitation signal line (AE), a mutual capacitance input signal line (AC) and a self-capacitance signal line (ASC). CDC1 and CDC2 are connected to the connection line group through their respective CDC coupling switches. As an example, the CDC coupling switches (KAEC1 and KACC1) corresponding to CDC1 are closed (and switches KAE1 and KAC2 are closed), so that CDC1 measures the mutual capacitance formed by the capacitor plates connected to the same capacitor ports (610 and 612) through the capacitor ports (610 and 612). At the same time or different time when CDC1 measures the mutual capacitance, the CDC coupling switch (KSC2) corresponding to CDC2 is closed (and switch KAS4 is closed), so that CDC2 measures the self-capacitance through the capacitor port (614).

[0134] exist Fig. 6A In the illustrated embodiment, each connection line of the connection line group is shared by CDC1 and CDC2. CDC1 and CDC2 cannot use the same connection line at the same time to avoid conflicts. Therefore, if the CDC coupling switch KAEC1 is closed, the switch KAEC2 should be opened to avoid connecting the connection line AE to the excitation signal line ports (AEC) of CDC1 and CDC2 at the same time. CDC1 and CDC2 share the connection lines of the connection line group in a time-sharing manner. For example, CDC1 is connected to the mutual capacitance input signal line AC at time T1, while CDC2 cannot be connected to the mutual capacitance input signal line AC at time T1, but can only be connected to the mutual capacitance input signal line AC at a time different from T1.

[0135] according to Fig. 6AIn an embodiment, the analog signal router connects multiple CDCs through multiple groups of CDC coupling switches (KAEC1, KACC1 and KSC1, and KAEC2, KACC2 and KSC2), and each group of CDC coupling switches is used to connect a connection line group to one of the CDCs. Multiple CDCs use the same connection line of the connection line group in a time-sharing manner. At any time, one connection line of the connection line group is connected to at most one CDC.

[0136] Figure 6B A block diagram of an analog signal router according to another embodiment of the present application is shown.

[0137] same Fig. 6A Compared with the embodiment, Figure 6B In the embodiment of the present invention, the analog signal router provides a shared excitation signal line AE for multiple CDCs, and provides each CDC with its own mutual capacitance input signal line (AC1, AC2 and AC3). The capacitor ports are connected through corresponding sub-switch groups (KAE1, KAC11, KAC21 and KAC31, KAE2, KAC12, KAC22 and KAC32, KAE3, KAC13, KAC23 and KAC33, KAE4, KAC14, KAC24 and KAC34, KBE1, KBC11, KBC21 and KBC31, KBE2, KBC12, KBC22 and KBC32, KBE3, KBC13, KBC23 and KBC33, KBE4, KBC14, KBC24 and KBC34, KCE1, KCC11, KCC21 and KCC31, KCE2, KCC12, KCC22 and KCC32, KCE3, KCC13, KCC23 and KCC33, KCE4, KCC14, KCC24 and KCC34,

[0138] ) is connected to the excitation signal line AE and the mutual capacitance input signal lines (AC1, AC2 and AC3).

[0139] exist Figure 6BIn the example, the capacitance measurement unit includes multiple CDCs (CDC1, CDC2 and CDC3 are shown). Multiple CDCs can work simultaneously to measure multiple capacitances simultaneously. CDC1 and CDC2 each include an excitation signal line port (AEC) and a mutual capacitance input signal line port (ACC), and CDC3 only includes a mutual capacitance input signal line port (ACC). As an example, the excitation signal line ports of CDC1 and CDC2 are independent of each other, so that CDC1 and CDC2 can output different excitation signals at the same time. CDC3 does not have an excitation signal line port, but borrows the excitation signal line port (AEC) of CDC1 or CDC2. Taking CDC3 borrowing the excitation signal line port (AEC) of CDC1 as an example, when it measures mutual capacitance, it provides an excitation signal to the measured capacitance through the excitation signal line port (AEC) of CDC1, and receives the response of the measured capacitance to the excitation signal from the mutual capacitance input signal line port (ACC) of CDC3. Optionally, each CDC also measures self-capacitance. When CDC1 or CDC2 measures self-capacitance, its mutual capacitance input signal line port (ACC) applies excitation to the plate of the measured capacitance in time-sharing and obtains a response, and the applied excitation is generated by the excitation signal source of CDC1 or CDC2 itself. When CDC3 measures self-capacitance, its mutual capacitance input signal line port (ACC) applies excitation to the plate of the measured capacitance in time-sharing and obtains a response, and the applied excitation is generated by, for example, the excitation signal source of CDC1. Inside each CDC, the excitation signal source of CDC1 is coupled to CDC3.

[0140] according to Figure 6B In an embodiment of the present invention, the analog signal router includes a plurality of CDC coupling switch groups (KAEC1 and KACC1, KAEC2 and KACC2, and KACC3), each CDC coupling switch group corresponds to one of the CDCs, and the CDC coupling switch group is used to couple its corresponding CDC to the connection line group. Optionally, the number of switches in the CDC coupling switch group is the same as the number of ports of the corresponding CDC. Multiple CDCs use the same connection line of the connection line group in a time-sharing manner. At any time, a connection line of the connection line group is connected to at most one CDC.

[0141] In order to adapt to the change in the number of CDCs, Figure 6B In the illustrated embodiment, the group where the excitation signal line (AE) is located is called a connection line group, and the group where one of the mutual capacitance input signal lines (AC1, AC2 or AC3) is located is called a capacitance channel connection line group. Figure 6BIn the embodiment, the connection line group includes only the excitation signal line (AE), and each capacitor channel connection line group includes one of the mutual capacitance input signal lines. The connection lines of the capacitor channel connection line group are also connected to the capacitor port through the capacitor port coupling switch. Accordingly, the capacitor port couples each connection line of the connection line group with all the capacitor channel connection line groups through the sub-switch group, so that the number of switches of the sub-switch group is the same as the sum of the number of all connection lines of the connection line group with all the capacitor channel connection line groups, and they correspond one to one. For a sub-switch group, its multiple switches, at most only one switch is closed at any time, and the other switches are all open, so that the capacitor port is at most coupled to one of all the connection lines of the connection line group with all the capacitor channel connection line groups at any time.

[0142] At a certain moment, it is allowed that multiple sub-switch groups couple their respective corresponding capacitor ports to one of the connection lines of the connection line group or the capacitor channel connection line group, so as to simultaneously couple a certain connection line of the connection line group or the capacitor channel connection line group to multiple capacitor ports.

[0143] The capacitor channel connection line group corresponds to the CDC one by one. Therefore, if the number of CDCs to be coupled increases, the capacitor channel connection line group only needs to be increased according to the number of CDCs. However, only one connection line group is provided in the analog signal router. In one example, a single connection line group is connected to all CDCs through a CDC coupling switch. In another example, the connection line group is coupled to one of the CDCs, and multiple CDCs share the excitation signal source.

[0144] Figure 6C A block diagram of an analog signal router according to another embodiment of the present application is shown.

[0145] same Figure 6B Compared with the embodiment, Figure 6C In an embodiment of the present invention, the connection line group further includes an active shielding signal line (ASH) and / or a synchronous clock signal line (ACLK). The active shielding signal line (ASH) corresponds to the excitation signal line (AE). The active shielding signal line (ASH) is coupled to the CDC via a CDC coupling switch. Optionally, each CDC shares the active shielding signal line (ASH), so that the active shielding signal line (ASH) is coupled to one of the CDCs via a CDC coupling switch.

[0146] Optionally, the synchronous clock signal line (ACLK) does not belong to the connection line of the connection line group. Still optionally, each CDC shares the synchronous clock signal line (ACLK)

[0147] Figure 6CIn the embodiment of the present invention, each sub-switch group further includes switches (KASH1, KASH2, ..., KCSH4) for connecting the active shielding signal line (ASH) to the capacitor port corresponding to the sub-switch group. The analog signal router further includes a CDC coupling switch KCL for connecting the synchronous clock signal line (ACLK) to the synchronous clock signal line port (CLK) of the CDC.

[0148] exist Figure 6C In the example, the connection line group is shared by all CDCs, and the capacitor channel connection line group corresponds to the CDC one by one. To adapt to the increase of CDCs, the capacitor channel connection line group is increased with the same number as the CDC, and a CDC coupling switch group is added to connect the newly added capacitor channel connection line group with the newly added CDC, and a capacitor port coupling switch is added to each sub-switch group to couple the capacitor port corresponding to the sub-switch group to the newly added capacitor channel connection line group.

[0149] According to the analog signal router of the embodiment of the present application, different paths are formed by opening or closing the switches of the analog switch matrix, and the CDC is able to measure different capacitances coupled to different paths through these paths. The path formed by the analog signal router for measuring capacitance for the CDC is called a capacitance channel. The capacitance channel is used to couple the CDC with the capacitor plate so that the CDC measures the capacitance formed by the capacitor plate. The capacitance channel is dynamic and can be changed as the switch is opened or closed. The capacitance channel is associated with time, and the capacitance channel is created, changed or released as time changes.

[0150] According to an embodiment of the present application, generally, a capacitance channel is a path formed by coupling a connection line group to at least one capacitance port and a capacitance-to-digital converter by an analog switch matrix at a specified time. The capacitance channel includes a path of an electrical signal formed by one or more connection lines of the connection line group, one or more capacitance ports, and one or more switches with specified states of the analog switch matrix. Normally, for a single CDC, at the same time, the analog signal router only provides a single capacitance channel to the CDC, so that the CDC measures capacitance through the single capacitance channel. And as the capacitance measurement is completed or time changes, the switch state of the analog signal router is changed to provide another capacitance channel to the CDC, so that the CDC measures capacitance through the other capacitance channel.

[0151] The capacitor channel has designated resources provided by the analog signal router, including one or more connection lines of the connection line group / capacitor channel connection line group, one or more capacitor ports, and one or more switches with designated states of the analog switch matrix. At the same time, the resources are exclusively used by the capacitor channel. At different times, each capacitor channel can share resources.

[0152] For multiple CDCs, at the same time, the analog signal router can provide respective capacitance channels to each CDC. The capacitance channels provided to each CDC have different resources to avoid interference among the capacitance channels.

[0153] The capacitance channel includes a self-capacitance channel and a mutual capacitance channel. CDC measures self-capacitance through the self-capacitance channel and measures mutual capacitance through the mutual capacitance channel.

[0154] Fig. 7A A schematic diagram of a capacitor channel according to an embodiment of the present application is shown.

[0155] Fig. 7A In FIG. 1 , the bold lines indicate mutual capacitance channels, which are used to measure mutual capacitance A1 ; the dotted lines indicate self-capacitance channels, which are used to measure mutual capacitance Cs. Fig. 7A In the embodiment, the resources included in the mutual capacitance channel include an excitation signal line (AE), a mutual capacitance input signal line (AC), capacitance ports (710 and 712), switches KAE1, KAC2, KAEC and KACC.

[0156] In the capacitance channel for measuring mutual capacitance A1, by setting the states of multiple switches of the analog signal router, the excitation signal line port (AEC) of the CDC is connected to the excitation signal line (AE) through the switch KAEC, the mutual capacitance input signal line port (ACC) of the CDC is connected to the mutual capacitance input signal line (AC) through the switch KACC, the capacitance port (710) is connected to the excitation signal line (AE) through the switch KAE1, and the capacitance port (712) is connected to the mutual capacitance input signal line (AC) through the switch KAC2. The capacitance plates connected to the capacitance port (710) and the capacitance port (712) respectively form the mutual capacitance A1. When measuring mutual capacitance, the switches KAE1, KAC2, KAEC and KACC are closed, and the remaining switches of the analog switch matrix of the analog signal router remain in the open state, so that the excitation signal line port (AEC), the mutual capacitance A1 and the mutual capacitance input signal line port (ACC) of the CDC and the corresponding connecting lines constitute a path for measuring mutual capacitance A1, and the CDC measures the mutual capacitance A1 on the path.

[0157] Fig. 7A In the example, the resources of the self-capacitance channel include the self-capacitance signal line (ASC), the capacitance ports (720 and 722, coupling the capacitance plates A3 and A4, respectively), the switches KAS3, KAS4 and KSC. Fig. 7AIn the example, the self-capacitance signal line port (ASC) of the CDC is connected to the self-capacitance signal line (ASC) through the switch KSC, the capacitor plate A3 is connected to the self-capacitance signal line (ASC) through the switch KAS3, and the capacitor plate A4 is connected to the self-capacitance signal line (ASC) through the switch KAS4. Capacitor plates A3 and A4 constitute the plates of the self-capacitance Cs. When measuring the self-capacitance, switches KAS3, KAS4 and KSC are closed, and the other switches of the analog switch matrix are disconnected. The potentials of capacitor plates A3 and A4 are equal, so that the capacitor plates A3 and A4 are combined to form a plate of the measured self-capacitance Cs. The earth serves as another plate of the self-capacitance Cs. The self-capacitance Cs, the self-capacitance signal line (ASC), the earth and the connecting wires therebetween constitute a path for measuring the self-capacitance Cs, and the CDC measures the self-capacitance Cs on the path.

[0158] Further, by closing the switch connecting the self-capacitance signal line (ASC) and other capacitance ports (e.g., KAS1, KAS2, ...), a further capacitance channel is formed, which connects the capacitance plate for measuring the self-capacitance to more capacitance ports, so that the capacitance plate of the self-capacitance can have a larger area and a different shape. Thus, according to an embodiment of the present application, different capacitance channels are formed by configuring the opening or closing of the switch of the analog signal router, so that the CDC can measure different capacitances through different capacitance channels without changing the deployed hardware.

[0159] Figure 7B A schematic diagram of a capacitor channel according to another embodiment of the present application is shown.

[0160] Figure 7B The example shows two capacitance channels that exist simultaneously, one is a mutual capacitance channel (indicated by a bold line), and the other is a self capacitance channel (indicated by a dotted line). CDC1 measures mutual capacitance Cm through the mutual capacitance channel, and CDC2 measures self capacitance Cs through the self capacitance channel. Optionally, CDC1 and CDC2 perform their respective capacitance measurements simultaneously or in a time-sharing manner.

[0161] In the mutual capacitance channel, switches KAE1, KAC2 and the corresponding switches KAEC, KACC of CDC1 are closed, so that the excitation signal line (AE), the mutual capacitance input signal line (AC), the capacitor ports (730, 732) and the switches (KAE1, KAC2, KAEC and KACC) form a mutual capacitance channel.

[0162] In the self-capacitor channel, switches KBS3, KBS4 and switch KSC2 corresponding to CDC2 are closed, so that the self-capacitor signal line (ASC), capacitor ports (740 and 742) and switches (KBS3, KBS4 and KSC2) form a self-capacitor channel. The switches KBS3 and KBS4 are closed at the same time to expand the area of ​​the capacitor plate of the self-capacitor.

[0163] In the analog switch matrix, except for switches KAE1, KAC2, KAEC, KACC, KBS3, KBS4 and KSC2, all other switches remain open.

[0164] Thus, multiple capacitance channels that exist simultaneously are formed through the analog signal router, so that multiple CDCs can measure multiple capacitances simultaneously and in parallel through their respective capacitance channels.

[0165] In an optional embodiment, CDC1 and CDC2 share the excitation signal source internally, and CDC2 uses the excitation signal line port (AEC) of CDC1. In this case, CDC1 and CDC2 cannot work at the same time. Accordingly, Figure 4C The mutual capacitance channel and self-capacitance channel provided by the analog signal router cannot work at the same time, but work in time division. For example, at time T1, CDC1 measures the mutual capacitance Cm through the mutual capacitance channel, and at a later or different time T2, CDC2 measures the self-capacitance Cs through the self-capacitance channel.

[0166] Fig. 8A A block diagram of an analog signal router according to another embodiment of the present application is shown.

[0167] same Fig. 7A Compared to the analog signal router shown, Fig. 8A The analog signal router also includes an analog routing controller. The analog routing controller couples one or more switches of the analog switch matrix of the analog signal router and controls the opening or closing of the one or more switches. By setting the analog routing controller, it is helpful to change the capacitance channel provided by the analog signal router at the work site. It can be understood that the analog routing controller is not necessary. The opening or closing of the switches of the analog switch matrix can be set on the production line and / or at the work site of the analog router in the manner of the prior art. The analog routing controller takes over the control of the switches of the analog switch matrix and can establish a higher description level, such as abstracting the control object as a capacitance channel rather than a switch. Thereby, the outside world, for example, instructs the analog routing controller to create and release a specified capacitance channel, and the outside world does not have to care about the states of the individual switches required to build the capacitance channel.

[0168] As an example, Fig. 8AThe analog routing controller records the states of all switches of the analog switch matrix of the analog signal router, and the analog routing controller is connected to the control end of each switch of the analog switch matrix. The control end of the switch determines the action and / or state of the switch according to the control signal received from the analog routing controller. The analog routing controller also receives external configuration information to change the states of one or more switches of the analog switch matrix recorded by it. And the configuration information also indicates the timing when the analog routing controller applies the states of one or more switches recorded to the control end of one or more switches.

[0169] Still as an example. The analog routing controller is operated by an internal component such as a CPU or an external component as a control interface of the analog signal router. The CPU or a program memory accessed by the CPU can be programmed to set the way the CPU operates the analog signal router. By operating or configuring the analog routing controller, the internal or external component controls the analog signal router to form a capacitive channel.

[0170] As another example, the analog routing controller includes a memory, and the states of one or more switches of the analog switch matrix recorded in the memory are set by programming the memory, or the states of one or more switches of the analog switch matrix at different times.

[0171] Fig. 8A In the example shown, the analog routing controller includes a matrix control register set, a sequence state controller, and a selector.

[0172] The matrix control register group includes a plurality of registers, and the registers of the matrix control register group include a plurality of bits, each bit corresponding to the state information of one of the switches of the analog switch matrix. In one example, the number of bits of the registers of the matrix control register group is the same as the number of switches of the analog switch matrix, so that each bit of the register corresponds to the switch of the analog switch matrix one by one. In another example, the number of bits of the registers of the matrix control register group is less than the number of switches of the analog switch matrix, for example, the register is a 32-bit register. Thus, the plurality of registers of the matrix control register group jointly store the state information of all switches of the analog switch matrix.

[0173] The matrix control register group records the state information of switches of the analog switch matrix for, for example, multiple capacitor channels. For example, each register of the matrix control register group corresponds to the state information of switches of the analog switch matrix required to construct one of the capacitor channels. In another example, multiple (but not all) registers of the matrix control register group correspond to the state information of switches of the analog switch matrix required to construct one of the capacitor channels. The sequential state controller successively selects multiple registers required to construct a certain capacitor channel, and uses the values ​​of each bit of these registers to set the states of multiple switches in the analog switch matrix.

[0174] The sequential state controller is a sequence generator, a state machine or a microprocessor, which outputs a specified value or a specified sequence of values ​​corresponding to the input. The value output by the sequential state controller is used to indicate the selection of one of the registers in the matrix control register group. Optionally, the matrix control register group is coupled to a selector, and the selector selects one of the registers of the matrix control register group as an output according to the output of the sequential state controller and provides it to a plurality of switches of the analog switch matrix.

[0175] In one example, the number of bits of the registers of the matrix control register group is the same as the number of switches of the analog switch matrix, and accordingly, to create a capacitor channel, the sequential state controller selects a single register of the matrix control register group to set the state of each switch of the analog switch matrix. In another example, the number of bits of the registers of the matrix control register group is less than the number of switches of the analog switch matrix, and accordingly, to create a capacitor channel, the sequential state controller selects multiple registers of the matrix control register group through a sequence of multiple values ​​to set the states of multiple switches of the analog switch matrix.

[0176] The selector outputs each bit of the register of the currently selected matrix control register group to the control port of the corresponding switch of the analog switch matrix to control the opening or closing of the corresponding switch.

[0177] The matrix control register set may be configured to write control information for controlling switches of the analog switch matrix thereto, for example, by updating the values ​​of registers of the matrix control register set via an external configuration port or a processor.

[0178] Figure 8B A block diagram of an analog signal router according to another embodiment of the present application is shown.

[0179] Figure 8B In the example shown, the analog routing controller includes a register 810. The number of bits of the register 810 is the same as the number of switches of the analog switch matrix, for example. The bits of the register 810 correspond one-to-one to the switches of the analog switch matrix of the analog routing controller, and each bit of the register 810 of the analog routing controller is coupled to one of the switches of the analog switch matrix of the analog routing controller, and the bit of the register 810 is used to control the opening or closing of the corresponding switch. For example, the analog switch matrix has 128 switches, and accordingly, the width of the register 810 of the analog routing controller is 128 bits.

[0180] according to Figure 8BIn the embodiment of the present invention, the value of the register 810 of the analog routing controller corresponds to one or more capacitance channels provided by the analog signal router at a certain moment. When the value of the register 810 corresponds to multiple capacitance channels, these capacitance channels exist simultaneously. In response to the update of the value of the register 810 of the analog routing controller, one or more switches (corresponding to the bits of the register that have changed) of the analog switch matrix of the analog signal router are reset to a working state, and accordingly, the capacitance channels provided by the analog signal router also change.

[0181] In an alternative embodiment, Figure 8B The register 810 of the analog routing controller corresponds to multiple bus addresses. For example, the register width is 128 bits, corresponding to 4 addresses (e.g., A0-A3) of a 32-bit bus, and 32 bits of the register are accessed through each bus address. External components such as a CPU that are also coupled to the bus set the register by accessing the bus address (A0-A3) to update the capacitance channel provided by the analog signal router at runtime.

[0182] Figure 8B In the example shown, the analog routing controller further includes a matrix control register group 820 and a selector.

[0183] The selector selects one of the matrix control registers 820 as output according to the instruction of an external component such as a CPU, and uses the selected output to set the register 810. Each bit of the register whose output is selected by the selector is respectively coupled to one of the switches of the analog switch matrix of the analog signal router to control the open or closed state of the corresponding switch.

[0184] In some cases, the width of the bus (such as 32 bits) is much smaller than the number of switches in the analog switch matrix. By setting the matrix control register set, an external component such as a CPU can output all the state information required to set the analog switch matrix through a single bus access, thereby setting all switches of the analog switch matrix at the same time.

[0185] Optionally, a bus address is provided for the control port of each switch of the analog switch matrix, so that the external component can directly set the switches of the analog switch matrix by accessing the bus. Although the number of switches set each time is less than or equal to the bus width, the state update of all switches of the analog switch matrix is ​​completed through multiple bus cycles. In some cases, only the state of some switches of the analog switch matrix changes in two adjacent capacitance measurements, so only the state of these switches needs to be updated.

[0186] The R-SpiNNaker system includes multiple nodes and can be deployed over a larger area. By measuring (multiple) capacitors that may exist anywhere in space, the characteristics of objects in space are sensed. The R-SpiNNaker system includes multiple R-SpiNNaker chips distributed in different locations. Each R-SpiNNaker chip includes one or more CDCs and is connected to one or more capacitor plates. The CDC and the capacitor plates are dynamically combined into a capacitance measurement unit. In addition to being able to change the area of ​​the capacitor plate to adapt to targets to be detected of different distances, shapes, and materials, it is also possible to coordinate multiple capacitor plates located at different positions in space / time to obtain spatial / temporal perceptions such as differentiation / tracking of the target to be detected.

[0187] Fig. 9 The R-SpiNNaker system according to an embodiment of the present application is demonstrated.

[0188] See also Fig. 9 , the R-SpiNNaker system includes two R-SpiNNaker chips (900 and 950). The two R-SpiNNaker chips have, for example, the same configuration. The chips of the R-SpiNNaker system have the same configuration, which is conducive to the large-scale production and deployment of the R-SpiNNaker chips. Optionally, the R-SpiNNaker chips of the R-SpiNNaker system have different configurations, for example, some nodes include CDC and some nodes do not include CDC, to further reduce costs.

[0189] The two R-SpiNNaker chips (900 and 950) each include an analog signal router (910 and 960) and a CDC (CDC1 and CDC2). The analog signal router 910 is connected to CDC1, and the analog signal router 960 is connected to CDC2. As an example, the CDC includes a shared port (ACC / SCA), which is used as both a mutual capacitance input signal line port (ACC) and a self-capacitance signal line port (SCA).

[0190] The analog signal router (e.g., 910 or 960) includes a mutual capacitance input signal line AC, a cross-chip mutual capacitance input signal line IAC, and multiple switches (KIACE, KIACW, KIACS, and KIACN, also referred to as analog signal port coupling switches). The combination of multiple switches of the analog signal router is referred to as an analog switch matrix. The mutual capacitance input signal line AC corresponds to the cross-chip mutual capacitance input signal line IAC and is connected to each other. The mutual capacitance input signal line AC connects the port (ACC / SCA) of the CDC. The cross-chip mutual capacitance input signal line IAC is coupled to the analog signal ports (IACE, IACW, IACS, and IACN) of the R-SpiNNaker chip through switches (KIACE, KIACW, KIACS, and KIACN). The switches (KIACE, KIACW, KIACS and KIACN) correspond one-to-one to the analog signal ports (IACE, IACW, IACS and IACN), thereby coupling the cross-chip mutual capacitance input signal line IAC to one or more analog signal ports, and the analog signal port (for example, IACW 912) can only be connected to the cross-chip mutual capacitance input signal line IAC through its corresponding switch (KIACW).

[0191] As an example, the four analog signal ports (IACE, IACW, IACS and IACN) of the analog signal router 910 are all analog signal ports for the cross-chip mutual capacitance input signal line IAC, and are respectively located in the east (E), west (W), south (S) and north (N) directions of the chip to which the analog signal router belongs (the chip where the node is located), so as to facilitate leading out in the east, west, south and north directions to the outside of the chip when the chip is deployed or installed on a plane such as a circuit board. Fig. 9 In the figure, although for the purpose of drawing simplicity and / or the limitation of the plane topology, the switch KIACS is shown to be directly connected to the mutual capacitance input signal line AC, in an optional embodiment, the mutual capacitance input signal line AC is not directly connected to the switch KIACS, but the cross-chip mutual capacitance input signal line IAC is extended to the other end (south end) of the chip through another wiring layer of the chip and connected to the switch KIACS. Optionally, the mutual capacitance input signal line AC is directly connected to the switch KIACS. It can be understood that the analog signal ports (IACW (912), IACN (914), IACE and IACS (916)) are also analog signal ports of the R-SpiNNaker chip 900.

[0192] The analog signal port and the cross-chip connection line are adapted to be connected to the outside of the chip and further connected to another chip containing a node including an analog signal router (e.g., 960) according to an embodiment of the present application, so that the electrical characteristics of the analog signal port and the cross-chip connection line can be different from the mutual capacitance input signal line AC. Optionally, the analog signal port is also used to connect the capacitor plate.

[0193] exist Fig. 9 In the example, the analog signal port IACW (912) of the analog signal router 910 is connected to a capacitor plate, which forms a self-capacitance (Cs1) relative to the ground. CDC1 applies excitation to the capacitor plate connected to the analog signal port IACW (612) through the mutual capacitance input signal line AC of the analog signal router 910, the cross-chip mutual capacitance input signal line IAC, and the switch KIACW and measures its self-capacitance. The analog signal port (IACS) (916) is connected to the analog signal port (IACN) (974) of the analog signal router 920 through the lead 915.

[0194] The R-SpiNNaker chip 900 includes four point-to-point ports (942, 944, 946 and 948), which are respectively located in the east (E), west (W), south (S) and north (N) directions of the chip to which the analog signal router belongs (the chip where the node is located), so that when the chip is deployed or installed on a plane such as a circuit board, leads are extended to the east, west, south and north directions outside the chip to connect the point-to-point ports of other R-SpiNNaker chips with the digital router. The digital router forwards the received configuration or programming data packet to the analog signal router. For example, the analog routing controller of the analog signal router receives the configuration or programming data packet and obtains the configuration or programming information for the analog switch matrix from it. Fig. 9 In the example, the point-to-point port 946 of the R-SpiNNaker chip 900 is connected to the point-to-point port 992 of the R-SpiNNaker chip 950, so that the digital router of the R-SpiNNaker chip 900 exchanges data packets with the digital router of the R-SpiNNaker chip 950 through the point-to-point port 946 and the point-to-point port 992, wherein the exchanged data packets include configuration or programming data packets and / or AER packets.

[0195] The analog signal router 960 is connected to CDC2. The analog signal router 960 also includes analog signal ports (IACW (972), IACN (974), IACE and IACS (976)). The analog signal port IACW (972) of the analog signal router 960 is connected to a capacitor plate, which forms a self-capacitance (Cs2) relative to the ground. It can be understood that the analog signal port (IACW (972), IACN (974), IACE and IACS (976)) is also the analog signal port of the R-SpiNNaker chip 950.

[0196] According to an embodiment of the present application, the analog signal routers 910 and 960 can work together to enable CDC1 to measure capacitance using a capacitor plate connected to any one of the R-SpiNNaker chips (900 and 950). Similarly, CDC2 can also measure capacitance using a capacitor plate connected to any one of the R-SpiNNaker chips (900 and 950). As an example, the switches KIACS of the analog signal router 910 and the switches KIACN and KIACW of the analog signal router 960 are closed, so that the port (ACC / SCA) of CDC1 is connected to the mutual capacitance input signal line AC of the analog signal router 910 and the cross-chip mutual capacitance input signal line IAC ( Fig. 9 Not shown are the connection between the mutual capacitance input signal line AC and the cross-chip mutual capacitance input signal line IAC on the south side of the analog signal router 910), the switch KIACS and the analog signal port IACS (916), which are connected to the capacitor plate (and other switches are disconnected) via the lead 915, and then through the analog signal port IACN (974) of the analog signal router 960, the switch KIACN, the cross-chip mutual capacitance input signal line IAC, the switch KIACW and the analog signal port IACW (972), so that CDC1 can measure the self-capacitance Cs2 formed by the capacitor plate that does not belong to the same node as it.

[0197] As another example, the switch KIACN of the analog signal router 960, the switches KIACS and KIACW of the analog signal router 910 are closed, so that the port (ACC / SCA) of CDC2 passes through the mutual capacitance input signal line AC of the analog signal router 970, the cross-chip mutual capacitance input signal line IAC, the switch KIACN and the analog signal port IACN (974), through the lead 915, and then through the analog signal port IACS (916) of the analog signal router 910, the switch KIACS, the cross-chip mutual capacitance input signal line IAC ( Fig. 9Not shown are the cross-chip mutual capacitance input signal lines IAC connected to the switches KIACS), the switches KIACW, and the analog signal port IACW (912) connected to the capacitor plates (and other switches disconnected), so that CDC2 can measure the self-capacitance Cs1.

[0198] The R-SpiNNaker chip (900 and 950) or its analog signal router (910 and 960) also includes one or more capacitor ports (934, 984). The capacitor port is used to connect the capacitor plate of the R-SpiNNaker chip. The analog signal router (910 and 960) of the R-SpiNNaker chip also includes capacitor port coupling switches (KAC1, KAC2, KAC3 and KAC4) corresponding to the capacitor ports one by one. The capacitor port coupling switch is used to connect its corresponding capacitor port to the mutual capacitance input signal line (AC), or disconnect the capacitor port from the mutual capacitance input signal line (AC). By closing multiple capacitor port coupling switches at the same time, the mutual capacitance input signal line (AC) is simultaneously connected to multiple capacitor ports, thereby connecting the capacitor plates connected to these capacitor ports. The analog signal router (such as 910 or 960) also includes a CDC coupling switch (KACC) for controlling the connection or disconnection of the mutual capacitance input signal line (AC) with the CDC port (ACC / SCA). Disconnect the CDC of the node from the analog signal router to reduce the interference caused by the CDC, which is beneficial for the analog signal router of the node to provide signals to other nodes.

[0199] CDC1 / CDC2 can be configurably coupled to one or more of the capacitor plates of the two R-SpiNNaker chips through the analog signal router 910 and / or the analog signal router 960, and the self-capacitance of these capacitor plates to ground is measured. The capacitor plates of the R-SpiNNaker chip include capacitor plates connected through capacitor ports and / or capacitor plates connected through analog signal ports.

[0200] Fig.10 An R-SpiNNaker system according to yet another embodiment of the present application is demonstrated.

[0201] Fig.10In the example, the two R-SpiNNaker chips constituting the R-SpiNNaker system each include an analog signal router (1010 and 1050) and a CDC (CDC1 and CDC2). The analog signal router 1010 is connected to CDC1, and the analog signal router 1050 is connected to CDC2. The CDC (CDC1 and CDC2) includes an excitation signal line port (AEC) and a mutual capacitance input signal line port (ACC). The CDC measures mutual capacitance through the excitation signal line port (AEC) and the mutual capacitance input signal line port (ACC), and measures self capacitance through one of its ports.

[0202] same Fig. 9 Compared with the R-SpiNNaker chip shown, Fig.10 In the embodiment, the analog signal router (e.g., 1010) of the R-SpiNNaker chip further includes an excitation signal line (AE) and a cross-chip excitation signal line (IAE) connected to the excitation signal line (AE), a capacitor port coupling switch (KAE1-KAE4) and corresponding capacitor ports, an analog signal port (IAEE, IAEW, IAES, IAEN) and a CDC coupling switch (KAEC). The analog signal router (e.g., 1010) further includes an optional synchronous clock signal line port (CLK), a CDC coupling switch (KCL), a synchronous clock signal line (ACLK), a switch (KCLK) and a synchronous clock port ICLK.

[0203] The cross-chip excitation signal line (IAE) is coupled to the corresponding analog signal ports (IAEE, IAEW, IAES, IAEN) through switches (KIAEE, KIAEW, KIAES, KIAEN). The switches (KIAEE, KIAEW, KIAES, KIAEN) correspond one-to-one to the analog signal ports (IAEE, IAEW, IAES, IAEN). Fig.10 It is shown that the excitation signal line (AE) is connected to the analog signal port (IAES) through a switch. It can be understood that in an optional embodiment, the excitation signal line AE is not directly connected to the analog signal port (IAES), but is connected to the analog signal port (IAES) through the cross-chip excitation signal line IAE via the switch.

[0204] The capacitor port coupling switches (KAE1-KAE4) correspond to the capacitor ports one by one. The capacitor port coupling switches (KAE1-KAE4) are used to connect the corresponding capacitor ports to the excitation signal line (AE). The CDC coupling switch (KAEC) connects the excitation signal line AE to the excitation signal line port (AEC) of the CDC.

[0205] The combination of the excitation signal line AE and the mutual capacitance input signal line AC is called a connection line group. The combination of the inter-chip excitation signal line IAE and the inter-chip mutual capacitance input signal line IAC is called an inter-chip connection line group.

[0206] A plurality of (e.g., two) capacitor port coupling switches (e.g., KAE1 and KAC1, KAE2 and KAC2) that connect the same capacitor port to each connection line of the connection line group are called a sub-switch group. At the same time, at most only one of the multiple (two) switches of the sub-switch group is closed, so that the capacitor port is connected to at most one connection line of the connection line group at any time. And through the setting of the sub-switch group, the capacitor port can be connected to any connection line of the connection line at different times. And multiple switches (e.g., KAE1-KAE4) that connect multiple capacitor ports to a connection line of the connection line group can be closed at the same time to connect the connection line to multiple capacitor ports at the same time.

[0207] exist Fig.10 In the embodiment, the analog signal port can only be connected to one of the cross-chip connection lines of the cross-chip connection line group inside the analog signal router. For example, the analog signal port IAEN of the analog signal router 1010 can only be connected to the cross-chip excitation signal line IAE, and the analog signal port IACN can only be connected to the cross-chip mutual capacitance input signal line IAC. Thus, for an analog signal port, it is connected to the cross-chip connection line group (and thus can only be connected to one of the cross-chip connection lines of the cross-chip connection line group) through only one switch. For a capacitance port, it is connected to the connection line group through a sub-switch group including multiple switches, wherein the number of multiple switches of the sub-switch group is the same as the number of connection lines of the connection line group, and the switches of the sub-switch group correspond one-to-one to the connection lines of the connection line group.

[0208] Through such an arrangement, the number of switches required for the analog signal router 1010 is reduced to reduce cost and complexity, and the interference of the switch on the transmitted signal when the analog signal is transmitted over a long distance is also reduced. For example, the analog signal port IACN is connected to the excitation signal line AC through only one switch (KIACN), while the capacitance port (such as 654) is connected to the mutual capacitance input signal line IAC through two switches. In addition, sufficient analog signal ports and cross-chip connection line resources are reserved for transmitting analog signals between chips. For example, the excitation signal and the response to the excitation signal can be transmitted between two nodes at the same time.

[0209] Further, the cross-chip connection line (e.g., IAE) is connected to multiple analog signal ports (IAEE, IAEW, IAES, IAEN) through multiple switches (e.g., KIAEE, KIAEW, KIAES, KIAEN). By closing these switches at the same time, the cross-chip connection line is connected to multiple analog signal ports at the same time, so that the cross-chip connection line is connected to multiple nodes and / or capacitor plates at the same time.

[0210] The CDC coupling switch (KCL) of the analog signal router connects the synchronous clock signal line (ACLK) to the synchronous clock signal line port (CLK) of the CDC. The synchronous clock signal line (ACLK) is also connected to the synchronous clock port (ICLK) through the switch (KCLK). The switch (KCLK) is not necessary. Optionally, the synchronous clock port ICLK is directly connected to the synchronous clock signal line (ACLK) without passing through the switch (KCLK).

[0211] Optionally, the synchronous clock port is replaced by an analog signal port, and accordingly, the cross-chip connection line group also includes a cross-chip synchronous clock signal line (not shown), the cross-chip synchronous clock signal line is connected to the synchronous clock connection line, and the switch couples the cross-chip synchronous clock signal line to the analog signal port.

[0212] Continue to view Fig.10 As an example, CDC2 is used to measure the mutual capacitance Cm formed by the capacitor plates connected to the capacitor port 1014 and the capacitor port 1054 respectively. The capacitor ports 1014 and 1054 are respectively located in two R-SpiNNaker chips, so that the capacitor plates connected to the capacitor ports 1014 and 1054 form mutual capacitance in a larger spatial range. Furthermore, the R-SpiNNaker system according to the embodiment of the present application is able to detect objects that appear in the spatial range corresponding to the capacitor plates connected to the capacitor ports 1014 and 1054. By closing the switches KACC and KAC1 of the analog signal router 1050, the mutual capacitance input signal line port (ACC) of CDC2 is connected to the capacitor port 1054. And by closing the switches KAEC and KIAEN of the analog signal router 1050, closing the switches KIEAS and KAE3 of the analog signal router 1010, the excitation signal line input port (AEC) of CDC2 is connected to the capacitor port 1014. CDC2 applies an excitation signal to the capacitor plate connected to the capacitor port 1014, obtains a response to the excitation signal from the capacitor plate connected to the capacitor port 1054, and measures the mutual capacitance Cm.

[0213] exist Fig.10In the example, the switch KAEC, the excitation signal line AE, the cross-chip excitation signal line IAE, the switch KIAEN, the analog signal port IAEN, the lead connecting the analog signal port IAEN (1052) and the analog signal port IAES (1012) of the analog switch matrix 1050, the analog signal port IAES (1012) of the analog switch matrix 1010, the cross-chip excitation connection line IAEC, the switch KIAES, the excitation signal line AE, the switch KAE3 and the capacitance port 1014, and the switch KACC, the mutual capacitance input signal line AC and the switch KAC1 of the analog switch matrix 1050 form a capacitance channel for measuring the mutual capacitance Cm. By changing the state of the switches of the switch matrix of the analog switch matrix 1010 and / or the analog switch matrix 1050, different capacitance channels are created so that CDC1 and / or CDC2 measure the capacitance through the capacitance channel. The capacitance channel is dynamic. The capacitance plate and CDC connected to the capacitance channel form a capacitance measurement unit.

[0214] Still as an example, the capacitor plates connected to the capacitor ports 1014 and 1016 form a mutual capacitance Cm1; and the capacitor plates connected to the capacitor ports 1056 and 1058 form a mutual capacitance Cm2. Both CDC1 and CDC2 can measure the mutual capacitance Cm1 or Cm2 through the analog signal router 1010 and / or the analog signal router 1050. For another example, the switches KAEC, KACC, KAE3 and KAC4 of the analog signal router 1010 are closed (other switches are open), so that CDC1 applies an excitation signal to the capacitor plate connected to the capacitor port 1014 through the excitation signal line port (AEC), and obtains the response of the mutual capacitance Cm1 to the excitation signal from the capacitor plate connected to the capacitor port 1016 through the mutual capacitance input signal line port (ACC). Thereby, the mutual capacitance Cm1 is measured by CDC1.

[0215] Still as an example, the switches KAEC and KIAES of the analog signal router 1010 are closed, and the switches KIAEN and KAE3 of the analog signal router 10500 are closed, so that CDC1 applies an excitation signal to the capacitor plate connected to the capacitor port 1056 through the excitation signal line port (AEC); and the switches KACC and KIACS of the analog signal router 1010 are closed, and the switches KIACN and KAC4 of the analog signal router 1050 are closed, so that CDC1 obtains the response of the mutual capacitance Cm2 to the excitation signal from the capacitor plate connected to the capacitor port 1058 through the mutual capacitance input signal line port (ACC). The other switches not mentioned remain open. Thus, the mutual capacitance Cm2 is measured by CDC1.

[0216] Other implementations, such as parallel measurement of two self-capacitances or one self-capacitance and one mutual capacitance, etc., can also be configured as needed.

[0217] For ease of deployment, the R-SpiNNaker system can easily cover a variety of or any shape of areas to be measured, and analog signal ports are set in different directions of the chip. For example, analog signal ports are set in two orthogonal directions of the R-SpiNNaker chip, so that the R-SpiNNaker chip can be connected to other R-SpiNNaker chips in two directions, thereby forming an R-SpiNNaker system with a mesh topology.

[0218] Optionally, the CDC in the R-SpiNNaker chip also includes an active shielded signal line port (SHD) ( Fig.10 (not shown), accordingly, the analog signal router includes an active shielding signal line, a switch connecting the active shielding signal line and the active shielding signal line port. The active shielding signal line is also connected to the capacitor port or the analog signal port through the switch.

[0219] See also Figure 6B and Figure 6C, to adapt to the implementation of the R-SpiNNaker chip including multiple CDCs, in an optional implementation, the connection line group of the analog signal router and the capacitor channel connection line group. The connection line group is shared by multiple CDCs, and the capacitor channel connection line group is connected to the CDC one-to-one, providing a corresponding capacitor channel connection line group for each CDC. And the sub-switch group corresponding to each capacitor port includes switches that correspond one-to-one to the connection lines of the same connection line group and all the capacitor channel connection line groups. Optionally, the analog signal router provides a larger number of capacitor channel connection line groups to support more CDCs when deployed. And optionally, one or more capacitor channel connection line groups are not connected to the CDC, that is, these capacitor channel connection line groups do not work. Therefore, when deployed, the analog signal router and the CDC can be provided separately without being pre-configured together, which improves the flexibility of deployment. The analog signal router also includes a cross-chip connection line group, and the cross-chip connection line group includes a cross-chip connection line that corresponds one-to-one to the connection line of the same connection line group and all the capacitor channel connection line groups. The analog signal ports of the analog signal router in each direction of east (E), west (W), south (S), and north (N) correspond one-to-one to the cross-chip connection lines of the cross-chip connection line group. For example, the cross-chip connection line group includes 5 connection lines. Accordingly, the analog signal router includes 5 analog signal ports in each direction of east (E), west (W), south (S), and north (N), which are respectively used to connect the corresponding connection lines of the cross-chip connection line group. Two R-SpiNNaker chips are connected correspondingly through analog signal ports. For example, the 5 analog signal ports of one R-SpiNNaker chip in the east (E) direction are correspondingly connected to the 5 analog signal ports of another R-SpiNNaker chip in the west (W) direction.

[0220] Fig.11 An R-SpiNNaker system according to yet another embodiment of the present application is demonstrated.

[0221] Fig.11 In the example of , the R-SpiNNaker system includes four R-SpiNNaker chips (1100, 1120, 1140, and 1160). The four chips each include an analog signal router (1110, 1130, 1150, and 1170) and a CDC (CDC1, CDC2, CDC3, and CDC4).

[0222] By networking multiple (for example, four) chips, it is possible to arrange capacitor plates over a larger area and measure capacitance and other analog quantities. It also expands the scale of the SNN unit, making it possible to build SNNs with stronger computing power and / or more SNNs to meet a variety of computing needs.

[0223] exist Fig.11In the example, each R-SpiNNaker chip includes 2 analog signal ports and 1 point-to-point port in each of the four directions of East (E), West (W), South (S), and North (N) (right, left, bottom, and top). In the R-SpiNNaker system, the R-SpiNNaker chips are arranged in rows and / or columns. The R-SpiNNaker chips belonging to the same row are connected to each other through the ports in the East (E) and West (W) directions. For example, see Fig.11 , R-SpiNNaker chips 1100 and 1120 belong to the same row, and the analog signal ports (IACE and IAEE) and point-to-point ports of the east (E) direction of the R-SpiNNaker chip 1100 are correspondingly connected to the analog signal ports (IACW and IAEW) and point-to-point ports of the west (W) direction of the R-SpiNNaker chip 1120. Therefore, the digital routers of the R-SpiNNaker chips 1100 and 1120 can exchange data packets, and the analog signal routers of the R-SpiNNaker chips 1100 and 1120 can establish analog signal passage and capacitor channels between the two chips. For another example, R-SpiNNaker chips 1100 and 1140 belong to the same column, and the analog signal ports (IACS and IAES) and point-to-point ports of the south (S) direction of the R-SpiNNaker chip 1100 are correspondingly connected to the analog signal ports (IACN and IAEN) and point-to-point ports of the north (N) direction of the R-SpiNNaker chip 1140. Thus, the digital routers of R-SpiNNaker chips 1100 and 1140 can exchange data packets, and the analog signal routers of the two chips can establish analog signal transmission and capacitance channels. Furthermore, with R-SpiNNaker chip 1100 as a relay, R-SpiNNaker chips 1120 and 1140 can also exchange data packets and establish capacitance channels.

[0224] exist Fig.11 In the example, when multiple R-SpiNNaker chips form an R-SpiNNaker system on a plane, each chip (not located at the network boundary) connects to other chips in the four directions of east, west, south and north. In this way, the deployment of a larger number of R-SpiNNaker chips to form an R-SpiNNaker system is simplified, and the number of nodes is not limited. And based on the position of the R-SpiNNaker chip in the network topology, some chips connect to 1, 2 or 3 other chips.

[0225] The leads connecting the R-SpiNNaker chips can have any shape, so the deployment of multiple R-SpiNNaker chips is not limited to a planar structure, but can form a curve or a curved surface.

[0226] Although Fig.11The R-SpiNNaker system shown in FIG. 1 includes 2 nodes per row and 2 nodes per column. It is understood that in an optional embodiment, the number of nodes included in the rows and columns of the R-SpiNNaker system is arbitrary and not limited. The number of rows and columns of the R-SpiNNaker system is also arbitrary.

[0227] Optionally, for a certain R-SpiNNaker chip, its south (S) and north (N) directions are called longitudinal directions, and other R-SpiNNaker chips are connected longitudinally through analog signal ports / point-to-point ports in the south (S) and north (N) directions (longitudinal directions), and other R-SpiNNaker chips are further connected through other connected R-SpiNNaker chips, so that in the longitudinal extension, the connected R-SpiNNaker chips can have any number. Similarly, in the lateral extension (its east (E) and west (W) directions), the connected R-SpiNNaker chips can have any number. This can meet the needs of various capacitor plate combinations in areas to be measured in different shapes, as well as the needs of motion measurement and calculation near nodes.

[0228] The R-SpiNNaker chips are connected via analog signal ports / point-to-point ports located in designated directions of the R-SpiNNaker chips, which is also useful for configuring or programming the analog switch matrix and digital routers of the analog signal routers of each R-SpiNNaker chip. For example, the east-bound analog signal port / point-to-point port of an R-SpiNNaker chip is only connected to the west-bound analog signal port / point-to-point port of another R-SpiNNaker chip (but not to the east-, south-, or north-bound analog signal port / point-to-point port of the other R-SpiNNaker chip); the west-bound analog signal port / point-to-point port of an R-SpiNNaker chip is only connected to the east-bound analog signal port / point-to-point port of another R-SpiNNaker chip; the south-bound analog signal port / point-to-point port of an R-SpiNNaker chip is only connected to the north-bound analog signal port / point-to-point port of another R-SpiNNaker chip (but not to the south-, east-, or west-bound analog signal port / point-to-point port of another R-SpiNNaker chip); the north-bound analog signal port / point-to-point port of an R-SpiNNaker chip is only connected to the south-bound analog signal port / point-to-point port of another R-SpiNNaker chip.

[0229] Therefore, in addition to corresponding to the designated cross-chip connection line, the analog signal port / point-to-point port of the chip also has a direction attribute, and the switch connecting the analog signal port to the cross-chip connection line also has the same direction attribute. The direction attribute is used to address the switch to be operated when programming or configuring the analog switch matrix, and is also used to describe the point-to-point port to forward data packets in the routing table of the digital router.

[0230] Furthermore, in addition to the direction attribute, the analog signal port / point-to-point port of the node also has a row / column attribute (row number or column number), and the switch connecting the analog signal port to the cross-chip connection line also has the same row / column attribute. The row / column attribute is used to address a set of switches to be operated when programming or configuring the analog switch matrix, and is also used to describe a set of point-to-point ports when setting the routing table. Therefore, each chip of the R-SpiNNaker system can be addressed, further simplifying the configuration or programming of the analog switch matrix of each analog signal router, and slowing down the setting of the routing table.

[0231] Fig.11 The R-SpiNNaker system forms a capacitive sensor network. A CDC, one of the R-SpiNNaker chips, is able to measure capacitance using capacitor plates coupled to each R-SpiNNaker chip in the sensor network. For example, CDC1 measures mutual capacitance via capacitor plates 1112 and 1114, mutual capacitance via capacitor plates 1132 and 1134, mutual capacitance via capacitor plates 1152 and 1154, and mutual capacitance via capacitor plates 1172 and 1174. CDC1 can also measure mutual capacitance via capacitor plates 1112 and 1134, measure mutual capacitance formed by two combined capacitor plates by combining (equipotential) capacitor plates 1112 and 1114, and combining (equipotential) capacitor plates 1132 and 1134. CDC1 can also measure the self-capacitance of a capacitor plate or a combination of (equipotential) capacitor plates relative to the ground. CDC1 can also measure multiple capacitors in sequence according to the required timing, for example, measuring the mutual capacitance formed by capacitor plates 1112 and 1114, the mutual capacitance formed by capacitor plates 1132 and 1134, the mutual capacitance formed by capacitor plates 1152 and 1154, and the mutual capacitance formed by capacitor plates 1172 and 1174 in sequence, for example, to identify the position change of an object relative to each node.

[0232] In the application of electronic skin, for example, functions similar to human conditioned reflex and unconditioned reflex are needed. Unconditioned reflex refers to the innate reflex that people are born with. It is a relatively low-level neural activity that can be completed by the participation of nerve centers below the cerebral cortex (such as brainstem and spinal cord). Unconditioned reflexes include knee jerk reflex, blink reflex, hand retraction reflex, infant sucking and urination reflex, etc., while conditioned reflex is an acquired reflex that is gradually formed in the course of life after birth. It is completed on the basis of unconditioned reflex, after a certain process, with the participation of the cerebral cortex. It is a high-level neural activity and the basic mode of high-level neural activity. In modular electronic skin applications, each basic unit of the electronic skin has an R-SpiNNaker chip. When the basic unit of the electronic skin is stimulated by some external factors, it should be able to make rapid response decisions and actions similar to human conditional or unconditional reflexes without the participation of the robot brain or only through the participation of some areas of the distributed robot brain (for example, when the robot hand touches a high temperature or sharp object, or accidentally touches the human body, it needs to immediately retract its hand to avoid it). Therefore, each R-SpiNNaker chip needs a control unit, which can make local action decisions and drive the local action actuator to perform the necessary actions only within the chip or in coordination with adjacent chips. Local decision-making and control execution can be completed independently in the control unit, or with the participation of the computing unit and SNN unit, or even with the participation of the SNN units and control units of multiple related chips.

[0233] Fig. 12A A schematic diagram of the R-SpiNNaker chip architecture according to another embodiment of the present application is shown.

[0234] Fig. 12A The R-SpiNNaker chip on display Figure 3 The R-SpiNNaker chip of the embodiment also integrates a control unit and a GPIO unit. The GPIO unit provides chip pins for driving external execution units. The output of the control unit is connected to the GPIO unit, and the control unit provides driving information to the execution unit through the GPIO unit. The execution unit is, for example, a motor, a switch, etc., which enables the manipulator to perform an action such as retracting its hand to avoid. The control unit is provided by the CPU core executing software, or the control unit is implemented by a hardware circuit.

[0235] The control unit receives data packets forwarded by the digital router. The data packets forwarded by the digital router to the control unit are AER packets or data packets dedicated to the control unit. The control unit extracts the actions to be implemented from the received data packets and drives the execution unit through the GPIO unit. Optionally, the control unit also includes SNN neurons, which constitute the SNN, receive the AER packets provided by the digital router as output, and output the control signals provided to the GPIO unit. Still optionally, the SNN neurons of the control unit and the SNN neurons of the SNN unit together constitute the SNN, and output the control signals provided to the GPIO unit.

[0236] exist Fig. 12A In the embodiment shown, optionally, some or all of the chip pins required for the capacitor port / analog signal port are also provided by the GPIO unit. The control unit, the analog signal port and / or the capacitor port are connected to the pins provided by the GPIO unit by configuration or programming. Thus, the chip pins are shared by the control unit, the analog signal port and / or the capacitor port. In one or more R-SpiNNaker chips in some applications or R-SpiNNaker systems, the pins provided by GPIO are used for the capacitor port and the analog signal port to collect analog signals and / or measure capacitance, while in other R-SpiNNaker chips, the pins provided by GPIO are used to drive the execution unit. The number of pins of the chip is limited and is positively correlated with the cost of the chip. The produced R-SpiNNaker chip includes a plurality of pins provided by the GPIO unit. After deployment at the application site, each pin of each chip is set with a specified purpose by configuration or programming, so that the chip with a limited number of pins can be applied to more application scenarios or uses. Thus, some pins of the chip can be used for both capacitor ports and analog signal ports and drive execution units. Optionally, the chip provides multiple types of pins. For example, pins with relatively stronger driving capability and pins with relatively lower noise are suitable for driving execution units or providing active shielding signals, while pins with lower noise are suitable for connecting capacitor plates or providing capacitor channels across chips.

[0237] Optionally, the control unit also transmits the analog or digital input signal of the GPIO to the computing unit through the digital router for filtering or function model processing, and encodes the signal provided by the control unit into an AER packet in the computing unit. Optionally or further, the control unit also manages each component or each processor core of the R-SpiNNaker chip, for example: loading code for each processor core when the R-SpiNNaker chip is powered on, initializing each component, constructing SNN by setting the routing table of the digital router, setting the parameters of each SNN neuron, etc.

[0238] R-SpiNNaker pursues low-cost multi-chip distributed collaborative applications, and does not pursue large computing power of a single chip. However, multi-chip collaboration can also form large computing power. The design idea of ​​R-SpiNNaker single chip only requires 4 logical cores (which can be 4 physical cores or 4 physical single-core multi-threaded simulated logical cores) is more suitable for the industrial application of low-cost large-area electronic skin and electronic geographic skin.

[0239] Fig. 12B A schematic diagram of the R-SpiNNaker chip architecture according to another embodiment of the present application is shown.

[0240] exist Fig. 12B Based on the R-SpiNNaker chip shown, Fig. 12B The displayed R-SpiNNaker chip includes a local SNN unit and a shared SNN unit. The local SNN unit and the shared SNN unit can each be implemented by a CPU core or a hardware circuit, or can be implemented separately in a single CPU core through different threads or processes. The local SNN unit and the shared SNN unit are respectively connected to a digital router. Optionally, the local SNN unit and the shared SNN unit are not directly connected to each other, so the R-SpiNNaker chip does not adopt a symmetric multi-processing (SMP, Symmetrical Multi-Processing) structure, but provides the local SNN unit and the shared SNN unit. The respective CPU cores each have a memory, and are connected to the digital router to exchange AER packets with the digital router. When the SNN neuron in the local SNN unit needs to send an AER packet to the SNN neuron of the shared SNN unit, it is necessary to first send the AER packet to the digital router, and the digital router then forwards the AER packet to the SNN neuron in the shared SNN unit according to the information in the routing table.

[0241] There are two purposes for setting up a local SNN unit. The first is to make local rapid decisions. For example, when the R-SpiNNaker chip where the local SNN unit is located is exposed to local high temperature or the local pressure exceeds the upper limit threshold, it is necessary to sense such events and make underlying decisions. The second is to extract local underlying feature parameters. For example, the R-SpiNNaker chip where the local SNN unit is located recognizes the local material category of the external object that has been in contact or is about to be in contact, the speed of the external object approaching, the three-dimensional force vector of the local contact, whether there is vibration in the local contact, the amplitude and frequency of the vibration, whether there is sliding in the local contact, the direction and speed of sliding, etc.

[0242] According to an embodiment of the present application, the AER packets received by the local SNN unit only come from the computing unit and / or control unit of the chip where it is located, and the AER packets output by it can be forwarded by the digital router to the shared SNN unit and / or the chip where it is located. Multiple SNN neurons of the local SNN unit can construct one or more SNNs, and the constructed SNNs can be independently learned and trained in a modular and standardized manner. Except for its output layer, the neurons of the SNN of the local SNN unit are invisible to the SNN of the shared SNN unit or other R-SpiNNaker chips. In other words, among the neurons of the local SNN unit, except for the neurons that serve as the output layer of the SNN, the AER packets output by other SNN neurons will not be forwarded by the digital router to the shared SNN unit or other R-SpiNNaker chips.

[0243] Optionally, even if the multiple SNN neurons included in the SNN unit are implemented by, for example, the same CPU, in order to simplify the design and programming model, the transmission of AER packets between the SNN neurons within the SNN unit is also relayed by a digital router.

[0244] The main purpose of the shared SNN unit is to build inter-chip SNNs for multi-chip (multi-CPU core) collaborative computing, which is similar to the SpiNNaker system. Large-scale SNNs can be distributed on multiple chips for collaborative computing. The difference is that each SNN of the shared SNN unit can have a local output layer, the purpose of which is to issue local control instructions to the control unit based on the results of the collaborative computing of the entire network. In the case of single-chip applications, the shared SNN unit can also be configured as a local SNN unit through the routing table of the digital router.

[0245] Fig.13A A schematic diagram of constructing an SNN according to an SNN unit of an embodiment of the present application is shown.

[0246] SNN is composed of multiple interconnected SNN neurons. The multiple SNN neurons included in the SNN unit are used to construct SNN. The routing table of the digital router records the connection relationship between SNN neurons. For example, the routing table records one or more AER packets (denoted as S2) to which an AER packet (denoted as S1) sent by a certain SNN neuron should be forwarded (thereby indicating that in the SNN, the output of SNN neuron S1 is connected to the input of SNN neuron S2, and there can be multiple neurons S2), point-to-point ports / network ports, and control units.

[0247] SNN has specified functions, such as identifying the approach of a finger, detecting the material of an object, identifying the speed / moving direction of a target, etc. SNN includes, for example, three layers, an input layer, an intermediate layer, and an output layer. Each layer is composed of SNN neurons. The SNN neurons that constitute the input layer are called input layer neurons, the SNN neurons that constitute the output layer are called output layer neurons, and the SNN neurons that constitute the intermediate layer are called intermediate layer neurons.

[0248] The input received by SNN is neural pulses. The characteristics of neural pulses, such as the time and number of occurrences, represent the information to be recognized by SNN. Fig.13A In the figure, the vertical line between the digital router and the input layer neuron represents the nerve pulse (also represents the AER packet), and the horizontal position of the vertical line represents the time when the nerve pulse occurs. The closer to the right side, the earlier it occurs.

[0249] In an optional embodiment, the input layer neurons only receive AER packets provided, for example, from the output layer neurons of the computing unit or other SNNs. Through the routing rules set in the routing table of the digital router, it is determined that the AER packets to be forwarded to the input layer neurons can come from the output layer neurons of the computing unit or other SNNs, but not from the intermediate layer neurons. The intermediate layer neurons only receive AER packets output from the input layer neurons of the SNN in which they are located or the intermediate layer neurons of the SNN in which they are located, and the output of the intermediate layer neurons is only provided to the output layer neurons of the SNN in which they are located. The output layer neurons of the SNN only receive AER packets output by the intermediate layer neurons of the SNN in which they are located. The AER packets output by the output layer neurons of the SNN can be provided to the control unit and / or the input layer neurons of other SNNs.

[0250] The output of SNN is neural pulses. The characteristics of neural pulses, such as the time and quantity, also represent the results of SNN processing. Fig.13A In the figure, the neural pulses output by the output layer neurons of the SNN are provided to the digital router (represented by the dotted line). The digital router also forwards the received AER packets (representing neural pulses) to the control unit and / or the input layer neurons of other SNNs according to the routing table. Fig.13A Two digital routers are shown for the purpose of clarity. In the R-SpiNNaker chip, only a single digital router is provided, which provides AER packets to the SNN, and the AER packets output by the SNN are also provided to the digital router.

[0251] Fig.13AThe communication connection between the SNN neurons (nodes represented by circles) of the SNN and the digital router is also shown. The AER packet output by the SNN neuron is first sent to the digital router, and then sent by the digital router to another designated SNN neuron. In this way, the information path between the SNN unit and the digital router is simplified. The SNN unit or SNN may include a large number of SNN neurons, and it is difficult to provide each SNN neuron with a dedicated information path to the digital router. However, the SNN unit has an information path with the digital router, and all SNN neurons of the SNN unit share the information path to exchange AER packets with the digital router.

[0252] It can be understood that there may be no difference between the SNN neurons of the SNN unit, but the routing rules provided by the routing table of the digital router describe the layer (input layer, middle layer, output layer) to which the SNN neurons belong, as well as the connection relationship between the SNN neurons.

[0253] Fig. 13B A schematic diagram of constructing an SNN using an SNN unit according to another embodiment of the present application is shown.

[0254] Fig. 13B In the example, the R-SpiNNaker chip includes a local SNN unit and a shared SNN unit, and the local SNN unit and the shared SNN unit are each provided by a CPU core. Multiple SNN neurons of the local SNN unit constitute an SNN. Multiple SNN neurons of the shared SNN unit constitute an SNN. The forwarding targets of the AER packets output by the input layer neurons and the intermediate layer neurons of the SNN in the local SNN unit are all SNN neurons of the local SNN. Only the AER packets output by the output layer neurons may be forwarded outside the local SNN unit. Optionally, the AER packets output by the SNN neurons of the local SNN unit will not be forwarded outside the R-SpiNNaker chip to which it belongs, so that the computing resources of the local SNN unit are not shared among multiple R-SpiNNaker chips. The AER packets received by the input layer neurons of the SNN in the local SNN unit come from the computing unit of the R-SpiNNaker chip to which it belongs, or other SNNs in the local SNN unit.

[0255] The forwarding targets of the AER packets output by the input layer neurons and the intermediate layer neurons of the SNN in the shared SNN unit are all the SNN neurons of the shared SNN. Only the AER packets output by the output layer neurons may be forwarded outside the shared SNN unit, including other SNN neurons in the shared SNN unit that do not belong to the SNN, the local SNN unit of the R-SpiNNaker chip to which the shared SNN unit belongs, and / or other R-SpiNNaker chips other than the R-SpiNNaker chip to which the shared SNN unit belongs. The AER packets received by the input layer neurons of the SNN in the shared SNN unit come from the local SNN unit of the chip to which the shared SNN unit belongs, other neurons of the shared SNN unit, or other R-SpiNNaker chips.

[0256] In an optional embodiment, the shared SNN units of multiple R-SpiNNaker chips of the R-SpiNNaker system jointly construct an SNN. The shared SNN units of the multiple R-SpiNNaker chips provide one or more SNN neurons for the constructed SNN. The digital routers of these R-SpiNNaker chips jointly define the topology of the SNN neurons for the constructed SNN and distribute AER packets to the SNN neurons. Optionally, the shared SNN units of multiple R-SpiNNaker chips jointly construct an SNN, and the input layer neurons, intermediate layer neurons and output layer neurons of the constructed SNN can be provided by any shared SNN unit, and the AER packets output by the input layer neurons, intermediate layer neurons and output layer neurons can also be sent to any shared SNN unit that provides neurons for the SNN, and the AER packets output by the output layer neurons can also be provided to the control unit of the R-SpiNNaker chip where any shared SNN unit that provides neurons for the SNN is located.

[0257] Fig.14 A schematic diagram of the R-SpiNNaker chip architecture according to another embodiment of the present application is shown.

[0258] Fig.14 The R-SpiNNaker chip on display includes four CPU cores (1420, 1422, 1424 and 1426), a digital router, an analog signal router, a CDC, a point-to-point port, a GPIO unit and an optional analog signal port.

[0259] The CPU core 1420 provides a computing unit. The computing unit includes a SNN neuron computing model represented by a function f(x) and an encoder. The CPU core 1420 implements the function f(x) to calculate the timing of outputting neural pulses based on one or more capacitance measurements (at one or more times) provided by the CDC, and the encoder encodes the pulses into AER packets and sends them to the digital router.

[0260] The four CPU cores are directly connected to the digital router respectively, or the digital router is used as an on-chip bus device of the chip, and each CPU core is connected to the digital router through the on-chip bus.

[0261] CPU core 1422 provides a local SNN unit. CPU core 1426 provides a shared SNN unit. CPU core 1424 provides a control unit that drives an external device to perform a specified action in response to receiving an AER packet or other data packet from a digital router. The external device is not part of the R-SpiNNaker chip, but is connected to the R-SpiNNaker chip through GPIO.

[0262] The digital router connects four point-to-point connection ports located in the east, west, south and north directions of the R-SpiNNaker chip. The point-to-point port is used to connect to the point-to-point port of other R-SpiNNaker chips and transmit AER packets. The point-to-point port includes, for example, two leads, and the point-to-point ports communicate with each other through, for example, two leads. Optionally, the CPU core 1424 also provides a digital router.

[0263] The analog signal router establishes a capacitive channel between the CDC and the GPIO and / or analog signal ports. The GPIO is connected to the capacitive port, or some of the GPIO pins are configured to provide a capacitive port. The analog signal router connects four groups of analog signal ports located in the east, west, south and north directions of the R-SpiNNaker chip. The analog signal ports are used to connect to the analog signal ports of other R-SpiNNaker chips and transmit analog signals. Each group of analog signal ports includes, for example, a cross-chip excitation signal line port, a cross-chip mutual capacitance input signal line port and a cross-chip synchronization clock signal line, so that a group of analog signal ports is connected to a group of analog signal ports of another chip through three leads.

[0264] The analog signal router can be configured or programmed. For example, the digital router forwards a data packet to the analog signal router to provide information for configuration or programming. For another example, the CPU core 1424 acts as a control unit to configure or program the analog signal router.

[0265] It is understandable that in other embodiments, the R-SpiNNaker chip may include more or fewer CPU cores, more or fewer CDCs, more or fewer analog signal ports / point-to-point ports. Optionally, the point-to-point interface is replaced by a network port, or the R-SpiNNaker chip includes both a network port and a point-to-point port.

[0266] Still optionally, the R-SpiNNaker chip includes a plurality of capacitor ports, and each group of capacitor ports includes 4 or 5 capacitor ports to facilitate adaptation of the capacitor unit.

[0267] Optionally, the R-SpiNNaker chip further includes a configuration port, which is used to provide configuration information to the computing unit, digital router, CDC, analog signal router, neural unit and / or control unit, and still optionally, to debug the R-SpiNNaker chip or output status information of the R-SpiNNaker chip through the configuration port.

[0268] Fig.15 An R-SpiNNaker system according to yet another embodiment of the present application is demonstrated.

[0269] Fig.15 In the example, the R-SpiNNaker system includes four R-SpiNNaker chips (1510, 1520, 1530 and 1540). R-SpiNNaker chip 1510 has multiple CPU cores and CDC. R-SpiNNaker chips 1520, 1530 and 1540 are different from R-SpiNNaker chip 1510. Optionally, R-SpiNNaker chips 1520, 1530 and 1540 include digital routers, analog signal routers, analog signal ports, capacitor ports and point-to-point ports for providing capacitor plates, transmitting analog signals and forwarding AER packets in the R-SpiNNaker system. R-SpiNNaker chip 1510 is a fully functional R-SpiNNaker chip that can measure capacitance and build SNNs. The R-SpiNNaker chip 1510 can measure capacitance using the capacitor plates connected to all capacitor ports / analog signal ports in the R-SpiNNaker system, and configure the digital routers and analog signal routers of each R-SpiNNaker chip in the R-SpiNNaker system to form a capacitor channel.

[0270] Optionally, R-SpiNNaker chips 1520, 1530, and 1540 include processor cores and provide SNN units (but not CDC). The SNN units of the four R-SpiNNaker chips (1510, 1520, 1530, and 1540) provide SNN neurons and construct one or more SNNs in the R-SpiNNaker system.

[0271] As an example, the capacitor port of the R-SpiNNaker chip is connected to a capacitor unit. The capacitor unit includes, for example, four sector-shaped electrodes forming a circle and one multifunctional electrode. The R-SpiNNaker chip is connected to one capacitor unit via a group of five capacitor ports. Fig.15 In the example, each R-SpiNNaker chip is connected to 2 capacitor units. Each R-SpiNNaker chip also includes 4 analog signal ports and 4 point-to-point ports, which are located in the east, west, south and north directions of the chip. The analog signal ports and point-to-point ports on the east side of R-SpiNNaker chip 1510 are connected to the analog signal ports and point-to-point ports on the west side of R-SpiNNaker chip 1520. The analog signal ports and point-to-point ports on the east side of R-SpiNNaker chip 1530 are connected to the analog signal ports and point-to-point ports on the west side of R-SpiNNaker chip 1540. The analog signal ports and point-to-point ports on the south side of R-SpiNNaker chip 1510 are connected to the analog signal ports and point-to-point ports on the north side of R-SpiNNaker chip 1530. The analog signal ports and point-to-point ports on the south side of R-SpiNNaker chip 1520 are connected to the analog signal ports and point-to-point ports on the north side of R-SpiNNaker chip 1540.

[0272] The digital routers of each R-SpiNNaker chip are connected through point-to-point ports and exchange data packets. The exchanged data packets include, for example, AER packets carrying pulses of SNN neurons, data packets for configuring analog signal routers, and data packets for synchronizing the operation of CDC of each R-SpiNNaker chip.

[0273] Fig.16A A schematic diagram of the SNN constructed in the R-SpiNNaker system according to an embodiment of the present application is shown.

[0274] Fig.16AIn the example, the R-SpiNNaker system includes two R-SpiNNaker chips (1610 and 1620). The shared SNN units of the two chips provide SNN neurons to construct SNN (Spiking Neural Network) 1630. The input layer neurons of SNN 1630 come from the shared SNN unit of R-SpiNNaker chip 1610, the middle layer neurons of SNN 1630 come from the shared SNN unit of R-SpiNNaker chip 1620, and the output layer neurons of SNN 1630 come from the shared SNN units of both R-SpiNNaker chips 1610 and 1620. It can be understood that Fig.16A The source of the SNN neurons of the shown SNN 1630 is for illustrative purposes, and in various embodiments, the SNN neurons of the SNN collaboratively constructed by the R-SpiNNaker systems of the R-SpiNNaker system may come from (the shared SNN units of) any R-SpiNNaker chip of the R-SpiNNaker system.

[0275] The topology of the SNN neurons of SNN 1630 is defined by the routing table of the digital router of the R-SpiNNaker chips (1610 and 1620). In order to provide the output AER packet to another SNN neuron connected to it, an SNN neuron of SNN 1630 needs to provide the output AER packet to the digital router of the chip to which it belongs (for example, 1610), and the digital router forwards the AER packet to the other SNN neuron. When necessary, the digital router also forwards the AER packet through the digital router of another R-SpiNNaker chip (for example, 1620) to provide the AER packet to the SNN neuron located in another R-SpiNNaker chip chip.

[0276] exist Fig.16A In the example, the local neural units of the two R-SpiNNaker chips (1610 and 1620) do not participate in the construction of SNN1630, so as to reserve the required computing resources for the R-SpiNNaker chip itself to complete perception or other applications.

[0277] Fig. 16B A schematic diagram of an SNN constructed in the R-SpiNNaker system according to another embodiment of the present application is shown.

[0278] Fig. 16BIn the figure, the R-SpiNNaker system includes 9 R-SpiNNaker chips (1650, 1652, 1654, 1660, 1662, 1664, 1670, 1672 and 1674) arranged in 3 rows and 3 columns. These R-SpiNNaker chips construct 6 SNNs (1651, 1653, 1655, 1661, 1663 and 1671). Each of these SNNs is an independently working and completed SNN, and they process tasks collaboratively through a hierarchical structure. For example, SNN 1651 is constructed by SNN neurons provided by the local SNN unit of R-SpiNNaker chip 1650, and the AER packets transmitted between neurons inside SNN 1651 are only transmitted inside SpiNNaker chip 1650 through its digital router, and will not be forwarded to the outside of SpiNNaker chip 1650, so as not to affect the network. Fig. 16B The communication bandwidth between other chips of the R-SpiNNaker system is affected. SNN 1651 is used to sense objects detected by, for example, the capacitance value of the capacitor plate connected to SpiNNaker chip 1650 or the CDC output of SpiNNaker chip 1650, such as sensing the appearance, movement speed, material and other specific / clear physical quantities of the object. Similarly, SNN 1653 is constructed by SNN neurons provided by the local SNN unit of R-SpiNNaker chip 1652, and the AER packets transmitted between neurons inside SNN 1653 are only transmitted through its digital router inside SpiNNaker chip 1652. SNN 1655 is constructed by SNN neurons provided by the local SNN unit of R-SpiNNaker chip 1654, and the AER packets transmitted between neurons inside SNN 1655 are only transmitted through its digital router inside SpiNNaker chip 1654.

[0279] SNN 1661 is constructed by SNN neurons provided by the shared SNN unit of R-SpiNNaker chip 1660, and the AER packets transmitted between neurons inside SNN1661 are only transmitted through the digital router inside SpiNNaker chip 1660. SNN1663 is constructed by SNN neurons provided by the shared SNN unit of R-SpiNNaker chips 1662 and 1664, and the AER packets transmitted between neurons inside SNN 1663 are transmitted with the help of the digital routers of SpiNNaker chips 1662 and 1664. SNN 1671 is constructed by SNN neurons provided by the shared SNN unit of R-SpiNNaker chip 1670.

[0280] Optionally, the SNN constructed by the R-SpiNNaker system may be composed of SNN neurons provided by shared SNN units from one or more R-SpiNNaker chips.

[0281] exist Fig. 16B In the embodiment of , SNN (1651, 1653, 1655) is the bottom layer SNN, SNN (1661 and 1663) is the middle layer SNN, and SNN (1671) is the upper layer SNN. Each SNN can be trained independently and outputs a result with clear physical meaning, which is used as the input information of the next layer. Fig. 16B In the example, the middle layer SNN is the next layer relative to the bottom layer SNN, and the upper layer SNN is the next layer relative to the middle layer SNN.

[0282] Multiple SNNs with similar or logically equivalent functions are in the same layer. The physical results output by these SNNs are used as inputs to SNNs at a higher abstraction layer (complete and independent SNNs) according to different abstraction requirements or generalization requirements. The neural networks in each layer and each partition are trained and inferred independently.

[0283] Taking the touch of the robot armored electronic skin as an example, the touch of each part of the right hand (such as the palm, back of the hand and wrist) corresponds to a SNN (1651, 1653 and 1655) respectively. Each SNN outputs a clear touch feature, such as contact or sliding. The touch features of the back of the right hand, palm and wrist are integrated into the touch features of the entire right hand, represented by SNN 1663. The output of SNN (1651, 1653 and 1655) is provided to SNN 1663 as input. SNN 1671 represents the tactile features of the right body of the robot, which receives the input of SNN 1663. By combining abstractions in sequence, the touch cognition of the entire robot is constructed. The biggest advantage of hierarchical computing is to reduce and lower the data communication bandwidth requirements of each layer and each area of ​​the neural network. Transmitting features saves more data communication than transmitting raw data.

[0284] Optionally, the higher the level of SNN, the higher the level of abstraction, and the correspondingly smaller the number of computing resources (such as R-SpiNNaker chips) required.

[0285] Still optionally or further, the transmission of AER packets between the layers of SNN is unidirectional, in the direction of increasing abstraction level. For example, the AER packet representing the output of the bottom layer SNN 1651 is provided to the middle layer SNN 1663, and conversely, the AER packet output by the middle layer SNN 1663 is not provided to the bottom layer SNN.

[0286] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A system comprising a plurality of chips, one or more of which comprises a digital router, an analog signal router and one or more network ports or point-to-point ports; A network port or a point-to-point port of a first chip among the plurality of chips is coupled to a network port or a point-to-point port of a second chip among the plurality of chips; The digital router of the first chip receives a data packet through a network port or a point-to-point port of the chip where the digital router is located; The digital router of the first chip forwards the received data packet carrying the configuration information or programming information of the analog signal router to the analog signal router of the chip where the digital router is located, so as to set one or more switches of the analog signal router of the first chip according to the data of the received data packet carrying the configuration information or programming information of the analog signal router; wherein the data packet carrying the configuration information or programming information of the analog signal router includes data corresponding to the open or closed state of one or more switches of the analog signal router; Each of the plurality of chips further includes a ground port.

2. The system according to claim 1, wherein The digital router of the first chip sends a data packet carrying configuration information or programming information of the analog signal router to one or more of the multiple chips through its network port or point-to-point port.

3. The system according to claim 1 or 2, wherein The first chip of the plurality of chips is further coupled to the network ports or point-to-point ports of other chips of the plurality of chips through other network ports or point-to-point ports.

4. The system according to claim 1, wherein One or more of the plurality of chips further comprises a neural unit, the neural unit coupled to the digital router; The neural unit includes a plurality of neurons; The digital router forwards the received first type data packet indicating a trigger pulse to one or more neurons of the neural unit to the one or more neurons of the neural unit or to the outside of the chip.

5. The system according to claim 4, wherein The neurons of the neural unit generate a first type of data packet and send it to the digital router.

6. The system according to claim 5, wherein The plurality of neurons of the neural unit constitute a spiking neural network.

7. The system according to claim 6, wherein The neural unit includes a first neural unit and a second neural unit; The first neural unit includes a plurality of neurons; The second neural unit includes a plurality of neurons; The first neural unit and the second neural unit are each coupled to a data router of the chip to which they belong; One or more neurons of the first neural unit constitute a first neural network; One or more neurons of the second neural unit constitute a second neural network.

8. The system according to claim 7, wherein One or more neurons of each of the second neural units of one or more chips of the multiple chips together constitute a third neural network.

9. The system according to claim 7, wherein The digital router of the chip to which the neural unit belongs routes the first type of data packet sent by the neurons of the first neural unit to one or more neurons of the first neural unit and / or one or more neurons of the second neural unit; The digital router of the chip to which the neural unit belongs routes the first type of data packet emitted by the neurons of the second neural unit to one or more neurons of the second neural unit and / or to the outside of the chip, but not to any neuron of the first neural unit.

10. The system according to claim 4, wherein: The first type of data packet includes the identification of the chip and / or the identification of the neuron that generates the data packet.

11. The system according to claim 4, wherein: The first type of data packet generated by the first neuron is provided to the digital router; The digital router forwards the first type of data packet to the second neuron according to the address and routing table carried in the received first type of data packet, and the first neuron and the second neuron have a connection relationship in the pulse neural network.

12. The system according to claim 7, wherein The neurons of the first neural unit construct one or more neural networks; The neurons of the second neural unit construct one or more neural networks; The routing table of the digital router defines the topology of the constructed neural network.

13. The system of claim 4, wherein The neural unit is provided by a processor core; The processor core of the neural unit is coupled to the digital router of the chip where the processor core is located to receive the first type of data packet provided by the digital router and / or send the first type of data packet to the digital router.

14. The system of claim 1, wherein One or more of the plurality of chips further comprises a capacitance-to-digital converter; The capacitance-to-digital converter is coupled to an analog signal router of the chip where the capacitance-to-digital converter is located, and the capacitance is measured through the analog signal router of the chip where the capacitance-to-digital converter is located.

15. The system of claim 14, wherein One or more analog signal routers of the plurality of chips cooperate to form a capacitance channel, and a capacitance-to-digital converter measures capacitance through the capacitance channel.

16. The system of claim 14, wherein One or more of the plurality of chips further comprises a computing unit; The computing unit generates a first type of data packet indicating a trigger pulse to one or more neurons of the neural unit according to the measured value of the analog quantity; The computing unit is coupled to a digital router of the chip where the computing unit is located, and the first type of data packet generated by the computing unit is provided to the digital router of the chip where the computing unit is located; The calculation unit receives the measurement value of the analog quantity output by the capacitance-to-digital converter or ADC of the chip where the calculation unit is located.

17. The system of claim 1, wherein One or more of the plurality of chips further comprises one or more analog signal ports; The analog signal port is used to couple with a capacitor plate located outside the chip or an analog signal port of another chip.

18. The system of claim 17, wherein One or more of the plurality of chips further comprises one or more capacitor ports; The capacitor ports are only used to couple capacitor plates that are external to the chip.

19. The system of claim 18, wherein The analog signal router couples at least one analog signal port and / or at least one capacitance port of the chip to which it belongs with the capacitance-to-digital converter of the chip to which it belongs, so that the capacitance-to-digital converter of the chip to which it belongs measures capacitance through at least one analog signal port and / or at least one capacitance port of one or more chips of the system.

20. The system of claim 19, wherein The analog signal router includes a connection line group and an analog switch matrix; The connecting wire group includes at least a first connecting wire and / or a second connecting wire; The analog switch matrix configurably or programmably couples the connection line group to the capacitor port of the chip to which it belongs, wherein at any time, the analog switch matrix couples one capacitor port to at most one connection line of the connection line group, and the analog switch matrix couples one connection line of the connection line group to zero, one or more capacitor ports; The analog switch matrix also configurably or programmably couples the set of connection lines to the capacitance-to-digital converter.

21. The system of claim 20, wherein The analog switch matrix couples the first connection line to the first capacitor port of the chip to which it belongs, couples the second connection line to the second capacitor port of the chip to which it belongs, and couples the first connection line and the second connection line to the capacitance-to-digital converter of the chip to which they belong, so that the capacitance-to-digital converter of the chip to which they belong measures the mutual capacitance formed by the capacitor plate coupled to the first capacitor port and the capacitor plate coupled to the second capacitor port.

22. The system of claim 21, wherein The analog signal router of one or more of the plurality of chips further comprises a set of cross-chip connection wires; The cross-chip connection line group includes at least a first cross-chip connection line; the first cross-chip connection line is coupled with the first connection line of the analog signal router to which it belongs; The analog switch matrix of the analog signal router to which the cross-chip connection line group belongs configurably or programmably couples the cross-chip connection line group to the analog signal port of the chip to which it belongs, wherein at any time, the analog switch matrix of the analog signal router to which the cross-chip connection line group belongs couples at most one analog signal port of the chip to which it belongs to only one connection line of the cross-chip connection line group, and the analog switch matrix of the analog signal router to which the cross-chip connection line group belongs couples one connection line of the cross-chip connection line group to zero, one or more analog signal ports of the chip to which it belongs.

23. The system of claim 22, wherein The cross-chip connection line group includes a first cross-chip connection line and a second cross-chip connection line; The analog switch matrix of the analog signal router to which the cross-chip connection line group belongs couples the first cross-chip connection line and the second cross-chip connection line of the chip to which it belongs to to the analog signal port of the chip to which it belongs respectively; At any time, the analog switch matrix couples an analog signal port to at most one connection line of the cross-chip connection line group of the analog signal router to which it belongs, and the analog switch matrix couples one connection line of the cross-chip connection line group of the analog signal router to which it belongs to zero, one or more analog signal ports of the chip to which it belongs.

24. The system of claim 23, wherein The one or more analog signal ports of the plurality of chips include one or more analog signal ports for first cross-chip connection lines of the chips to which they belong and one or more analog signal ports for second cross-chip connection lines of the chips to which they belong; The analog switch matrix is ​​configured to couple, at any time, an analog signal port of the chip to which it belongs for a first cross-chip connection line to at most only the first cross-chip connection line of the chip to which it belongs, couple an analog signal port of the chip to which it belongs for a second cross-chip connection line to at most only the second cross-chip connection line of the chip to which it belongs, couple the first cross-chip connection line of the chip to which it belongs to zero, one or more analog signal ports for the first cross-chip connection line, and couple the second cross-chip connection line of the chip to which it belongs to zero, one or more analog signal ports for the second cross-chip connection line.

25. The system of claim 24, wherein The cross-chip connection line group also includes a cross-chip synchronous clock signal line; The cross-chip synchronous clock signal line is coupled with the analog signal port of the chip to which it belongs.

26. The system of claim 1, wherein One or more of the plurality of chips further comprises a control unit; The control unit is coupled to a digital router of the chip to which it belongs; The control unit generates a driving signal for a device outside the chip to which it belongs according to the first type of data packets forwarded by the digital router.

27. The system of claim 17, wherein A first analog signal port of the first chip is coupled to a second analog signal port of the second chip; The digital router of the second chip receives a data packet carrying configuration information or programming information of the analog signal router through its network port or point-to-point port; The first chip sets an analog switch matrix of the first chip according to data of a data packet carrying configuration information or programming information of an analog signal router to couple a first inter-chip connection line (IAE) or a second inter-chip connection line (IAC) of the first chip with a first analog signal port of the first chip; The second chip sets an analog switch matrix of the second chip according to data of a data packet carrying configuration information or programming information of the analog signal router to couple a first inter-chip connection line (IAE) or a second inter-chip connection line (IAC) of the second chip with a second analog signal port of the second chip; The first inter-chip connection line (IAE) or the second inter-chip connection line (IAC) of the first chip is coupled with the first inter-chip connection line (IAE) or the second inter-chip connection line (IAC) of the second chip accordingly.

28. The system of claim 17, wherein One or more chips of a first plurality of chips of the plurality of chips are each coupled to one or more other chips of the first plurality of chips via an analog signal port thereof; The digital routers of the first plurality of chips of the plurality of chips receive a data packet carrying configuration information or programming information of the analog signal router, and set their analog switch matrices according to the received data packets carrying configuration information or programming information of the analog signal router to couple their first inter-chip connection lines (IAE) or second inter-chip connection lines (IAC) with the analog signal ports of the chips to which they belong, so that the first inter-chip connection lines (IAE) or second inter-chip connection lines (IAC) of the first plurality of chips are correspondingly coupled with the first inter-chip connection lines (IAE) or second inter-chip connection lines (IAC) of one or more other chips of the first plurality of chips.

29. The system of claim 1, wherein The analog signal router includes an analog routing controller and an analog switch matrix, wherein the analog routing controller couples multiple switches of the analog switch matrix and controls the opening or closing of multiple switches of the analog switch matrix; In response to receiving a data packet carrying configuration information or programming information of an analog signal router, an analog routing controller is set according to data of the data packet carrying configuration information or programming information of the analog signal router to control the opening or closing of one or more switches of an analog switch matrix of the analog signal router to which it belongs.

30. The system of claim 29, wherein Analog routing controller register bank, sequential state controller and selector; The register set comprises a plurality of registers, wherein a value of each bit of each register of the plurality of registers indicates an opening or closing of one of the switches of the analog switch matrix; The output of the sequential state controller controls the selector to select one of the plurality of registers as the output of the analog routing controller; In response to receiving a data packet carrying configuration information or programming information of the analog signal router, a register set and a sequential state controller of the analog routing controller are set according to data of the data packet carrying configuration information or programming information of the analog signal router.

31. The system of claim 30, wherein In response to the sequential state controller being set with a state sequence, starting to select one of the plurality of registers as an output of the analog routing controller according to each state of the state sequence; or In response to the cross-chip synchronization clock signal or the first type of data packet indicating the start, the sequential state controller starts selecting one of the plurality of registers as the output of the analog routing controller according to each state of the state sequence.

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