Semiconductor device package and method of manufacturing the same

Abstract

The present disclosure relates to a semiconductor device package and a manufacturing method thereof. The semiconductor device package has an antenna. The antenna includes a first dielectric layer, a first conductive layer and a second dielectric layer. The first dielectric layer has a first surface and a second surface opposite to the first surface. The first conductive layer is located on the first surface of the first dielectric layer. The first conductive layer has a feed-in terminal. The second dielectric layer is located on the first dielectric layer. The second dielectric layer covers a portion of the first conductive layer and exposes the feed-in terminal of the first conductive layer.

Description

Technical Field

[0001] The present disclosure generally relates to a semiconductor device package and a method of manufacturing the same, and to a semiconductor device package including an antenna. Background Art

[0002] Wireless communication devices such as mobile phones usually include antennas for transmitting and receiving radio frequency (RF) signals. In recent years, with the continuous development of mobile communications and the urgent need for high data rates and stable communication quality, relatively high-frequency wireless transmission (e.g., 28 GHz or 60 GHz) has become one of the most important issues in the mobile communications industry.

[0003] As wireless communication applications increase, the radiation directions of frequency setting signals also increase. For example, frequency setting signals can be emitted from various directions (such as vertical or horizontal directions) of a communication device to increase the applicability of the communication device. Therefore, how to design an antenna module with horizontally transmitted signals is an important topic of the present disclosure. Summary of the invention

[0004] In one or more embodiments, an antenna includes a first dielectric layer, a first conductive layer, and a second dielectric layer. The first dielectric layer has a first surface and a second surface opposite to the first surface. The first conductive layer is located on the first surface of the first dielectric layer. The first conductive layer has a feeding end. The second dielectric layer is located on the first dielectric layer. The second dielectric layer covers a portion of the first conductive layer and exposes the feeding end of the first conductive layer.

[0005] In one or more embodiments, a semiconductor device package includes a substrate, an antenna structure and a package body. The antenna structure is located on the substrate. The antenna structure has a first antenna pattern and a second antenna pattern separated from the first antenna pattern. The distance between the first antenna pattern and the substrate is greater than the distance between the second antenna pattern and the substrate. The package body is located on the substrate and covers the antenna structure.

[0006] In one or more embodiments, a method for manufacturing an antenna includes: (a) forming a first dielectric layer; (b) forming a plurality of first conductive layers on the first dielectric layer, wherein each first conductive layer is separated from each other; (c) forming a second dielectric layer on the first dielectric layer, wherein the second dielectric layer covers a portion of each first conductive layer and exposes a feed end of each first conductive layer; and (d) performing a singulation process to separate the first dielectric layer and the second dielectric layer between two adjacent first conductive layers. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] When read together with the accompanying drawings, the various aspects of the present disclosure can be easily understood from the following detailed description. It should be noted that the various features may not necessarily be drawn to scale. For the sake of clarity of discussion, the size of the various features may be arbitrarily increased or reduced.

[0008] Figure 1A A cross-sectional view of a semiconductor device package according to some embodiments of the present disclosure is shown.

[0009] Figure 1B Some embodiments of the present disclosure are shown Figure 1A An enlarged schematic diagram of the antenna is shown.

[0010] Figure 1C Some embodiments of the present disclosure are shown Figure 1A Top view of the substrate.

[0011] Figure 1D Some embodiments of the present disclosure are shown Figure 1A Front view of the area enclosed by the dotted box.

[0012] Figure 1E Some embodiments of the present disclosure are shown Figure 1A Dorsal view of the area enclosed by the dotted box.

[0013] Figure 1F Some embodiments of the present disclosure are shown Figure 1A Cross-sectional view of the area enclosed by the dashed box.

[0014] Figure 1G Some embodiments of the present disclosure are shown Figure 1A Cross-sectional view of the area enclosed by the dashed box.

[0015] Figure 1H Some embodiments of the present disclosure are shown Figure 1A Cross-sectional view of the area enclosed by the dashed box.

[0016] Figure 2A Some embodiments of the present disclosure are shown Figure 1A A front view of the antenna is shown.

[0017] Figure 2B Some embodiments of the present disclosure are shown Figure 1A A front view of the antenna is shown.

[0018] Figure 2C Some embodiments of the present disclosure are shown Figure 1A Back view of the antenna shown.

[0019] Figure 2D Some embodiments of the present disclosure are shown Figure 1A Back view of the antenna shown.

[0020] Figure 2E Some embodiments of the present disclosure are shown Figure 1A Back view of the antenna shown.

[0021] Figure 3 A cross-sectional view of a semiconductor device package according to some embodiments of the present disclosure is shown.

[0022] Figure 4A , Figure 4B , Figure 4C , Figure 4D , Figure 4E , Figure 4F , Figure 4G , Figure 4H , Fig. 4I and Figure 4J One or more stages of a method of manufacturing a semiconductor device package according to some embodiments of the present disclosure are presented.

[0023] Figure 5A , Figure 5B , Figure 5C , Figure 5D , Figure 5E , Fig. 5F , Figure 5G , Figure 5H and Fig.5I One or more stages of a method of manufacturing a semiconductor device package according to some embodiments of the present disclosure are presented.

[0024] Fig. 6A and Figure 6B One or more stages of a method of manufacturing a semiconductor device package according to some embodiments of the present disclosure are presented.

[0025] Fig. 7A , Figure 7B and Figure 7C One or more stages of a method of manufacturing a semiconductor device package according to some embodiments of the present disclosure are presented.

[0026] Throughout the drawings and detailed description, common reference numerals are used to indicate the same or similar components. The present disclosure will become more apparent from the following detailed description taken in conjunction with the accompanying drawings. DETAILED DESCRIPTION

[0027] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and arrangements are described below. Of course, these are merely examples and are not intended to be restrictive. In the present disclosure, references to forming a first feature on or on a second feature may include embodiments in which the first feature and the second feature are formed to be in direct contact, and may also include embodiments in which additional features may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat reference numerals and / or letters in various examples. This repetition is for simplicity and clarity and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0028] The following is a detailed discussion of embodiments of the present disclosure. However, it should be understood that the present disclosure provides many applicable concepts that can be embodied in a variety of specific contexts. The specific embodiments discussed are merely illustrative and do not limit the scope of the present disclosure.

[0029] Figure 1A A schematic diagram of a semiconductor device package 1 according to some embodiments of the present disclosure is shown. The semiconductor device package 1 includes a substrate 10, an electronic component 11, an antenna 12 and a package body 13.

[0030] The substrate 10 may be, for example, a printed circuit board, such as a paper-based copper foil laminate, a composite copper foil laminate, or a polymer-impregnated glass fiber-based copper foil laminate. In some embodiments, the substrate 10 may be a multilayer substrate including a core layer and a conductive material and / or structure. For example, the substrate 10 includes a core portion and may be of a wafer type, a panel type, or a strip type.

[0031] The electronic component 11 is placed on the substrate 10 and electrically connected to the substrate 10, and the electrical connection can be achieved by flip chip or wire bonding technology. The electronic component 11 can be a chip or a tube die, and the chip or tube die includes a semiconductor substrate, one or more integrated circuit devices and one or more overlying interconnect structures therein. The integrated circuit device can include active devices such as transistors and / or passive devices such as resistors, capacitors, inductors, etc. or a combination thereof.

[0032] One or more antennas 12 are disposed on the substrate 10 and electrically connected to the substrate 10. In some embodiments, the semiconductor device package 1 may include N antennas, where N is a positive integer greater than 1. In some embodiments, the antenna 12 may be disposed along one or more edges of the substrate 10. Figure 1A Only four antennas 12 are shown disposed on one edge of the substrate 10. However, according to different design requirements, each edge of the substrate 10 may include the same or different numbers of antennas 12. In some embodiments, the antenna 12 may be or may include a patch antenna or other types of antennas.

[0033] Figure 1B Some embodiments of the present disclosure are shown Figure 1A An enlarged schematic diagram of the antenna 12 is shown. Figure 1C Shown Figure 1A A top view of a substrate 10 is shown. Figure 1D Shown Figure 1A Front view of the area enclosed by the dotted box A (along the Figure 1A DY direction as shown). Figure 1E Shown Figure 1A Back view of the area enclosed by the dotted box A (along the Figure 1A in the opposite direction of DY as shown). Figure 1F Demonstrates some embodiments of the Figure 1A Cross-sectional view of the dotted box A (along Figure 1A DX direction as shown). Figure 1G Demonstrates some embodiments of the Figure 1A Cross-sectional view of the dotted box A (along Figure 1A DX direction as shown). Figure 1H Demonstrates some embodiments of the Figure 1A Cross-sectional view of the dotted box A (along Figure 1A DX direction as shown).

[0034] like Figure 1B , 1C As shown in Figures 1D, 1E, 1F, 1G and 1H, the antenna 12 may include a packaging body 12m, conductive layers 12c1 and 12c2, dielectric layers 12d1, 12d2, 12d3, 12d4 and seed layers 12s1 and 12s2.

[0035] In some embodiments, the encapsulation body 12m includes epoxy resin with filler, molding material (such as epoxy molding material or other molding material), polyimide, phenolic compound or material, material with silicone dispersed therein, or a combination thereof.

[0036] The dielectric layers 12d1 and 12d3 are located on opposite surfaces of the package body 12m and are in contact with the surfaces respectively. In other words, the package body 12m is sandwiched between the dielectric layers 12d1 and 12d3. The dielectric layer 12d2 is located on the surface of the dielectric layer 12d1 facing away from the package body 12m. The dielectric layer 12d4 is located on the surface of the dielectric layer 12d3 facing away from the package body 12m. The dielectric layers 12d1, 12d2, 12d3, 12d4 may include pre-impregnated composite fibers (e.g., prepregs), borophosphosilicate glass (BPSG), silicon oxide, silicon nitride, silicon oxynitride, undoped silicate glass (USG), any combination of two or more thereof, and the like. Examples of prepregs may include, but are not limited to, multilayer structures formed by stacking or laminating a variety of prepreg materials / sheets.

[0037] In some embodiments, the roughness of the surface of the dielectric layer 12d1 facing away from the substrate 10 is different from the roughness of the surface of the dielectric layer 12d1 in contact with the dielectric layer 12d2. In some embodiments, the roughness of the surface of the dielectric layer 12d2 facing away from the substrate 10 is different from the roughness of the surface of the dielectric layer 12d2 and the surface of the dielectric layer 12d2 facing away from the dielectric layer 12d1. In some embodiments, the roughness of the surface of the dielectric layer 12d4 facing away from the substrate 10 is different from the roughness of the surface of the dielectric layer 12d4 facing away from the dielectric layer 12d3. In some embodiments, the roughness of the surface of the dielectric layer 12d3 facing away from the substrate 10 is different from the roughness of the surface of the dielectric layer 12d3 in contact with the dielectric layer 12d4.

[0038] The conductive layer 12c1 is covered by the dielectric layer 12d1. In some embodiments, the seed layer 12s1 is located between the conductive layer 12c1 and the dielectric layer 12d2. In other words, the conductive layer 12c1 and the dielectric layer 12d2 are separated from each other by the seed layer 12s1. The seed layer 12s1 is in contact with the dielectric layer 12d2. The conductive layer 12c2 is at least partially covered by the dielectric layer 12d4. In some embodiments, the seed layer 12s2 is located between the conductive layer 12c2 and the dielectric layer 12d3. In other words, the conductive layer 12c2 and the dielectric layer 12d3 are separated from each other by the seed layer 12s2. The seed layer 12s2 is in contact with the dielectric layer 12d3. The conductive layer 12c1 and the conductive layer 12c2 are electrically connected to the conductive layer 10c exposed from the dielectric layer 10d in the substrate 10 through the conductive structure 10s (such as a solder ball). Specifically, the dielectric layer 10d of the substrate 10 may define one or more openings to expose a portion of the conductive layer 10c. The conductive structure 10s is filled in the openings and contacts the conductive layer 10c to electrically connect the conductive layer 12c1 and the conductive layer 12c2 to the conductive layer 10c.

[0039] In some embodiments, the conductive layers 12c1, 12c2 are or include conductive materials such as metals or metal alloys. Examples of conductive materials include gold (Au), silver (Ag), copper (Cu), platinum (Pt), palladium (Pd), one or more other metals or one or more alloys or a combination of two or more thereof. Any number of dielectric layers and conductive layers may exist according to different design specifications.

[0040] In some embodiments, Figure 1F As shown, the dielectric layer 12d2 has a shorter length than the dielectric layer 12d1 to expose a portion of the seed layer 12s1 and the conductive layer 12c1. Similarly, the dielectric layer 12d4 has a shorter length than the dielectric layer 12d3 to expose a portion of the seed layer 12s2 and the conductive layer 12c2. In other words, the dielectric layer 12d4 (or the dielectric layer 12d2) and the dielectric layer 12d3 (or the dielectric layer 12d1) define a groove 12r to expose a portion of the seed layer 12s2 (or the seed layer 12s1) and the conductive layer 12c2 (or the conductive layer 12c1). The conductive structure 10s can cover the exposed surfaces of the conductive layers 12c1, 12c2 (or the seed layers 12s1, 12s2).

[0041] In some embodiments, Figure 1B As shown, the conductive layers 12c1 and 12c2 exposed outside the dielectric layer (such as the dielectric layers 12d2 and 12d4) and the structure connecting the conductive layers 12c1 and 12c2 (which may include the dielectric layers 12d1, 12d3 and the package body 12m) may define a "T" shaped structure. For example, the width of the exposed conductive layer 12c2 is less than the width of the exposed conductive layer 12c1. For example, the width of the exposed conductive layer 12c2 is less than or equal to the width of the structure connecting the conductive layers 12c1 and 12c2. In some embodiments, the width of the exposed conductive layer 12c1 is less than the width of the dielectric layer 12d4. In some embodiments, a portion of the conductive layer 12c2 exposed outside the dielectric layer 12d4 may be a feed-in terminal. In other words, the side surface of the feed-in terminal is exposed outside the dielectric layer 12d4.

[0042] like Figure 1C As shown, the dielectric layer 10d of the substrate 10 has a groove to expose a portion of the conductive layer 10c. Figure 1C The groove (and the shape of the exposed conductive layer 10c) shown in FIG. Figure 1B The "T" structures shown correspond to each other. For example, Figure 1C The groove and the exposed conductive layer 10c are in a "T" shape, and their dimensions are similar to those of the Figure 1B The "T" structure shown is similar or slightly larger to accommodate Figure 1B The "T" knot shown. In other words, Figure 1B The "T" knot shown can be inserted into Figure 1C The groove of the substrate 10 is shown to be connected to the conductive layer 10 c of the substrate 10 , thereby increasing the stability of the connection between the antenna 12 and the substrate 10 .

[0043] Figure 1B The antenna 12 is drawn with Figure 1C The substrate 10 shown in FIG. Figure 1D and Figure 1E .like Figure 1D As described above, the feed end of the conductive layer 12c2 exposed outside the dielectric layer 12d4 is inserted (or embedded) into the groove defined by the dielectric layer 10d of the substrate 10 (eg, Figure 1C In some embodiments, the feed-in terminal of the conductive layer 12c2 exposed outside the dielectric layer 12d4 can directly contact the conductive layer 10c exposed from the dielectric layer 10d in the substrate 10.

[0044] like Figure 1E As described above, a portion of the conductive layer 12c1 exposed outside the dielectric layer 12d2 is inserted (or embedded) into the groove defined by the dielectric layer 10d of the substrate 10 (eg, Figure 1C In some embodiments, a portion of the conductive layer 12c1 exposed outside the dielectric layer 12d2 may be in direct contact with the conductive layer 10c exposed from the dielectric layer 10d in the substrate 10.

[0045] In some embodiments, Figure 1D and 1E As shown in FIG. 1 (which shows the top view and the bottom view of the antenna 12 respectively), the shapes or areas of the conductive layers 12c1 and 12c2 of the antenna 12 are different. Figure 1D , the shape of the conductive layer 12c2 may be a "T" shape. In other words, the conductive layer 12c2 may include two portions having different widths. In some embodiments, the portion having the smaller width may be or may include the feed end 12cf of the antenna 12. Figure 1E , the shape of the conductive layer 12c1 may be a rectangle. In other words, the conductive layer 12c1 has a single width. In different embodiments, according to different design requirements, the conductive layer 12c1 and the conductive layer 12c2 may have other arbitrary shapes.

[0046] In some embodiments, the conductive layer 12c2 may be or may include an antenna layer (or a radiation layer) for transmitting and receiving electromagnetic waves (or wireless signals). The conductive layer 12c1 may be or may include a ground layer. Electromagnetic waves may be transmitted and received in a direction perpendicular to the conductive layer 12c2. For example, referring to Figure 1A , the antenna 12 transmits and receives electromagnetic waves in a direction opposite to the direction DY. Therefore, according to the embodiment of the present disclosure, the semiconductor device package 1 can transmit and receive electromagnetic waves in a direction horizontal to the substrate 10.

[0047] In some embodiments, Figure 1A The antenna 12 in the embodiment can be replaced by a via wall formed by a plurality of conductive vias. For example, a plurality of conductive vias can be formed in a substrate, and the substrate can be vertically connected to the substrate 10 to achieve horizontal radiation or lateral radiation (i.e., in a direction parallel to the surface of the substrate 10). However, due to the limitation of the manufacturing process (e.g., the process of etching the substrate to form an opening and filling the opening to form a conductive via), the conductive via has a relatively large roughness (about 10 microns to 20 microns), which will cause a large loss to the antenna, thereby affecting the antenna radiation performance.

[0048] According to the present disclosure Figure 1A to Figure 1H In an embodiment of the present invention, the roughness of the surface of the antenna layer (such as the conductive layer 12c2) facing away from the dielectric layer 12d3 is less than 1 micron, which will greatly reduce the loss of the antenna and thus improve the antenna radiation performance. In addition, due to process reasons (the relevant process will be described in detail later), it is easier to control the shape and area of ​​the conductive layer 12c2, and it is also easier to control the impedance of the antenna. In addition, in an embodiment of the present disclosure, the distance between the antenna layer (such as the conductive layer 12c2) and the ground layer (such as the conductive layer 12c1) of the antenna 12 can be controlled by the thickness of the package 12m. Compared to using a dielectric layer, it is easier to control the thickness of the package 12m, so the distance between the antenna layer and the ground layer of the antenna 12 can be more precise.

[0049] Back to Figure 1A , a package body 13 is disposed on the substrate 10. The package body 13 covers the electronic component 11 and the antenna 12. In some embodiments, the package body 13 includes an epoxy resin having a filler dispersed therein.

[0050] In some embodiments, Figure 1H As shown, the dielectric layer 12d2 (and the dielectric layer 12d4) and the dielectric layer 12d1 (and the dielectric layer 12d3) have substantially the same length. In other words, the seed layer 12s1 and the conductive layer 12c1 (and the seed layer 12s2 and the conductive layer 12c2) are completely covered by the dielectric layer 12d2 (and the dielectric layer 12d4). Figure 1F The structure shown, Figure 1B and Figure 1F Parts of the conductive layers 12c1 and 12c2 are exposed from the dielectric layer 12d2 and the dielectric layer 12d4 respectively, so as to increase the contact area between the conductive structure 10s and the conductive layers 12c1 and 12c2, thereby increasing the stability of the electrical connection between the antenna 12 and the substrate 10.

[0051] Figure 1G Some embodiments of the present disclosure are shown Figure 1A An enlarged schematic diagram of the antenna 12 is shown. Figure 1G The structure shown is Figure 1F The structures shown are similar, the only difference being that Figure 1G A portion of the dielectric layer 10d' of the substrate 10 in the embodiment has a recess. Specifically, the dielectric layer 10d' of the substrate 10 located below the antenna 12 is recessed downward compared to other dielectric layers of the substrate 10. In other words, the dielectric layer 10d' of the substrate 10 located below the antenna 12 and the adjacent dielectric layers define a groove. Figure 1G As shown, a portion of the antenna 12 is disposed in the groove, and the dielectric layers 12d2 and 12d4 of the antenna 12 are engaged with the corners of the groove. This can fix the antenna 12 and prevent the antenna 12 from tilting during the manufacturing process.

[0052] Figure 2A Some embodiments of the present disclosure are shown Figure 1A The front view of the antenna 12 is shown (along the Figure 1A According to some embodiments of the present disclosure, Figure 2A Shown Figure 1F A front view of antenna 12 is shown. Figure 2A The antenna shown has a feeding terminal 22 p 1 which can be electrically connected to the substrate 10 .

[0053] Figure 2B Other embodiments according to the present disclosure are shown Figure 1A The front view of the antenna 12 is shown (along the Figure 1A DX direction as shown). Figure 2B The antenna shown is Figure 2A The antennas shown are similar and differ only in that Figure 2B The antenna shown further has conductive pads 22p2 and 22p3, which are respectively located on both sides of the feeding end 22p1. The feeding end 22p1 and the conductive pads 22p2 and 22p3 are separated from each other. In some embodiments, the conductive pads 22p2 and 22p3 are dummy pads. In some embodiments, the conductive pads 22p2 and 22p3 can be grounded.

[0054] Figure 2C Some embodiments of the present disclosure are shown Figure 1A The rear view of the antenna 12 is shown (along the Figure 1A opposite direction of DX shown). Figure 2C The antenna shown is Figure 1E The antennas shown are similar and differ only in that Figure 2CThe width of the exposed portion 22p4 (also referred to as "conductive pad 22p4") of the conductive layer 12c1 of the antenna shown from the dielectric layer 12d2 is less than the width of the conductive layer 12c1.

[0055] Figure 2D Shows a Figure 1A rear view of the antenna 12 shown (along the Figure 1A opposite direction of the DX shown). Figure 2D The antenna shown and Figure 2C the antenna shown are similar, except that Figure 2D the antenna shown further has conductive pads 22p5 and 22p6, which are respectively located on both sides of the conductive pad 22p4. The conductive pads 22p4, 22p5, and 22p6 are separated from each other.

[0056] Figure 2E Shows a Figure 1A rear view of the antenna 12 shown (along the Figure 1A opposite direction of the DX shown). Figure 2E The antenna shown and Figure 2C the antenna shown are similar, except that Figure 2E the antenna shown has a continuous conductive pad 22p8, which can provide a larger grounding area. In other words, the width of the conductive pad 22p8 is substantially the same as the width of the conductive layer 12c1.

[0057] In some embodiments of the present disclosure, as Figure 1A the antenna 12 shown may have a front view as Figure 2A or Figure 2B shown, and may also have a rear view as Figure 2C , Figure 2D or Figure 2E shown. For example, the front view of the antenna 12 may have a structure as Figure 2B shown, and the rear view of the antenna 12 may have a structure as Figure 2D shown. In this embodiment, the conductive pads 22p1, 22p2, and 22p3 may be respectively aligned with the feeding terminals 22p1, the conductive pad 22p5, and 22p6.

[0058] Figure 3 Shows a schematic diagram of a semiconductor device package 3 according to some embodiments of the present disclosure. The semiconductor device package 3 is similar to Figure 1A the semiconductor device package 1 shown, and the difference is that Figure 1A the antenna portion of Figure 3The antenna portion includes only one antenna structure 32, and the antenna structure 32 may have a plurality of antenna patterns 32a, 32b, 32c, and 32d.

[0059] The antenna structure 32 may have a package body (eg Figure 1F The package body 12m shown in FIG. 1 is provided with antenna patterns 32a, 32b, 32c, and 32d disposed on a surface of the package body (eg, Figure 1F Conductive layer 12c2 shown). In some embodiments, antenna patterns 32a, 32b, 32c, 32d are separated from each other and electrically connected to substrate 10. In some embodiments, antenna patterns 32a, 32b, 32c, 32d may have the same or different levels. For example, antenna patterns 32a and 32c have the same level. Antenna patterns 32b and 32d have the same level. Antenna patterns 32a, 32c have different levels from antenna patterns 32b and 32d. In other words, the distance between antenna patterns 32a and 32c and substrate 10 is less than the distance between antenna patterns 32b and 32d and substrate 10. In some embodiments, antenna pattern 32a at least partially overlaps or completely overlaps with antenna pattern 32b in a direction perpendicular to substrate 10. In some embodiments, antenna pattern 32c does not overlap with antenna pattern 32d at all in a direction perpendicular to substrate 10. This can increase the flexibility of antenna structure 32 design and its applicability.

[0060] Figure 4A , Figure 4B , Figure 4C , Figure 4D , Figure 4E , Figure 4F , Figure 4G , Figure 4H , Fig. 4I and Figure 4J are cross-sectional views of semiconductor device packages at various stages of fabrication according to some embodiments of the present disclosure. At least some of these drawings have been simplified to provide a better understanding of features of the present disclosure.

[0061] refer to Figure 4A , providing a carrier 49. The carrier 49 may have a connection layer 49h. In some embodiments, the connection layer 49h may be or may include glue, tape, an adhesive metal layer, etc.

[0062] refer to Figure 4B , the conductive layer 12c1 is formed on the carrier 49 and connected to the carrier 49 via the connecting layer 49h. In some embodiments, the conductive layer 12c1 can be formed by electroplating or other suitable methods. The pattern of the conductive layer 12c1 can be defined by photoresist. After the patterned conductive layer 12c1 is formed, the photoresist is removed.

[0063] refer to Figure 4C , a dielectric layer 12d1 is formed on the carrier 49 to cover the conductive layer 12c1.

[0064] refer to Figure 4D The package body 12m is formed on the dielectric layer 12d1. The package body 12m may be formed by a molding technique such as transfer molding, compression molding, or any other suitable process.

[0065] refer to Figure 4E , a dielectric layer 12d3 is formed on the package body 12m.

[0066] refer to Figure 4F , the conductive layer 12c2 is formed on the dielectric layer 12d3. In some embodiments, before forming the conductive layer 12c2, a seed layer 12s2 may be formed first, and then the conductive layer 12c2 may be formed on the seed layer 12s2. The conductive layer 12c2 may be formed by electroplating or other suitable methods. The pattern of the conductive layer 12c2 may be defined by a photoresist. After forming the patterned conductive layer 12c2, the photoresist is removed.

[0067] refer to Figure 4G , a dielectric layer 12d4 is formed on the dielectric layer 12d3 and covers the conductive layer 12c2.

[0068] refer to Figure 4H , remove the carrier 49 and the connection layer 49h to expose the conductive layer 12c1 and the dielectric layer 12d1. In some embodiments, the connection layer 49h can be removed by etching or other suitable methods.

[0069] refer to Fig. 4I , a dielectric layer 12d2 is formed on the exposed conductive layer 12c1 and the dielectric layer 12d1.

[0070] refer to Figure 4J , a singulation process may be performed to separate the individual antennas. That is, the singulation process is performed through the dielectric layers 12d1, 12d2, 12d3, 12d4 and the package body 12m. The singulation process may be performed, for example, by using a dicing machine, a laser, or other suitable cutting technique. In some embodiments, Figure 4J The antenna and Figure 1H The antennas shown in are similar, the only difference is that Figure 4J The antenna does not include Figure 1H Seed layer 12s1 is shown.

[0071] Figure 5A , Figure 5B , Figure 5C , Figure 5D , Figure 5E , Fig. 5F , Figure 5G and Figure 5Hare cross-sectional views of semiconductor device packages at various stages of fabrication according to some embodiments of the present disclosure. At least some of these drawings have been simplified to provide a better understanding of features of the present disclosure.

[0072] refer to Figure 5A , providing a carrier 59. The carrier 59 may have a connection layer 59h. In some embodiments, the connection layer 59h may be or may include glue, tape, an adhesive metal layer, etc. The dielectric layer 12d2 is formed on the carrier 59 and connected to the carrier 59 via the connection layer 59h. The seed layer 12s1 is then formed on the dielectric layer 12d2.

[0073] refer to Figure 5B , the conductive layer 12c1 is formed on the seed layer 12s1. In some embodiments, the conductive layer 12c1 can be formed by electroplating or other suitable methods. The pattern of the conductive layer 12c1 can be defined by photoresist. After the patterned conductive layer 12c1 is formed, the photoresist is removed. Then, the seed layer not covered by the conductive layer 12c1 can be removed by etching or other suitable methods.

[0074] refer to Figure 5C , a dielectric layer 12d1 is formed on the dielectric layer 12d2 to cover the conductive layer 12c1.

[0075] refer to Figure 5D The package body 12m is formed on the dielectric layer 12d1. The package body 12m may be formed by a molding technique such as transfer molding, compression molding, or any other suitable process.

[0076] refer to Figure 5E , a dielectric layer 12d3 is formed on the package body 12m.

[0077] refer to Figure 5E , the conductive layer 12c2 is formed on the dielectric layer 12d3. In some embodiments, before forming the conductive layer 12c2, a seed layer 12s2 may be formed first, and then the conductive layer 12c2 may be formed on the seed layer 12s2. The conductive layer 12c2 may be formed by electroplating or other suitable methods. The pattern of the conductive layer 12c2 may be defined by a photoresist. After forming the patterned conductive layer 12c2, the photoresist is removed.

[0078] refer to Figure 5G , a dielectric layer 12d4 is formed on the dielectric layer 12d3 and covers the conductive layer 12c2.

[0079] refer to Figure 5H , remove the carrier 59 and the connection layer 59h to expose the dielectric layer 12d2. In some embodiments, the connection layer 59h can be removed by etching or other suitable methods.

[0080] refer to Fig.5I , a singulation process may be performed to separate the individual antennas. That is, the singulation process is performed through the dielectric layers 12d1, 12d2, 12d3, 12d4 and the package body 12m. The singulation process may be performed, for example, by using a dicing machine, a laser, or other suitable cutting technique. In some embodiments, Fig.5I The antenna and Figure 1H The antenna is the same as shown in FIG.

[0081] Fig. 6A and Figure 6B are cross-sectional views of semiconductor device packages at different stages of manufacture according to some embodiments of the present disclosure. At least some of these drawings have been simplified to facilitate a better understanding of aspects of the present disclosure. In some embodiments, Fig. 6A The steps can be found in Figure 5H Then execute.

[0082] refer to Fig. 6A , a portion of the dielectric layer 12d4 is removed to form a groove 12r to expose a portion of the conductive layer 12c2. Similarly, a portion of the dielectric layer 12d2 is removed to form a groove 12r1 to expose a portion of the seed layer 12s1 and the conductive layer 12c1.

[0083] refer to Figure 6B , a singulation process may be performed to separate the individual antennas. That is, the singulation process is performed through the dielectric layers 12d1, 12d2, 12d3, 12d4 and the package body 12m. The singulation process may be performed, for example, by using a dicing machine, a laser, or other suitable cutting technique. In some embodiments, Figure 6B The antenna and Figure 1F The antenna is the same as shown in FIG.

[0084] As disclosed in this 4A to 6B As shown, the antenna layer of the antenna structure is defined by a patterned conductive layer (such as conductive layer 12c2). Since the conductive layer 12c2 is completed by a lithography process. For example, the pattern of the conductive layer 12c2 can be defined by photoresist, and the conductive layer 12c2 can be formed by electroplating or other suitable methods. Since the pattern, shape, and area of ​​the conductive layer 12c2 are easier to control, the flexibility in the antenna pattern design can be increased. In addition, the conductive layer 12c2 formed by the lithography process has a lower roughness (less than 1 micron), so using the conductive layer 12c2 as the antenna pattern will greatly reduce the antenna loss, thereby increasing the radiation efficiency of the antenna.

[0085] Fig. 7A , Figure 7B and Figure 7Cis a schematic diagram of a semiconductor device package at different stages of manufacture according to some embodiments of the present disclosure. At least some of these drawings have been simplified to facilitate a better understanding of aspects of the present disclosure. According to some embodiments of the present disclosure, Fig. 7A , Figure 7B and Figure 7C The steps shown can be used to make Figure 1A A semiconductor device package 1 is shown.

[0086] refer to Fig. 7A , providing a substrate 10. The substrate 10 may be, for example, a printed circuit board, such as a paper-based copper foil laminate, a composite copper foil laminate, or a polymer-impregnated glass fiber-based copper foil laminate. In some embodiments, the substrate 10 may be a multilayer substrate including a core layer and a conductive material and / or structure. For example, the substrate 10 includes a core portion and may be of a wafer type, a panel type, or a strip type.

[0087] One or more antennas 12 are placed on the substrate 10. The antennas 12 may be placed along one or more edges of the substrate 10. The antennas 12 may be connected to the substrate 10 by surface mount technology (SMT) or other techniques. In some embodiments, the antennas 12 may be or may include: Figure 4J , Fig.5I or Figure 6B The antenna structure shown.

[0088] refer to Figure 7B , the electronic component 11 is placed on the substrate 10 and electrically connected to the substrate 10. In some embodiments, the electronic component 11 can be electrically connected to the substrate 10 by flip chip, bonding wire or other methods.

[0089] refer to Figure 7C The package body 13 is formed on the substrate 10 to cover the antenna 12 and the electronic component 11. The package body 13 may be formed by a molding technique such as transfer molding, compression molding, or any other suitable process.

[0090] Spatially relative terms such as "under," "below," "lower," "above," "upper," "left," "right," and the like may be used herein for ease of description to describe the relationship of one component or feature to another or more components or features as shown in the accompanying drawings. Spatially relative terms are intended to cover different orientations of the device when in use or operating in addition to the orientations depicted in the accompanying drawings. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein may be interpreted accordingly. It should be understood that when a component is referred to as being "connected to" or "coupled to" another component, it may be directly connected to or coupled to the other component, or there may be intermediate components.

[0091] As used herein, the terms "approximately", "substantially", "substantially" and "about" are used to describe and explain small changes. When used in conjunction with an event or situation, the term can refer to an instance where the event or situation occurs precisely and an instance where the event or situation is close to occurring. As used herein with respect to a given value or range, the term "approximately" generally means within ±10%, ±5%, ±1% or ±0.5% of a given value or range. The range can be expressed as one endpoint to another endpoint or between two endpoints herein. All ranges disclosed herein include endpoints unless otherwise specified. The term "substantially coplanar" can refer to a position difference of two surfaces positioned along the same plane within a few microns (μm), such as a position difference positioned along the same plane within 10 μm, within 5 μm, within 1 μm or within 0.5 μm. When a numerical value or characteristic is referred to as being "substantially" the same, the term can refer to a value within ±10%, ±5%, ±1% or ±0.5% of the average value of the value.

[0092] The foregoing summarizes the features of several embodiments and detailed aspects of the present disclosure. The embodiments described in the present disclosure can be easily used as a basis for designing or modifying other processes and structures to facilitate the implementation of the same or similar purposes and / or to achieve the same or similar advantages of the embodiments introduced herein. Such equivalent constructions do not depart from the spirit and scope of the present disclosure, and various changes, substitutions and modifications may be made without departing from the spirit and scope of the present disclosure.

Claims

1. An antenna, include: A first dielectric layer (12d3) having a first surface and a second surface opposite to the first surface; a first conductive layer (12c2) contacting the first surface of the first dielectric layer and exposing a portion of the first surface, the first conductive layer having a feeding end (12cf); and a second dielectric layer (12d4) contacting the portion of the first surface of the first dielectric layer, wherein the second dielectric layer covers and contacts the upper surface and a portion of the side surface of the first conductive layer, and exposes the side surface and the lower surface of the feed end of the first conductive layer, wherein the side surface and the lower surface of the feed end contact the conductive structure (10s) and are connected to the substrate (10) through the conductive structure, wherein the width of the lower surface of the feeding end is smaller than the width of the lower surface of the first conductive layer, and The side surface of the feeding end is substantially parallel to the first surface.

2. The antenna according to claim 1, further comprising: include: A package body (12m) having a first surface and a second surface opposite to the first surface, wherein the first surface of the package body contacts the second surface of the first dielectric layer; a third dielectric layer (12d1), wherein the package body is sandwiched between the first dielectric layer and the third dielectric layer; and The side surface of the package body is exposed from the first dielectric layer and the third dielectric layer and contacts the substrate, and the side surface of the package body is substantially perpendicular to the side surface of the feeding end, wherein the package body and the first dielectric layer have different materials.

3. The antenna according to claim 2, further comprising: include: A second conductive layer (12c1) is located on the second surface of the package body and separated from the second surface of the package body, and serves as a ground layer of the antenna, wherein the third dielectric layer (12d1) covers and contacts a portion of the upper surface and the side surface of the second conductive layer.

4. The antenna according to claim 3, wherein the substrate comprises a conductive layer (10c), a first dielectric layer portion and a second dielectric layer portion, wherein the side surface of the package body contacts the second dielectric layer portion (10d'), and the side surface of the feeding end faces the first dielectric layer portion (10d), wherein the width of the lower surface of the feeding end is smaller than the width of the second conductive layer (12c1).

5. The antenna according to claim 1, wherein the first conductive layer comprises a plurality of conductive pads (22p2, 22p3). The antenna according to claim 5 , wherein the plurality of conductive pads comprise dummy pads. 7 . The antenna according to claim 3 , wherein the first conductive layer, the second conductive layer, and the connection structure form a protruding structure on the side surface of the package body.

8. The antenna according to claim 5, wherein the plurality of conductive pads include: A first welding pad, which is disposed on a first side of the feeding end and is separated from the feeding end; and A second soldering pad is disposed on a second side of the feeding end opposite to the first side and is separated from the feeding end; wherein the first pad and the second pad are configured to be grounded; The lower surface of the first dielectric layer extends between the first surface and the second surface.

9. The antenna of claim 7, wherein the protruding structure is configured to be inserted into a groove of the substrate. 10 . The antenna of claim 1 , wherein the first dielectric layer has a lower surface extending between the first surface of the first dielectric layer and the second surface of the first dielectric layer.

11. The antenna according to claim 10, further comprising: include: A packaging body (12m) contacting the second surface of the first dielectric layer; The package body and the first dielectric layer are made of different materials.

12. The antenna according to claim 11, further comprising: include: A third dielectric layer (12d1), wherein the package is sandwiched between the first dielectric layer and the third dielectric layer, and the thickness of the package is configured to control the distance between the first dielectric layer and the third dielectric layer.

13. The antenna of claim 9, wherein the protruding structure is configured to be electrically connected to a conductive layer of the substrate.

14. A semiconductor device package, applied to the antenna according to claim 1, wherein the semiconductor device package include: a substrate having an upper surface; an antenna structure (32) having a first surface, a second surface opposite to the first surface, and a side surface extending between the first surface and the second surface, wherein the side surface of the antenna structure (32) contacts the upper surface of the substrate; The antenna structure (32) has a first antenna pattern and a second antenna pattern separated from the first antenna pattern, the first antenna pattern and the second antenna pattern are located above the first surface, and the distance between the upper surface of the first antenna pattern and the upper surface of the substrate is greater than the distance between the upper surface of the second antenna pattern and the upper surface of the substrate; and The second packaging body (13) is located on the upper surface of the substrate and contacts the antenna structure and the substrate. 15 . The semiconductor device package according to claim 14 , wherein the antenna structure has a third antenna pattern, and the first antenna pattern, the second antenna pattern, and the third antenna pattern at least partially overlap in a direction perpendicular to the upper surface of the substrate. 16 . The semiconductor device package according to claim 14 , wherein the antenna structure has a pattern corresponding to a groove of the substrate and is configured to be inserted into the groove of the substrate.

17. A method for manufacturing the antenna according to claim 1, said method include: (a) forming a connecting layer (49h); (b) forming a plurality of second conductive layers (12c1) on the connection layer by electroplating, wherein the second conductive layers are separated from each other; (c) forming a third dielectric layer (12d1) on the connecting layer and covering the plurality of second conductive layers; (d) forming a first dielectric layer (12d3) on the third dielectric layer; and (e) forming a plurality of first conductive layers (12c2) on the first dielectric layer (12d3) by a lithography process, wherein the first conductive layers are separated from each other.

18. The method according to claim 17, further comprising: include: (f) forming a second dielectric layer (12d4) on the first surface of the first dielectric layer, wherein the second dielectric layer partially covers each first conductive layer (12c2), and removing a portion of the second dielectric layer to expose a side surface of a feed-in end of each first conductive layer, wherein the side surface is substantially parallel to the first surface.

19. The method of claim 18, wherein step (d) further comprises include: A package body is formed on the third dielectric layer, and then the first dielectric layer is formed on the package body.

20. The method according to claim 19, further comprising: include: (g) removing the connecting layer to expose the plurality of second conductive layers and the third dielectric layer; and (h) forming a fourth dielectric layer (12d2) on the plurality of second conductive layers and the third dielectric layer.

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