Universal satellite signal receiving platform based on software configuration

The software-configured universal satellite signal receiving platform integrates GPS, GLONASS, and BeiDou systems, addressing non-upgradability issues by enabling flexible algorithm updates and reducing development costs and cycles.

CN113848575BActive Publication Date: 2024-12-24HARBIN ENG UNIV
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Patent Information

Application Number
CN202111123911.X
Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
Filing Date
2021-09-24
Publication Date
2024-12-24
Estimated Expiration
2041-09-24

AI Technical Summary

Technical Problem

Existing satellite navigation systems lack universalization and integration, with baseband signal processing algorithms being non-upgradable and leading to high development costs and cycles.

Method used

A software-configured universal satellite signal receiving platform that integrates modules for GPS, GLONASS, and BeiDou systems, enabling flexible algorithm updates and upgrades through programming, utilizing FPGA and DSP chips for signal processing and navigation solutions.

Benefits of technology

The platform achieves universal reception across multiple satellite systems, reduces development costs and cycles, and enhances performance indicators by allowing software-based upgrades and algorithm encapsulation.

✦ Generated by Eureka AI based on patent content.

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Abstract

The present application relates to the field of global satellite navigation application technology, and discloses a satellite signal universal receiving platform based on software configuration, comprising: a three-mode receiving module, configured to receive satellite signals from GPS, GLONASS and Beidou satellite navigation systems, and perform high-gain low-noise amplification processing and filtering on the satellite signals to obtain radio frequency input signals; a radio frequency front-end receiving module, configured to communicate with the three-mode receiving module, and convert the radio frequency input signals into intermediate frequency signals; an intermediate frequency signal processing module, configured to obtain the intermediate frequency signals, and perform differential reception processing on the intermediate frequency signals to convert them into corresponding digital signals; a universal baseband signal processing module, configured to call a corresponding algorithm according to the type of the satellite signal, perform data processing and positioning solution on the digital signals through the corresponding algorithm, and obtain navigation positioning data; and a terminal device, configured to communicate with the universal baseband signal processing module.
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Description

Technical Field

[0001] The present application relates to the field of global satellite navigation application technology, for example, to a universal satellite signal receiving platform based on software configuration. Background Art

[0002] At present, satellite navigation systems can provide users with high-precision, all-day, all-weather navigation, positioning, timing and communication services. Satellite navigation systems are one of the core contents of the information development of countries around the world, as well as technical support for national defense technology and an important guarantee technology for national security. With the modernization of GPS (Global Positioning System), the update and development of GLONASS (Global Navigation Satellite System) and the full completion and opening of the Beidou satellite navigation system, the future will surely be more universal and integrated in the field of global satellite navigation.

[0003] Among them, in terms of related equipment research, the document "Research and Implementation of Beidou Second Generation Navigation Receiver Technology" (2015) mainly focuses on Beidou navigation receiver technology, "Configurable Hardware Design of GPS / Beidou Navigation Receiver Capture" (2013) mainly focuses on Beidou navigation receiver hardware design, and "Device and Method for Improving the Baseband Signal Processing Capability of Satellite Navigation Terminal Receivers", "Method and Device for Baseband Signal Processing of High Dynamic Satellite Navigation Receivers", and "Satellite Navigation System Baseband Signal Processing System and Method" mainly study satellite system signal processing methods.

[0004] In the process of implementing the embodiments of the present disclosure, it is found that there are at least the following problems in the related art:

[0005] The existing technologies have not achieved the universalization and integration of the receiving system of the global navigation satellite system. Summary of the invention

[0006] In order to provide a basic understanding of some aspects of the disclosed embodiments, a brief summary is given below. The summary is not an extensive review, nor is it intended to identify key / critical components or delineate the scope of protection of these embodiments, but rather serves as a prelude to the detailed description that follows.

[0007] The disclosed embodiments provide a universal satellite signal receiving platform based on software configuration to solve the problem of universalization and integration of the receiving system of the global navigation satellite system.

[0008] In some embodiments, the satellite signal universal receiving platform based on software configuration includes:

[0009] The three-mode receiving module is configured to receive satellite signals from GPS, GLONASS and BeiDou satellite navigation systems, and perform high-gain low-noise amplification and filtering on the satellite signals to obtain radio frequency input signals;

[0010] A radio frequency front-end receiving module is configured to communicate with the three-mode receiving module to obtain the radio frequency input signal and convert the radio frequency input signal into an intermediate frequency signal;

[0011] An intermediate frequency signal processing module is configured to communicate with the RF front-end receiving module to obtain the intermediate frequency signal and perform differential reception processing on the intermediate frequency signal to convert it into a corresponding digital signal;

[0012] The universal baseband signal processing module is configured to call a corresponding algorithm according to the type of the satellite signal, perform data processing and positioning calculation on the digital signal through the corresponding algorithm, and obtain navigation positioning data;

[0013] The terminal device is configured to communicate with the universal baseband signal processing module, display the navigation positioning data through the human-computer interaction interface of the terminal device, and feed back the operation instructions generated based on the human-computer interaction interface to the universal baseband signal processing module.

[0014] Optionally, the three-mode receiving module includes:

[0015] A first low noise amplifier is configured to amplify a satellite signal from a GPS received through a tri-band antenna;

[0016] A second low noise amplifier is configured to amplify a satellite signal from GLONASS received through the tri-band antenna;

[0017] A third low noise amplifier is configured to amplify a satellite signal from a BeiDou satellite navigation system received through the tri-band antenna;

[0018] The bandpass filter is configured to be communicated with the first low noise amplifier, the second low noise amplifier and the second low noise amplifier respectively to filter the satellite signal from the GPS, the satellite signal from the GLONASS or the satellite signal from the Beidou satellite navigation system to obtain the RF input signal.

[0019] Optionally, the intermediate frequency signal processing module includes:

[0020] A first differential converter, configured to convert the intermediate frequency signal into a first differential signal in a single-ended manner;

[0021] A second differential converter, configured to convert the intermediate frequency signal into a second differential signal in a single-ended manner;

[0022] A first analog-to-digital converter is configured to convert the first differential signal into a corresponding digital signal and transmit the digital signal to an interface of the FPGA middle layer board;

[0023] A second analog-to-digital converter is configured to convert the second differential signal into a corresponding digital signal and transmit the digital signal to an interface of the FPGA middle layer board;

[0024] The phase-locked loop is configured to output a sampling clock signal to the first analog-to-digital converter and the second analog-to-digital converter through a crystal oscillator to provide a reference clock.

[0025] Optionally, the universal baseband signal processing module includes:

[0026] The FPGA chip is configured to obtain the digital signal from the interface of the FPGA middle layer board to capture, track and perform pseudo-range measurement processing on the digital signal;

[0027] The DSP chip is configured to communicate with the FPGA chip via the SRIO protocol to perform navigation and positioning solutions on the digital signal, and the DSP chip is communicated with the terminal device via the user datagram protocol to achieve data interaction and operation instruction feedback based on the human-computer interaction interface.

[0028] Optionally, the FPGA chip includes:

[0029] The sampling rate conversion module is configured to perform sampling rate conversion on the received digital signal to generate a corresponding digital quantity;

[0030] A three-mode receiving compatible channel is configured to perform signal acquisition, tracking and pseudo-range measurement processing on the digital quantity according to the type of satellite signal;

[0031] The SRIO interface module is configured to transmit the processed digital quantity to the DSP chip so that the DSP chip performs navigation solution to obtain navigation positioning data.

[0032] Optionally, the three-mode receiving compatible channel includes:

[0033] The carrier oscillator module is configured to address the sine table module with the output carrier phase and output two orthogonal signals I and Q according to the frequency control word sent by the DSP chip through the capture / tracking bus;

[0034] The digital down-conversion module is configured to down-convert the intermediate frequency signal into a baseband signal according to the digital quantity, the orthogonal signal I and the orthogonal signal Q.

[0035] Optionally, the three-mode receiving compatible channel further includes:

[0036] A code oscillator module is configured to output a chip clock signal for driving a pseudo code generator according to a frequency control word sent by the DSP chip through a capture / tracking bus;

[0037] A pseudo code generator is configured to generate an advance code, a lag code and an immediate code according to a phase code control word sent by the DSP chip through a capture / tracking bus, and perform an integral operation with an orthogonal signal I and an orthogonal signal Q output by the digital down-conversion module;

[0038] The bit / frame synchronization module is configured to perform bit / frame synchronization processing on the integral operation result of the integral operation to obtain a navigation message, and transmit the navigation message and the original observation amount to the DSP chip through the SRIO interface module.

[0039] Optionally, the DSP chip includes:

[0040] The navigation data solving module is configured to obtain the navigation message and the original observation value through the SRIO interface module of the FPGA chip, and call the corresponding algorithm to solve the navigation message and the original observation value according to the type of the satellite signal to generate navigation positioning data;

[0041] The transit scheduling module is configured to realize data interaction and operation instruction transmission between terminal devices, DSP chips and FPGA chips through the SYS / BIOS system, and to call the algorithm for data solution inside the DSP chip by IPC inter-core communication.

[0042] Optionally, it is characterized in that the universal baseband signal processing module further includes:

[0043] The PCIe switching chip is configured to communicate with the FPGA chip and the DSP chip respectively through the PCIe bus, and to communicate with the terminal device through a standard CPCI interface, so as to enable the terminal device to perform data interaction and operation instruction feedback with the FPGA chip through the PCIe bus;

[0044] The PCIE / PCI bridge chip is configured to communicate and connect with the PCIe switch chip through the PCIe bus and to communicate and connect with the terminal device through a standard CPCI interface.

[0045] Optionally, the terminal device includes at least a personal computer, a satellite signal receiving device and a navigation receiver;

[0046] Wherein, the personal computer is equipped with a human-computer interaction interface for realizing control operations and display of navigation and positioning data.

[0047] The software-configured universal satellite signal receiving platform provided by the embodiments of the present disclosure can achieve the following technical effects: by integrating corresponding signal receiving modules and encapsulating corresponding algorithm solving modules, a three-in-one universal receiving platform of GPS, GLONASS and Beidou navigation systems based on software configuration is formed, which can meet the universal receiving requirements of GPS, GLONASS and Beidou navigation satellite systems, and the system can be upgraded and updated through programming and software configuration, which solves the problem that the baseband signal processing algorithm cannot be upgraded, can improve the performance indicators of the equipment, has a lower development cycle and development cost, and has a wide range of application value.

[0048] The above general description and the following description are exemplary and explanatory only and are not intended to limit the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] One or more embodiments are exemplarily described by corresponding drawings, which do not limit the embodiments. Elements with the same reference numerals in the drawings are shown as similar elements, and the drawings do not constitute a scale limitation, and wherein:

[0050] Figure 1 is a structural block diagram of a satellite signal universal receiving platform based on software configuration provided by an embodiment of the present disclosure;

[0051] Figure 2 is a structural block diagram of a three-mode receiving module provided in an embodiment of the present disclosure;

[0052] Figure 3 is a structural block diagram of an intermediate frequency signal processing module provided in an embodiment of the present disclosure;

[0053] Figure 4 is a structural block diagram of a universal baseband signal processing module provided by an embodiment of the present disclosure;

[0054] Figure 5 It is a block diagram of the internal structure of the FPGA chip of the universal baseband signal processing module provided in the embodiment of the present disclosure;

[0055] Figure 6 It is a structural block diagram of the three-mode receiving compatible channel of the FPGA chip provided by the embodiment of the present disclosure. DETAILED DESCRIPTION

[0056] In order to be able to understand the features and technical contents of the embodiments of the present disclosure in more detail, the implementation of the embodiments of the present disclosure is described in detail below in conjunction with the accompanying drawings. The attached drawings are for reference only and are not used to limit the embodiments of the present disclosure. In the following technical description, for the convenience of explanation, a full understanding of the disclosed embodiments is provided through multiple details. However, one or more embodiments can still be implemented without these details. In other cases, to simplify the drawings, well-known structures and devices can be simplified for display.

[0057] The terms "first", "second", etc. in the specification and claims of the embodiments of the present disclosure and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the terms used in this way can be interchanged where appropriate, so that the embodiments of the embodiments of the present disclosure described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions.

[0058] In the embodiments of the present disclosure, the terms "upper", "lower", "inside", "middle", "outside", "front", "back" and the like indicate directions or positional relationships based on the directions or positional relationships shown in the accompanying drawings. These terms are mainly intended to better describe the embodiments of the present disclosure and their embodiments, and are not intended to limit the indicated devices, elements or components to have a specific direction, or to be constructed and operated in a specific direction. Moreover, in addition to being used to indicate directions or positional relationships, some of the above terms may also be used to indicate other meanings. For example, the term "upper" may also be used to indicate a certain dependency or connection relationship in certain circumstances. For those of ordinary skill in the art, the specific meanings of these terms in the embodiments of the present disclosure can be understood according to specific circumstances.

[0059] In addition, the terms "disposed", "connected", and "fixed" should be understood in a broad sense. For example, "connected" can be a fixed connection, a detachable connection, or an integral structure; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate medium, or it can be an internal connection between two devices, elements, or components. For those of ordinary skill in the art, the specific meanings of the above terms in the embodiments of the present disclosure can be understood according to specific circumstances.

[0060] Unless otherwise stated, the term "plurality" means two or more.

[0061] In the embodiment of the present disclosure, the character " / " indicates that the preceding and following objects are in an "or" relationship. For example, A / B indicates: A or B.

[0062] The term "and / or" is a description of the association relationship between objects, indicating that three relationships can exist. For example, A and / or B means: A or B, or, A and B.

[0063] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present disclosure may be combined with each other.

[0064] Combination Figure 1 As shown, the embodiment of the present disclosure provides a universal satellite signal receiving platform based on software configuration, including a three-mode receiving module, a radio frequency front-end receiving module, an intermediate frequency signal processing module, a universal baseband signal processing module and a terminal device, wherein the three-mode receiving module is configured to receive satellite signals from GPS, GLONASS and Beidou satellite navigation systems, and perform high-gain low-noise amplification and filtering on the satellite signals to obtain radio frequency input signals; the radio frequency front-end receiving module is configured to communicate with the three-mode receiving module to obtain the radio frequency input signal and convert the radio frequency input signal into an intermediate frequency signal; the intermediate frequency signal processing module The module is configured to communicate with the RF front-end receiving module to obtain the intermediate frequency signal, and perform differential reception processing on the intermediate frequency signal to convert it into a corresponding digital signal; the universal baseband signal processing module is configured to call the corresponding algorithm according to the type of the satellite signal, perform data processing and positioning calculation on the digital signal through the corresponding algorithm, and obtain navigation positioning data; the terminal device is configured to communicate with the universal baseband signal processing module, display the navigation positioning data through the human-computer interaction interface of the terminal device, and feed back the operation instructions generated based on the human-computer interaction interface to the universal baseband signal processing module.

[0065] Optionally, in an embodiment of the present application, the operating frequency range of the three-mode receiving module is 2MHz to 3GHz, which can meet the frequency coverage of the Beidou navigation system, GPS navigation system and GLONASS navigation system. The three-mode receiving module converts the received satellite signal into a radio frequency input signal and inputs it into the radio frequency front-end receiving module. The radio frequency front-end receiving module converts the radio frequency input signal into an intermediate frequency signal (70MHz or 220MHz) and then outputs it to the intermediate frequency signal processing module. The intermediate frequency signal processing module converts the input intermediate frequency signal into a digital signal after differential reception processing and outputs it to the universal baseband signal processing module. The universal baseband signal processing module calls the corresponding algorithm to perform capture, tracking, synchronization, pseudorange measurement and navigation solution on the input digital signal according to the type of satellite signal, and then outputs the navigation positioning data to the terminal device. The terminal device sends an operation instruction to the universal baseband signal processing module.

[0066] By adopting the universal satellite signal receiving platform based on software configuration provided by the embodiment of the present disclosure, by integrating the corresponding signal receiving modules and encapsulating the corresponding algorithm solving modules, a three-in-one universal receiving platform of GPS, GLONASS and Beidou navigation systems based on software configuration is formed, which can meet the universal receiving requirements of GPS, GLONASS and Beidou navigation satellite systems, and the system can be upgraded and updated through programming and software configuration, which solves the problem that the baseband signal processing algorithm cannot be upgraded, can improve the performance indicators of the equipment, has a lower development cycle and development cost, and has a wide range of application value.

[0067] In the embodiments of the present application, Figure 2 As shown, the three-mode receiving module includes a first low-noise amplifier, a second low-noise amplifier, a third low-noise amplifier and a bandpass filter, wherein the first low-noise amplifier is configured to amplify the satellite signal from GPS received through the three-band antenna; the second low-noise amplifier is configured to amplify the satellite signal from GLONASS received through the three-band antenna; the third low-noise amplifier is configured to amplify the satellite signal from the Beidou satellite navigation system received through the three-band antenna; the bandpass filter is configured to communicate with the first low-noise amplifier, the second low-noise amplifier and the second low-noise amplifier respectively to filter the satellite signal from GPS, the satellite signal from GLONASS or the satellite signal from the Beidou satellite navigation system to obtain the RF input signal.

[0068] Optionally, a first low noise amplifier suitable for GPS, a second low noise amplifier suitable for GLONASS and a third low noise amplifier suitable for the Beidou satellite navigation system are integrated in the three-mode receiving module, and its operating frequency range is 2MHz to 3GHz, which can meet the frequency coverage of B1 frequency, B2 frequency and B3 frequency of the Beidou-2 satellite navigation system, among which the operating frequency of B1 frequency is 1561.098±2.046MHz, the operating frequency of B2 frequency is 1207.14±2.046MHz, and the operating frequency of B3 frequency is 1268.52±10.2 3MHz; it can also meet the frequency coverage of L1, L2 and L5 bands of GPS, among which the operating frequency of L1 is 1575.42MHz±1.023MHz, the operating frequency of L2 is 1227.60MHz±1.023MHz, and the operating frequency of L5 is 1176.45MHz±1.023MHz; it can meet the frequency coverage of L1 and L2 working bands of GLONASS, among which the operating frequency of L1 is 1602+0.5625*k(MHz), and the operating frequency of L2 is 1246+0.4375*k(MHz).

[0069] In this way, the acquisition and preprocessing of three common mainstream satellite signals can be better realized, which can not only cover multiple frequency bands and meet the needs of multi-system compatible navigation equipment, but also effectively improve the noise problem of satellite signals through low-noise amplifiers and bandpass filters.

[0070] In the embodiments of the present application, Figure 3 As shown, the intermediate frequency signal processing module includes a first differential converter, a second differential converter, a first analog-to-digital converter (ADC), a second analog-to-digital converter and a phase-locked loop, wherein the first differential converter is configured to convert the intermediate frequency signal into a first differential signal in a single-ended manner; the second differential converter is configured to convert the intermediate frequency signal into a second differential signal in a single-ended manner; the first analog-to-digital converter is configured to convert the first differential signal into a corresponding digital signal and transmit it to an interface of an FPGA middle layer board; the second analog-to-digital converter is configured to convert the second differential signal into a corresponding digital signal and transmit it to an interface of an FPGA middle layer board (FPGA Mezzanine Card, FMC); the phase-locked loop (PLL) is configured to output a sampling clock signal to the first analog-to-digital converter and the second analog-to-digital converter through a crystal oscillator to provide a reference clock.

[0071] Optionally, the crystal oscillator can provide a 20MHz reference clock for the phase-locked loop, and the phase-locked loop outputs a 1GHz sampling clock for providing it to two high-speed ADCs (i.e., the first analog-to-digital converter and the second analog-to-digital converter) respectively. The first differential converter converts the intermediate frequency signal into a single-ended differential output and sends it to the first analog-to-digital converter. The second differential converter converts the intermediate frequency signal into a single-ended differential output and sends it to the second analog-to-digital converter. The first analog-to-digital converter and the second analog-to-digital converter input the output digital signals into the interface of the FMC, wherein the two high-speed ADCs have their own extractors and can output four channels of 250MHz / 12bit digital data.

[0072] In this way, by performing differential processing on the intermediate frequency signal and inputting it into the interface of the FPGA middle layer board after analog-to-digital conversion via two high-speed ADCs, the subsequent processing of the intermediate frequency signal can be better realized, thereby improving the reliability of the navigation and positioning data.

[0073] In the embodiments of the present application, Figure 4As shown, the universal baseband signal processing module includes an FPGA (Field Programmable Gate Array) chip and a DSP (Digital Signal Processing) chip, wherein the FPGA chip is configured to obtain the digital signal from the interface of the FPGA middle layer board to capture, track and perform pseudo-range measurement processing on the digital signal; the DSP chip is configured to communicate with the FPGA chip through the SRIO (Serial Rapid I / O) protocol to perform navigation and positioning solution on the digital signal, and the DSP chip is communicated with the terminal device through the user datagram protocol to realize data interaction and operation instruction feedback based on the human-computer interaction interface.

[0074] Optionally, the universal baseband signal processing module includes an FMC interface, and completes data processing such as satellite signal capture, tracking, synchronization, pseudo-range measurement, and navigation solution by utilizing an FPGA chip and a DSP chip.

[0075] Specifically, the FPGA chip can be an EP2S90F1020I4 field programmable gate array of Altera Corporation, including a sampling rate conversion module, a three-mode reception compatible channel and an SRIO interface module, wherein the sampling rate conversion module is configured to perform sampling rate conversion on the received digital signal to generate a corresponding digital quantity; the three-mode reception compatible channel is configured to perform signal capture, tracking and pseudo-range measurement processing on the digital quantity according to the type of satellite signal; the SRIO interface module is configured to transmit the processed digital quantity to the DSP chip, so that the DSP chip performs navigation positioning solution to obtain navigation positioning data.

[0076] Among them, the sampling rate conversion module downsamples the 250MHz / 12bit digital signal output by the intermediate frequency signal processing module by 5 times to obtain a 50MHz / 12bit digital output, and then inputs the obtained digital quantity in parallel into the three-mode reception compatible channel. It is only necessary to obtain the four channel signals in the three-mode reception compatible channel to complete the capture, tracking and pseudo-range measurement of the digital signal, and then transmit the processed digital quantity to the DSP chip through the SRIO interface module and call the corresponding algorithm to complete the navigation data solution, and finally obtain the navigation positioning data.

[0077] Further, the three-mode receiving compatible channel includes a carrier oscillator (Numerically Controlled Oscillator, NCO) module, a sine table module, a digital down-conversion module, a code oscillator module, a pseudo code generator, a baseband correlator module, a bit / frame synchronization module, an SRIO interface module and a capture / tracking bus interface, wherein the carrier oscillator module is configured to address the sine table module with the output carrier phase to output two orthogonal signals I and Q according to the frequency control word sent by the DSP chip through the capture / tracking bus; the digital down-conversion module is configured to down-convert the intermediate frequency signal into a baseband signal according to the digital quantity, the orthogonal signal I and the orthogonal signal Q; The code oscillator module is configured to output a code chip clock signal for driving a pseudo code generator according to a frequency control word sent by the DSP chip through a capture / tracking bus; the pseudo code generator is configured to generate an advance code, a lag code and an immediate code according to a phase code control word sent by the DSP chip through a capture / tracking bus, and perform an integral operation with the orthogonal signal I and the orthogonal signal Q output by the digital down-conversion module; the bit / frame synchronization module is configured to perform bit / frame synchronization processing on the integral operation result of the integral operation to obtain a navigation message, and transmit the navigation message and the original observation quantity to the DSP chip through the SRIO interface module.

[0078] In an application embodiment of the present application, the sampling rate conversion module downsamples the 250MHz / 12bit digital signal from the Beidou satellite navigation system by 5 times to obtain a 50MHz / 12bit digital output, which is input in parallel to the three-mode reception compatible channel, and the 32bit frequency control word sent by the DSP chip through the capture / tracking bus is input to the carrier oscillator module, and the sine table is addressed to output two orthogonal signals I and Q with the output carrier phase, wherein the 50MHz / 12bit digital quantity, the orthogonal signal I and the orthogonal signal Q are input to the digital down-conversion module, and the 70MHz or 2 The 20MHz intermediate frequency signal is down-converted to the baseband signal, and the 32-bit frequency control word sent by the DSP chip obtained by the capture / tracking bus is input into the code oscillator module, and the pseudo code generator is driven by the code chip clock. At the same time, the 15-bit phase code control word transmitted by the DSP chip through the capture / tracking bus is input into the pseudo code generator to generate the leading code, lagging code and immediate code, and the correlation integral operation is performed with the I / Q signal output by the down-conversion module, and the result is output to the bit / frame synchronization module. After the synchronization is completed, the navigation message is obtained, and it is sent together with the original observation through the SRIO interface module to the navigation data solution platform based on the DSP chip.

[0079] Optionally, the DSP chip includes a navigation data solution module and a transit scheduling module, wherein the navigation data solution module is configured to obtain navigation messages and original observation quantities through the SRIO interface module of the FPGA chip, and call corresponding algorithms to perform data solution on the navigation messages and original observation quantities according to the types of satellite signals to generate navigation positioning data; the transit scheduling module is configured to implement data interaction and operation instruction transmission between terminal devices, DSP chips and FPGA chips through the SYS / BIOS system, and use IPC inter-core communication to implement the call of the algorithm for data solution inside the DSP chip.

[0080] Specifically, the DSP chip can be a DSP-TMS320C66678 chip from Texas Instruments, in which the navigation data solution module completes channel initialization, reading and storage of leading, immediate and lagging correlation values ​​of each channel, loop control of the carrier tracking loop and the code tracking loop, carrier phase assisted pseudorange smoothing, tracking Doppler Kalman filtering, and selects the corresponding algorithm for positioning solution and speed solution according to the navigation message input by the FPGA chip through the SRIO interface module.

[0081] Optionally, the universal baseband signal processing module also includes a PCIe (Peripheral Component Interconnect) switching chip of PLX and a PCIe / PCI (Peripheral Component Interconnect Express) bridge chip of Peripheral Semiconductor, wherein the PCIe switching chip is configured to communicate and connect with the FPGA chip and DSP chip respectively through a PCIe bus, and to communicate and connect with the terminal device through a standard CPCI (Compact Peripheral Component Interconnect) interface, so as to enable the terminal device to interact with the FPGA chip through the PCIe bus and provide feedback on operation instructions; the PCIE / PCI bridge chip is configured to communicate and connect with the PCIe switching chip respectively through the PCIe bus, and to communicate and connect with the terminal device through a standard CPCI interface.

[0082] In this way, the present application adopts a software-based configuration method through the DSP chip, which, on the one hand, solves the development cycle and cost of replacing the receiving chip to receive different satellite signals. On the other hand, the baseband signal processing module of the present invention is fully programmable, which can better solve the problem of non-upgradability caused by the solidification of the algorithm of a certain navigation system dedicated chip.

[0083] Optionally, the terminal device includes at least a personal computer, a satellite signal receiving device and a navigation receiver, wherein the personal computer is configured with a human-computer interaction interface for realizing control operations and display of navigation and positioning data.

[0084] The above description and the accompanying drawings sufficiently illustrate the embodiments of the present disclosure to enable those skilled in the art to practice them. Other embodiments may include structural and other changes. The embodiments represent only possible variations. Unless explicitly required, individual components and functions are optional, and the order of operations may vary. Portions and features of some embodiments may be included in or replace portions and features of other embodiments. The embodiments of the present disclosure are not limited to the structures described above and shown in the accompanying drawings, and various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.

Claims

1. A universal satellite signal receiving platform based on software configuration, characterized in that: include: The three-mode receiving module is configured to receive satellite signals from GPS, GLONASS and BeiDou satellite navigation systems, and perform high-gain low-noise amplification and filtering on the satellite signals to obtain radio frequency input signals; A radio frequency front-end receiving module is configured to communicate with the three-mode receiving module to obtain the radio frequency input signal and convert the radio frequency input signal into an intermediate frequency signal; An intermediate frequency signal processing module is configured to communicate with the RF front-end receiving module to obtain the intermediate frequency signal and perform differential reception processing on the intermediate frequency signal to convert it into a corresponding digital signal; The universal baseband signal processing module is configured to call a corresponding algorithm according to the type of the satellite signal, perform data processing and positioning calculation on the digital signal through the corresponding algorithm, and obtain navigation positioning data; A terminal device is configured to communicate with the universal baseband signal processing module, display the navigation positioning data through a human-computer interaction interface of the terminal device, and feed back an operation instruction generated based on the human-computer interaction interface to the universal baseband signal processing module; The universal baseband signal processing module comprises: The FPGA chip is configured to obtain the digital signal from the interface of the FPGA middle layer board to capture, track and perform pseudo-range measurement processing on the digital signal; The DSP chip is configured to communicate with the FPGA chip through the SRIO protocol to perform navigation and positioning calculations on the digital signal, and the DSP chip is communicated with the terminal device through the user datagram protocol to achieve data interaction and operation instruction feedback based on a human-computer interaction interface; The FPGA chip comprises: The sampling rate conversion module is configured to perform sampling rate conversion on the received digital signal to generate a corresponding digital quantity; The three-mode receiving compatible channel is configured to perform signal capture, tracking and pseudo-range measurement processing on the digital quantity according to the type of satellite signal; the three-mode receiving compatible channel includes: The carrier oscillator module is configured to address the sine table module with the output carrier phase and output two orthogonal signals I and Q according to the frequency control word sent by the DSP chip through the capture / tracking bus; A digital down-conversion module is configured to down-convert the intermediate frequency signal into a baseband signal according to the digital quantity, the orthogonal signal I and the orthogonal signal Q; A code oscillator module is configured to output a chip clock signal for driving a pseudo code generator according to a frequency control word sent by the DSP chip through a capture / tracking bus; A pseudo code generator is configured to generate an advance code, a lag code and an immediate code according to a phase code control word sent by the DSP chip through a capture / tracking bus, and perform an integral operation with an orthogonal signal I and an orthogonal signal Q output by the digital down-conversion module; A bit / frame synchronization module is configured to perform bit / frame synchronization processing on the integral operation result of the integral operation to obtain a navigation message, and transmit the navigation message and the original observation amount to the DSP chip through the SRIO interface module; The DSP chip comprises: The navigation data solving module is configured to obtain the navigation message and the original observation value through the SRIO interface module of the FPGA chip, and call the corresponding algorithm to solve the navigation message and the original observation value according to the type of the satellite signal to generate navigation positioning data; The transfer scheduling module is configured to realize data interaction and operation instruction transmission between the terminal device, DSP chip and FPGA chip through the SYS / BIOS system, and to call the algorithm for data solution inside the DSP chip by using the IPC inter-core communication method; Among them, the navigation data solution module completes the initialization of the channel, the reading and storage of the leading, immediate and lagging correlation values ​​of each channel, the loop control of the carrier tracking loop and the code tracking loop, the carrier phase assisted pseudo-range smoothing processing, the tracking Doppler Kalman filter processing, and selects the corresponding algorithm for positioning settlement and velocity solution according to the navigation message input by the FPGA chip through the SPIO interface module.

2. The universal receiving platform according to claim 1, characterized in that: The three-mode receiving module comprises: A first low noise amplifier is configured to amplify a satellite signal from a GPS received through a tri-band antenna; a second low noise amplifier configured to amplify a satellite signal from GLONA SS received via the tri-band antenna; A third low noise amplifier is configured to amplify a satellite signal from a BeiDou satellite navigation system received through the tri-band antenna; The bandpass filter is configured to be communicated with the first low noise amplifier, the second low noise amplifier and the second low noise amplifier respectively to filter the satellite signal from the GPS, the satellite signal from the GLONASS or the satellite signal from the Beidou satellite navigation system to obtain the RF input signal.

3. The universal receiving platform according to claim 1, characterized in that: The intermediate frequency signal processing module comprises: A first differential converter, configured to convert the intermediate frequency signal into a first differential signal in a single-ended manner; A second differential converter, configured to convert the intermediate frequency signal into a second differential signal in a single-ended manner; A first analog-to-digital converter is configured to convert the first differential signal into a corresponding digital signal and transmit the digital signal to an interface of the FPGA middle layer board; A second analog-to-digital converter is configured to convert the second differential signal into a corresponding digital signal and transmit the digital signal to an interface of the FPGA middle layer board; The phase-locked loop is configured to output a sampling clock signal to the first analog-to-digital converter and the second analog-to-digital converter through a crystal oscillator to provide a reference clock.

4. The universal receiving platform according to claim 1, characterized in that: The FPGA chip further includes: The SRIO interface module is configured to transmit the processed digital quantity to the DSP chip so that the DSP chip performs navigation solution to obtain navigation positioning data.

5. The universal receiving platform according to any one of claims 1 to 4, characterized in that: The universal baseband signal processing module further includes: The PCIe switching chip is configured to communicate with the FPGA chip and the DSP chip respectively through the PCIe bus, and communicate with the terminal device through a standard CPCI interface, so as to realize data interaction and operation instruction feedback between the terminal device and the FPGA chip through the PCIe bus; The PCIE / PCI bridge chip is configured to communicate and connect with the PCIe switch chip through the PCIe bus and to communicate and connect with the terminal device through a standard CPCI interface.

6. The universal receiving platform according to claim 1, characterized in that: The terminal device at least includes a personal computer, a satellite signal receiving device and a navigation receiver; Wherein, the personal computer is equipped with a human-computer interaction interface for realizing control operations and display of navigation and positioning data.

Citation Information

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