Semiconductor package

Abstract

A semiconductor package includes a first stack, a plurality of TSVs passing through the first stack, a second stack on the first stack and including a second surface facing a first surface of the first stack, a first pad on the first stack and in contact with the TSVs, a second pad on the second stack, a bump connecting the first pad and the second pad, a first redundant pad on the first surface of the first stack, spaced apart from the first pad, and not in contact with the TSVs, a second redundant pad on the second surface of the second stack, and spaced apart from the second pad, and a redundant bump connecting the first redundant pad and the second redundant pad, wherein the first pad and the first redundant pad are electrically connected to each other, and the second pad and the second redundant pad are electrically connected to each other.

Description

[0001] Cross-references to related applications

[0002] Korean Patent Application No. 10-2020-0078062, filed on June 25, 2020 with the Korean Intellectual Property Office and entitled "Semiconductor Package", is incorporated herein by reference. Technical Field

[0003] The embodiments relate to a semiconductor package. Background Technology

[0004] With the rapid development of the electronics industry and user demands, electronic devices have become smaller, lighter, and more multifunctional. Therefore, smaller, lighter, and more multifunctional semiconductor packages can be used in electronic devices. Summary of the Invention

[0005] The embodiment can be implemented by providing a semiconductor package comprising: a first stack including a first semiconductor substrate; a plurality of through-silicon vias (TSVs) passing through the first semiconductor substrate; a second stack located on the first stack, the second stack including a second surface facing a first surface of the first stack; a first pad located on the first surface of the first stack, the first pad contacting one or more of the plurality of TSVs; a second pad located on the second surface of the second stack; a bump connecting the first pad and the second pad; a first redundant pad located on the first surface of the first stack, the first redundant pad being spaced apart from the first pad and not contacting the plurality of TSVs; a second redundant pad located on the second surface of the second stack, the second redundant pad being spaced apart from the second pad; and a redundant bump connecting the first redundant pad and the second redundant pad, wherein the first pad and the first redundant pad are electrically connected to each other, and the second pad and the second redundant pad are electrically connected to each other.

[0006] The embodiment can be implemented by providing a semiconductor package comprising: a first stack including an intermediate region and an edge region surrounding the intermediate region, the first stack including a first semiconductor substrate; a plurality of through-silicon vias (TSVs) passing through the first semiconductor substrate; one or more first pads located on the top surface of the edge region of the first stack, the one or more first pads contacting one or more of the plurality of TSVs; one or more first redundant pads located on the top surface of the edge region of the first stack, the one or more first redundant pads being spaced apart from the one or more first pads and not contacting the plurality of TSVs; and one or more first interconnects extending along the top surface of the edge region of the first stack to electrically connect the one or more first pads and the one or more first redundant pads.

[0007] Embodiments can be implemented by providing a semiconductor package including a first semiconductor chip including a first semiconductor substrate and a first semiconductor device layer on a bottom surface of the first semiconductor substrate, a second semiconductor chip including a second semiconductor substrate and a second semiconductor device layer on a bottom surface of the second semiconductor substrate, and located on the first semiconductor chip, a plurality of first through silicon vias (TSVs) through the first semiconductor substrate, a first pad on a top surface of the first semiconductor substrate, the first pad in contact with one or more of the plurality of first TSVs, a second pad on the bottom surface of the second semiconductor device layer, a bump connecting the first pad and the second pad, a first redundant pad on the top surface of the first semiconductor substrate, the first redundant pad spaced apart from the first pad and not in contact with the plurality of first TSVs, an interconnect line extending along the top surface of the first semiconductor substrate and connecting the first pad and the first redundant pad, a second redundant pad on the bottom surface of the second semiconductor device layer, the second redundant pad spaced apart from the second pad, and a redundant bump connecting the first redundant pad and the second redundant pad, wherein the second semiconductor device layer electrically connects the second pad and the second redundant pad. BRIEF DESCRIPTION OF DRAWINGS

[0008] The exemplary embodiments will become more fully understood from the detailed description and accompanying drawings, wherein:

[0009] Figure 1 is a layout diagram of a semiconductor package according to some embodiments.

[0010] Figure 2 is a cross-sectional view taken along line A-A of Figure 1

[0011] Figure 3 is a magnified view of region R1 of Figure 2

[0012] Figure 4A and Figure 4B are magnified views of a semiconductor package according to some embodiments.

[0013] Figure 5 is a cross-sectional view of a semiconductor package according to some embodiments.

[0014] Figures 6 to 11 is a layout diagram of a semiconductor package according to some embodiments.

[0015] Figures 12 to 15 is a cross-sectional view of a semiconductor package according to some embodiments. DETAILED DESCRIPTION

[0016] ​​Although first, second, etc. are used herein to describe various elements or components, it should be understood that these elements or components should not be limited by these terms. These terms are simply used to differentiate one element or component from another element or component, and are not intended to require sequential inclusion of these elements. Thus, it will be understood that a first element or component described below could be a second element or component within the spirit of the technology disclosed.

[0017] In the following, reference will be made to Figures 1 to 3 A semiconductor package according to some embodiments will be described.

[0018] Figure 1 is a layout diagram of a semiconductor package according to some embodiments. Figure 2 is a cross-sectional view taken along line A-A of Figure 1 Figure 3 is an enlarged view for describing a region R1 of Figure 2

[0019] Referring to Figures 1 to 3 , a semiconductor package according to some embodiments can include a first stack 100, a second stack 200, a plurality of first through silicon vias (TSVs) 150, a first pad 180, a second pad 270, a first bump 290, a first redundant pad 185, a second redundant pad 275, and a first redundant bump 195.

[0020] The first stack 100 can include a central area CA and an edge area EA. In an implementation, as shown in Figure 1 , the edge area EA can surround the central area CA and constitute an edge of the first stack 100. In an implementation, the first stack 100 can include an edge surface 100S extending (e.g., longitudinally extending) in the second direction Y. The edge area EA can be defined as an area spaced apart (e.g., inwardly spaced apart) from the edge surface 100S by a predetermined distance, for example, in the first direction X (intersecting the second direction Y). In an implementation, a distance D1 (e.g., a width of the edge area EA in the first direction X) by which the edge area EA is spaced apart from the edge surface 100S can be less than or equal to about 200 pm.

[0021] The first stack 100 can include a first surface 100L and a second surface 100U opposite to each other. In an implementation, as shown in Figure 2 , the first surface 100L can be a bottom surface of the first stack 100, and the second surface 100U can be a top surface of the first stack 100.

[0022] ​​The second stack 200 can be stacked on the first stack 100. The second stack 200 can include a third surface 200L and a fourth surface 200U opposite to each other. The third surface 200L of the second stack 200 can face the second surface 100U of the first stack 100. In an embodiment, the third surface 200L can be a bottom surface of the second stack 200, and the fourth surface 200U can be a top surface of the second stack 200.

[0023] Each of the first stack 100 and the second stack 200 can be a substrate constituting a semiconductor package or a substrate of a semiconductor package. In an embodiment, each of the first stack 100 and the second stack 200 can be, for example, a printed circuit board (PCB), a ceramic substrate, or a plug-in. In an embodiment, each of the first stack 100 and the second stack 200 can be a semiconductor chip including a semiconductor device. In an embodiment, as discussed below, the first stack 100 and the second stack 200 can be semiconductor chips.

[0024] In an embodiment, the first stack 100 can include a first semiconductor substrate 110 and a first semiconductor device layer 120, and the second stack 200 can include a second semiconductor substrate 210 and a second semiconductor device layer 220.

[0025] Each of the first semiconductor substrate 110 and the second semiconductor substrate 210 can be, for example, a bulk silicon substrate or a silicon-on-insulator (SOI) substrate. In an embodiment, each of the first semiconductor substrate 110 and the second semiconductor substrate 210 can be a silicon substrate, or can include other materials such as silicon germanium, silicon germanium on insulator (SGOI), indium antimonide, tellurium lead compound, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. As used herein, the term "or" is not an exclusive term, for example, "A or B" will include A, B, or both A and B.

[0026] The first semiconductor device layer 120 can be located on the first semiconductor substrate 110, and the second semiconductor device layer 220 can be located on the second semiconductor substrate 210. In an embodiment, the first semiconductor device layer 120 can cover a bottom surface of the first semiconductor substrate 110, and the second semiconductor device layer 220 can cover a bottom surface of the second semiconductor substrate 210. In an embodiment, a bottom surface of the first semiconductor device layer 120 can constitute the first surface 100L of the first stack 100, and a bottom surface of the second semiconductor device layer 220 can constitute the third surface 200L of the second stack 200.

[0027] Each of the first semiconductor device layer 120 and the second semiconductor device layer 220 can include a plurality of individual devices of different kinds and an interline insulating film. The plurality of individual devices can include various microelectronic devices, for example, a metal oxide semiconductor field effect transistor (MOSFET) such as a complementary metal oxide semiconductor (CMOS) transistor, a system large scale integration (LSI), a flash memory, a dynamic random access memory (DRAM), a static random access memory (SRAM), an electrically erasable programmable read-only memory (EEPROM), a phase change random access memory (PRAM), a magnetoresistive random access memory (MRAM), a resistive random access memory (RRAM), an image sensor such as a CMOS imaging sensor (CIS), a micro electro mechanical system (MEMS), an active device, or a passive device.

[0028] In an embodiment, the first protective layer 130 can be located on the first semiconductor substrate 110, and the second protective layer 230 can be located on the second semiconductor substrate 210. In an embodiment, the first protective layer 130 can cover a top surface of the first semiconductor substrate 110, and the second protective layer 230 can cover a top surface of the second semiconductor substrate 210. In an embodiment, a top surface of the first protective layer 130 can constitute a second surface 100U of the first stack 100, and a top surface of the second protective layer 230 can constitute a fourth surface 200U of the second stack 200.

[0029] Each of the first protective layer 130 and the second protective layer 230 can include a non-conductive film (NCF). In an embodiment, each of the first protective layer 130 and the second protective layer 230 can include an insulating polymer. In an embodiment, the first protective layer 130 and the second protective layer 230 can be formed by, for example, a spin coating process or a spray coating process.

[0030] In an embodiment, the base pad 170 and the base bump 190 can be located on the first surface 100L of the first stack 100. A plurality of base pads 170 can be located on the first surface 100L of the first stack 100. Each of the base pads 170 can be electrically connected to the first semiconductor device layer 120. The base bump 190 can be connected to the base pad 170. The base bump 190 can have various shapes, for example, a column structure, a ball structure, or a solder layer.

[0031] A plurality of first TSVs 150 can pass through the first semiconductor substrate 110. In an embodiment, each of the first TSVs 150 can be exposed from or at the second surface 100U of the first stack 100, and pass through the first semiconductor substrate 110 and the first protective layer 130. Each of the first TSVs 150 can have a cylindrical shape extending in the third direction Z (e.g., a direction intersecting the first surface 100L and the second surface 100U).

[0032] A plurality of second TSVs 250 can pass through the second semiconductor substrate 210. In an embodiment, each of the second TSVs 250 can be exposed from or at the fourth surface 200U of the second stack 200, and can pass through the second semiconductor substrate 210 and the second protective layer 230. Each of the second TSVs 250 can have a cylindrical shape extending in the third direction Z (a direction intersecting the third surface 200L and the fourth surface 200U).

[0033] In an embodiment, the first TSVs 150 can be connected to the first semiconductor device layer 120 through the first semiconductor substrate 110, and the second TSVs 250 can be connected to the second semiconductor device layer 220 through the second semiconductor substrate 210. In an embodiment, as shown in FIG. 2B, the second semiconductor device layer 220 can include a first interline insulating film 222 and first lines 224a, 224b, and 224c in the first interline insulating film 222. The first lines 224a, 224b, and 224c can be sequentially stacked from a bottom surface of the second semiconductor substrate 210. The second TSVs 250 can be electrically connected to the second semiconductor device layer 220 through the first lines 224a, 224b, and 224c. Figure 3

[0034] In an embodiment, the second TSVs 250 can be in contact (e.g., direct contact) with an uppermost line 224a among the first lines 224a, 224b, and 224c. The uppermost line 224a in the second semiconductor device layer 220 can be a line (e.g., in the third direction Z) closest to or proximate to the second semiconductor substrate 210 among the first lines 224a, 224b, and 224c.

[0035] ​In an embodiment, each of the first TSV 150 and the second TSV 250 can include a barrier film on a surface of a cylindrical shape and a buried conductive layer filled in the barrier film. The barrier film can include, for example, titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), ruthenium (Ru), cobalt (Co), manganese (Mn), tungsten nitride (WN), nickel (Ni), or nickel boron (NiB). The buried conductive layer can include, for example, copper (Cu), a copper alloy such as copper tin (CuSn), copper magnesium (CuMg), copper nickel (CuNi), copper zinc (CuZn), copper palladium (CuPd), copper gold (CuAu), copper rhenium (CuRe), or copper tungsten (CuW), tungsten (W), a W alloy, Ni, Ru, or Co.

[0036] In an embodiment, an insulating film can be located between the first semiconductor substrate 110 and the first TSV 150 and between the second semiconductor substrate 210 and the second TSV 250. The insulating film can include, for example, an oxide film, a nitride film, a carbide film, a polymer, or a combination thereof.

[0037] A plurality of first pads 180 can be located on the second surface 100U of the first stack 100. Each of the first pads 180 can be in contact (e.g., direct contact) with at least one of the plurality of first TSVs 150. In an embodiment, the first pads 180 can be located on the first protective layer 130 and can be in contact with the first TSVs 150 exposed through the first protective layer 130.

[0038] In an embodiment, a width W1 of the first pads 180 (e.g., in the first direction X) can be in a range of 15 µm to 30 µm.

[0039] A plurality of second pads 270 can be located on the third surface 200L of the second stack 200. Each of the second pads 270 can be electrically connected to the second semiconductor device layer 220. In an embodiment, the second pads 270 can be electrically connected to individual devices of the second semiconductor device layer 220 or the second TSVs 250.

[0040] Each of the first pads 180 and the second pads 270 can include, for example, aluminum (Al), Cu, Ni, W, platinum (Pt), gold (Au), or a combination thereof.

[0041] A first bump 290 can be located between the first pad 180 and the second pad 270. The first bump 290 can have various shapes, for example, a pillar structure, a ball structure, or a solder layer.

[0042] The first bump 290 can electrically connect the first pad 180 and the second pad 270. In embodiments, the first stack 100 and the second stack 200 can be electrically connected. In embodiments, the first semiconductor device layer 120 can be electrically connected to the second semiconductor device layer 220 or the second TSV 250 through the first TSV 150, the first pad 180, the first bump 290, and the second pad 270.

[0043] The first redundant pad 185 can be located on the second surface 100U of the first stack 100. The first redundant pad 185 can be spaced apart (e.g., in the first direction X) from the first pad 180. In embodiments, the first redundant pad 185 can not be in contact with the plurality of first TSVs 150. In embodiments, the first protective layer 130 can completely cover a bottom (e.g., a surface facing the first stack 100) surface of the first redundant pad 185.

[0044] The first redundant pad 185 can include, for example, Al, Cu, Ni, W, Pt, Au, and combinations thereof. In embodiments, the first redundant pad 185 can be at a same horizontal level as the first pad 180. The term “same horizontal level” as used herein means formed by the same manufacturing process (e.g., formed simultaneously with the same material).

[0045] The first redundant pad 185 can be electrically connected to at least one of the plurality of first pads 180. In embodiments, the first pad 180 and the first redundant pad 185 can be electrically connected through the first interconnect line 160. The first interconnect line 160 can extend along the second surface 100U of the first stack 100 (e.g., in the first direction X). In embodiments, the first interconnect line 160 can extend along a top surface of the first protective layer 130 to electrically connect the first pad 180 and the first redundant pad 185. In embodiments, the first interconnect line 160 can be a redistribution layer (RDL) on the second surface 100U of the first stack 100.

[0046] In embodiments, the first redundant pad 185 can be located on the edge region EA. The first redundant pad 185 on the edge region EA can be electrically connected to the first pad 180 on the edge region EA. In embodiments, as shown in FIG. 1C, the first pad 180 and the first redundant pad 185 can be arranged to be adjacent to each other (e.g., aligned along the first direction X) on the edge region EA. The first interconnect line 160 can extend (e.g., longitudinally) in the first direction X on the edge region EA to connect the first pad 180 and the first redundant pad 185. Figure 1

[0047] ​In embodiments, a width W2 of the first redundant pad 185 (e.g., in the first direction X) can be in a range from about 15 pm to about 30 pm. In embodiments, the width W2 of the first redundant pad 185 can be equal to a width W1 of the first pad 180. The term “equal to” as used herein includes the meaning of exactly equal as well as slight differences that can occur due to process margins, etc.

[0048] In embodiments, a distance D2 by which the first pad 180 and the first redundant pad 185 are spaced apart from each other can be in a range from about 3 pm to about 8 pm. Maintaining the distance D2 by which the first pad 180 and the first redundant pad 185 are spaced apart from each other at about 3 pm or more can help ensure that the first redundant pad 185 is not too close to the first TSV 150, thereby avoiding non-wetting failure of the bump to be described below. Maintaining the distance D2 by which the first pad 180 and the first redundant pad 185 are spaced apart from each other at about 8 pm or less can help prevent electrical connection failure between the first pad 180 and the first redundant pad 185.

[0049] In embodiments, the first interconnect line 160 can be shorter than or shorter than the first pad 180 and the second pad 270 (e.g., when measured in the third direction Z). In embodiments, as shown in FIG. 1C, the first interconnect line 160 can be shorter than the first pad 180 and the second pad 270 (e.g., when measured in the third direction Z). Figure 3 In embodiments, a height H1 of the first pad 180 and a height H2 of the first redundant pad 185 can be greater than a height H3 of the first interconnect line 160, based on or when measured in the third direction Z from the second surface 100U of the first stack 100.

[0050] In embodiments, the height H2 of the first redundant pad 185 can be equal to the height H1 of the first pad 180.

[0051] In embodiments, the first interconnect line 160 can be in contact (e.g., direct contact) with a side surface of the first pad 180 and a side surface of the first redundant pad 185.

[0052] The second redundant pad 275 can be located on the third surface 200L of the second stack 200. The second redundant pad 275 can include, for example, Al, Cu, Ni, W, Pt, Au, or a combination thereof. In embodiments, the second redundant pad 275 can be located at a same horizontal level as the second pad 270.

[0053] The second redundant pad 275 can be electrically connected to at least one of the plurality of second pads 270. In embodiments, the second pad 270 and the second redundant pad 275 can be electrically connected through the second semiconductor device layer 220. In embodiments, as shown in FIG. 1C, the second pad 270 and the second redundant pad 275 can be electrically connected through the second semiconductor device layer 220. Figure 3As shown in FIG. 2, the second pad 270 and the second redundant pad 275 can be electrically connected by the first lines 224a, 224b, and 224c of the second semiconductor device layer 220.

[0054] In an embodiment, the second pad 270 and the second redundant pad 275 can be electrically connected by the lowermost line 224c among the first lines 224a, 224b, and 224c. The lowermost line 224c in the second semiconductor device layer 220 can be the line (e.g., along the third direction Z) closest to the third surface 200L of the second stack 200 among the first lines 224a, 224b, and 224c. The second pad 270 and the second redundant pad 275 can each be connected to the lowermost line 224c of the second semiconductor device layer 220 to be electrically connected to each other. In an embodiment, a trench exposing the lowermost line 224c can be located in the first inter-line insulating film 222. The second pad 270 and the second redundant pad 275 can fill the trench.

[0055] In an embodiment, the height H5 of the second redundant pad 275 can be equal to the height H2 of the second pad 270 (e.g., when measured in the third direction Z).

[0056] The first redundant bump 195 can be located between the first redundant pad 185 and the second redundant pad 275. The first redundant bump 195 can have various shapes, such as a column structure, a ball structure, or a solder layer. In an embodiment, the first redundant bump 195 can be located at the same horizontal level as the first bump 290.

[0057] The first redundant bump 195 can electrically connect the first redundant pad 185 and the second redundant pad 275. In an embodiment, the first stack 100 and the second stack 200 can be electrically connected to each other. In an embodiment, the first semiconductor device layer 120 can be electrically connected to the second semiconductor device layer 220 or the second TSV 250 through the first TSV 150, the first pad 180, the first interconnection line 160, the first redundant pad 185, the first redundant bump 195, the second redundant pad 275, and the first lines 224a, 224b, and 224c.

[0058] In an embodiment, the first redundant bump 195 can be spaced apart from the first bump 290 (e.g., in the first direction X). In an embodiment, the first bump 290 and the first redundant bump 195 can not be in contact with each other.

[0059] In a semiconductor chip (e.g., the first stack 100 or the second stack 200) in which a TSV (e.g., the first TSV 150) is formed and a multi-chip semiconductor package in which a plurality of semiconductor chips are stacked, a pad (e.g., the first pad 180 and the second pad 270) connected to the TSV and a bump (e.g., the first bump 290) can interconnect the semiconductor chips. In a process of forming the bump on the pad, the TSV can serve as a heat transfer path, which can cause a failure of the bump. For example, the bump can be formed by a thermal compression bonding process to interconnect the pads of the semiconductor chips. The pad in contact with the TSV can have a low temperature in the thermal compression bonding process, thereby causing a non-wetting failure of the bump. Such a failure can be more serious in an edge region of the semiconductor chip.

[0060] A semiconductor package according to some embodiments can help to prevent the failure by including a first redundant pad 185 and a first redundant bump 195. In an implementation, the first redundant pad 185 can not be in contact (e.g., direct contact) with the first TSV 150, can prevent a non-wetting failure of the first redundant bump 195 due to the first TSV 150. In an implementation, the first redundant pad 185 can be electrically connected to the first pad 180 in contact with the first TSV 150, and can maintain the electrical connection between the first redundant pad 185 and the first TSV 150 even if a non-wetting failure occurs in the first bump 290 on the first pad 180. Accordingly, a semiconductor package with improved product reliability can be provided, for example, by preventing the failure of the first bump 290.

[0061] In a semiconductor package according to some embodiments, the first redundant pad 185 can be electrically connected to the first pad 180 on the edge region EA. In an implementation, a semiconductor package with improved product reliability can be provided by preventing a failure of the first bump 290 in the edge region EA.

[0062] In an implementation, a third stack 300 can be located on the second stack 200. The third stack 300 can include a fifth surface 300L and a sixth surface 300U opposite each other. The fifth surface 300L of the third stack 300 can face the fourth surface 200U of the second stack 200. In an implementation, the fifth surface 300L can be a bottom surface of the third stack 300, and the sixth surface 300U can be a top surface of the third stack 300.

[0063] In an embodiment, the third stack 300 can include a third semiconductor substrate 310 and a third semiconductor device layer 320. The third semiconductor substrate 310 can be similar to the first semiconductor substrate 110 or the second semiconductor substrate 210 described above, and the third semiconductor device layer 320 can be similar to the first semiconductor device layer 120 or the second semiconductor device layer 220 described above, and thus, a repeated detailed description thereof can be omitted in the following description.

[0064] In an embodiment, the stacked first stack 100, the second stack 200, and the third stack 300 can constitute a multi-chip semiconductor package such as a high bandwidth memory (HBM).

[0065] In an embodiment, the third pad 280, the fourth pad 370, the second bump 390, the third redundant pad 285, the fourth redundant pad 375, the second redundant bump 295, and the second interconnection line 260 can be located between the second stack 200 and the third stack 300. The third pad 280, the fourth pad 370, the second bump 390, the third redundant pad 285, the fourth redundant pad 375, the second redundant bump 295, and the second interconnection line 260 can be similar to the first pad 180, the second pad 270, the first bump 290, the first redundant pad 185, the second redundant pad 275, the first redundant bump 195, and the first interconnection line 160 described above, respectively. In an embodiment, the first pad 180, the second pad 270, the first bump 290, the first redundant pad 185, the second redundant pad 275, the first redundant bump 195, and the first interconnection line 160 described above can be stacked and repeatedly formed over a plurality of stacked stacks.

[0066] In an embodiment, a first filler layer 140 can be located between the first stack 100 and the second stack 200, and a second filler layer 240 can be located between the second stack 200 and the third stack 300. The first filler layer 140 can fill a space between the first stack 100 and the second stack 200, and the second filler layer 240 can fill a space between the second stack 200 and the third stack 300. The first filler layer 140 can cover the first pad 180, the second pad 270, the first bump 290, the first redundant pad 185, the second redundant pad 275, the first redundant bump 195, and the first interconnection line 160. The second filler layer 240 can cover the third pad 280, the fourth pad 370, the second bump 390, the third redundant pad 285, the fourth redundant pad 375, the second redundant bump 295, and the second interconnection line 260.

[0067] The first filler layer 140 and the second filler layer 240 can include, for example, an epoxy resin. In an embodiment, each of the first filler layer 140 and the second filler layer 240 can include a filler. The filler can include, for example, silica. In an embodiment, the filler can each have a size of 0.1 μm to several μm, and can have an average size of about 0.3 μm to 1 μm. In an embodiment, the first filler layer 140 and the second filler layer 240 can include the filler in an amount of about 55 wt% to 75 wt% with respect to 100 wt% of the first filler layer 140 or the second filler layer 240, respectively.

[0068] Hereinafter, various semiconductor packages according to some embodiments will be described with reference to the accompanying drawings. Figures 4A to 15 A semiconductor package according to some embodiments will be described.

[0069] Figure 4A and Figure 4B is a magnified view of a semiconductor package according to some embodiments. For ease of description, portions overlapping those described above with reference to Figures 1 to 3 may be described briefly or the description thereof can be omitted.

[0070] With reference to Figure 4A , a semiconductor package according to some embodiments can further include a first under bump metal layer 184, a second under bump metal layer 274, a third under bump metal layer 189, and a fourth under bump metal layer 279.

[0071] The first under bump metal layer 184 can be located between the first pad 180 and the first bump 290. In an embodiment, the first under bump metal layer 184 can extend along a top surface of the first pad 180. The first under bump metal layer 184 can help to improve adhesion between the first pad 180 and the first bump 290, and can help to improve wettability of the first bump 290.

[0072] The second under bump metal layer 274 can be located between the second pad 270 and the first bump 290. In an embodiment, the second under bump metal layer 274 can extend along a bottom surface of the second pad 270. The second under bump metal layer 274 can help to improve adhesion between the second pad 270 and the first bump 290, and can help to improve wettability of the first bump 290.

[0073] A third under-bump metal layer 189 can be located between the first redundant pad 185 and the first redundant bump 195. In an embodiment, the third under-bump metal layer 189 can extend along a top surface of the first redundant pad 185. The third under-bump metal layer 189 can help improve adhesion between the first redundant pad 185 and the first redundant bump 195, and can help improve wetting of the first redundant bump 195. In an embodiment, the third under-bump metal layer 189 can be located at the same horizontal level as the first under-bump metal layer 184.

[0074] A fourth under-bump metal layer 279 can be located between the second redundant pad 275 and the first redundant bump 195. In an embodiment, the fourth under-bump metal layer 279 can extend along a bottom surface of the second redundant pad 275. The fourth under-bump metal layer 279 can help improve adhesion between the second redundant pad 275 and the first redundant bump 195, and can help improve wetting of the first redundant bump 195. In an embodiment, the fourth under-bump metal layer 279 can be located at the same horizontal level as the second under-bump metal layer 274.

[0075] Each of the first through fourth under-bump metal layers 184, 274, 189, and 279 can be formed of a single layer, or can be formed of multiple layers including an adhesion layer and a solder wetting layer.

[0076] In an embodiment, the first conductive pattern 272 can connect the second pad 270 and the first lines 224a, 224b, and 224c. In an embodiment, a trench exposing the lowermost line 224c can be located in the first inter-line insulating film 222. The first conductive pattern 272 can extend conformally along the first inter-line insulating film 222 and the trench. The second pad 270 can extend along the first conductive pattern 272.

[0077] In an embodiment, a second conductive pattern 277 connecting the second redundant pad 275 and the first lines 224a, 224b, and 224c can be formed. In an embodiment, a trench exposing the lowermost line 224c can be located in the first inter-line insulating film 222. The second conductive pattern 277 can extend conformally along the first inter-line insulating film 222 and the trench. The second redundant pad 275 can extend along the second conductive pattern 277. In an embodiment, the second conductive pattern 277 can be located at the same horizontal level as the first conductive pattern 272.

[0078] Referring to Figure 4B In a semiconductor package according to some embodiments, the first pad 180 and the first redundant pad 185 can be located on a top surface of the first interconnect line 160.

[0079] In implementations, each of the first pad 180 and the first redundant pad 185 can be in contact (e.g., direct contact) with a top surface of the first interconnect line 160. In implementations, a height H1 of the first pad 180 and a height H2 of the first redundant pad 185 can be greater than a height H3 of the first interconnect line 160, based on or when measured from a second surface 100U of the first stack 100 in a third direction Z. For example, a surface of the second stack 200 facing the first pad 180 and the first redundant pad 185 can be closer to the second surface 100U of the first stack 100 in the third direction Z than a surface of the second stack 200 facing the first interconnect line 160.

[0080] Figure 5 is a cross-sectional view of a semiconductor package according to some embodiments. For ease of description, portions that overlap those described above with reference to Figures 1 to 4B may be described briefly, or their descriptions can be omitted.

[0081] Referring to Figure 5 , a semiconductor package according to some embodiments can further include a third interconnect line 165 and a fourth interconnect line 265.

[0082] The third interconnect line 165 can electrically connect the second pad 270 and the second redundant pad 275. The third interconnect line 165 can extend along a third surface 200L of the second stack 200. In implementations, the third interconnect line 165 can extend along a bottom surface of the second semiconductor device layer 220 to electrically connect the second pad 270 and the second redundant pad 275. In implementations, the third interconnect line 165 can be an RDL on the third surface 200L of the second stack 200.

[0083] In implementations, the electrical connection between the second pad 270 and the second redundant pad 275 can not be made through the second semiconductor device layer 220. In implementations, the second pad 270 and the second redundant pad 275 can not be connected to the first lines 224a, 224b, and 224c of the Figure 3 .

[0084] The fourth interconnect line 265 can electrically connect the fourth pad 370 and the fourth redundant pad 375. The fourth interconnect line 265 can extend along a fifth surface 300L of the third stack 300. In implementations, the fourth interconnect line 265 can extend along a bottom surface of the third semiconductor device layer 320 to electrically connect the fourth pad 370 and the fourth redundant pad 375. In implementations, the fourth interconnect line 265 can be an RDL on the fifth surface 300L of the third stack 300.

[0085] In implementations, the electrical connection between the fourth pad 370 and the fourth redundant pad 375 can be made without the third semiconductor device layer 320.

[0086] Figures 6 to 11 is a layout diagram of a semiconductor package according to some embodiments. For ease of description, portions that overlap those described above with reference to Figures 1 to 5 may be described briefly, or their descriptions can be omitted.

[0087] Referring to Figure 6 , in a semiconductor package according to some embodiments, the first redundant pads 185 can be closer to the edge surface 100S than the first pads 180 to the edge surface 100S.

[0088] In implementations, the first redundant pads 185 can be located (e.g., in the first direction X) between the edge surface 100S and the first pads 180. In implementations, the first pads 180 and the first redundant pads 185 can be arranged adjacent to each other in the first direction X on the edge region EA. The first interconnect lines 160 can extend in the first direction X on the edge region EA to connect the first pads 180 and the first redundant pads 185.

[0089] Referring to Figure 7 , in a semiconductor package according to some embodiments, the first pads 180 and the first redundant pads 185 can be arranged parallel to the edge surface 100S (e.g., equidistant to the edge surface 100S in the first direction X).

[0090] In implementations, the first pads 180 and the first redundant pads 185 can be arranged adjacent to each other or aligned along the second direction Y. The first interconnect lines 160 can extend in the second direction Y to connect the first pads 180 and the first redundant pads 185.

[0091] Referring to Figure 8 , in a semiconductor package according to some embodiments, each of the first pads 180 can be connected to a plurality of first redundant pads 185a and 185b.

[0092] In implementations, the semiconductor package can include a fifth redundant pad 185a and a sixth redundant pad 185b that can be connected to each of the first pads 180. The fifth redundant pad 185a and the sixth redundant pad 185b can be spaced apart from each other.

[0093] In an embodiment, the first pads 180 and the fifth redundant pads 185a can be arranged adjacent to each other or aligned along the first direction X, and the first pads 180 and the sixth redundant pads 185b can be arranged adjacent to each other or aligned along the second direction Y.

[0094] In an embodiment, the semiconductor package can include a fifth interconnect line 160a connecting the first pad 180 and the fifth redundant pad 185a, and a sixth interconnect line 160b connecting the first pad 180 and the sixth redundant pad 185b. In an embodiment, the fifth interconnect line 160a can extend in the first direction X to connect the first pad 180 and the fifth redundant pad 185a, and the sixth interconnect line 160b can extend in the second direction Y to connect the first pad 180 and the sixth redundant pad 185b.

[0095] Referring to Figure 9 In the semiconductor package according to some embodiments, each of the first pads 180 can be connected to three first redundant pads 185a, 185b, and 185c or more.

[0096] In an embodiment, the semiconductor package can include a seventh redundant pad 185c connected to the first pad 180. The seventh redundant pad 185c can be spaced apart from the fifth redundant pad 185a and the sixth redundant pad 185b.

[0097] In an embodiment, the first pads 180 and the seventh redundant pad 185c can be arranged adjacent to each other in a direction (e.g., a diagonal direction) different from the first direction X and the second direction Y. In an embodiment, the seventh redundant pad 185c can be arranged together with the fifth redundant pad 185a in the first direction X, and can be arranged together with the sixth redundant pad 185b in the second direction Y.

[0098] In an embodiment, the semiconductor package can include a seventh interconnect line 160c connecting the first pad 180 and the seventh redundant pad 185c. In an embodiment, the seventh interconnect line 160c can extend in a direction (e.g., a diagonal direction) different from the first direction X and the second direction Y to connect the first pad 180 and the seventh redundant pad 185c.

[0099] Referring to Figure 10 In the semiconductor package according to some embodiments, the number of the first redundant pads 185a, 185b, 185c, 185d, 185e, and 185f connected to each of the first pads 180a, 180b, and 180c can increase as the distance from the center 100C of the first stack 100 in a plan view increases.

[0100] In an embodiment, the semiconductor package can include a fifth pad to a seventh pad 180a, 180b, and 180c on the first stack 100.

[0101] A distance from the center 100C of the first stack 100 to the sixth pad 180b can be greater than a distance from the center 100C of the first stack 100 to the fifth pad 180a. In an embodiment, a number of first redundant pads connected to the sixth pad 180b can be greater than a number of first redundant pads connected to the fifth pad 180a. In an embodiment, the fifth pad 180a can be connected to one first redundant pad (e.g., a fifth redundant pad 185a), and the sixth pad 180b can be connected to two first redundant pads (e.g., a sixth redundant pad 185b and a seventh redundant pad 185c).

[0102] In an embodiment, a distance from the center 100C of the first stack 100 to the seventh pad 180c can be greater than a distance from the center 100C of the first stack 100 to the sixth pad 180b. In an embodiment, a number of first redundant pads connected to the seventh pad 180c can be greater than a number of first redundant pads connected to the sixth pad 180b. In an embodiment, the sixth pad 180b can be connected to two first redundant pads (e.g., a sixth redundant pad 185b and a seventh redundant pad 185c), and the seventh pad 180c can be connected to three first redundant pads (e.g., an eighth redundant pad 185d, a ninth redundant pad 185e, and a tenth redundant pad 185f).

[0103] In an embodiment, the semiconductor package can include an eighth interconnect line 160d connecting the seventh pad 180c and the eighth redundant pad 185d, a ninth interconnect line 160e connecting the seventh pad 180c and the ninth redundant pad 185e, and a tenth interconnect line 160f connecting the seventh pad 180c and the tenth redundant pad 185f.

[0104] Referring to Figure 11 In a semiconductor package according to some embodiments, a plurality of first pads 180a and 180b can share a first redundant pad 185.

[0105] In an embodiment, the fifth pad 180a and the sixth pad 180b can both be connected to the first redundant pad 185. The fifth pad 180a and the sixth pad 180b can be spaced apart from each other.

[0106] In an embodiment, the fifth pad 180a, the first redundant pad 185, and the sixth pad 180b can be sequentially arranged adjacent to each other in the second direction Y.

[0107] In an embodiment, the fifth interconnection line 160a can connect the first pad 180 and the fifth redundant pad 185a, and the sixth interconnection line 160b can connect the first pad 180 and the sixth redundant pad 185b. In an embodiment, the fifth interconnection line 160a can extend in the second direction Y to connect the first pad 180 and the fifth redundant pad 185a, and the sixth interconnection line 160b can extend in the second direction Y to connect the first pad 180 and the sixth redundant pad 185b.

[0108] Figures 12 to 15 FIG. 1 is a cross-sectional view of a semiconductor package according to some embodiments. For ease of description, portions overlapping those described above with reference to FIGS. 1A to 1C can be briefly described or the description thereof can be omitted. Figures 1 to 11 FIG. 2 is a cross-sectional view of a semiconductor package according to some embodiments. For ease of description, portions overlapping those described above with reference to FIGS. 1A to 1C can be briefly described or the description thereof can be omitted.

[0109] FIG. 3 is a cross-sectional view of a semiconductor package according to some embodiments. For ease of description, portions overlapping those described above with reference to FIGS. 1A to 1C can be briefly described or the description thereof can be omitted. Figure 12 FIG. 4 is a cross-sectional view of a semiconductor package according to some embodiments. For ease of description, portions overlapping those described above with reference to FIGS. 1A to 1C can be briefly described or the description thereof can be omitted.

[0110] The substrate 10 can be a substrate for a package. In an embodiment, the substrate 10 can be a PCB, a ceramic substrate, or the like. In an embodiment, the substrate 10 can be a substrate for a wafer level package (WLP) manufactured in a wafer level. The substrate 10 can include a bottom surface and a top surface opposite to each other.

[0111] The semiconductor chip 20 can be located on the substrate 10. The semiconductor chip 20 can be an integrated circuit (IC) in which more than several hundreds to several million semiconductor devices are integrated into one chip. In an embodiment, the semiconductor chip 20 can be an application processor (AP) such as a central processing unit (CPU), a graphics processing unit (GPU), a field programmable gate array (FPGA), a digital signal processor, a cryptographic processor, a microprocessor, a microcontroller, or the like. In an embodiment, the semiconductor chip 20 can be a logic chip such as an analog-to-digital converter (ADC), an application specific IC (ASIC), or the like, and can be a memory chip such as a volatile memory (e.g., a DRAM), a non-volatile memory (e.g., a read only memory (ROM) or a flash memory), or the like. In an embodiment, the semiconductor chip 20 can be formed by combining these chips with each other.

[0112] The semiconductor chip 20 can be stacked on the top surface of the substrate 10. In an embodiment, the substrate pad 14 can be located on the top surface of the substrate 10, and the first chip pad 22 can be located on the bottom surface of the semiconductor chip 20. The substrate pad 14 and the first chip pad 22 can be connected by the third bump 28. In an embodiment, the substrate 10 and the semiconductor chip 20 can be electrically connected to each other.

[0113] In an embodiment, the first stack 100 can be stacked on the semiconductor chip 20. In an embodiment, the second chip pad 24 can be located on a top surface of the semiconductor chip 20. The second chip pad 24 and the base pad 170 can be connected by the base bump 190. In an embodiment, the semiconductor chip 20 and the first stack 100 can be electrically connected to each other.

[0114] Referring to Figure 13 , the semiconductor package according to some embodiments can further include a third TSV 25.

[0115] In an embodiment, the semiconductor chip 20 can include a fourth semiconductor substrate 21 and a wire layer 26. The third TSV 25 can pass through the fourth semiconductor substrate 21. In an embodiment, the second chip pad 24 can be in contact with the third TSV 25. In an embodiment, the second chip pad 24 can be in contact with the third TSV 25 exposed from a top surface of the semiconductor chip 20 through the fourth semiconductor substrate 21 or the third TSV 25 exposed on the top surface of the semiconductor chip 20.

[0116] In an embodiment, an eleventh redundant pad 27, a twelfth redundant pad 175, and a third redundant bump 95 can be formed.

[0117] The eleventh redundant pad 27 can be located on a top surface of the semiconductor chip 20. The eleventh redundant pad 27 can be spaced apart from the second chip pad 24. In an embodiment, the eleventh redundant pad 27 can not be in contact with the third TSV 25. The eleventh redundant pad 27 can be electrically connected to the second chip pad 24. In an embodiment, the second chip pad 24 and the eleventh redundant pad 27 can be electrically connected by an eleventh interconnection line 29. In an embodiment, the eleventh interconnection line 29 can extend along the top surface of the semiconductor chip 20.

[0118] The twelfth redundant pad 175 can be located on a bottom surface of the first stack 100. The twelfth redundant pad 175 can be spaced apart from the base pad 170. The twelfth redundant pad 175 can be electrically connected to the base pad 170. In an embodiment, the base pad 170 and the twelfth redundant pad 175 can be electrically connected by the first semiconductor device layer 120.

[0119] The third redundant bump 95 can be located between the eleventh redundant pad 27 and the twelfth redundant pad 175. The third redundant bump 95 can have various shapes, for example, a pillar structure, a ball structure, or a solder layer. The third redundant bump 95 can electrically connect the eleventh redundant pad 27 and the twelfth redundant pad 175.

[0120] Referring to Figure 14 , the semiconductor package according to some embodiments can further include a plug-in 40.

[0121] The interposer 40 can be located between the substrate 10 and the first stack 100. In an embodiment, the interposer 40 can be stacked on the top surface of the substrate 10. In an embodiment, the first interposer pads 42 can be located on the bottom surface of the interposer 40. The substrate pads 14 and the first interposer pads 42 can be connected by fourth bumps 48. In an embodiment, the substrate 10 and the interposer 40 can be electrically connected to each other.

[0122] In an embodiment, the first stack 100 can be stacked on the interposer 40. In an embodiment, the second interposer pads 43 can be located on the top surface of the interposer 40. The second interposer pads 43 and the base pads 170 can be connected by the base bumps 190. In an embodiment, the interposer 40 and the first stack 100 can be electrically connected to each other.

[0123] In an embodiment, the first stack 100 and the semiconductor chip 20 can be stacked in series on the top surface of the interposer 40. The interposer 40 can facilitate the connection between the substrate 10 and the first stack 100 or the connection between the semiconductor chip 20 and the first stack 100. In an embodiment, the interposer 40 can help to reduce or prevent warpage of the semiconductor package.

[0124] In an embodiment, the interposer 40 can include the fifth semiconductor substrate 41, the second interline insulating film 44, and the second wires 46 in the second interline insulating film 44. The second wires 46 can be stacked from the top surface of the fifth semiconductor substrate 41. In an embodiment, some of the second wires 46 can connect the substrate 10 and the first stack 100, and some other of the second wires 46 can connect the semiconductor chip 20 and the second stack 200.

[0125] Referring to Figure 15 The semiconductor package according to some embodiments can further include a fourth TSV 45.

[0126] The fourth TSV 45 can pass through the fifth semiconductor substrate 41. In an embodiment, the first interposer pads 42 can be in contact with the fourth TSV 45. In an embodiment, the first interposer pads 42 can be in contact with the fourth TSV 45 exposed from the bottom surface of the interposer 40 through the fifth semiconductor substrate 41 or the fourth TSV 45 exposed at the bottom surface of the interposer 40.

[0127] In an embodiment, the semiconductor package can include the thirteenth redundancy pad 15, the fourteenth redundancy pad 43_1, and the fourth redundancy bump 49.

[0128] A thirteenth redundant pad 15 can be located on the top surface of the substrate 10. The thirteenth redundant pad 15 can be spaced apart from the substrate pad 14. The thirteenth redundant pad 15 can be electrically connected to the substrate pad 14. In embodiments, the substrate pad 14 and the thirteenth redundant pad 15 can be electrically connected by a twelfth interconnect line 16. The twelfth interconnect line 16 may, for example, extend along the top surface of the substrate 10.

[0129] A fourteenth redundant pad 43_1 can be located on the bottom surface of the interposer 40. The fourteenth redundant pad 43_1 can be spaced apart from the first interposer pad 42. In embodiments, the fourteenth redundant pad 43_1 can not be in contact with the fourth TSV 45. The fourteenth redundant pad 43_1 can be electrically connected to the first interposer pad 42. In embodiments, the first interposer pad 42 and the fourteenth redundant pad 43_1 can be electrically connected by a thirteenth interconnect line 47. The thirteenth interconnect line 47 may, for example, extend along the bottom surface of the interposer 40.

[0130] A fourth redundant bump 49 can be located between the thirteenth redundant pad 15 and the fourteenth redundant pad 43_1. The fourth redundant bump 49 can have various shapes, for example, a pillar structure, a ball structure, or a solder layer. The fourth redundant bump 49 can electrically connect the thirteenth redundant pad 15 and the fourteenth redundant pad 43_1.

[0131] By way of summary and review, semiconductor chips in which through silicon vias (TSVs) are formed and multi-chip semiconductor packages in which a plurality of semiconductor chips are stacked have been considered.

[0132] One or more embodiments can provide a semiconductor package including through silicon vias (TSVs).

[0133] One or more embodiments can provide a semiconductor package having improved product reliability.

[0134] Example embodiments have been disclosed herein, although the use of specific terms is solely for the purpose of providing a specific example embodiment and not in a limiting sense. In some instances, features, characteristics, and / or elements described in connection with a particular embodiment can be used in conjunction with, or switched with, features, characteristics, and / or elements described in connection with other embodiments, unless otherwise contraindicated by the context. Therefore, those skilled in the art will recognize that the spirit and scope of the present application are dictated by the appended claims, and the description in this document is to be construed as only a limiting to the pertinence of the inventive subject matter.

Claims

1. A semiconductor package, comprising: A first stacked assembly includes a first semiconductor substrate; Multiple through-silicon vias pass through the first semiconductor substrate; A second stack member is located on the first stack member, and the second stack member includes a second surface facing the first surface of the first stack member; A first pad is located on a first surface of the first stack, and the first pad is in contact with one or more of the plurality of through-silicon vias; The second pad is located on the second surface of the second stack; A bump that connects the first pad and the second pad; A first redundant pad is located on a first surface of the first stack, the first redundant pad is spaced apart from the first pad and does not contact the plurality of through-silicon vias; The second redundant pad is located on the second surface of the second stack and is spaced apart from the second pad. Redundant bumps, which connect the first redundant pad and the second redundant pad; and Interconnect lines extending along the first surface of the first stack, in: The first pad and the first redundant pad are electrically connected to each other. The second pad and the second redundant pad are electrically connected to each other, and The interconnect is electrically connected to the first pad and the first redundant pad.

2. The semiconductor package according to claim 1, wherein: When measured from the first surface of the first stack, the height of the first pad is greater than the height of the interconnect, and When measured from the first surface of the first stack, the height of the first redundant pad is greater than the height of the interconnect.

3. The semiconductor package according to claim 1, wherein: The second stack includes a second semiconductor substrate and a semiconductor device layer on the second semiconductor substrate, and The semiconductor device layer is electrically connected to the second pad and the second redundant pad.

4. The semiconductor package according to claim 3, wherein: The semiconductor device layer includes an inter-line insulating film and lines stacked in the inter-line insulating film, and The line closest to the second surface stacked in the inter-line insulating film contacts the second pad and also contacts the second redundant pad.

5. The semiconductor package of claim 1, further comprising a second interconnect extending along a second surface of the second stack, in, The second interconnect is electrically connected to the second pad and the second redundant pad.

6. The semiconductor package according to claim 1, wherein, The distance between the first pad and the first redundant pad is in the range of 3μm to 8μm.

7. The semiconductor package according to claim 1, wherein, The width of the first pad is in the range of 15μm to 30μm.

8. A semiconductor package, comprising: A first stack includes a central region and an edge region surrounding the central region, the first stack including a first semiconductor substrate; Multiple through-silicon vias pass through the first semiconductor substrate; One or more first pads are located on the top surface of the edge region of the first stack, and the one or more first pads are in contact with one or more of the plurality of through-silicon vias; One or more first redundant pads are located on the top surface of the edge region of the first stack, the one or more first redundant pads are spaced apart from the one or more first pads and do not contact the plurality of through silicon vias; as well as One or more first interconnects extend along the top surface of the edge region of the first stack to electrically connect the one or more first pads and the one or more first redundant pads. Wherein, the first semiconductor substrate includes an edge surface extending in a first direction, and The distance between the edge region and the edge surface is 200 μm or less.

9. The semiconductor package according to claim 8, wherein: The one or more first redundant pads include a plurality of first redundant pads, and The number of first redundant pads electrically connected to a first pad close to the center of the first stack in the plan view is less than the number of first redundant pads electrically connected to another first pad far from the center of the first stack in the plan view.

10. The semiconductor package according to claim 8, wherein: The one or more first pads and the one or more first redundant pads are arranged in the first direction.

11. The semiconductor package according to claim 8, wherein: The one or more first pads and the one or more first redundant pads are arranged in a second direction intersecting the first direction.

12. The semiconductor package of claim 11, further comprising: The second redundant pad is located on the top surface of the edge region of the first stack, the second redundant pad is spaced apart from the one or more first pads and the one or more first redundant pads, and does not contact the plurality of through-silicon vias; as well as A second interconnect extends along the top surface of the edge region of the first stack to electrically connect the one or more first pads and the second redundant pad. The one or more first pads and the second redundant pads are arranged in the first direction.

13. The semiconductor package according to claim 12, further comprising: A third redundant pad is located on the top surface of the edge region of the first stack, the third redundant pad being spaced apart from the one or more first pads, the one or more first redundant pads and the second redundant pad, and not in contact with the plurality of through-silicon vias; as well as A third interconnect extends along the top surface of the edge region of the first stack to electrically connect the one or more first pads and the third redundant pad. Wherein, the one or more first pads and the third redundant pads are arranged in a third direction different from the first direction and the second direction.

14. The semiconductor package according to claim 8, wherein, The first interconnect is in contact with the side surface of the one or more first pads and the side surface of the one or more first redundant pads.

15. The semiconductor package according to claim 8, wherein, Each first pad and each first redundant pad are in contact with the top surface of the first interconnect.

16. A semiconductor package, comprising: A first semiconductor chip includes a first semiconductor substrate and a first semiconductor device layer on the bottom surface of the first semiconductor substrate; The second semiconductor chip includes a second semiconductor substrate and a second semiconductor device layer on the bottom surface of the second semiconductor substrate, and the second semiconductor chip is located on the first semiconductor chip; Multiple first through-silicon vias pass through the first semiconductor substrate; A first pad is located on the top surface of the first semiconductor substrate, and the first pad is in contact with one or more of the plurality of first through-silicon vias; The second pad is located on the bottom surface of the second semiconductor device layer; A bump that connects the first pad and the second pad; The first redundant pad is located on the top surface of the first semiconductor substrate. The first redundant pad is spaced apart from the first pad and does not contact the plurality of first through-silicon vias; Interconnects that extend along the top surface of the first semiconductor substrate and connect the first pad and the first redundant pad; The second redundant pad is located on the bottom surface of the second semiconductor device layer and is spaced apart from the second pad. as well as Redundant bumps connect the first redundant pad and the second redundant pad. The second semiconductor device layer is electrically connected to the second pad and the second redundant pad.

17. The semiconductor package of claim 16, wherein: The first semiconductor chip further includes a protective layer that covers the top surface of the first semiconductor substrate, and The plurality of first through-silicon vias pass through the protective layer.

18. The semiconductor package of claim 16, further comprising a filler layer filling the space between the first semiconductor chip and the second semiconductor chip.

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