3D NAND memory and method of manufacturing the same

Abstract

The application provides a manufacturing method of a 3D NAND memory, comprising the following steps: forming at least one first insulating layer and at least one first sacrificial layer on a substrate; forming a second sacrificial layer with a thickness greater than the first sacrificial layer; etching and removing a preset size portion of the second sacrificial layer and a preset size portion of the at least one first sacrificial layer; forming at least one first charge storage layer and a second charge storage layer, wherein the width of the first charge storage layer is greater than that of the second charge storage layer; and etching and removing the second charge storage layer and part of the at least one first charge storage layer. The manufacturing method of the 3D NAND memory provided by the application does not include a charge storage layer in the top selection gate layer, and in the process of opening or closing the top selection gate, the weak electron injection effect caused by the migration of electrons in the polycrystalline silicon channel layer to the charge storage layer can be avoided, so that the threshold voltage of the top selection gate is stable.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor manufacturing, and particularly relates to a 3D NAND memory and a manufacturing method thereof. BACKGROUND

[0002] NAND flash is a better storage device than hard disk drive, and is widely used in electronic products as people pursue low power consumption, light weight and good performance nonvolatile storage products. The planar structure of NAND flash has reached the limit of practical expansion, in order to further improve the storage capacity and reduce the cost per bit of storage, the 3D structure of NAND memory is proposed.

[0003] At present, the TSG (top select gate) of the CTF (charge trapping) type 3D NAND memory is ONOP (blocking layer-charge storage layer-tunneling layer-polysilicon channel layer) type, when the TSG is turned on or turned off, the distribution of charges in the polysilicon channel layer is affected, part of the electrons in the polysilicon channel layer migrate to the charge storage layer, and a weak electron injection effect is generated, so that the threshold voltage of the TSG is unstable, and the data read-write ability of the 3D NAND memory is unstable, thereby affecting the control ability of the TSG. SUMMARY

[0004] In order to solve the above technical problems, the present application provides a 3D NAND memory and a manufacturing method thereof, the top select gate of the 3D NAND memory does not exist charge storage layer, in the process of turning on or turning off the top select gate, the migration of the electrons in the polysilicon channel layer to the charge storage layer can be avoided, so that the top select gate has a stable threshold voltage.

[0005] The application provides a manufacturing method of a 3D NAND memory, which comprises the following steps: providing a substrate; forming a stack layer on the substrate, wherein the stack layer comprises at least one first insulating layer and at least one first sacrificial layer, and the first insulating layer and the first sacrificial layer are alternately stacked, and the number of layers of the at least one first insulating layer is one more than the number of layers of the at least one first sacrificial layer; forming a second sacrificial layer on a side of the stack layer away from the substrate, and the thickness of the second sacrificial layer is greater than the thickness of the first sacrificial layer; forming a second insulating layer on a side of the second sacrificial layer away from the stack layer; etching the second insulating layer, the second sacrificial layer and the stack layer in a stacking direction to form at least one channel hole penetrating through the second insulating layer, the second sacrificial layer and the stack layer, so that the second insulating layer, the second sacrificial layer, the at least one first insulating layer and the at least one first sacrificial layer have side walls exposed to the at least one channel hole; etching and removing a preset size of the second sacrificial layer and a preset size of the at least one first sacrificial layer from the at least one channel hole, so that the side walls of the second sacrificial layer and each first sacrificial layer are recessed inward by the same size; depositing and forming a charge storage layer in the at least one channel hole, wherein the charge storage layer comprises at least one first charge storage layer covering the side wall of the first sacrificial layer and a second charge storage layer covering the side wall of the second sacrificial layer, and the width of the first charge storage layer is greater than that of the second charge storage layer, so that the side wall of the first charge storage layer protrudes from the side wall of the second charge storage layer; etching the charge storage layer from the at least one channel hole, and removing the second charge storage layer and part of the at least one first charge storage layer, to form at least one target charge storage layer covering the side wall of the first sacrificial layer.

[0006] The 3D NAND memory provided by the application comprises a substrate, a top selection gate layer, at least one control gate layer, at least one first insulating layer, at least one channel hole and a second insulating layer. Each control gate layer comprises a first conductive layer and a target charge storage layer, and the first insulating layer and the first conductive layer are alternately stacked on the substrate. The number of layers of the at least one first insulating layer is one more than the number of layers of the first conductive layer of the at least one control gate layer, and the first insulating layer protrudes from the first conductive layer in a direction perpendicular to the stacking direction. The top selection gate layer comprises a second conductive layer, and the second conductive layer is stacked on a side of the first insulating layer away from the control gate layer. The thickness of the second conductive layer is greater than the thickness of the first conductive layer, and the first insulating layer adjacent to the second conductive layer protrudes from the second conductive layer in a direction perpendicular to the stacking direction. The second insulating layer covers a side of the second conductive layer away from the first insulating layer, and the second insulating layer protrudes from the second conductive layer in a direction perpendicular to the stacking direction. The channel hole penetrates the second insulating layer, the second conductive layer, the first insulating layer and the first conductive layer in the stacking direction, and the charge storage layer covers the side wall of the first conductive layer exposed to the at least one channel hole.

[0007] The 3D NAND memory and the manufacturing method thereof provided by the application remove the second charge storage layer covering the side wall of the second sacrificial layer by etching to form a top selection gate layer not comprising a charge storage layer, so that when the top selection gate is opened or turned off, the electrons in the second polysilicon channel layer of the top selection gate layer cannot migrate to the charge storage layer, and the threshold voltage of the top selection gate is stable, so that the top selection gate has stable control ability, and the first charge storage layer covering the side wall of the first sacrificial layer is reserved, so that the data storage function of the control gate layer comprising the first charge storage layer is not affected. BRIEF DESCRIPTION OF DRAWINGS

[0008] In order to more clearly illustrate the technical solutions of the application, the drawings required in the embodiments will be briefly introduced below. Obviously, the drawings described below are some embodiments of the application, and other drawings can also be obtained by those skilled in the art without creative effort.

[0009] Figure 1 The manufacturing method flow chart of the 3D NAND memory provided by the embodiment of the application.

[0010] Figures 2 to 8 The cross-sectional structure schematic diagram of the 3D NAND memory corresponding to the steps in the embodiment. Figure 1 ​

[0011] Figure 9 A cross-sectional structure schematic diagram of the 3D NAND memory after forming the blocking layer.

[0012] Figure 10 A cross-sectional structure schematic diagram of the 3D NAND memory after removing the third charge storage layer.

[0013] Figure 11 A flow chart of a manufacturing method of the 3D NAND memory provided by another embodiment of the present application.

[0014] Figures 12 to 17 A cross-sectional structure schematic diagram of the 3D NAND memory corresponding to the step in the Figure 11

[0015] Figure 18 A cross-sectional structure schematic diagram of the 3D NAND memory provided by an embodiment of the present application.

[0016] Reference signs:

[0017] Substrate 10; stacked layer 20; first insulating layer 201; first sacrificial layer 202; second sacrificial layer 30; second insulating layer 40; channel hole 50; blocking layer 60; first blocking layer 601; second blocking layer 602; third blocking layer 603; charge storage layer 70; first charge storage layer 701; second charge storage layer 702; target charge storage layer 703; third charge storage layer 705; tunneling layer 80; first tunneling layer 801; second tunneling layer 802; third tunneling layer 803; polysilicon channel layer 85; first polysilicon channel layer 851; second polysilicon channel layer 852; third polysilicon channel layer 853; oxide layer 90; polysilicon plug 95; first recess 2021; second recess 301; third recess 303; fourth recess 2013; first conductive layer 2022; second conductive layer 302; control gate layer 11; top select gate layer 12; 3D NAND memory 100. DETAILED DESCRIPTION

[0018] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort belong to the scope of protection of the present application.

[0019] ​In the description of the present application, the terms "first", "second", "third", etc. are used to distinguish different objects, and are not used to describe a specific order, in addition, the terms "upper", "inner", "outer", etc. indicate the orientation or positional relationship shown in the drawings, and are only used to facilitate the description of the present application and simplify the description, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present application.

[0020] It should be noted that the diagrams provided in the embodiments of the present application only schematically illustrate the basic concepts of the present application, although only the components related to the present application are shown in the diagrams, rather than the number, shape and size of the components when actually implemented, the actual implementation of each component can be arbitrarily changed in shape, number and proportion, and the layout form of the components can also be more complex.

[0021] Please refer to Figures 1 to 8 , Figure 1 The flow chart of the manufacturing method of the 3D NAND memory provided in the embodiments of the present application is shown in Figures 2 to 8 The cross-sectional structure schematic diagram of the 3D NAND memory corresponding to the steps in Figure 1 The manufacturing method of the 3D NAND memory includes the following steps: Figure 1

[0022] S101: providing a substrate 10.

[0023] S102: as shown in the figure, a stack layer 20 is formed on the substrate 10, the stack layer 20 includes at least one first insulating layer 201 and at least one first sacrificial layer 202, the first insulating layer 201 and the first sacrificial layer 202 are alternately stacked, wherein the number of layers of the at least one first insulating layer 201 is one more than the number of layers of the at least one first sacrificial layer 202. Figure 2 S103: as shown in the figure, a second sacrificial layer 30 is formed on the side of the stack layer 20 away from the substrate 10, the thickness of the second sacrificial layer 30 is greater than the thickness of the first sacrificial layer 202.

[0024] Figure 3 S104: as shown in the figure, a second insulating layer 40 is formed on the side of the second sacrificial layer 30 away from the stack layer 20.

[0025] S105: as shown in the figure, Figure 4

[0026] S106: as shown in the figure, Figure 5 ​​​As shown, the second insulating layer 40, the second sacrificial layer 30, and the stacked layer 20 are etched along the stacking direction of each layer of the stacked layer 20 to form at least one channel hole 50 penetrating the second insulating layer 40, the second sacrificial layer 30, and the stacked layer 20, such that the second insulating layer 40, the second sacrificial layer 30, the at least one first insulating layer 201, and the at least one first sacrificial layer 202 have sidewalls exposed in the at least one channel hole 50.

[0027] S106: As Figure 6 As shown, a predetermined size portion of the second sacrificial layer 30 and a predetermined size portion of the at least one first sacrificial layer 202 are etched away from the at least one channel hole 50, such that the sidewalls of the second sacrificial layer 30 and each of the first sacrificial layers 202 are all recessed inward by the same size. Here, the predetermined size portion refers to a portion having a predetermined size, so that after etching away the predetermined size portion of the second sacrificial layer 30 and the predetermined size portion of the at least one first sacrificial layer 202, the sidewalls of the second sacrificial layer 30 and each of the first sacrificial layers 202 are all recessed inward by the same predetermined size. The predetermined size refers to the size along a direction perpendicular to the hole wall of the channel hole 50.

[0028] S107: As Figure 7 As shown, a charge storage layer 70 is deposited within the at least one channel hole 50. The charge storage layer 70 includes at least one first charge storage layer 701 covering the sidewall of the first sacrificial layer 202 and a second charge storage layer 702 covering the sidewall of the second sacrificial layer 30. The width of the first charge storage layer 701 is greater than that of the second charge storage layer 702, such that the sidewall of the first charge storage layer 701 protrudes beyond the sidewall of the second charge storage layer 702.

[0029] S108: As Figure 8 As shown, the charge storage layer 70 is etched from the at least one channel hole 50, while the second charge storage layer 702 and a portion of the at least one first charge storage layer 701 are removed to form at least one target charge storage layer 703, which covers the sidewall of the first sacrificial layer 202.

[0030] The substrate 10 may be a semiconductor material, such as silicon or germanium.

[0031] The first insulating layer 201 and the second insulating layer 40 may be silicon dioxide layers. The first sacrificial layer 202, the second sacrificial layer 30, and the charge storage layer 70 may be silicon nitride layers.

[0032] The thickness of the second sacrificial layer 30 and the first sacrificial layer 202 is the dimension of the second sacrificial layer 30 and the first sacrificial layer 202 in the stacking direction.

[0033] The widths of the first charge storage layer 701 and the second charge storage layer 702 are the dimensions of the first charge storage layer 701 and the second charge storage layer 702 in the direction perpendicular to the stacking direction.

[0034] The following is combined Figures 2 to 8 The manufacturing method of the 3D NAND memory will be further described in detail.

[0035] Please refer to it again. Figure 2 , Figure 2 for Figure 1 A schematic diagram of the cross-sectional structure of the 3D NAND memory obtained after step S102. Figure 2 As shown, forming the stacked layer 20 on the substrate 10 includes: forming a first insulating layer 201 on the substrate 10; forming a first sacrificial layer 202 on the side of the first insulating layer 201 away from the substrate 10; and repeatedly and alternately stacking the first insulating layer 201 and the first sacrificial layer 202 to form at least one first insulating layer 201 and at least one first sacrificial layer 202, wherein the number of layers of the at least one first insulating layer 201 is one more than the number of layers of the at least one first sacrificial layer 202.

[0036] Specifically, the first insulating layer 201 can be formed by chemical vapor deposition. For example, the substrate 10 is placed in the reaction chamber of a vertical furnace tube, and TEOS (tetraethyl orthosilicate) and carrier gas N2 are introduced into the reaction chamber. TEOS decomposes to produce silicon dioxide, and the silicon dioxide is uniformly deposited on the substrate 10 to form the first insulating layer 201. Alternatively, the substrate 10 is placed in the reaction chamber of a vertical furnace tube, and DCS (dichlorosilane) and N2O are introduced into the reaction chamber. DCS and N2O react to generate SiO2, N2 and HCl, and the generated SiO2 is uniformly deposited on the substrate 10 to form the first insulating layer 201.

[0037] In some other embodiments, the first insulating layer 201 can be formed by atomic layer deposition. For example, the substrate 10 is placed in the reaction chamber of a vertical furnace tube, and Si[N(CH3)3]3H and O3 are introduced into the reaction chamber. Si[N(CH3)3]3H and O3 react to generate silicon dioxide, and the generated silicon dioxide is uniformly deposited on the substrate 10 to form the first insulating layer 201.

[0038] In some embodiments, the first sacrificial layer 202 can be formed by a chemical vapor deposition process, for example, DCS (dichlorosilane) and ammonia gas are introduced into a reaction chamber, the DCS reacts with the ammonia gas to generate silicon nitride, and the generated silicon nitride is uniformly deposited on the first insulating layer 201 to form the first sacrificial layer 202; for another example, SiH4 and ammonia gas are introduced into a reaction chamber, the SiH4 reacts with the ammonia gas to generate silicon nitride, and the generated silicon nitride is uniformly deposited on the first insulating layer 201 to form the first sacrificial layer 202.

[0039] Please refer again to Figure 3 , Figure 3 for Figure 1 the cross-sectional structure of the 3D NAND memory obtained after step S103 is completed. As shown in Figure 3 , a second sacrificial layer 30 is formed on the side of the stack layer 20 away from the substrate 10, and the thickness of the second sacrificial layer 30 is greater than the thickness of the first sacrificial layer 202.

[0040] Among them, the second sacrificial layer 30 can be formed by a chemical vapor deposition process, and the specific process can refer to the process of forming the first sacrificial layer 202 described above, which will not be repeated here.

[0041] Please refer again to Figure 4 , Figure 4 for Figure 1 the cross-sectional structure of the 3D NAND memory obtained after step S104 is completed. As shown in Figure 4 , a second insulating layer 40 is formed on the side of the second sacrificial layer 30 away from the stack layer 20. Among them, the second insulating layer 40 can be formed by a chemical vapor deposition process or an atomic layer deposition process, and the specific process can refer to the process of forming the first insulating layer 201 described above, which will not be repeated here.

[0042] Please refer again to Figure 5 , Figure 5 for Figure 1 the cross-sectional structure of the 3D NAND memory obtained after step S105 is completed. As shown in Figure 5 , the second insulating layer 40, the second sacrificial layer 30 and the stack layer 20 are etched along the stacking direction to form at least one channel hole 50 penetrating through the second insulating layer 40, the second sacrificial layer 30 and the stack layer 20, so that the second insulating layer 40, the second sacrificial layer 30, the at least one first insulating layer 201 and the at least one first sacrificial layer 202 have a side wall exposed to the at least one channel hole 50.

[0043] The at least one channel hole 50 can be formed by photolithography and etching processes. Specifically, photoresist is spin-coated onto the second insulating layer 40 to form a photoresist layer covering the top of the second insulating layer 40. Part of the photoresist layer is removed by exposure and development processes to form at least one opening in the photoresist layer, the opening exposing part of the second insulating layer 40. Then, the at least one channel hole 50 is formed by sequentially etching the second insulating layer 40, the second sacrificial layer 30, the at least one first insulating layer 201, and the at least one first sacrificial layer 202 from the at least one opening by dry or wet etching processes.

[0044] Please refer to it again. Figure 6 , Figure 6 This is a schematic diagram of the cross-sectional structure of the 3D NAND memory after step S106 is completed. Figure 6 As shown, in some embodiments, a wet etching process is used to etch away a preset size portion of the second sacrificial layer 30 and a preset size portion of the at least one first sacrificial layer 202, so that the sidewalls of the second sacrificial layer 30 and each first sacrificial layer 202 are recessed inward by the same size.

[0045] Specifically, a wet etching machine is used for etching. The wet etching machine includes an etching tank filled with a hot phosphoric acid solution. The 3D NAND memory is completely immersed in the hot phosphoric acid solution for a preset time t1. The hot phosphoric acid solution enters the 3D NAND memory through at least one channel hole 50 and selectively etches the second sacrificial layer 30 and the first sacrificial layer 202. The preset time t1 can be obtained based on the etching rate v1 of the wet etching process and the preset size L of the second sacrificial layer 30 and the first sacrificial layer 202 to be removed, that is, t1 = L / v1.

[0046] The volume fraction of the hot phosphoric acid solution ranges from 85% to 88%, and the temperature range of the hot phosphoric acid solution ranges from 155°C to 165°C.

[0047] After the etching process, the sidewall of the second sacrificial layer 30 is recessed inward so that the second sacrificial layer 30 and the two adjacent first insulating layers 201 form a third groove 303. The sidewall of each first sacrificial layer 202 is recessed inward so that the first sacrificial layer 202 and the two adjacent first insulating layers 201 form a fourth groove 2013. The inner diameter of the third groove 303 is larger than that of the fourth groove 2013.

[0048] In some other embodiments, the 3D NAND memory can be completely immersed in a hydrofluoric acid solution, and the preset size portion of the second sacrificial layer 30 and the preset size portion of the first sacrificial layer 202 can be removed by hydrofluoric acid etching.

[0049] In other embodiments, a predetermined size portion of the second sacrificial layer 30 and a predetermined size portion of the at least one first sacrificial layer 202 can be etched away using a dry etching process. Specifically, the 3D NAND memory is placed in the reaction chamber of an ICP (inductively coupled plasma) device, and a fluorine-containing gas, such as CHF3, is introduced into the reaction chamber. The plasma generated by the device and the fluorine-containing gas work together to etch away the predetermined size portion of the second sacrificial layer 30 and the predetermined size portion of the at least one first sacrificial layer 202.

[0050] Please refer to it again. Figure 7 , Figure 7 This is a schematic diagram of the cross-sectional structure of the 3D NAND memory after step S107 is completed. Figure 7 As shown, a charge storage layer 70 is deposited within the at least one channel hole 50. The charge storage layer 70 includes at least one first charge storage layer 701 covering the sidewall of the first sacrificial layer 202 and a second charge storage layer 702 covering the sidewall of the second sacrificial layer 30. The width of the first charge storage layer 701 is greater than that of the second charge storage layer 702, such that the sidewall of the first charge storage layer 701 protrudes beyond the sidewall of the second charge storage layer 702.

[0051] Specifically, the charge storage layer 70 can be formed by chemical vapor deposition or atomic layer deposition. For example, the 3D NAND memory is placed in the reaction chamber of a vertical furnace tube, and DCS (dichlorosilane) and ammonia are introduced into the reaction chamber for a preset time t2. The DCS and ammonia react to generate silicon nitride. The generated silicon nitride is uniformly deposited in the third groove 303 and covers the sidewall of the second sacrificial layer 30 to form the second charge storage layer 702. At the same time, the silicon nitride is uniformly deposited in the fourth groove and covers the sidewall of the first sacrificial layer 202 to form the first charge storage layer 701.

[0052] The preset time t2 can be calculated according to the deposition rate v2 of the silicon nitride and the deposition thickness T1 of the silicon nitride, that is, t2=T1 / v2. The deposition thickness T1 of the silicon nitride is greater than half of the thickness of the first sacrificial layer 202 and less than half of the thickness of the second sacrificial layer 30, so that the silicon nitride can fill the fourth groove 2013 when deposited in the fourth groove 2013, and the silicon nitride covers the inner wall of the third groove 303 when deposited in the third groove 303, without filling the third groove 303, so that the width of the first charge storage layer 701 covering the side wall of the first sacrificial layer 202 is greater than the width of the second charge storage layer 702 covering the side wall of the second sacrificial layer 30. The width of the first charge storage layer 701 and the second charge storage layer 702 is the size of the first charge storage layer 701 and the second charge storage layer 702 in the direction perpendicular to the stacking direction, so that part of the first charge storage layer 701 covering the side wall of the first sacrificial layer 202 is removed while the second charge storage layer 702 covering the side wall of the second sacrificial layer 30 is completely removed by the etching process, and the remaining part of the first charge storage layer 701 still covers the side wall of the first sacrificial layer 202 to form the target charge storage layer 703.

[0053] Please refer again to Figure 8 , Figure 8 The cross-sectional structure of the 3D NAND memory after step S108 is shown in FIG. 10. As shown in FIG. 10, in some embodiments, the wet etching process is used to etch the charge storage layer 70 from the at least one channel hole 50, and the second charge storage layer 702 and part of the at least one first charge storage layer 701 are removed. Figure 8

[0054] Specifically, a wet etching machine is used for etching, which includes an etching tank containing a hot phosphoric acid solution. The 3D NAND memory is completely immersed in the hot phosphoric acid solution for a preset time t3, which can be calculated according to the etching rate v3 of the wet etching process and the width W of the second charge storage layer 702, that is, t3=W / v3. The hot phosphoric acid solution enters the 3D NAND memory from the at least one channel hole 50 and selectively etches the charge storage layer 70. Because the width of the first charge storage layer 701 is greater than the width of the second charge storage layer 702, the second charge storage layer 702 is completely removed and part of the first charge storage layer 701 is removed at the same etching time, and the remaining part of the first charge storage layer 701 still covers the side wall of the first blocking layer 601 to form the target charge storage layer 703. ​

[0055] wherein the hot phosphoric acid solution has a volume fraction ranging from 85% to 88% and a temperature ranging from 155°C to 165°C.

[0056] In some other embodiments, the 3D NAND memory can be completely immersed in a hydrofluoric acid solution, and a preset size portion of the second sacrificial layer 30 and a preset size portion of the first sacrificial layer 202 can be removed by etching with the hydrofluoric acid.

[0057] In some other embodiments, the charge storage layer 70 can be etched by a dry etching process. Specifically, the 3D NAND memory is placed in a reaction chamber of an ICP (inductively coupled plasma) device, a fluorine-containing gas, for example, CHF3, is introduced into the reaction chamber, and a plasma generated by the device acts together with the fluorine-containing gas to simultaneously etch and remove the second charge storage layer 702 and part of the at least one first charge storage layer 701.

[0058] Please refer to Figure 9 , Figure 9 is a schematic cross-sectional structure diagram of the 3D NAND memory after the formation of the blocking layer. As shown in Figure 9 some embodiments, before the formation of the charge storage layer 70, the manufacturing method of the 3D NAND memory further comprises: depositing a blocking layer 60 from the at least one channel hole 50, the blocking layer 60 comprising at least one first blocking layer 601 covering the sidewall of the first sacrificial layer 202 and at least one second blocking layer 602 covering the sidewall of the second sacrificial layer 30. The deposition of the charge storage layer 70 from the at least one channel hole 50, the charge storage layer 70 comprising at least one first charge storage layer 701 covering the sidewall of the first blocking layer 601 and at least one second charge storage layer 702 covering the sidewall of the second blocking layer 602, comprises: depositing the charge storage layer 70 from the at least one channel hole 50, the charge storage layer 70 comprising at least one first charge storage layer 701 covering the sidewall of the first blocking layer 601 and at least one second charge storage layer 702 covering the sidewall of the second blocking layer 602.

[0059] wherein the blocking layer 60 can be formed by a chemical vapor deposition process or an atomic layer deposition process. Specifically, the 3D NAND memory is placed in a reaction chamber of a vertical furnace tube, and TEOS (tetraethyl orthosilicate) and a carrier gas N2 are introduced into the reaction chamber for a preset time t4. TEOS is decomposed to generate silicon dioxide, which is uniformly deposited in the at least one channel hole 50 and covers the sidewalls of the first sacrificial layer 202 and the second sacrificial layer 30 to form the first blocking layer 601 and the second blocking layer 602, respectively, and the thicknesses of the first blocking layer 601 and the second blocking layer 602 are the same.

[0060] wherein the preset time t4 can be calculated according to the deposition rate v4 of the silicon dioxide and the deposition thickness T2 of the silicon dioxide, i.e., t4 = T2 / v4, wherein the deposition thickness T2 of the silicon dioxide is less than half of the thickness of the second sacrificial layer 30, so that when the silicon dioxide is deposited in the fourth recess 2013, the silicon dioxide covers the inner wall of the fourth recess 2013 and does not fill the fourth recess 2013, so that the silicon nitride can be deposited in the fourth recess 2013 to fill the fourth recess 2013 when the charge storage layer 70 is formed.

[0061] Please refer to Figure 9 In some embodiments, the blocking layer 60 further comprises at least one third blocking layer 603 covering the sidewall of the first insulating layer 201, and the process of forming the third blocking layer 603 can be simultaneously performed with the process of forming the first blocking layer 601 and the second blocking layer 602. The charge storage layer 70 further comprises at least one third charge storage layer 705 covering the third blocking layer 603, and the process of forming the third charge storage layer 705 can be simultaneously performed with the process of forming the first charge storage layer 701 and the second charge storage layer 702.

[0062] Please refer to Figure 10 , Figure 10 is a cross-sectional structure diagram of a 3D NAND memory after removing the third charge storage layer 705. As Figure 10 shown, when the charge storage layer 70 further comprises at least one third charge storage layer 705, the manufacturing method of the 3D NAND memory further comprises etching to remove the at least one third charge storage layer 705, wherein the process of etching to remove the third charge storage layer 705 can be simultaneously performed with the process of etching to remove the second charge storage layer 702.

[0063] Please refer to Figures 11 to 17 , Figure 11 is a flow chart of a manufacturing method of a 3D NAND memory provided by another embodiment of the present application, Figures 12 to 17 is a cross-sectional structure diagram of a 3D NAND memory corresponding to the steps in Figure 11 . As Figure 11 shown, in some embodiments, the manufacturing method of the 3D NAND memory further comprises:

[0064] S110: as Figure 12As shown, a tunneling layer 80 is formed by deposition from the at least one channel hole 50, the tunneling layer 80 including at least a first tunneling layer 801 covering sidewalls of the target charge storage layer 703 and a second tunneling layer 802 covering sidewalls of the second blocking layer 602.

[0065] S111: As shown, Figure 13 As shown, a polysilicon channel layer 85 is formed by deposition from the at least one channel hole 50, the polysilicon channel layer 85 including at least a first polysilicon channel layer 851 covering sidewalls of the first tunneling layer 801 and a second polysilicon channel layer 852 covering sidewalls of the second tunneling layer 802.

[0066] S112: As shown, Figure 14 As shown, an oxide layer 90 is formed by deposition from the at least one channel hole 50, the oxide layer 90 covering sidewalls of the polysilicon channel layer 85.

[0067] S113: As shown, Figure 15 As shown, a polysilicon plug 95 is formed covering a top of the oxide layer 90.

[0068] S114: As shown, Figure 16 As shown, the at least one first sacrificial layer 202 and the second sacrificial layer 30 are etched to form at least one first recess 2021 and a second recess 301, respectively.

[0069] S115: As shown, Figure 17 As shown, the at least one first recess 2021 and the second recess 301 are filled with a conductive material to form at least one first conductive layer 2022 and a second conductive layer 302, respectively, to form at least one control gate layer 11 and a top select gate layer 12, respectively, the control gate layer 11 including the first conductive layer 2022, a first blocking layer 601, a target charge storage layer 703, a first tunneling layer 801, and a first polysilicon channel layer 851, the top select gate layer 12 including the second conductive layer 302, a second blocking layer 602, a second tunneling layer 802, and a second polysilicon channel layer 852.

[0070] Wherein, the tunneling layer 80 can be a silicon dioxide layer, the oxide layer 90 can be a silicon dioxide layer, and the conductive material can be tungsten.

[0071] Wherein, the tunneling layer 80, the polysilicon channel layer 85, the oxide layer 90, and the polysilicon plug 95 can be formed by a chemical vapor deposition process or an atomic layer deposition process.

[0072] In some embodiments, the tunneling layer 80 further includes at least one third tunneling layer covering the sidewalls of the third barrier layer 603, and the polysilicon channel layer 85 includes at least one third polysilicon channel layer covering the sidewalls of the third tunneling layer. The formation of the third tunneling layer can be performed simultaneously with the aforementioned formation of the first tunneling layer 801 and the second tunneling layer 802, and the formation of the third polysilicon channel layer can be performed simultaneously with the aforementioned formation of the first polysilicon channel layer 851 and the second polysilicon channel layer 852.

[0073] The manufacturing method of 3D NAND memory provided in this application embodiment removes the second charge storage layer 702 covering the sidewall of the second sacrificial layer 30 by etching, thereby forming a top select gate layer 12 that does not include the charge storage layer. This prevents electrons in the second polysilicon channel layer 852 of the top select gate layer 12 from migrating to the charge storage layer when the top select gate is turned on or off, thus stabilizing the threshold voltage of the top select gate. This results in stable control capability of the top select gate and stable data read / write capability of the 3D NAND memory. Furthermore, the first charge storage layer 701 covering the sidewall of the first sacrificial layer 202 is retained, so that the data storage function of the control gate layer 11 including the first charge storage layer 701 is not affected.

[0074] Please see Figure 18 , Figure 18 This is a schematic cross-sectional view of the 3D NAND memory 100 provided in an embodiment of this application. Figure 18 As shown, the 3D NAND memory 100 includes: a substrate 10, at least one control gate layer 11, a top select gate layer 12, at least one first insulating layer 201, a second insulating layer 40, and at least one channel via 50. Each control gate layer 11 includes a first conductive layer 2022 and a target charge storage layer 703. The top select gate layer 12 includes a second conductive layer 302.

[0075] The first insulating layer 201 and the first conductive layer 2022 are alternately stacked on the substrate 10. The number of layers of the at least one first insulating layer 201 is one more than the number of layers of the at least one control gate layer 11 first conductive layer 2022. The first insulating layer 201 protrudes from the first conductive layer 2022 in a direction perpendicular to the stacking direction.

[0076] The second conductive layer 302 is stacked on the first insulating layer 201 away from the control gate layer 11, wherein the thickness of the second conductive layer 302 is greater than the thickness of the first conductive layer 2022, and the thickness of the second conductive layer 302 and the first conductive layer 2022 is the dimension of the second conductive layer 302 and the first conductive layer 2022 in the stacking direction. The first insulating layer 201 adjacent to the second conductive layer 302 protrudes from the second conductive layer 302 in a direction perpendicular to the stacking direction.

[0077] The second insulating layer 40 covers the side of the second conductive layer 302 away from the first insulating layer 201, and the second insulating layer 40 protrudes from the second conductive layer 302 in a direction perpendicular to the stacking direction.

[0078] The at least one channel hole 50 penetrates the second insulating layer 40, the second conductive layer 302, the first insulating layer 201, and the first conductive layer 2022 in the stacking direction of the first insulating layer 201 and the first conductive layer 2022 and extends to the substrate 10.

[0079] The target charge storage layer 703 covers the side wall of the first conductive layer 2022 exposed to the at least one channel hole 50.

[0080] Please refer to Figure 18 In some embodiments, each control gate layer 11 further includes a first barrier layer 601, a first tunneling layer 801, and a first polysilicon channel layer 851, wherein the first barrier layer 601 covers the side wall of the first conductive layer 2022 exposed to the at least one channel hole 50 and is between the side wall of the first conductive layer 2022 and the target charge storage layer 703, and the first tunneling layer 801 and the first polysilicon channel layer 851 cover the side wall of the target charge storage layer 703 in turn.

[0081] The top select gate layer 12 further includes a second barrier layer 602, a second tunneling layer 802, and a second polysilicon channel layer 852, wherein the second barrier layer 602, the second tunneling layer 802, and the second polysilicon channel layer 852 cover the side wall of the second conductive layer 302 exposed to the at least one channel hole 50 in turn.

[0082] The oxide layer 90 covers the side wall of the first polysilicon channel layer 851 and the second polysilicon channel layer 852 exposed to the at least one channel hole 50.

[0083] The 3D NAND memory 100 further comprises an oxide layer 90 and a polysilicon plug 95, wherein the oxide layer 90 covers the exposed sidewalls of the first and second polysilicon channel layers 851 and 852 in the at least one channel hole 50, and the polysilicon plug 95 is arranged on top of the oxide layer 90.

[0084] The first insulating layer 201, the second insulating layer 40 and the oxide layer 90 can all be silicon dioxide layers.

[0085] The first barrier layer 601, the second barrier layer 602, the first tunneling layer 801 and the second tunneling layer 802 can all be silicon dioxide layers.

[0086] The target charge storage layer 703 can be a silicon nitride layer.

[0087] The first conductive layer 2022 and the second conductive layer 302 can both be tungsten layers.

[0088] In some embodiments, the 3D NAND memory 100 further comprises at least one third barrier layer 603, at least one third tunneling layer 803 and at least one third polysilicon channel layer 853, wherein the third barrier layer 603 covers the exposed sidewalls of the first insulating layer 201 in the at least one channel hole 50, the third tunneling layer 803 covers the sidewalls of the third barrier layer 603, and the third polysilicon channel layer 853 covers the sidewalls of the third tunneling layer 803.

[0089] The top select gate layer 12 of the 3D NAND memory 100 provided by the present application does not comprise a charge storage layer, so that when the top select gate is turned on or turned off, the electrons in the second polysilicon channel layer 852 of the top select gate layer 12 will not migrate to the charge storage layer, so that the threshold voltage of the top select gate is stable, thereby making the top select gate have stable control ability and making the data read-write ability of the 3D NAND memory 100 stable.

[0090] The 3D NAND memory 100 provided by the above embodiments corresponds to the manufacturing method of the 3D NAND memory described above, and the relevant parts can be mutually referred to.

[0091] It should be noted that, for the above-mentioned method embodiments, in order to simply describe, they are all expressed as a series of action combinations, but those skilled in the art should know that the present application is not limited by the action sequence described, because according to the present application, certain steps can be performed in other sequences or simultaneously.

[0092] In the above embodiments, the description of each embodiment has its own focus, and the parts not described in detail in a certain embodiment can be referred to the relevant description of other embodiments.

[0093] The above is the implementation of the embodiments of the present application. It should be pointed out that, for ordinary skilled in the art, without departing from the principles of the embodiments of the present application, a number of improvements and refinements can be made, which are also considered within the scope of protection of the present application.

Claims

1. A method of manufacturing a 3D NAND memory, characterized by, The method comprises the following steps: providing a substrate; forming a stack layer on the substrate, the stack layer comprising at least one first insulating layer and at least one first sacrificial layer, the first insulating layer and the first sacrificial layer being alternately stacked, wherein the number of layers of the at least one first insulating layer is one more than the number of layers of the at least one first sacrificial layer; forming a second sacrificial layer on a side of the stack layer away from the substrate, the second sacrificial layer having a thickness greater than that of the first sacrificial layer; forming a second insulating layer on a side of the second sacrificial layer away from the stack layer; etching the second insulating layer, the second sacrificial layer, and the stack layer in a stacking direction to form at least one channel hole penetrating through the second insulating layer, the second sacrificial layer, and the stack layer, so that the second insulating layer, the second sacrificial layer, the at least one first insulating layer, and the at least one first sacrificial layer have side walls exposed to the at least one channel hole; etching and removing a preset size portion of the second sacrificial layer and a preset size portion of the at least one first sacrificial layer from the at least one channel hole, so that the side walls of the second sacrificial layer and each first sacrificial layer are recessed inward by the same size; depositing a charge storage layer in the at least one channel hole, the charge storage layer comprising at least one first charge storage layer covering the side walls of the first sacrificial layer and at least one second charge storage layer covering the side walls of the second sacrificial layer, wherein the width of the first charge storage layer is greater than that of the second charge storage layer, so that the side walls of the first charge storage layer protrude from the side walls of the second charge storage layer; and etching the charge storage layer from the at least one channel hole while removing the second charge storage layer and part of the at least one first charge storage layer to form at least one target charge storage layer covering the side walls of the first sacrificial layer.

2. The method of claim 1, wherein, The etching and removing of the preset size portion of the second sacrificial layer and the preset size portion of the at least one first sacrificial layer from the at least one channel hole comprises: etching and removing the preset size portion of the second sacrificial layer and the preset size portion of the at least one first sacrificial layer using a wet etching process.

3. The method of claim 2, wherein, The etching and removing of the preset size portion of the second sacrificial layer and the preset size portion of the at least one first sacrificial layer using a wet etching process comprises: immersing the 3D NAND memory in a hot phosphoric acid solution for a preset time to etch the second sacrificial layer and the at least one first sacrificial layer by the hot phosphoric acid.

4. The method of claim 1, wherein, The etching of the charge storage layer from the at least one channel hole while removing the second charge storage layer and part of the at least one first charge storage layer comprises: etching the charge storage layer using a wet etching process while removing the second charge storage layer and part of the at least one first charge storage layer.

5. The method of claim 4, wherein, The etching of the charge storage layer using a wet etching process while removing the second charge storage layer and part of the at least one first charge storage layer comprises: immersing the 3D NAND memory in a hot phosphoric acid solution for a preset time to etch the charge storage layer by the hot phosphoric acid. immersing the 3D NAND memory in a hot phosphoric acid solution for a preset time, etching the second charge storage layer and etching the at least one first charge storage layer by the hot phosphoric acid.

6. The method of claim 1, wherein, Before the forming the charge storage layer, the method further comprises: depositing a barrier layer from the at least one channel hole, the barrier layer comprising at least one first barrier layer covering the first sacrificial layer sidewall and at least one second barrier layer covering the second sacrificial layer sidewall; depositing a charge storage layer from the at least one channel hole, the charge storage layer comprising at least one first charge storage layer covering the first barrier layer sidewall and at least one second charge storage layer covering the second barrier layer sidewall, comprising: depositing a charge storage layer from the at least one channel hole, the charge storage layer comprising at least one first charge storage layer covering the first barrier layer sidewall and at least one second charge storage layer covering the second barrier layer sidewall.

7. The method of claim 6, wherein, The barrier layer further comprises at least one third barrier layer covering the first insulating layer sidewall, and the charge storage layer further comprises at least one third charge storage layer covering the third barrier layer sidewall, and the method further comprises: etching to remove the at least one third charge storage layer.

8. The method of claim 6, wherein, The method further comprises: depositing a tunneling layer from the at least one channel hole, the tunneling layer comprising at least one first tunneling layer covering the target charge storage layer sidewall and at least one second tunneling layer covering the second barrier layer sidewall; depositing a polysilicon channel layer from the at least one channel hole, the polysilicon channel layer comprising at least one first polysilicon channel layer covering the first tunneling layer sidewall and at least one second polysilicon channel layer covering the second tunneling layer sidewall; depositing an oxide layer covering the polysilicon channel layer sidewall from the at least one channel hole; forming a polysilicon plug covering the top of the oxide layer; etching to remove the at least one first sacrificial layer and the second sacrificial layer to form at least one first recess and at least one second recess, respectively; and filling a conductive material in the at least one first recess and the at least one second recess to form at least one first conductive layer and at least one second conductive layer, respectively, to form at least one control gate layer and at least one top select gate layer, respectively, the control gate layer comprising the first conductive layer, the first barrier layer, the target charge storage layer, the first tunneling layer, and the first polysilicon channel layer, and the top select gate layer comprising the second conductive layer, the second barrier layer, the second tunneling layer, and the second polysilicon channel layer.

9. A 3D NAND memory, characterized by, The 3D NAND memory comprises: a substrate, a top select gate layer, at least one control gate layer, at least one first insulating layer, at least one channel hole, and a second insulating layer; each control gate layer comprises a first conductive layer and a target charge storage layer; the first insulating layer and the first conductive layer are alternately stacked on the substrate, the number of layers of the at least one first insulating layer is one more than the number of layers of the first conductive layer of the at least one control gate layer, and the first insulating layer protrudes from the first conductive layer in a direction perpendicular to the stacking direction; The top select gate layer comprises a second conductive layer; The second conductive layer is stacked on a side of the first insulating layer away from the control gate layer, wherein the thickness of the second conductive layer is greater than the thickness of the first conductive layer, and the first insulating layer adjacent to the second conductive layer protrudes from the second conductive layer in a direction perpendicular to the stacking direction; The second insulating layer covers a side of the second conductive layer away from the first insulating layer, and the second insulating layer protrudes from the second conductive layer in a direction perpendicular to the stacking direction; The channel hole penetrates the second insulating layer, the second conductive layer, the first insulating layer and the first conductive layer in the stacking direction; The charge storage layer covers the side wall of the first conductive layer exposed to the at least one channel hole.

10. The 3D NAND memory of claim 9, wherein, Each control gate layer further comprises a first blocking layer, a first tunneling layer and a first polysilicon channel layer, wherein the first blocking layer covers the side wall of the first conductive layer exposed to the at least one channel hole and is between the side wall of the first conductive layer and the charge storage layer, and the first tunneling layer and the first polysilicon channel layer cover the side wall of the target charge storage layer in sequence; The top select gate layer further comprises a second blocking layer, a second tunneling layer and a second polysilicon channel layer, wherein the second blocking layer, the second tunneling layer and the second polysilicon channel layer cover the side wall of the second conductive layer exposed to the at least one channel hole in sequence; The 3D NAND memory further comprises an oxide layer and a polysilicon plug, wherein the oxide layer covers the side wall of the first polysilicon channel layer and the second polysilicon channel layer exposed to the at least one channel hole, and the polysilicon plug is stacked on the top of the oxide layer.

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