Bandwidth allocation apparatus and method

Abstract

The application provides a bandwidth allocation device and method, each output port of MAC outputs bandwidth to be allocated, CPU controls path conduction or disconnection between host serial bus channel of PHY and line serial bus channel according to configuration requirement, and PHY allocates the bandwidth to be allocated and outputs. Since a group of line serial bus channels of the PHY and at least two groups of line serial bus channels share a group of host serial bus channels, and a second port encapsulated by the line serial bus channel of the PHY is compatible with optical modules of a first type and optical modules of a second type, high bandwidth utilization under low cost condition can be realized by CPU controlling path conduction or disconnection between the host serial bus channel and the line serial bus channel.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of wireless communication, in particular to a bandwidth allocation device and method. BACKGROUND

[0002] With the commercialization of 5G, coupled with the rapid development of information technology such as cloud computing, big data, the Internet of Things, artificial intelligence, and the digital transformation of traditional industries, as well as the rapid construction of data centers, the demand for optical modules for interconnection within and between data centers has increased exponentially. The uplink ports of access switches and aggregation switches have transitioned from 40G to 100G or higher bandwidth ports; the interconnection ports of data center switches have gradually transitioned from 100G to 200G and 400G. Since 2019, both 200G and 400G have grown at a rate exceeding 100G, especially the demand for 400G.

[0003] Based on the current market demand, the port design of data center switches needs to meet both 200G and 400G applications. Currently, most manufacturers either produce two types of boards to adapt to two different bandwidth outputs, which greatly increases the design and manufacturing and maintenance costs; or integrate the above two boards into one, causing serious bandwidth waste; or design several independent 200G ports and several independent 400G ports on the board, but only in a combination of one or the other, not in a compatible design.

[0004] In summary, the ports in the prior art cannot achieve a compatible design with high bandwidth utilization at a low cost when compatible with both 200G and 400G bandwidth outputs. SUMMARY

[0005] The present application provides a bandwidth allocation device and method to solve the problem that the ports in the prior art cannot achieve a compatible design with high bandwidth utilization at a low cost when compatible with both 200G and 400G bandwidth outputs.

[0006] In a first aspect, an embodiment of the present application provides a bandwidth allocation device, which comprises a media access controller (MAC), at least one physical port transceiver (PHY), and a central processing unit (CPU);

[0007] Each output port of the MAC is connected to at least two groups of host serial bus channels of the at least one PHY, wherein the at least two groups of host serial bus channels are located on the same PHY or on different PHYs;

[0008] At least one of the PHYs has a group of line-side serial bus channels encapsulated into a first port compatible with a first type of optical module, at least two groups of line-side serial bus channels of the at least one of the PHYs are encapsulated into a second port compatible with the first type and a second type of optical module, and one of the group of line-side serial bus channels and the at least two groups of line-side serial bus channels shares a group of host-side serial bus channels;

[0009] The MAC is configured to output the bandwidth to be allocated;

[0010] The CPU is configured to control the path conduction or disconnection between the host-side serial bus channels and the line-side serial bus channels according to a configuration requirement, so that the bandwidth to be allocated of each port of the MAC is fully allocated according to the configuration requirement;

[0011] The at least one of the PHYs is configured to allocate the bandwidth to be allocated and output.

[0012] In a possible implementation, the CPU is specifically configured to control part or all of the following:

[0013] Control the path conduction between the line-side serial bus channels of the first port and the shared host-side serial bus channels;

[0014] Control the path conduction between one of the line-side serial bus channels of the second port and the corresponding host-side serial bus channels;

[0015] Control the path conduction between all the line-side serial bus channels of the second port and the corresponding host-side serial bus channels.

[0016] In a possible implementation, the MAC includes a plurality of output ports, and each output port of the MAC outputs a bandwidth to be allocated of 400G;

[0017] The first type of optical module is a four-channel optical module, and the second type of optical module is an eight-channel optical module.

[0018] In a possible implementation, the corresponding bandwidth of the second type of optical module is n times the corresponding bandwidth of the first type of optical module, where n is a positive integer greater than or equal to 2.

[0019] In a possible implementation, the number of the PHYs is three, and each of the PHYs includes four groups of host-side serial bus channels and four groups of line-side serial bus channels;

[0020] Each output port of the MAC is connected to two groups of host-side serial bus channels of the three PHYs.

[0021] The line-end serial bus channels of the three PHYs corresponding to the two groups of host-end serial bus channels are encapsulated into a second port, and the rest of each group of line-end serial bus channels is encapsulated into a first port.

[0022] The four groups of host-end serial bus channels connected with any two output ports of the MAC are not located in the same PHY.

[0023] In a second aspect, an embodiment of the present application provides a switch comprising the bandwidth allocation device as described in the first aspect or any optional implementation of the first aspect.

[0024] In a third aspect, an embodiment of the present application provides a bandwidth allocation method applied to the bandwidth allocation device as described in the first aspect or any optional implementation of the first aspect, and the method comprises:

[0025] Outputting the bandwidth to be allocated through each output port of the MAC;

[0026] Controlling, by the CPU, the path conduction or disconnection between the host-end serial bus channel and the line-end serial bus channel of at least one PHY according to the configuration requirement, so that the bandwidth to be allocated of each port of the MAC is fully allocated according to the configuration requirement;

[0027] Allocating the bandwidth to be allocated by at least one PHY and outputting.

[0028] In a possible implementation, the controlling, by the CPU, the path conduction or disconnection between the host-end serial bus channel and the line-end serial bus channel of at least one PHY according to the configuration requirement comprises some or all of the following:

[0029] Controlling, by the CPU, the path conduction between the line-end serial bus channel of the first port and the shared host-end serial bus channel;

[0030] Controlling the path conduction between one group of line-end serial bus channels of the line-end serial bus channels of the second port and the corresponding host-end serial bus channel;

[0031] Controlling, by the CPU, the path conduction between all line-end serial bus channels of the second port and the corresponding host-end serial bus channel.

[0032] In a possible implementation, the MAC comprises a plurality of output ports, and the bandwidth to be allocated output by each output port of the MAC is 400G;

[0033] The first type of optical module is a four-channel optical module, and the second type of optical module is an eight-channel optical module.

[0034] In a possible implementation, the bandwidth corresponding to the second type of optical module is n times the bandwidth corresponding to the first type of optical module, where n is a positive integer greater than or equal to 2.

[0035] In a fourth aspect, an embodiment of the present application provides a computer readable storage medium, which stores a program, and when the program runs on a computer, the computer is caused to implement the method according to the third aspect or any optional implementation of the third aspect.

[0036] The present application has the following advantages:

[0037] The present application discloses a bandwidth allocation device and method, MAC, each output port is connected with at least two groups of host-side serial bus channels of PHY, a group of line-side serial bus channels of PHY is encapsulated into a first port compatible with a first type of optical module, at least two groups of line-side serial bus channels of PHY are encapsulated into a second port compatible with the first type and a second type of optical module, a group of line-side serial bus channels and a group of serial bus channels in the at least two groups of line-side serial bus channels share a group of host-side serial bus channels, the bandwidth to be allocated is output through each output port of MAC, a CPU controls the conduction or disconnection of the path between the host-side serial bus channel and the line-side serial bus channel according to the configuration requirement, and the PHY is used for allocating the bandwidth to be allocated and output. Since a group of line-side serial bus channels and a group of serial bus channels in the at least two groups of line-side serial bus channels share a group of host-side serial bus channels, and the second port is compatible with the first type of optical module and the second type of optical module, the conduction or disconnection of the path between the host-side serial bus channel and the line-side serial bus channel is controlled by the CPU, so that high bandwidth utilization can be realized under the condition of low cost. BRIEF DESCRIPTION OF DRAWINGS

[0038] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0039] Figure 1 A structural schematic diagram of a bandwidth allocation device provided by an embodiment of the present application is shown in the figure.

[0040] Figure 2 A first PHY working mode provided by the present application is shown in the figure.

[0041] Figure 3 This is a schematic diagram of the second PHY operating mode provided by the present invention;

[0042] Figure 4 This is a schematic diagram of the third PHY operating mode provided by the present invention;

[0043] Figure 5 This is a schematic diagram of a bandwidth allocation method provided by the present invention. Detailed Implementation

[0044] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are merely some embodiments of this invention, and not all embodiments. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this invention.

[0045] Based on current market demands, data center switch port designs need to simultaneously support 200G and 400G applications. Currently, most manufacturers produce two types of boards to adapt to the two different bandwidth outputs, which greatly increases design, manufacturing, and maintenance costs. Alternatively, they integrate both boards onto a single board, resulting in significant bandwidth waste. Another approach is to design several independent 200G ports and several independent 400G ports on the same board, but this method only allows for one possible combination and cannot achieve compatible design. Clearly, current technologies cannot achieve a high-bandwidth utilization compatible design at a low cost.

[0046] To address the aforementioned issues, this invention provides a bandwidth allocation device and method to solve the problem that existing technologies cannot achieve high bandwidth utilization in a compatible design under low-cost conditions.

[0047] The bandwidth allocation device provided by the exemplary embodiments of this application will be described below with reference to the accompanying drawings and the application scenarios described above. It should be noted that the application scenarios described above are only shown to facilitate understanding of the spirit and principles of this application, and the embodiments of this application are not limited in any way in this respect.

[0048] like Figure 1 The diagram shown is a schematic diagram of a bandwidth allocation device provided in an embodiment of the present invention. The device includes: a media access controller (MAC), at least one physical port transceiver 20 (Physical layer, PHY), and a central processing unit (CPU).

[0049] Each output port of the MAC 10 is connected with at least two groups of host-side serial bus channels of the at least one PHY 20;

[0050] The at least one group of line-side serial bus channels of the PHY 20 is packaged into a first port compatible with the optical module of the first type, and the at least two groups of line-side serial bus channels of the at least one PHY 20 are packaged into a second port compatible with the optical module of the first type and the optical module of the second type, wherein the at least two groups of line-side serial bus channels of the PHY 20 are located on the same PHY 20 or different PHYs 20, and one group of serial bus channels in the at least two groups of line-side serial bus channels shares one group of host-side serial bus channels with the one group of line-side serial bus channels;

[0051] The MAC 10 is configured to output the bandwidth to be allocated;

[0052] The CPU 30 is configured to control the path conduction or disconnection between the host-side serial bus channels and the line-side serial bus channels according to the configuration requirement;

[0053] The at least one PHY 20 is configured to allocate the bandwidth to be allocated and output.

[0054] The bandwidth allocation device provided by the embodiment of the present application comprises a MAC, each output port of the MAC is connected with at least two groups of host-side serial bus channels of a PHY, one group of line-side serial bus channels of the PHY is packaged into a first port compatible with an optical module of a first type, at least two groups of line-side serial bus channels of the PHY are packaged into a second port compatible with the optical module of the first type and an optical module of a second type, one group of serial bus channels in the at least two groups of line-side serial bus channels shares one group of host-side serial bus channels with the one group of line-side serial bus channels, the MAC is configured to output the bandwidth to be allocated, a CPU is configured to control the path conduction or disconnection between the host-side serial bus channels and the line-side serial bus channels according to the configuration requirement, and the PHY is configured to allocate the bandwidth to be allocated and output. Since one group of serial bus channels in the at least two groups of line-side serial bus channels shares one group of host-side serial bus channels with the one group of line-side serial bus channels, and the second port is compatible with the optical module of the first type and the optical module of the second type, the path conduction or disconnection between the host-side serial bus channels and the line-side serial bus channels can be controlled by the CPU, so that the high bandwidth utilization rate can be realized under the condition of low cost.

[0055] In the embodiment of the present application, the MAC 10 can comprise a plurality of output ports, the bandwidth to be allocated output by each output port of the MAC 10 can be 400G, the optical module of the first type can be a four-channel optical module, and the optical module of the second type can be an eight-channel optical module.

[0056] For example, asFigure 1 As shown, the MAC 10 includes four output ports.

[0057] In a specific implementation, the bandwidth corresponding to the second type of optical module can be n times of the bandwidth corresponding to the first type of optical module, where n is a positive integer greater than or equal to 2.

[0058] For example, if the bandwidth corresponding to the first type of optical module is 200G, the bandwidth corresponding to the second type of optical module can be 400G, can be 600G, or can be 800G.

[0059] In an implementation, when the CPU 30 controls the path between the host-side serial bus channel and the line-side serial bus channel to be on or off according to the configuration requirement, the CPU 30 can control the path between the line-side serial bus channel of the first port and the shared host-side serial bus channel to be on, and control the path between a group of line-side serial bus channels of the second port and the corresponding host-side serial bus channels to be on; or

[0060] Control the path between all line-side serial bus channels of the second port and the corresponding host-side serial bus channels to be on.

[0061] In an embodiment, when the MAC 10 includes four output ports and includes three PHYs 20, each output port of the MAC 10 is connected with two groups of host-side serial bus channels in the three PHYs, the line-side serial bus channels corresponding to the two groups of host-side serial bus channels in the three PHYs 20 are packaged into a second port, and the remaining line-side serial bus channels in each group are packaged into a first port; wherein the four groups of host-side serial bus channels connected with any two output ports of the MAC 10 are not located in the same PHY 20.

[0062] For example, the first output port of the MAC is connected with the host-side serial bus channels H0-H3, H8-H11 of the first PHY, respectively; the second output port of the MAC is connected with the host-side serial bus channels H4-H7 of the first PHY and the host-side serial bus channels H0-H3 of the second PHY, respectively; the third output port of the MAC is connected with the host-side serial bus channels H12-H15 of the second PHY and the host-side serial bus channels H0-H3 of the third PHY, respectively; and the fourth output port of the MAC is connected with the host-side serial bus channels H4-H7, H8-H11 of the third PHY, respectively.

[0063] The packaging mode of the line-side serial bus channels of the first PHY, the line-side serial bus channels of the second PHY, and the line-side serial bus channels of the third PHY includes part or all of the following:

[0064] The line-end serial bus channels L0-L3 of the first PHY and the line-end serial bus channels L8-L11 of the first PHY are packaged into a second port; the line-end serial bus channels L4-L7 of the first PHY and the line-end serial bus channels L0-L3 of the second PHY are packaged into a second port; the line-end serial bus channels L12-L15 of the first PHY are packaged into a first port; the line-end serial bus channels L4-L7 of the second PHY are packaged into a first port; the line-end serial bus channels L8-L11 of the second PHY are packaged into a first port; the line-end serial bus channels L12-L15 of the second PHY and the line-end serial bus channels L0-L3 of the third PHY are packaged into a second port; the line-end serial bus channels L4-L7 of the third PHY and the line-end serial bus channels L8-L11 of the third PHY are packaged into a second port; and the line-end serial bus channels L12-L15 of the third PHY are packaged into a first port.

[0065] The specific structure and connection relationship of the bandwidth allocation device provided in the embodiment of the application will be described in detail below. Figure 1 The specific structure and connection relationship of the bandwidth allocation device provided in the embodiment of the application will be described in detail below.

[0066] Figure 1 The device includes one MAC 10, three PHYs 20, one CPU 30 and eight ports. The CPU 30 is connected to the MAC 10 and controls the path conduction or disconnection between the host-end serial bus channels and the line-end serial bus channels through the serial management interface (SMI) signal line of the MAC 10. The MAC 10 includes four output ports. Each PHY 20 includes host-end serial bus channels H0-H15 and line-end serial bus channels L0-L15. The first output port of the MAC 10 is connected to the host-end serial bus channels H0-H3 of the first PHY and the host-end serial bus channels H8-H11 of the first PHY respectively. The second output port of the MAC 10 is connected to the host-end serial bus channels H4-H7 of the first PHY and the host-end serial bus channels H0-H3 of the second PHY respectively. The third output port of the MAC 10 is connected to the host-end serial bus channels H12-H15 of the second PHY and the host-end serial bus channels H0-H3 of the third PHY respectively. The fourth output port of the MAC 10 is connected to the host-end serial bus channels H4-H7 of the third PHY and the host-end serial bus channels H8-H11 of the third PHY respectively.

[0067] The line-end serial bus channels L0-L3 of the first PHY and the line-end serial bus channels L8-L11 of the first PHY are packaged into a second port Port1 compatible with the optical modules of the first type and the second type; the line-end serial bus channels L4-L7 of the first PHY and the line-end serial bus channels L0-L3 of the second PHY are packaged into a second port Port2 compatible with the optical modules of the first type and the second type; the line-end serial bus channels L12-L15 of the first PHY are packaged into a first port Port3 adapted to the optical modules of the first type; the line-end serial bus channels L4-L7 of the second PHY are packaged into a first port Port4 adapted to the optical modules of the first type; the line-end serial bus channels L8-L11 of the second PHY are packaged into a first port Port5 adapted to the optical modules of the first type; the line-end serial bus channels L12-L15 of the second PHY and the line-end serial bus channels L0-L3 of the third PHY are packaged into a second port Port6 compatible with the optical modules of the first type and the second type; the line-end serial bus channels L4-L7 of the third PHY and the line-end serial bus channels L8-L11 of the third PHY are packaged into a second port Port7 compatible with the optical modules of the first type and the second type; and the line-end serial bus channels L12-L15 of the third PHY are packaged into a first port Port8 adapted to the optical modules of the first type.

[0068] The line-end serial bus channels L8-L11 of the first PHY share the host-end serial bus channels H8-H11 of the first PHY with the line-end serial bus channels L12-L15 of the first PHY; the line-end serial bus channels L0-L3 of the second PHY share the host-end serial bus channels H0-H3 of the second PHY with the line-end serial bus channels L4-L7 of the second PHY; the line-end serial bus channels L8-L11 of the second PHY share the host-end serial bus channels H12-H15 of the second PHY with the line-end serial bus channels L12-L15 of the second PHY; and the line-end serial bus channels L8-L11 of the third PHY share the host-end serial bus channels H8-H11 of the third PHY with the line-end serial bus channels L12-L15 of the third PHY.

[0069] Specifically, the first type of optical module used in the embodiment of the present application can be a QSFP56 optical module with a bandwidth of 200G, which supports 4-channel full duplex and has a maximum rate of up to 212.5Gbps (4x50GPAM4); the second type of optical module can be a QSFP-DD optical module with a bandwidth of 400G, which supports 8-channel full duplex and has a maximum rate of up to 425Gbps (8x50G PAM4), and can support 212.5Gbps (4x50G PAM4) downward compatible according to needs; the PHY in the embodiment of the present application can support four-pulse amplitude modulation (PAM4), PAM4 is a popular signal transmission technology for high-speed signal interconnection in next-generation data centers, and is widely used in electrical or optical signal transmission of 200G / 400G interfaces, PAM4 uses 4 different signal levels for signal transmission, and each symbol period can represent 2 bytes of logical information (00, 01, 10, 11).

[0070] The following will further explain the bandwidth allocation scheme of the above device by taking the bandwidth to be allocated by each output port of the MAC 10 as 400G as an example. It should be noted that each output port of the MAC 10 actually outputs 8 bandwidths of 50G, and the MAC 10 includes 4 output ports, so the total bandwidth to be allocated by the MAC 10 is 1600G.

[0071] Embodiment 1: 8 ports with a bandwidth of 200G are configured.

[0072] When 8 ports with a bandwidth of 200G are configured, that is, the bandwidth to be allocated by each output port of the MAC 10 in Figure 2 is 400G, and the bandwidths output by the ports Port1-Port8 are 200G. The following will explain this embodiment in combination with Figure 2 and Table 1.

[0073] Figure 2 A schematic diagram of a working mode of the bandwidth allocation device of the present application is provided. Table 1 is a table of a working mode of the PHY. From Figure 2As shown in Table 1, the first output port of MAC 10 outputs 200G of bandwidth to be allocated to the host-side serial bus channels H0-H3 and H8-H11 of the first PHY, respectively; the second output port of MAC 10 outputs 200G of bandwidth to be allocated to the host-side serial bus channels H4-H7 of the first PHY and H0-H3 of the second PHY, respectively; the third output port of MAC 10 outputs 200G of bandwidth to be allocated to the host-side serial bus channels H12-H15 of the second PHY and H0-H3 of the third PHY, respectively; and the fourth output port of MAC 10 outputs 200G of bandwidth to be allocated to the host-side serial bus channels H4-H7 and H8-H11 of the third PHY, respectively.

[0074] CPU 30 controls the path connection between the host-side serial bus channels H0-H3 and the line-side serial bus channels L0-L3 of the first PHY, the path connection between the host-side serial bus channels H4-H7 and the line-side serial bus channels L4-L7 of the first PHY, the path connection between the host-side serial bus channels H8-H11 and the line-side serial bus channels L12-L15 of the first PHY, and the path connection between the host-side serial bus channels H0-H3 and the line-side serial bus channels L0-L3 of the second PHY. The paths between the host-side serial bus channels H12-H15 and the line-side serial bus channels L8-L11 of the second PHY are connected; the paths between the host-side serial bus channels H0-H3 and the line-side serial bus channels L0-L3 of the third PHY are connected; the paths between the host-side serial bus channels H4-H7 and the line-side serial bus channels L4-L7 of the third PHY are connected; and the paths between the host-side serial bus channels H8-H11 and the line-side serial bus channels L12-L15 of the third PHY are connected.

[0075] The PHY 20 distributes the received bandwidth to the corresponding port through the path between the host-side serial bus channel and the line-side serial bus channel.

[0076]

[0077] Table 1

[0078] Example 2: Configure 4 ports with a bandwidth of 400G.

[0079] When configuring four ports with a bandwidth of 400G, that is... Figure 3 Each output port of MAC 10 has an allocated bandwidth of 400G, and ports Port1, Port2, Port6, and Port7 each have an output bandwidth of 400G. The following section combines...Figure 3 Table 2 illustrates this embodiment.

[0080] Figure 3 Fig. 2 is a schematic diagram illustrating another working mode of the bandwidth allocation device of the present application. Table 2 is a table of another working mode of the PHY. The working process of the MAC 10 is the same as that of the above-mentioned embodiment 1, which is not described here again.

[0081] From Figure 3 As can be seen from Table 2, the CPU 30 controls the path conduction between the host-side serial bus channels H0-H3 and the line-side serial bus channels L0-L3 of the first PHY, the path conduction between the host-side serial bus channels H4-H7 and the line-side serial bus channels L4-L7 of the first PHY, the path conduction between the host-side serial bus channels H8-H11 and the line-side serial bus channels L8-L11 of the first PHY, the path conduction between the host-side serial bus channels H0-H3 and the line-side serial bus channels L0-L3 of the second PHY, the path conduction between the host-side serial bus channels H12-H15 and the line-side serial bus channels L12-L15 of the second PHY, the path conduction between the host-side serial bus channels H0-H3 and the line-side serial bus channels L0-L3 of the third PHY, the path conduction between the host-side serial bus channels H4-H7 and the line-side serial bus channels L4-L7 of the third PHY, and the path conduction between the host-side serial bus channels H8-H11 and the line-side serial bus channels L8-L11 of the third PHY, respectively.

[0082] The PHY 20 allocates the received bandwidth to be allocated to the corresponding port through the path conduction between the host-side serial bus channels and the line-side serial bus channels.

[0083]

[0084] Table 2

[0085] Embodiment 3: 2 ports with bandwidth of 400G and 4 ports with bandwidth of 200G are configured.

[0086] When 2 ports with bandwidth of 400G and 4 ports with bandwidth of 200G are configured, i.e. Figure 4 The bandwidth to be allocated output by each output port of the MAC 10 in Table 2 is 400G, the bandwidth output by the ports Port1 and Port2 is 400G, and the bandwidth output by the ports Port5, Port6, Port7 and Port7 is 200G. The following describes this embodiment in combination with Figure 4 Table 2.

[0087] Figure 4Fig. 3 is a schematic diagram of another working mode of the bandwidth allocation apparatus according to the present application. Table 3 is a table of another working mode of the PHY. The working process of the MAC 10 is the same as that of the above-mentioned embodiment 1, and thus is not described herein again.

[0088] The CPU 30 controls the path conduction between the host-side serial bus channels H0-H3 and the line-side serial bus channels L0-L3 of the first PHY 20, the path conduction between the host-side serial bus channels H4-H7 and the line-side serial bus channels L4-L7 of the first PHY, the path conduction between the host-side serial bus channels H8-H11 and the line-side serial bus channels L8-L11 of the first PHY, the path conduction between the host-side serial bus channels H0-H3 and the line-side serial bus channels L0-L3 of the second PHY, the path conduction between the host-side serial bus channels H12-H15 and the line-side serial bus channels L8-L11 of the second PHY, the path conduction between the host-side serial bus channels H0-H3 and the line-side serial bus channels L0-L3 of the third PHY, the path conduction between the host-side serial bus channels H4-H7 and the line-side serial bus channels L4-L7 of the third PHY, and the path conduction between the host-side serial bus channels H8-H11 and the line-side serial bus channels L12-L15 of the third PHY, respectively.

[0089] The PHY 20 allocates the received bandwidth to be allocated to the corresponding port through the path conduction between the host-side serial bus channels and the line-side serial bus channels.

[0090]

[0091] Table 3

[0092] It should be noted that the above three embodiments are only illustrative, and the bandwidth output by each port can also be in other forms.

[0093] Based on the same inventive concept, the present application also provides a bandwidth allocation method. Since the corresponding device of the method is the bandwidth allocation apparatus according to the present application, and the method has the similar problem-solving principle as the apparatus, the implementation of the method can be referred to the implementation of the bandwidth allocation apparatus, and the repeated parts are not described herein again.

[0094] As shown in Fig. 4, a bandwidth allocation method according to an embodiment of the present application comprises the following steps: Figure 5

[0095] Step 501: outputting the bandwidth to be allocated through each output port of the MAC 10;

[0096] ​Step 502, controlling, by the CPU 30, the path between the host-side serial bus channel and the line-side serial bus channel of the at least one PHY 20 to be conducted or disconnected according to the configuration requirement, so that the bandwidth to be allocated of each port of the MAC 10 is fully allocated according to the configuration requirement;

[0097] Step 503, allocating, by the at least one PHY 20, the bandwidth to be allocated and outputting.

[0098] Optionally, the controlling, by the CPU, the path between the host-side serial bus channel and the line-side serial bus channel of the at least one PHY according to the configuration requirement comprises some or all of the following:

[0099] controlling, by the CPU, the path between the line-side serial bus channel of the first port and the shared host-side serial bus channel to be conducted;

[0100] controlling the path between a group of line-side serial bus channels of the second port and the corresponding host-side serial bus channels to be conducted;

[0101] controlling, by the CPU, the path between all the line-side serial bus channels of the second port and the corresponding host-side serial bus channels to be conducted.

[0102] Optionally, the MAC comprises a plurality of output ports, and the bandwidth to be allocated of each output port of the MAC is 400G;

[0103] The first type of optical module is a four-channel optical module, and the second type of optical module is an eight-channel optical module.

[0104] Optionally, the bandwidth corresponding to the second type of optical module is n times the bandwidth corresponding to the first type of optical module, where n is a positive integer greater than or equal to 2.

[0105] Further, the embodiment of the present application also provides a computer readable storage medium, which stores computer instructions, when the computer instructions run on a computer, the computer executes the bandwidth allocation method provided by the embodiment of the present application.

[0106] The application discloses a bandwidth allocation device and method, each output port of a MAC is connected with at least two groups of host-side serial bus channels of a PHY, one group of line-side serial bus channels of the PHY is packaged into a first port compatible with a first type of optical module, at least two groups of line-side serial bus channels of the PHY are packaged into a second port compatible with the first type and a second type of optical module, one group of serial bus channels in the one group of line-side serial bus channels and the at least two groups of line-side serial bus channels shares one group of host-side serial bus channels, the bandwidth to be allocated is output through each output port of the MAC, a CPU controls the path between the host-side serial bus channels and the line-side serial bus channels to be on or off according to the configuration requirement, and the PHY is used for allocating the bandwidth to be allocated and output. Since one group of serial bus channels in the one group of line-side serial bus channels and the at least two groups of line-side serial bus channels shares one group of host-side serial bus channels, and the second port is compatible with the first type of optical module and the second type of optical module, the path between the host-side serial bus channels and the line-side serial bus channels can be controlled by the CPU to be on or off, so that high bandwidth utilization rate can be realized under low cost condition.

[0107] The application is herein described, by way of example only, with reference to the accompanying drawings, in which:

[0108] Accordingly, the present application can also be embodied in hardware and / or in software (including firmware, resident software, micro-code, etc.). Furthermore, the present application can take the form of a computer program product on a computer-usable or computer-readable storage medium having computer-usable or computer-readable program code embodied in the medium for use by or in connection with an instruction execution system. In the context of the present application, a computer-usable or computer-readable medium can be any medium that can contain, store, communicate, propagate, or transport the program for use by or in connection with the instruction execution system, apparatus, or device.

[0109] Obviously, various modifications and changes are possible in the present application without departing from the spirit and scope of the application. It is to be understood that the above description is intended to be illustrative and not restrictive. The scope of the application should be determined by reference to the appended claims, along with their full scope of equivalents, and the foreclosure of equivalency of alternative claims.

Claims

1. A bandwidth allocation apparatus, characterized by comprising: The device comprises a media access controller (MAC), at least one physical port transceiver (PHY), and a central processing unit (CPU); Each output port of the MAC is connected to at least two groups of host-side serial bus channels of at least one PHY, wherein the at least two groups of host-side serial bus channels are located on the same PHY or different PHYs; one group of line-side serial bus channels of at least one PHY is encapsulated into a first port compatible with a first type of optical module, and at least two groups of line-side serial bus channels of at least one PHY are encapsulated into a second port compatible with the first type and a second type of optical module; one group of line-side serial bus channels and one group of host-side serial bus channels share one group of line-side serial bus channels, and two groups of line-side serial bus channels sharing one group of host-side serial bus channels are connected to two paths of the shared group of host-side serial bus channels, wherein one path is on and the other path is off when one path is on; The MAC is configured to output the bandwidth to be allocated; The CPU is configured to control the on and off of the paths between the host-side serial bus channels and the line-side serial bus channels according to the configuration requirement, so that the bandwidth to be allocated of each port of the MAC is fully allocated according to the configuration requirement; The at least one PHY is configured to allocate the bandwidth to be allocated and output.

2. The apparatus of claim 1, wherein, The CPU is specifically configured to control part or all of the following: Control the on of the paths between the line-side serial bus channels of the first port and the shared host-side serial bus channels; Control the on of the paths between one group of line-side serial bus channels of the line-side serial bus channels of the second port and the corresponding host-side serial bus channels; Control the on of the paths between all line-side serial bus channels of the second port and the corresponding host-side serial bus channels.

3. The apparatus of claim 2, wherein, The MAC comprises four output ports, and the bandwidth to be allocated output by each output port of the MAC is 400G; The first type of optical module is a four-channel optical module, and the second type of optical module is an eight-channel optical module.

4. The device of any one of claims 1 to 3, wherein The bandwidth corresponding to the second type of optical module is n times the bandwidth corresponding to the first type of optical module, wherein n is a positive integer greater than or equal to 2.

5. The apparatus of claim 3, wherein, The number of the PHYs is three, and each PHY comprises four groups of host-side serial bus channels and four groups of line-side serial bus channels; Each output port of the MAC is connected to two groups of host-side serial bus channels of the three PHYs; The line-side serial bus channels of the three PHYs, corresponding to the two groups of host-side serial bus channels, are encapsulated into the second port, and the remaining each group of line-side serial bus channels is encapsulated into the first port; Wherein, the four groups of host-side serial bus channels connected to any two output ports of the MAC are not located on the same PHY.

6. A switch, characterized by The bandwidth allocation device comprises the bandwidth allocation device according to any one of claims 1-5.

7. A bandwidth allocation method characterized by, The method is applied to the bandwidth allocation device as claimed in any one of claims 1-5, and the method comprises: outputting the bandwidth to be allocated through each output port of the MAC; controlling, by the CPU, the path conduction or disconnection between the host-side serial bus channel and the line-side serial bus channel of at least one of the PHYs according to the configuration requirement, so that the bandwidth to be allocated of each port of the MAC is fully allocated according to the configuration requirement; allocating the bandwidth to be allocated by at least one of the PHYs and outputting.

8. The method of claim 7, wherein, The step of controlling, by the CPU, the path conduction or disconnection between the host-side serial bus channel and the line-side serial bus channel of at least one of the PHYs according to the configuration requirement comprises some or all of the following steps: controlling, by the CPU, the path conduction between the line-side serial bus channel of the first port and the shared host-side serial bus channel; controlling the path conduction between a group of line-side serial bus channels of the second port and the corresponding host-side serial bus channels; controlling, by the CPU, the path conduction between all the line-side serial bus channels of the second port and the corresponding host-side serial bus channels.

9. The method of claim 8, wherein, The MAC comprises a plurality of output ports, and the bandwidth to be allocated output by each output port of the MAC is 400G; The first type of optical module is a four-channel optical module, and the second type of optical module is an eight-channel optical module.

10. The method of any one of claims 7 to 9, wherein, The bandwidth corresponding to the second type of optical module is n times the bandwidth corresponding to the first type of optical module, where n is a positive integer greater than or equal to 2.

11. A computer readable storage medium, characterized in that, The storage medium stores a program, and when the program runs on the computer, the computer implements the method as claimed in any one of claims 7-10.

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