Method and apparatus for self-tuning memory devices

Abstract

The present disclosure relates to an integrated memory device comprising: - an array of memory cells with decoding and sensing circuitry; - a memory controller; - read and write circuitry associated with the sensing circuitry; - a logic circuit portion in the read and write circuitry comprising at least one logic element receiving a data stream on a data input and a clock signal on a clock input; - at least one programmable or trimmable delay element or circuit upstream of the data input or the clock input for self-trimming an internal timing of the at least one logic element by aligning the clock signal and / or the data stream in time. The present disclosure further relates to a method for setting an operating parameter of an integrated circuit, in particular for self-trimming an internal timing of the integrated circuit.

Description

Technical Field

[0001] This disclosure relates to a method for setting operating parameters of an integrated circuit. More specifically, this disclosure relates to a method for fine-tuning the operating parameters and internal timing of an integrated memory device.

[0002] This disclosure further relates to a non-volatile memory device with self-tuning capability in wide temperature range and wide voltage range applications. Background Technology

[0003] One of the main challenges in operating integrated circuits is ensuring functionality across all process extensions, supply variations, and temperature changes.

[0004] For example, any synchronous input addressed to an integrated circuit has appropriate setting and hold time specifications relative to the clock input.

[0005] The set time S is the amount of time (or time interval) during which the data received at the synchronous input of the simple flip-flop circuit D must remain stable before reaching the valid edge of the clock signal to allow the circuit to capture this data well. Similarly, the hold time H is the amount of time (or time interval) during which the data received at the synchronous input of the simple flip-flop circuit D must remain stable after reaching the valid edge of the clock signal.

[0006] The settings and holding parameters S and H must be set appropriately for the integrated circuit to function properly.

[0007] However, setting and holding are opposite parameters, in the sense explained better below; high temperatures generally slow down the two intervals, while low temperatures speed them up; therefore, the two parameters will shift accordingly over time.

[0008] Another parameter is given by the sum of two intervals, S + H = MPW, that should remain stable before and after a change in the clock input. This interval MPW has a minimum value that allows for normal operation, but it can be even longer because the signal can remain stable while waiting for sampling and subsequent changes.

[0009] In any case, violations of the set and hold timings can generate not only a single fault condition, but even serious faults such as metastability of the trigger output. These faults are undetermined and cannot be recovered unless a forced reset or power-off and power-on occurs.

[0010] While designing and simulating integrated circuits takes into account the aforementioned issues, it is impossible to guarantee performance and functionality within a specified range for some applications, such as those with large variations in power supply, temperature, and processing range.

[0011] In an attempt to overcome potential process scaling, some testing and fine-tuning were conducted at the factory; however, this usual practice is time-consuming because it must be performed on each individual IC; in other words, on a die-by-die basis. Summary of the Invention

[0012] In one aspect, this application provides a method for setting operating parameters of an integrated circuit, particularly a method for self-tuning the internal timing of the integrated circuit, the integrated circuit including circuit portions that receive a data stream at a data input and a clock signal at a clock input, the method comprising: aligning the clock signal and / or the data stream in time by inserting an upstream programmable or tuned delay element or circuit before one or both of the inputs.

[0013] On the other hand, this application provides a method for setting operating parameters of an integrated circuit, particularly a method for self-tuning the internal timing of the integrated circuit, the integrated circuit including at least one circuit portion that receives a data stream at a data input and a clock signal at a clock input, the method comprising: performing a tuning phase of setting time and / or holding time by inserting programmable or fine-tunable delay elements or circuits to change the relative time distance between the data stream received by the data input and the effective edge of the clock signal.

[0014] On the other hand, this application provides an integrated memory device comprising: an array of memory cells having a decoding and sensing circuitry system; a memory controller; a read and write circuitry system associated with the sensing circuitry system; a logic circuitry portion of the read and write circuitry system including at least one logic element that receives a data stream at a data input and a clock signal at a clock input; and at least one programmable or adjustable delay element or circuitry upstream of the data input or the clock input for self-adjusting the internal timing of the at least one logic element by aligning the clock signal and / or the data stream in time.

[0015] On the other hand, this application provides an integrated memory device structured to communicate with a host device or system-on-a-chip via a communication channel having corresponding pads; comprising: a memory cell array having a decoding and sensing circuitry system; a memory controller; an output buffer coupled to the memory cell array and including an optional final output stage coupled to the pads; and at least one programmable or tunable delay element or circuit upstream of the optional final output stage in the output buffer for selecting the output impedance of the buffer. Attached Figure Description

[0016] Figure 1 is a schematic diagram of a simple bistable circuit that receives data input and clock input according to a known scheme;

[0017] Figure 1A It is a comparison chart showing the data setup and hold time period compared to a known clock signal;

[0018] Figure 2 This is a schematic perspective view of a system-on-a-chip device having associated memory devices according to the present disclosure;

[0019] Figure 3 This is a block diagram of an example of a logic circuit portion incorporated into an integrated circuit (i.e., a memory device) according to an embodiment of the present disclosure.

[0020] Figure 4 This is a schematic diagram of a memory block formed by multiple rows of a memory array according to an embodiment of the present disclosure;

[0021] Figure 5 This is a schematic diagram of a portion of an integrated memory device implemented according to an embodiment of the present disclosure;

[0022] Figure 6 This is a diagram illustrating the selection points of the fine-tuning process performed by the optimization algorithm used according to this disclosure;

[0023] Figure 7 An example of an output buffer incorporated into the memory device of this disclosure and including a plurality of tri-state drivers is schematically shown;

[0024] Figure 8 It is a schematic diagram of a transmission model on a wired bus involving the output buffer of a memory device and another device communicating with the memory;

[0025] Figure 9 and 10 The report is in Figure 8 These are schematic diagrams of the voltage versus time at two opposite nodes A and B on opposite sides of a wired bus; these diagrams show the waveforms on the output buffer side and receiver side with and without noise, along with the corresponding and associated eye diagrams.

[0026] Figure 11 and 12 Practical and schematic representations of eye diagrams related to the output buffer of the memory device of this disclosure are shown, respectively. Detailed Implementation

[0027] In the following detailed description, reference is made to the accompanying drawings, which form a part of the description, and specific examples are illustrated therein. In the drawings, similar reference numerals describe substantially similar components in several views. Other embodiments may be disclosed, and structural, logical, and electrical changes may be made without departing from the scope of this disclosure. Therefore, the following detailed description should not be considered limiting.

[0028] This disclosure relates to a method for setting operating parameters of an integrated circuit, and more specifically, to operating parameters and internal timing of a self-tuning memory device, and to a method for assisting the memory host in finely setting the bus driver by optimizing impedance and timing matching.

[0029] The memory devices disclosed herein are respectively in Figure 2 The number 200 is used to indicate and in Figure 5 A non-volatile memory device or component, indicated by the number 500, is described. This memory device 200 is implemented as a separate die using a specific lithography process and can be coupled to a host device or system-on-a-chip via a communication channel. The host device may be a system-on-a-chip with embedded memory components or a more complex electronic device containing a system coupled to the memory device, as will be shown in the description of other embodiments of this disclosure with reference to other figures. In any case, the system-on-a-chip and the memory device are implemented on respective dies obtained using different lithography processes.

[0030] Alternatively, the system may be an external controller communicating with the system-on-chip, but for the purposes of this disclosure, a reference host device or SoC is used as an entity communicating with memory components. For example, system 10 may be one of a plurality of electronic devices capable of using memory for temporary or persistent storage of information. For example, the host device may be a computing device, a mobile phone, a tablet computer, or the central processing unit of an autonomous vehicle.

[0031] Non-volatile memory provides persistent data by retaining the stored data when no power is applied, and can include NAND flash memory, NOR flash memory, read-only memory (ROM), electrically erasable programmable or finely tuned ROM (EEPROM), erasable programmable or finely tuned ROM (EPROM), and resistive variable memory, such as phase-change random access memory (PCRAM), self-selected chalcogenide-based memory, resistive random access memory (RRAM), 3D XPoint memory (3DXP), and magnetoresistive random access memory (MRAM), etc.

[0032] Flash memory is a type of non-volatile memory that retains stored data and is characterized by very fast access times. Furthermore, it can be erased in blocks, rather than one byte at a time. Each erasable block of the memory comprises multiple non-volatile memory cells arranged in a matrix of rows and columns. Each cell is coupled to an access line and / or a data line. The cell is programmed and erased by manipulating voltages on the access and data lines.

[0033] like Figure 2As shown, according to this disclosure, the memory device 200 is removed from the prior art SoC structure, thus allowing the corresponding semiconductor region to be used for other logic circuits and providing support for a structurally independent memory component 200 that partially overlaps with the SoC structure 210. The memory component 200 has a variable size depending on the size of the memory array contained therein, and is manufactured according to user needs, for example, in the range of values ​​from 128 Mbit to 512 Mbit or greater.

[0034] The removal of the embedded memory portion in the prior art also has the great advantage of free space, thereby obtaining the semiconductor region 220 of the SoC structure 210, allowing the integration of additional user functions and / or reducing the overall chip area.

[0035] The result of this solution is Figure 2 The new SoC architecture is strictly associated with a new, structurally independent memory component 200, which is coupled to the SoC architecture 210, for example, via multiple coupling elements 230 (e.g., pillars) and via billiard balls, flip-chip technology, wireless interconnects (coils), etc. In a preferred embodiment, the coupling elements are pillars arranged in a semiconductor region 220 previously dedicated to the embedded memory portion.

[0036] In one embodiment of this disclosure, a memory component 200 for a SoC structure 210 includes at least a memory portion and a logic circuit portion for interacting with the memory portion and the SoC structure 210, wherein the memory component 200 is a structurally independent semiconductor device coupled to and overlapping with the SoC structure 210.

[0037] Logic circuitry 240 is integrated into SoC architecture 210 to work in conjunction with the logic circuitry portion of memory component 200.

[0038] The coupling between the SoC structure 210 and the memory component 200 is achieved by interconnecting multiple corresponding pads or pins that face each other in a circuit layout that maintains pad alignment even if the size of the memory component 200 is modified.

[0039] In one embodiment of this disclosure, pads for the memory component 200 have been arranged on the surface of the memory component 200. More specifically, the pads are arranged on an array such that when the memory component 200 is flipped, its pads face the corresponding pads of the SoC structure 210. In the known system-on-chip device 210, a semiconductor region 220 occupied by the embedded non-volatile memory portion is dedicated to accommodating interconnect pads corresponding to the pads of the memory component 200.

[0040] Even larger memory components can be supported and interconnected with the pads of the SoC structure 210, thereby maintaining the position and misalignment of its interconnect pads.

[0041] In the context of this disclosure, the top side of the SoC structure 210 is connected to the reverse side of the memory component 200, and the pads of the SoC structure 210 are aligned with the matching pads of the flipped memory component. Alternatively, the structurally independent memory component 200 can be wirelessly coupled to the SoC structure 210. If wireless coupling is used, stacks of memory components of the same size can overlap to achieve a stacked structure, wherein each independent component is addressed by the logic circuitry of the SoC structure 210 via a corresponding identification address.

[0042] The semiconductor region 220, previously occupied by the embedded memory portion, is now used to implement additional functions and prepare semiconductor devices for on-pad logic technology. The term "on-pad logic" means providing a logic circuit system that overlaps with some connection pads located inside the first layer or base layer represented by the complete semiconductor product (i.e., SoC structure 210).

[0043] Memory component 200 thus represents a layer coupled and interconnected to the underlying SoC structure 210. In known solutions where embedded memory portions occupy the space, memory component 200 overlaps with at least a portion of the SoC structure surface covering semiconductor region 220. However, memory component 200 with a larger capacity can cover a semiconductor region larger than semiconductor region 220.

[0044] In this respect, the size of the overlay memory component 200 is larger than the size of the overlay semiconductor region 220 dedicated to interconnecting with this overlay memory component 200. In other words, the area of ​​the overlay memory component 200 is larger than the semiconductor region 220 of the SoC structure 210 dedicated to the interconnect pads of the memory component 200.

[0045] Furthermore, in order to better operate the SoC architecture 210, it is even possible to remove the logic circuitry that is typically incorporated into the SoC and contains finite state machines or RISC architectures, and reorganize it in association with the memory component 200.

[0046] Therefore, according to this disclosure, the modified finite state machine or RISC 240 has been migrated to the memory component 200 to support write and erase phases performed on the larger memory component 200.

[0047] The separation and optimization of the logic circuitry further allows for enhanced functionality of the entire SoC architecture 210, resulting in a separate semiconductor memory component 200 coupled to the SoC architecture 210. Therefore, this separate semiconductor memory component 200 includes at least a memory portion (e.g., a non-volatile memory portion) and an associated modified finite state machine 240, both incorporated into the semiconductor product coupled to the SoC architecture 210. In this case, the memory logic in the SoC architecture 210 is the logic that handles memory interface communication.

[0048] In other words, both the non-volatile memory portion and the associated logic circuit portion are integrated in a separate semiconductor memory component 200 coupled to and connected to the SoC structure 210.

[0049] According to embodiments of this disclosure, the memory device 200 is a non-volatile flash memory type that includes at least the following components: I / O circuitry, a micro sequencer including control and JTAG logic, and a sense amplifier.

[0050] The flash memory device 200 further includes a command user interface (CUI), voltage and current reference generators, a charge pump, and a decoding circuit system. The flash memory also includes an internal microcontroller for executing erase and programming algorithms.

[0051] It should be remembered that when two semiconductor integrated devices are coupled together, some problems may arise in handling I / O signals between the two devices. Furthermore, if the controller is capable of operating at a clock frequency signal reaching at least 1 GHz (sometimes referred to as high frequency), other circuitry, such as associated memory components, is designed to operate at lower frequencies, such as a few hundred MHz (sometimes referred to as low frequency).

[0052] This type of situation typically occurs, for example, when a temperature rise occurs during the operation of a system associated with memory. Memory components suffer from thermal drift and / or other drift in the power supply or voltage level, which limits their ability to operate according to the original settings defined at the factory.

[0053] Another typical scenario is adapting a memory device to a host device (e.g., a board in which the memory device is mounted or a SoC that hosts the memory device). This adaptation involves impedance matching between the memory output buffer and the external bus, and external signal offset. These conditions may change during the device's lifespan because the external bus load may change (new device connection / disconnection, temperature variations, etc.).

[0054] To address these issues, namely, some instances of the methods according to this disclosure will be considered, such as resetting the settings and hold duration of the internal FSM and adjusting impedance matching plus signal offset. The methods must be considered as being implemented in an integrated circuit, for example, a memory device 200 (e.g., a memory device or component 200 coupled to SoC 210).

[0055] This integrated memory device 200 includes several basic circuit components, such as simple flip-flops, latches, or logic gates.

[0056] It is well known that simple flip-flops D (such as the known circuit shown in Figure 1) can suffer from metastability. The data signal must stabilize within a predetermined time period before the rising edge of the clock signal to allow for proper data capture. This predetermined time period is called the settling time S.

[0057] Furthermore, as mentioned earlier, the hold time H is the amount of time (or time interval) that the data received at the synchronous input of the simple flip-flop circuit D must remain stable after the effective edge of the clock signal arrives.

[0058] Figure 1 shows a schematic diagram of flip-flop D10, where the main block represents a simple logic gate that receives the data input DATA and the clock input CLK. A reset input Reset is further provided to reset flip-flop D10.

[0059] This diagram illustrates a logic synchronization circuit with at least inputs and outputs. Data inputs / outputs are managed by a clock signal. This circuit could be a simple latch or even a complex finite state machine, but this diagram is an example of the set-and-hold fine-tuning required to introduce each synchronization circuit.

[0060] Of course, the data input DATA is represented in Figure 1 by multiple numerical values ​​presented in parallel. In other words, the input DATA is the front end of the bus from the digital source.

[0061] Similarly, the data output OUT is shown as having multiple corresponding numeric output values.

[0062] It should be noted that the setting time S is defined for simple flip-flops D10 as well as more complex finite state machines containing hundreds of flip-flops or logic gates.

[0063] To avoid serious failures due to potential metastability of the triggers or critical competition in the internal synchronization circuit, possible readjustment of the operating parameters is highly desirable. Most likely, the effective window for data capture will drift due to inherent variations in the process; that is, line resistance can change, capacitance can change, and the time constant will change accordingly.

[0064] Furthermore, other operating parameters may require fine-tuning after a significant period of activity for the integrated circuit, or due to possible reconfiguration / updates of a board with new components that alter the impedance of the bus, where memory is hosted. For example, the output impedance toward the on-chip system may require similar readjustment by selecting one of the available drivers within the output buffer, ensuring impedance matching and optimal performance in terms of the speed and shape of the generated voltage / current signal. While this fine-tuning phase is suitable for inspecting the output of the integrated circuit (i.e., the memory device), the fine-tuning of the set and hold time intervals focuses on the internal activities of the integrated circuit.

[0065] According to some embodiments of this disclosure, at least a programmable or adjustable delay element or circuit is employed, which is inserted upstream of the clock input and / or data input for tuning the relative distance between the data input and the effective or leading edge of the clock signal.

[0066] In other words, at least a programmable or adjustable delay element or circuitry inserted upstream of the clock and / or data inputs is used to tune the relative distance between the data input and the effective or leading edge of the clock signal. This delay is added to the critical lines, i.e., clock, data, command, FSM, etc., with the aim of recentering all signals affected by aging drift.

[0067] The fine-tuning is accomplished by feeding a sequence read from a non-volatile region of the memory array to the FSM (or the circuit to be fine-tuned), and then checking whether the output of the FSM (or the circuit) matches the desired value.

[0068] Fine-tune and explore all possible delay values ​​to obtain the widest possible range of functionality around a specific condition (i.e., temperature).

[0069] Furthermore, the output buffers of the memory device 200 are also included in the fine-tuning operation, and more specifically, those buffers are processed as follows:

[0070] - Perform appropriate selection of the output buffer driver to best match the impedance between the storage buffer and the external bus; and

[0071] - Perform appropriate fine-tuning of the data path delay to ensure the correct offset between the external clock and the host device's signal.

[0072] The two processes described above are executed using a special structure within the output buffer.

[0073] In this more specific case, fine-tuning is performed using the read phase of a standard data path stored in a specific virtual row of a memory block. An external controller measures the quality of the read operation using an eye diagram and then provides feedback to the device regarding the read quality. Once the optimal settings are found, the process is complete.

[0074] In other words, the clock and data lines are realigned, and operating conditions are re-established when the device is new or brand new. According to some embodiments, the programmable delay setting is changed to reset the timing difference between the sampling clock signal and the sampling data signal.

[0075] According to one embodiment of this disclosure, a method for setting operating parameters of an integrated circuit is disclosed, particularly a method for self-tuning the internal timing of the integrated circuit, the integrated circuit comprising at least one circuit portion that receives a known data stream at a data input and a clock signal at a clock input, the method comprising:

[0076] The clock signal and / or the data stream are aligned in time by inserting an upstream programmable or finely adjustable delay element or circuit before one or two of the inputs.

[0077] In addition, the timing alignment phase includes establishing operating conditions when the integrated circuit is new or brand new from the factory.

[0078] Timing alignment is achieved by inserting a programmable or adjustable delay element or circuit upstream of the clock input to modify the relative distance between the data stream and the effective or leading edge of the clock signal.

[0079] The programmable or adjustable delay element or circuit is inserted upstream of the clock signal path relative to the clock input.

[0080] Alternatively, time alignment is achieved by inserting programmable or finely adjustable delay elements or circuits upstream of the data input to modify the relative distance between the data stream and the effective or leading edge of the clock signal.

[0081] In the last case, a programmable or adjustable delay element or circuit is inserted upstream of the data flow path relative to the data input. The above process can be performed at least for the first time in the factory when the device is first used, and this can be done using a test machine. The found value is stored in a non-volatile register for future use.

[0082] In another embodiment, a stage for time alignment of clock signals and / or data streams is achieved by programmable or finely adjustable delays upstream of the data input and clock input.

[0083] Another alternative in the factory is to use instructions from the design team to set all delays and leave it to the host for fine-tuning.

[0084] Alternatively, the setup phase can be performed automatically, for example, when the integrated circuit is reset.

[0085] Alternatively, the above process may be performed upon request from the host device, or in other words, upon request from the on-chip system associated with the integrated circuit (i.e., the memory device).

[0086] As an alternative, the process reported above is activated upon receiving a warning signal generated by the host device (e.g., after a failure to perform a multifunction or read message of the memory device has been detected, or if the host device detects a significant change in the operating conditions of the component (e.g., temperature increase / decrease)).

[0087] Other alternative warning messages can be defined as the starting point for the readjustment phase of the operating parameters of the integrated circuit.

[0088] For example, in cases where fine-tuning of output impedance and / or buffer delay is required, a specific event can be provided to generate a request to readjust operating parameters. For instance, due to load changes on I / O pins caused by host board reconfiguration, temperature changes, and other possible changes in operating conditions, it is recommended to fine-tune the buffer driver (e.g., select one from several available drivers) and data path delay to ensure the correct offset between external signals and the clock.

[0089] In one embodiment of this disclosure, such as Figure 3 As shown, the set time or hold time can be tuned by inserting some finely adjustable delay elements or circuits to change the relative distance between the data received from the data input and the effective edge of the clock. The figure illustrates a schematic general-purpose logic circuit section 150 containing at least one flip-flop 10, or a latch, or even a composite FSM containing at least one flip-flop, receiving a data stream and a clock signal at its inputs.

[0090] Typically, the delay is inserted into the CLK path, but in some critical cases, the delay is also used on the data path, especially if the input bus consists of signals from very different sources.

[0091] For example, in one instance, a first delay is inserted into a first data stream, and a second delay is inserted into a second data stream; the corresponding outputs of each delay block are summed and applied to the data input of the component to be fine-tuned.

[0092] Each delay block is programmable or fine-tunable via configuration commands.

[0093] According to one embodiment of this disclosure, for example, refer to Figure 3 As disclosed, delay chain 190 is inserted upstream of the clock signal path relative to clock input CLK.

[0094] The delay chain is programmable or finely tuned via the configuration signal CLK Delay config.

[0095] In addition, at least one other delay chain 170 is inserted upstream of the data input DATA in the data path.

[0096] More specifically, a first delay chain 170 is inserted between the first digital data source and the data input DATA, for example for the first group of 8 bits [0:7], while a second delay chain 180 is inserted between the second digital data source and the data input DATA, for example for the second group of 8 bits [7:15].

[0097] The corresponding outputs of the first and second data streams are added to a single data input at the digital DATA terminal of the flip-flop or latch 10.

[0098] Each delay chain is programmable or fine-tunable via the corresponding configuration signals (Data Delay config#1 and Data Delay config#2).

[0099] In one embodiment of this disclosure, the memory array is constructed as a collection of subarrays 120. Figure 4 and 5 (As shown in the diagram). In this way, if the number of sectors is smaller compared to known solutions, the access time is significantly reduced and the overall throughput of the memory component is improved.

[0100] Each subarray 120 can be independently addressed within the memory device 200. Each subarray 120 contains multiple memory blocks 160, such as... Figure 4 As shown.

[0101] In this way, if the block or sector size is smaller than known solutions (160), access time is significantly reduced and the overall throughput of the memory component is improved. The reduction in initial latency is at the block level because row and column latency, latency associated with read paths, and external communication have been optimized.

[0102] In the embodiments disclosed herein, the memory array comprises a plurality of subarrays 120, each subarray corresponding to a number of associated SoC cores and therefore to a number of corresponding communication channels. For example, at least four memory subarrays 120 are provided, each memory subarray for each communication channel corresponding to a SoC core.

[0103] The host device or system-on-a-chip typically contains more than one core, and each core is coupled to a corresponding bus or channel for receiving data and transmitting data to the memory device 200.

[0104] Therefore, in this implementation, each subarray 120 has access to a corresponding channel to communicate with the corresponding core of the on-chip system. The results of the memory block are directly driven to the SoC without the need for high-power output buffers and optimized paths.

[0105] The advantage of this architecture is its strong scalability, where the density of the final device can be increased or decreased simply by mirroring subarrays and generating connections or increasing the number of blocks per subarray (i.e., the available density per core).

[0106] Each subarray 120 can be independently addressed within the memory device 200. Furthermore, each memory array consists of at least four memory subarrays 120. This is the form factor for this device, but it may differ in other technologies and / or applications. As described, it contributes to low initial latency, matching the final word processed in the SoC of this particular application.

[0107] In one embodiment of this disclosure, the output of subarray 120 is formed by combining the following sequence: data unit plus address unit plus ECC unit. In the embodiments disclosed herein, the total number of bits may include 168 pads per channel.

[0108] In addition, such as Figure 4 As schematically shown, each memory subarray 120 is configured within a memory block 160. The architecture of the memory block 160, which includes each location of the memory array, can be defined as a superpage. In embodiments of this disclosure, the addressing of each independently addressable location of the block 160 of each memory subarray 120 will be an extension page 130, as defined below using the term superpage.

[0109] In other words, the 128-bit atomic pages in each subarray 120 used to fill the communication channels with SoC devices have been enlarged to contain the stored address and ECC.

[0110] As a non-limiting example, the extended page 130 includes a string containing a first set of at least 128 (128) bits for I / O data exchange with the SoC device, plus a second set of at least 24 (24) address bits, and a final or third set of at least 16 (16) ECC bits. The 24 (24) address bits are sufficient to address up to 2 gigabits of available memory space.

[0111] According to this disclosure, depending on the size of the memory array, the output of the sense amplifier SA prepares a double extended page at once, namely a super page 130 comprising multiple bits given by a dual combination of the three sets of data bits, address bits and ECC bits.

[0112] In the specific but non-limiting instances disclosed herein, each extended page 130 contains at least 168 bits, which are obtained by combining the above three groups of 128+24+16 data, address and ECC bits, and each superpage is formed by a pair of extended pages, i.e., a group of 168×2 bits.

[0113] For the sake of providing a non-limiting numerical example only, each row 125 of memory block 160 contains sixteen extended pages. Thus, the resulting row contains 2688 bits derived from the combination of sixteen independently addressable extended pages, and each contains 168 bits, or in other words, a combination of eight superpages.

[0114] The combined string of data unit + address unit + ECC unit allows for full bus security coverage according to standard requirements, because ECC covers the entire bus communication (data unit + address unit), and the presence of the address unit provides confidence that the data comes exactly from the addressing location of the controller.

[0115] Therefore, each line of 125 contains at least 16 pages, which includes a memory word plus the corresponding address bits and the corresponding ECC bits. Obviously, another size can be chosen, and the reported values ​​are for illustrative purposes only and are not intended to be limiting.

[0116] For the sake of completeness, it should be noted that, according to Figure 4 In one embodiment of the present disclosure described herein, virtual rows or lines 300 are associated with each block 160 of the memory subarray 120.

[0117] This virtual line 300 is located outside the address space of the memory array and is used for fine-tuning parameter optimization. This virtual line is inserted to monitor cell drift and simultaneously store optimal settings for different operating corners.

[0118] The primary purpose of this virtual row 300 is to track temperature, voltage, and process variations. In this way, parameters can be set according to optimal settings stored in the virtual row to perform read and write operations within the array.

[0119] Virtual row 300 contains a known pattern for a memory controller for memory device 200.

[0120] In fact, comparing the expected data with the content of virtual row 300 can provide information about changes that can lead to fine-tuning of parameters.

[0121] In this way, it is possible to optimize read operations that occur under different temperatures, voltages, or process values.

[0122] To provide this possibility, different pattern values ​​of the fine-tuning parameters are recorded in a programmable or fine-tunable register for each different temperature or voltage level. In other words, different read voltage values ​​are recorded in this programmable or fine-tunable register for use under different temperature or voltage conditions by performing the read phase by changing the fine-tuning parameters.

[0123] This allows for the detection and comparison of a known reference pattern at different temperature or voltage values. This known reference pattern is stored in the microcontroller's internal memory. The controller knows the address of this known reference pattern and can perform fine-tuning by reading internal adjustments until the optimal corner is found. At this point, the controller will use information contained in that row or another location within the memory that contains the "best" possible adjustment for the read and write phases.

[0124] To better understand this disclosure, by way of specific example only, suppose a known value such as 0x55 is recorded in hexadecimal form in virtual line 300. This value is particularly suitable because it contains the same number of logical "0" and logical "1" values.

[0125] Since this value is known prior, the system will perform several read cycles, changing the fine-tuning parameters until the value is correctly read. The correctly read changed fine-tuning parameters will correspond to the set temperature or set voltage value recorded in the programmable or fine-tunable register.

[0126] The reading phase of other parts or sectors of subarray 120 can only be performed when the read fine-tuning parameters correspond exactly to the correct read of the known values.

[0127] In other words, using a known data string stored in a specific virtual row 300 of array block 120 is useful for quickly comparing the current read with the reference read phase.

[0128] In practice, it is not necessary to store the aforementioned known values ​​under predetermined operating conditions, because the pattern is known to the internal controller and its address. Therefore, the controller can scan the fine-tuning parameters until the pattern is read with the best possible margin. At this point, the possible optimal corners are found, and the internal controller uses these settings for other operations.

[0129] The controller only requires additional checks when some data reads begin to show a high ECC, indicating that operating conditions have changed and a readjustment phase is needed.

[0130] Using the knowledge of this known string, it is possible to set calibration modes for setting and holding time intervals, as well as for other parameters that need to be fine-tuned periodically.

[0131] The specific information stored in the virtual line 300 is read during the calibration phase, and at very loose timings, making it unaffected by potential issues with the detection settings and hold intervals.

[0132] Under specific events (i.e., changes in temperature or reference voltage (Vdd)) or upon user request, the known pattern stored in virtual row 300 is read, and the internal calibration algorithm begins to fine-tune the configuration for optimal performance and to avoid any metastability.

[0133] Optionally, the integrated circuit may have the ability to store parameters obtained each time it is fine-tuned in the aforementioned programmable or fine-tunable register (e.g., lookup table) so that the parameters can be reused in future situations should the same or similar conditions occur.

[0134] Therefore, the controller of the integrated memory device can check whether a similar environmental condition has occurred before calculating a new fine-tuning. If a previous condition is detected by a positive result of a comparison between data retrieved from a programmable or fine-tunable register and data stored in reference virtual row 300, this indication can be used as a starting point for finding a new fine-tuning.

[0135] Alternatively, since no computation time is available due to ongoing emergency operations, the retrieved information itself can be used in the subsequent fine-tuning phase.

[0136] In any case, the need to detect the re-fine-tuning operation allows for the acceleration and optimization of the tuning process.

[0137] Now for more specific reference Figure 5 In one example, a fine-tuning block 155 has been provided within the memory device 200 as the core of the fine-tuning method.

[0138] This 155 chip receives at least a value indicating the operating temperature and information about the reference voltage Vdd level at its inputs. These signals can originate from external sources, meaning from the on-chip system or an external device.

[0139] In addition, one input can be an external calibration request.

[0140] The fine-tuner block 155 is also configured to use an internal detector to calculate internal temperature and Vdd information internally.

[0141] The digital output of the tuner block 155 is represented by a fine-tuning bus leading to multiple internal circuits indicated by the general-purpose block 150. This block is positioned between the output of the sense amplifier and the output buffer of the memory array. This block 150 provides clock and data to perform the fine-tuning operation. When this fine-tuning operation is performed, I / O is disconnected to isolate the memory during this calibration sequence. Simultaneously, a block 175, referred to as a "probe," performs an appropriate comparison between the data from the array and the data from the fine-tuning block.

[0142] Figure 5 The schematic diagram illustrates the read and write circuitry system at the output of the sense amplifier SA, representing logic circuitry 150, where the set and hold time intervals must be periodically fine-tuned. Delay fine-tuning is typically performed in a separate block containing the overall configuration of the device.

[0143] For sensing amplifiers and analog circuits that need to function correctly to use memory devices, fine-tune the data contained in this block 150.

[0144] These parameters can be block-dependent because the stored data (including the previously disclosed dummy pattern 0x55) can be written at any corner.

[0145] It should also be considered that the erase phase of array block 120 will delete "virtual row" 300 and its contents. Storage operations should always be performed before the erase phase to preserve optimal settings elsewhere in memory and restore them later.

[0146] Since the internal memory controller knows the location and content, a gold pattern (i.e., the stored 0x55 value) is not needed. A second important consideration is that erasing this block can occur at any corner, and this means that specific optimal parameters need to be restored, and then read using the optimal value found using the algorithm described above.

[0147] Figure 3 An example of this is a delayed configuration that is typically stored in a special configuration block inherent in the device at the factory.

[0148] The key is to correctly read the known content of virtual row 300, ensuring that all changes in this content, under real-world conditions, represent the fine-tuning necessary to bring the parameters to the reset settings and hold time intervals. As previously mentioned, delay fine-tuning is written into the configuration block of the entire memory and stored once in the factory. Clearly, this method can be applied, but an erase is never performed when the eye diagram is analyzed and the optimal point is found, and the optimal settings can be shared with the regular array block.

[0149] As previously described, delay fine-tuning is stored in a configuration block, such as block 160. Each of the memory subarrays 120 (or block 160, depending on the implementation) may contain virtual rows 300 to store the gold pattern and analog / digital calibration parameters. Therefore, the fine-tuning bus at the output of the fine-tuner block 155 is active on the data and clock inputs of the logic circuit to adjust and configure the reference. Figure 3 The system discloses delay blocks and allows for self-tuning of memory components intended for integrated circuits that require periodic adjustments.

[0150] Typically, the memory array and the fine-tuning block must be isolated from the outside world to ensure that the fine-tuning is not affected by noise from the I / O lines. In this regard, once a user request is received, the fine-tuning block begins to work, providing specific output commands to the isolator block 165HiZ.

[0151] First, the spinner 155 isolates the outside of the PCB by activating the isolator 165, for example by forcing the HiZ block 165 to operate as an output buffer.

[0152] Secondly, checking the 0x55 value allows the optimal fine-tuning to be found. Once the fine-tuning parameters are found, a lookup table is addressed to load all the appropriate settings. The appropriate settings may also contain data for performing the selected write and erase phases, as they will appear along with the optimal parameters found during the 0x55 probe and comparison.

[0153] Using a 0x55 trim will always point to a valid setting in the lookup table. This is because these settings are factory-selected and must cover the entire operating range of the memory.

[0154] If nothing is available (or the feature does not exist), fine-tune from scratch and activate the optimization algorithm.

[0155] In this regard, the optimization algorithm operates according to the following process:

[0156] Read special information lines (even several times) to build an eye diagram, and then select the optimal settings for the operating point where the memory is in use;

[0157] The spinner block 155 contains a gold pattern. This is because the gold pattern must always be rewritten whenever a subarray and / or subarray block and / or subarray group is erased.

[0158] At the end of the erase operation, the gold pattern write phase is performed by the flash memory controller. Essentially, the erase ends with the gold pattern being written and the optimal parameters being restored from the local storage area and / or copied from another similar block with virtual rows.

[0159] The spinner block requires read operations on a specific virtual row, but with standard timing (or optimal timing knowing the specific temperature / Vdd conditions). Standard timing is typically a default low-speed / safe parameter. In any case, the spinner block knows the pattern in the controller, so it can perform operations even with high memory array speeds due to the SoC 210's direct memory access. The memory logic will perform several reads of the stored gold pattern, changing the read parameters to find the optimal ones.

[0160] If no timing is available, the fine-tuner uses the best parameters obtainable from the design process. The algorithm described is implemented to find... Figure 6 The eye diagram shown has the optimal opening; that is, the read phase is performed step by step using all possible configurations, and the reads are compared to understand how good the golden configuration is. At the end of the operation, the eye diagram is examined and the optimal setting is selected.

[0161] Figure 7 This represents an example of a memory device incorporated into this disclosure and comprising several tri-state drivers 710 as the final stage output buffer 700. The output of stage 710 is addressed to output pad 750, wherein the output signal BUFFER#N_OUT is available.

[0162] Each drive 710 can be selectively selected using the drive selector 720. Once the selector 720 is enabled by setting the selector signal Drive selector config#N, the selection is provided by the input signal Data_sel[7:0].

[0163] The buffer input signal BUFFER#N_IN is received by input stage 740, which is coupled to driver series 710 via pre-driver stage 730.

[0164] Delay block 760 is coupled between the output of input stage 740 and the input of pre-driver stage 730. (Similar to reference...) Figure 3 In the publicly disclosed example, the delay block 760 receives the first signal Data Delay config#N and the second data signal Data[7:0] as input.

[0165] The fine-tuning of the output buffer 700 allows for selection of the correct output impedance. The fine-tuning of the delay block 760 allows for precise adjustment of the DATA_PATH, which serves as the data path from the memory array to the output PAD, to optimize settings and maintain timing relative to the SoC clock.

[0166] in this regard, Figure 8 A schematic diagram of a simplified model of transmission on a wired bus is shown. Figure 7The pad 750 shown should be considered to be coupled to the transmitter TX, which can be considered as one end A of a communication channel such as bus line 800. Therefore, the flash array output buffer communicates with the host device or SoC via line 800, and at the opposite end of this line is a node B representing the receiver RX of another device connected to the bus.

[0167] Figure 9 and 10 They reported separately Figure 8 A schematic diagram of the voltage values ​​at two opposite nodes A and B on opposite sides of a wired bus versus time.

[0168] It is understandable that the voltage value Va at node A is in the form of a square wave, while the obtained transmitted value Vb is a sine wave.

[0169] exist Figure 9 and 10 Each side of the diagram reports an eye diagram, which is a method for representing and analyzing high-speed digital signals. Eye diagrams allow for the rapid visualization and determination of key parameters related to the electrical quality of a signal. Data eye diagrams are constructed from digital waveforms by folding waveform portions corresponding to each individual bit into single diagrams having signal amplitude on the vertical axis and time on the horizontal axis.

[0170] therefore, Figure 9 and 10 The waveforms on the output buffer side and the receiver side, as well as the corresponding and associated eye diagrams, are depicted under noisy and noisy conditions.

[0171] From these expressions, it can be understood that Figure 9 This represents the ideal eye diagram, while Figure 10 This represents a true (or near-true) eye diagram that includes distortion (e.g., load-related distortion) and noise.

[0172] These figures clearly show that there exists an optimal point for sampling the output signal of the output buffer, and this point is essentially the central part or box of the eye, which defines the area where sampling is acceptable.

[0173] Of course, the goal of fine-tuning the delay or impedance and tuning the phase is to make the eye open well, which means that the sampling area is relatively wide.

[0174] The previously disclosed methods are also known as calibration and / or training in the DRAM and PCI domains, as follows:

[0175] 1. Compare the read value with the expected value.

[0176] a. If they match, the first phase (initial point) ends → see Figure 6 Point 610 in the diagram

[0177] b. If some outputs do not match, the configuration is changed until they match (therefore step (a) is iterated several times).

[0178] 2. Once the initial point is determined, each configuration is modified to find the widest functional interval. Figure 6 Point 620 in the diagram.

[0179] Optimization methods to reduce the time spent finding the optimal point to use can consider selecting appropriate values ​​in the lookup table based on one of the following:

[0180] Random search (bit by bit)

[0181] Binary search (bit-by-bit)

[0182] Gradient descent; this means that each data point [N-1:0] brings a solution space with 2N words.

[0183] The same approach can be used for any other parameters within the device, depending on the integrated circuit's Vdd / temperature / process or external conditions. This can also be useful considering process aging and when internal parameter readjustment is required.

[0184] This method can be substantially the same as the gold pattern stored in the flash internal controller disclosed above, and can be used as a method to find the deviation of the parameters relative to known values.

[0185] For example, this method can also be used to match PCB impedance, in which case different buffers Zout are selected for fine-tuning, and the feedback for the fine-tuner is a reflected signal.

[0186] Referring now to recalibration due to factors such as thermal drift, detecting the actual temperature value during the read phase is not important. This temperature may be higher (even much higher) or lower than the temperature level during the programming phase. The problem here is that temperature variations will generate virtual drift and amplify the internal horizontal distribution. This drift and amplification will generate errors due to the overlap of the distributions. This effect is most severe when the comparison device is new, and most severe when the device ages, because the distribution has already amplified at the start.

[0187] Using the method disclosed herein, the system will be automatically protected against any thermal drift because the fine-tuning parameters are selected after a correct read of the known sequence stored in virtual row 300 has been performed and the fine-tuning parameters contained in the programmable or fine-tunable register and used to read the same known value at different temperatures or with different reference voltage values ​​have been identified accordingly.

[0188] The process of identifying more suitable readout fine-tuning parameters for the correct readout phase at a given temperature value will not necessarily repeat in large periods. This process is performed when the external SoC requires it and / or when a high ECC level is detected during a read operation.

[0189] Conversely, this process can be performed periodically or in a more appropriate manner when a potential problem is detected by the ECC bit.

[0190] For example, a situation arises where increasing the number of ECC bits (array ECC may differ from the safety bits as previously commented) reports an excessive number of erroneous reads from the memory device. In this case, the system can automatically initiate a process to detect potential thermal drift and the subsequent need to adjust fine-tuning parameters.

[0191] In some cases, the process can be performed in response to changes in external conditions (e.g., by detecting changes in temperature or power supply voltage through corresponding sensors in the vehicle).

[0192] The architecture and method of this disclosure have several distinct advantages. For example, it provides the possibility of any thermal drift following the memory device or the environment in which the system of the memory device is embedded. This is associated with optimal setup. Additionally, it provides programmability of the system, as the virtual rows 300 in which known values ​​are recorded can be deleted and reprogrammed as needed, even according to changes in the environment of the memory device. This is because 0x55 can be retrieved from the internal flash memory controller as a location and pattern, while in this embodiment the lookup table can be derived from another subarray.

[0193] Although specific embodiments have been illustrated and described herein, those skilled in the art will understand that arrangements calculated to achieve the same results may replace the specific embodiments shown. This disclosure is intended to cover modifications or variations of various embodiments of this disclosure. It should be understood that the above description is illustrative rather than restrictive. After reading the above description, combinations of the above embodiments and other embodiments not specifically described herein will be apparent to those skilled in the art. The scope of the various embodiments of this disclosure includes other applications in which the above structures and methods are used. Therefore, the scope of the various embodiments of this disclosure should be determined by reference to the appended claims and the full scope of their equivalents.

Claims

1. A method for a self-tuning integrated circuit, comprising: In response to receiving an indication of a change in operating temperature or reference voltage, the system looks up the operating parameters corresponding to the current operating temperature and reference voltage in a lookup table. In response to the absence of the operating parameter corresponding to the current operating temperature and reference voltage: The operating parameters of the integrated circuit (200) are set for self-fine-tuning of the integrated circuit's internal timing, the integrated circuit including a circuit section that receives a data stream at a data input and a clock signal at a clock input. Setting the operating parameters includes aligning at least one of the clock signal or the data stream in time by inserting upstream programmable or adjustable delay elements or circuits (170, 180, 190) before one or two of the inputs, and The operating parameters are recorded in the lookup table relative to the current operating temperature and reference voltage.

2. The method of claim 1, further comprising establishing operating conditions when the integrated circuit is brand new.

3. The method of claim 1, wherein timing alignment includes inserting a programmable or adjustable delay element or circuit (190) upstream of the clock input to modify the relative distance between the data stream and the effective or leading edge of the clock signal.

4. The method of claim 1, wherein timing alignment includes inserting a programmable or adjustable delay element or circuit (170, 180) upstream of the data input to modify the relative distance between the data stream and the effective or leading edge of the clock signal.

5. The method of claim 1, wherein the self-adjustment of the internal timing of the integrated circuit is performed automatically.

6. The method of claim 1, wherein timing alignment includes adjusting the upstream programmable or finely adjustable delay element or circuit to reset the timing difference between the sampling clock signal and the sampling data signal.

7. The method of claim 1, wherein time alignment includes adjusting the setting time interval of the circuit portion.

8. The method of claim 1, wherein alignment in time phase includes adjusting the holding time interval of the circuit portion.

9. The method of claim 1, wherein timing alignment includes adjusting the upstream programmable or finely adjustable delay element or circuit by configuring a signal.

10. The method of claim 1, wherein timing alignment includes adjusting the upstream programmable or tunable delay element or circuit via a delay chain.

11. A method for a self-tuning integrated circuit, comprising: In response to receiving an indication of a change in operating temperature or reference voltage, the system looks up the operating parameters corresponding to the current operating temperature and reference voltage in a lookup table. In response to the absence of the operating parameter corresponding to the current operating temperature and reference voltage: The operating parameters of the integrated circuit (200) are set for self-fine-tuning of the integrated circuit's internal timing, the integrated circuit including a circuit section that receives a data stream at a data input and a clock signal at a clock input. Setting the operating parameters includes a tuning phase that involves changing the relative time distance between the data stream received by the data input terminal and the effective edge of the clock signal by inserting programmable or adjustable delay elements or circuits (170, 180, 190) to perform at least one of a setting time or a hold time. The operating parameters are recorded in the lookup table relative to the current operating temperature and reference voltage.

12. The method of claim 11, wherein performing the tuning phase includes adjusting the programmable or tunable delay element or circuit upstream of the clock input.

13. The method of claim 11, wherein performing the tuning phase includes adjusting the programmable or tunable delay element or circuit upstream of the data input.

14. The method of claim 11, wherein the tuning phase is performed automatically.

15. The method of claim 11, further comprising establishing operating parameters when the integrated circuit is brand new.

16. The method of claim 11, further comprising adjusting the programmable or adjustable delay element or circuit by configuring a signal.

17. The method of claim 11, wherein the programmable or adjustable delay element or circuit is implemented by a delay chain.

18. An integrated memory device comprising: A memory cell array with decoding and sensing circuitry systems; Memory controller; The read and write circuitry associated with the sensing circuitry system; The logic circuit portion (150) of the read and write circuit system includes logic elements that receive a data stream at the data input and a clock signal at the clock input; and A programmable or adjustable delay element or circuit (170, 180, 190) upstream of the data input or the clock input; and The trimmer includes a first input indicating the operating temperature and a second input indicating the reference voltage; In response to receiving an indication of a change in operating temperature or a change in reference voltage, the integrated memory device is configured to: Find the self-tuning operating parameters corresponding to the current operating temperature and reference voltage in the lookup table; and In response to the failure to find the self-tuning operating parameter corresponding to the current operating temperature and reference voltage, the programmable or adjustable delay element or circuitry is caused to: The internal timing of the logic element is fine-tuned by aligning it in time with at least one of the clock signal or the data stream; and The self-adjusting operating parameters are recorded in the lookup table relative to the indicated operating temperature and reference voltage.

19. The memory device of claim 18, wherein the programmable or adjustable delay element or circuit (190) is inserted upstream of the clock signal path relative to the clock input.

20. The memory device of claim 18, wherein the programmable or adjustable delay element or circuit (170, 180) is inserted upstream of the data flow path relative to the data input.

21. The memory device of claim 18, wherein the programmable or adjustable delay element or circuit is configured to automatically perform self-adjustment of the internal timing.

22. The memory device of claim 18, wherein the programmable or adjustable delay element or circuit is configured to reset the timing difference between the sampling clock signal and the sampling data signal.

23. The memory device of claim 18, wherein the programmable or adjustable delay element or circuit is configured to adjust the setting time interval of the logic element.

24. The memory device of claim 18, wherein the programmable or adjustable delay element or circuit is configured to adjust the hold time interval of the logic element.

25. The memory device of claim 18, wherein the programmable or adjustable delay element or circuit has an input configured to receive a configuration signal.

26. The memory device of claim 18, wherein the programmable or adjustable delay element or circuitry comprises a delay chain.

27. An integrated memory device, structured for communication with a host device or system-on-a-chip via a communication channel having corresponding pads (750); comprising: A memory cell array with decoding and sensing circuitry systems; Memory controller; An output buffer (700) is coupled to the memory cell array and includes multiple optional final output stages (710) coupled to the respective pads (750); The driver selector in the output buffer is used to select from the plurality of optional final output stages to select the output impedance of the output buffer; and The programmable or adjustable delay element or circuit (760) upstream of the plurality of optional final output stages in the output buffer is used to finely tune the output impedance of the output buffer.

28. The integrated memory device of claim 27, wherein the programmable or adjustable delay element or circuit is configured to adjust the path of data from the memory cell array to the corresponding pad (750).

Images