Method and apparatus for transmitting reference signals

Abstract

The present application provides a method and apparatus for transmitting reference signals, which can solve the problem of insufficient DMRS transmission resources, thereby improving the reliability of transmitting DMRS, and can be applied to 4G or 5G communication systems, such as LTE, NR, etc. The method includes: a network device sends a demodulation reference signal to a terminal device on a first symbol. Wherein, the first symbol is determined by the symbols occupied by the synchronization signal block, the system message, and the data channel respectively. Wherein, the first symbol may be the symbol in the symbols occupied by the data channel that is not occupied by the synchronization signal block and the system message.

Description

Technical Field

[0001] This application relates to the field of communications, and in particular, to a method and apparatus for transmitting a reference signal. Background Art

[0002] The existing New Radio (NR) protocol stipulates that: in the symbols occupied by the Physical Downlink Shared Channel (PDSCH), the Demodulation Reference Signal (DMRS) can only occupy 1 symbol, such as the 3rd or 4th symbol (i.e., symbol 2 or symbol 3), or the 1st symbol among the symbols after the symbols occupied by the Remaining System Information Control Resource Set (RMSICORESET, that is, the Physical Downlink Control Channel (PDCCH) of Type 0, hereinafter uniformly referred to as CORESET) and before the symbols occupied by the Synchronization Signal Block (SSB), that is, DMRS cannot occupy the same symbols as SSB and CORESET. Among them, CORESET needs to occupy the first 1 or 2 symbols, such as symbol 0, or symbols 0 and 1, and SSB also needs to occupy 4 consecutive symbols, such as symbols 2 - 5. Assume that PDSCH occupies symbols 0 - 6, and CORESET only needs to occupy symbol 0, then DMRS can, and can only, occupy symbol 1.

[0003] However, in the above example, if CORESET needs to occupy the first 2 symbols, that is, symbols 0 and 1, then all the symbols that DMRS can occupy have been occupied by CORESET and SSB, resulting in the inability to transmit DMRS normally. Summary of the Invention

[0004] Embodiments of this application provide a method and apparatus for transmitting a reference signal, which can solve the problem of insufficient DMRS transmission resources, thereby improving the reliability of transmitting DMRS.

[0005] To achieve the above object, this application adopts the following technical solutions:

[0006] In a first aspect, a method for transmitting a reference signal is provided. The method includes: a network device sending a demodulation reference signal to a terminal device on a first symbol. Wherein, the first symbol is determined by the symbols occupied by the synchronization signal block, system message, and data channel respectively.

[0007] In the transmission method of the reference signal provided by the embodiment of the present application, the network device can determine the first symbol according to the symbols occupied by the synchronization signal block, the system message, and the data channel respectively, and send DMRS to the terminal device on the first symbol, which can solve the problem that when the symbols occupied by the data channel, since the symbols that could originally be occupied by DMRS have all been occupied by the synchronization signal block and the system message, resulting in the inability to transmit DMRS, and can improve the reliability of transmitting DMRS.

[0008] Specifically, the first symbol can be the symbol among the symbols occupied by the data channel that is not occupied by the synchronization signal block and the system message.

[0009] In a possible design method, the number of the first symbols can be one. Correspondingly, the above-mentioned one first symbol is located before or after the symbol occupied by the synchronization signal block in the time domain.

[0010] Furthermore, the above-mentioned one first symbol can be: the last symbol located before the symbol occupied by the synchronization signal block in the time domain. Or, optionally, the above-mentioned one first symbol can also be: the first symbol located after the symbol occupied by the synchronization signal block in the time domain.

[0011] In another possible design method, the number of the first symbols is two. Correspondingly, one of the above-mentioned two first symbols is located before the symbol occupied by the synchronization signal block in the time domain, and the other is located after the symbol occupied by the synchronization signal block in the time domain. Or, optionally, the above-mentioned two first symbols are both located before the symbol occupied by the synchronization signal block in the time domain, and the above-mentioned two first symbols are not consecutive. Or, the above-mentioned two first symbols are both located after the symbol occupied by the synchronization signal block in the time domain, and the above-mentioned two first symbols are not consecutive.

[0012] Furthermore, the above-mentioned two first symbols are both located before the symbol occupied by the synchronization signal block in the time domain, and the above-mentioned two first symbols are not consecutive, which can include: the above-mentioned two first symbols can be: the first symbol and the last symbol located before the symbol occupied by the synchronization signal block in the time domain, and the above-mentioned two first symbols are not consecutive.

[0013] Furthermore, the above-mentioned two first symbols are both located after the symbol occupied by the synchronization signal block in the time domain, and the above-mentioned two first symbols are not consecutive, which can include: the above-mentioned two first symbols can be: the first symbol and the last symbol located after the symbol occupied by the synchronization signal block in the time domain, and the above-mentioned two first symbols are not consecutive.

[0014] In a second aspect, a method for transmitting a reference signal is provided. The method includes: a terminal device receives a synchronization signal block and parses a system message to determine a first symbol. The terminal device receives a demodulation reference signal from a network device on the first symbol.

[0015] Specifically, the first symbol may be a symbol among the symbols occupied by a data channel that is not occupied by the synchronization signal block and the system message.

[0016] In a possible design method, the number of the first symbols may be one. Accordingly, the above-mentioned one first symbol is located before or after the symbol occupied by the synchronization signal block in the time domain.

[0017] Furthermore, the above-mentioned one first symbol may be: the last symbol located before the symbol occupied by the synchronization signal block in the time domain. Or, optionally, the above-mentioned one first symbol may also be: the first symbol located after the symbol occupied by the synchronization signal block in the time domain.

[0018] In another possible design method, the number of the first symbols is two. Accordingly, one of the above-mentioned two first symbols is located before the symbol occupied by the synchronization signal block in the time domain, and the other is located after the symbol occupied by the synchronization signal block in the time domain. Or, optionally, both of the above-mentioned two first symbols are located before the symbol occupied by the synchronization signal block in the time domain, and the above-mentioned two first symbols are not consecutive. Or, the above-mentioned two first symbols are both located after the symbol occupied by the synchronization signal block in the time domain, and the above-mentioned two first symbols are not consecutive.

[0019] Furthermore, when both of the above-mentioned two first symbols are located before the symbol occupied by the synchronization signal block in the time domain and the above-mentioned two first symbols are not consecutive, it may include: the above-mentioned two first symbols may be: the first symbol and the last symbol located before the symbol occupied by the synchronization signal block in the time domain, and the above-mentioned two first symbols are not consecutive.

[0020] Furthermore, when both of the above-mentioned two first symbols are located after the symbol occupied by the synchronization signal block in the time domain and the above-mentioned two first symbols are not consecutive, it may include: the above-mentioned two first symbols may be: the first symbol and the last symbol located after the symbol occupied by the synchronization signal block in the time domain, and the above-mentioned two first symbols are not consecutive.

[0021] For the technical effects of the method for transmitting a reference signal described in the second aspect, reference may be made to the technical effects of the method for transmitting a reference signal described in the first aspect, which will not be elaborated here.

[0022] In a third aspect, a method for transmitting a reference signal is provided. The method includes: a network device sending a demodulation reference signal to a terminal device on a first symbol. The first symbol is a partial symbol among the symbols occupied by a synchronization signal block, and the synchronization signal block and a data channel occupy the same symbol.

[0023] In the method for transmitting a reference signal provided in the embodiments of this application, when the data channel and the synchronization signal block occupy the same symbol, the network device can determine a partial symbol occupied by the synchronization signal block as the first symbol, and use frequency division multiplexing to send the demodulation reference signal and the synchronization signal block on the first symbol, which can solve the problem that all the symbols occupied by the data channel have been occupied by the synchronization signal block, resulting in no complete symbol available for transmitting the DMRS, and further resulting in the inability to transmit the DMRS, and can improve the reliability of transmitting the DMRS.

[0024] In a possible design method, the number of the first symbols can be one. Correspondingly, the above one first symbol can be any one of the symbols occupied by the synchronization signal block. Usually, the symbols occupied by the synchronization signal block are 4 consecutive symbols.

[0025] Further, the above one first symbol can be: the second symbol or the third symbol among the symbols occupied by the synchronization signal block.

[0026] In another possible design method, the number of the first symbols is two. Correspondingly, the above two first symbols can be: any two non - consecutive symbols among the symbols occupied by the synchronization signal block, such as the first symbol and the third symbol, or the second symbol and the fourth symbol, or the first symbol and the fourth symbol.

[0027] Further, the above two first symbols can be: the first symbol and the last symbol among the symbols occupied by the synchronization signal block.

[0028] In a possible design method, the demodulation reference signal and the synchronization signal block can use frequency division multiplexing to jointly occupy the first symbol. Usually, the synchronization signal block occupies a part of the RBs near the carrier frequency, and the demodulation reference signal can occupy the sub - carriers other than those occupied by the synchronization signal block, such as sub - carriers with sub - carrier indices greater than, and / or, less than the sub - carrier indices occupied by the synchronization signal block.

[0029] In a fourth aspect, a method for transmitting a reference signal is provided. The method includes: a terminal device receiving a synchronization signal block and parsing a system message to determine a first symbol. The terminal device receives a demodulation reference signal from a network device on the first symbol. The first symbol is a partial symbol among the symbols occupied by the synchronization signal block, and the synchronization signal block and a data channel occupy the same symbol.

[0030] In a possible design method, the number of the first symbols can be one. Accordingly, any one of the symbols occupied by the synchronization signal block can be the above-mentioned one first symbol. Among them, the symbols occupied by the synchronization signal block are usually 4 consecutive symbols.

[0031] Further, the above-mentioned one first symbol can be: the second symbol or the third symbol among the symbols occupied by the synchronization signal block.

[0032] In another possible design method, the number of the first symbols is two. Accordingly, the above-mentioned two first symbols can be: any two non-consecutive symbols among the symbols occupied by the synchronization signal block, such as the first symbol and the third symbol, or the second symbol and the fourth symbol, or the first symbol and the fourth symbol.

[0033] Further, the above-mentioned two first symbols can be: the first symbol and the last symbol among the symbols occupied by the synchronization signal block.

[0034] In a possible design method, the demodulation reference signal and the synchronization signal block can adopt a frequency division multiplexing method and jointly occupy the first symbol. Among them, the synchronization signal block usually occupies a part of the RBs near the carrier frequency. The demodulation reference signal can occupy the subcarriers other than those occupied by the synchronization signal block, such as the subcarriers with subcarrier indices greater than and / or less than the subcarrier indices occupied by the synchronization signal block.

[0035] For the technical effects of the reference signal transmission method described in the fourth aspect, reference can be made to the technical effects of the reference signal transmission method described in the second aspect, which will not be elaborated here.

[0036] In a fifth aspect, a communication device is provided. The communication device includes: a processing module and a transceiver module. Among them, the processing module is used to determine the first symbol according to the symbols occupied by the synchronization signal block, the system message, and the data channel respectively. The transceiver module is used to send the demodulation reference signal to the terminal device on the first symbol.

[0037] Specifically, the first symbol can be the symbol among the symbols occupied by the data channel that is not occupied by the synchronization signal block and the system message.

[0038] In a possible design, the number of the first symbols can be one. Accordingly, the above-mentioned one first symbol is located before or after the symbols occupied by the synchronization signal block in the time domain.

[0039] Further, the above-mentioned one first symbol can be: the last symbol located before the symbols occupied by the synchronization signal block in the time domain. Or, optionally, the above-mentioned one first symbol can also be: the first symbol located after the symbols occupied by the synchronization signal block in the time domain.

[0040] In another possible design, the number of the first symbols is two. Accordingly, one of the above two first symbols is located in front of the symbol occupied by the synchronization signal block in the time domain, and the other is located behind the symbol occupied by the synchronization signal block in the time domain. Alternatively, optionally, both of the above two first symbols are located in front of the symbol occupied by the synchronization signal block in the time domain, and the above two first symbols are not consecutive. Or, both of the above two first symbols are located behind the symbol occupied by the synchronization signal block in the time domain, and the above two first symbols are not consecutive.

[0041] Further, both of the above two first symbols are located in front of the symbol occupied by the synchronization signal block in the time domain, and the above two first symbols are not consecutive, which may include: the above two first symbols may be: the first symbol and the last symbol located in front of the symbol occupied by the synchronization signal block in the time domain, and the above two first symbols are not consecutive.

[0042] Further, both of the above two first symbols are located behind the symbol occupied by the synchronization signal block in the time domain, and the above two first symbols are not consecutive, which may include: the above two first symbols may be: the first symbol and the last symbol located behind the symbol occupied by the synchronization signal block in the time domain, and the above two first symbols are not consecutive.

[0043] Optionally, the communication device described in the fifth aspect may further include a storage module that stores programs or instructions. When the processing module executes the programs or instructions, the communication device described in the fifth aspect can perform the functions of the network device described in the first aspect.

[0044] It should be noted that the communication device described in the fifth aspect may be a network device, or a chip or a chip system disposed in the network device, and the present application does not make any limitations in this regard.

[0045] The technical effects of the communication device described in the fifth aspect may refer to the technical effects of the reference signal transmission method described in the first aspect, and will not be elaborated here.

[0046] In a sixth aspect, a communication device is provided. The communication device includes: a processing module and a transceiver module. Among them, the transceiver module is used to receive a synchronization signal block and a system message. The processing module is used to determine a first symbol according to the synchronization signal block and the system message. The transceiver module is further used to receive a demodulation reference signal from a network device on the first symbol.

[0047] Specifically, the first symbol may be a symbol that is not occupied by the synchronization signal block and the system message among the symbols occupied by the data channel.

[0048] In a possible design, the number of the first symbols may be one. Accordingly, the above one first symbol is located in front of or behind the symbol occupied by the synchronization signal block in the time domain.

[0049] Further, one of the above first symbols may be: the last symbol in the time domain before the symbol occupied by the synchronization signal block. Alternatively, optionally, one of the above first symbols may also be: the first symbol in the time domain after the symbol occupied by the synchronization signal block.

[0050] In another possible design, the number of first symbols is two. Correspondingly, one of the two first symbols is in the time domain before the symbol occupied by the synchronization signal block, and the other is in the time domain after the symbol occupied by the synchronization signal block. Alternatively, optionally, both of the two first symbols are in the time domain before the symbol occupied by the synchronization signal block, and the two first symbols are not consecutive. Or, both of the two first symbols are in the time domain after the symbol occupied by the synchronization signal block, and the two first symbols are not consecutive.

[0051] Further, both of the two first symbols are in the time domain before the symbol occupied by the synchronization signal block, and the two first symbols are not consecutive, which may include: the two first symbols may be: the first symbol and the last symbol in the time domain before the symbol occupied by the synchronization signal block, and the two first symbols are not consecutive.

[0052] Further, both of the two first symbols are in the time domain after the symbol occupied by the synchronization signal block, and the two first symbols are not consecutive, which may include: the two first symbols may be: the first symbol and the last symbol in the time domain after the symbol occupied by the synchronization signal block, and the two first symbols are not consecutive.

[0053] Optionally, the communication device described in the sixth aspect may further include a storage module that stores programs or instructions. When the processing module executes the programs or instructions, the communication device described in the sixth aspect can perform the functions of the terminal device described in the second aspect.

[0054] It should be noted that the communication device described in the sixth aspect may be a terminal device, or a chip or a chip system disposed in the terminal device, and the present application does not limit this.

[0055] The technical effects of the communication device described in the sixth aspect can refer to the technical effects of the reference signal transmission method described in the first aspect, and will not be elaborated here.

[0056] In a seventh aspect, a communication device is provided. The communication device includes: a processing module and a transceiver module. Wherein, the processing module is configured to determine some symbols in the symbol occupied by the synchronization signal block as first symbols. Wherein, the synchronization signal block occupies the same symbol as the data channel. The transceiver module is configured to send a demodulation reference signal to the terminal device on the first symbols.

[0057] In a possible design, the number of first symbols can be one. Accordingly, the above-mentioned one first symbol can be any one of the symbols occupied by the synchronization signal block. Among them, the symbols occupied by the synchronization signal block are usually 4 consecutive symbols.

[0058] Furthermore, the above-mentioned one first symbol can be: the second symbol or the third symbol among the symbols occupied by the synchronization signal block.

[0059] In another possible design, the number of first symbols is two. Accordingly, the above-mentioned two first symbols can be: any two non-consecutive symbols among the symbols occupied by the synchronization signal block, such as the first symbol and the third symbol, or the second symbol and the fourth symbol, or the first symbol and the fourth symbol.

[0060] Furthermore, the above-mentioned two first symbols can be: the first symbol and the last symbol among the symbols occupied by the synchronization signal block.

[0061] In a possible design, the demodulation reference signal and the synchronization signal block can adopt a frequency division multiplexing method and jointly occupy the first symbol. Among them, the synchronization signal block usually occupies a part of the RBs near the carrier frequency, and the demodulation reference signal can occupy the subcarriers other than those occupied by the synchronization signal block, such as the subcarriers with subcarrier indices greater than and / or less than the subcarrier indices occupied by the synchronization signal block.

[0062] Optionally, the communication device described in the seventh aspect may further include a storage module that stores programs or instructions. When the processing module executes the programs or instructions, the communication device described in the seventh aspect can perform the functions of the network device described in the third aspect.

[0063] It should be noted that the communication device described in the seventh aspect can be a network device, or a chip or a chip system disposed in the network device, and this application does not make any limitations in this regard.

[0064] The technical effects of the communication device described in the seventh aspect can refer to the technical effects of the reference signal transmission method described in the third aspect, and will not be elaborated here.

[0065] In an eighth aspect, a communication device is provided. The communication device includes: a processing module and a transceiver module. Among them, the transceiver module is used to receive the synchronization signal block and the system message. The processing module is used to determine the first symbol according to the synchronization signal block and the system message. The first symbol is a part of the symbols occupied by the synchronization signal block, and the synchronization signal block and the data channel occupy the same symbols. The transceiver module is further used to receive the demodulation reference signal from the network device on the first symbol.

[0066] In a possible design, the number of the first symbols can be one. Accordingly, the above-mentioned one first symbol can be any one of the symbols occupied by the synchronization signal block. Usually, the symbols occupied by the synchronization signal block are 4 consecutive symbols.

[0067] Furthermore, the above-mentioned one first symbol can be: the second symbol or the third symbol among the symbols occupied by the synchronization signal block.

[0068] In another possible design, the number of the first symbols is two. Accordingly, the above-mentioned two first symbols can be: any two non-consecutive symbols among the symbols occupied by the synchronization signal block, such as the first symbol and the third symbol, or the second symbol and the fourth symbol, or the first symbol and the fourth symbol.

[0069] Furthermore, the above-mentioned two first symbols can be: the first symbol and the last symbol among the symbols occupied by the synchronization signal block.

[0070] In a possible design, the demodulation reference signal and the synchronization signal block can adopt a frequency division multiplexing method and jointly occupy the first symbol. Usually, the synchronization signal block occupies a part of the RBs near the carrier frequency. The demodulation reference signal can occupy the subcarriers other than those occupied by the synchronization signal block, such as the subcarriers with subcarrier indices greater than and / or less than the subcarrier indices occupied by the synchronization signal block.

[0071] Optionally, the communication device described in the eighth aspect may further include a storage module that stores programs or instructions. When the processing module executes the programs or instructions, the communication device described in the eighth aspect can perform the functions of the terminal device described in the fourth aspect.

[0072] It should be noted that the communication device described in the eighth aspect can be a terminal device, or a chip or a chip system disposed in the terminal device. This application does not make any limitation in this regard.

[0073] For the technical effects of the communication device described in the eighth aspect, reference can be made to the technical effects of the reference signal transmission method described in the third aspect, which will not be elaborated here.

[0074] In a ninth aspect, a communication device is provided. The communication device includes: a processor and a transceiver. The processor is used to determine the first symbol according to the symbols occupied by the synchronization signal block, the system message, and the data channel respectively. The transceiver is used to send the demodulation reference signal to the terminal device on the first symbol.

[0075] Specifically, the first symbol can be the symbol among the symbols occupied by the data channel that is not occupied by the synchronization signal block and the system message.

[0076] In a possible design, the number of first symbols can be one. Accordingly, the above-mentioned one first symbol is located before or after the symbol occupied by the synchronization signal block in the time domain.

[0077] Furthermore, the above-mentioned one first symbol can be: the last symbol located before the symbol occupied by the synchronization signal block in the time domain. Alternatively, optionally, the above-mentioned one first symbol can also be: the first symbol located after the symbol occupied by the synchronization signal block in the time domain.

[0078] In another possible design, the number of first symbols is two. Accordingly, one of the above-mentioned two first symbols is located before the symbol occupied by the synchronization signal block in the time domain, and the other is located after the symbol occupied by the synchronization signal block in the time domain. Alternatively, optionally, both of the above-mentioned two first symbols are located before the symbol occupied by the synchronization signal block in the time domain, and the above-mentioned two first symbols are not consecutive. Or, both of the above-mentioned two first symbols are located after the symbol occupied by the synchronization signal block in the time domain, and the above-mentioned two first symbols are not consecutive.

[0079] Furthermore, both of the above-mentioned two first symbols are located before the symbol occupied by the synchronization signal block in the time domain, and the above-mentioned two first symbols are not consecutive, which may include: the above-mentioned two first symbols can be: the first symbol and the last symbol located before the symbol occupied by the synchronization signal block in the time domain, and the above-mentioned two first symbols are not consecutive.

[0080] Furthermore, both of the above-mentioned two first symbols are located after the symbol occupied by the synchronization signal block in the time domain, and the above-mentioned two first symbols are not consecutive, which may include: the above-mentioned two first symbols can be: the first symbol and the last symbol located after the symbol occupied by the synchronization signal block in the time domain, and the above-mentioned two first symbols are not consecutive.

[0081] Optionally, the communication device described in the ninth aspect may further include a memory that stores programs or instructions. When the processor executes the programs or instructions, the communication device described in the ninth aspect can perform the functions of the network device described in the first aspect.

[0082] It should be noted that the communication device described in the ninth aspect can be a network device, or a chip or a chip system disposed in the network device. The present application does not make any limitation thereto.

[0083] The technical effects of the communication device described in the ninth aspect can refer to the technical effects of the method for transmitting reference signals described in the first aspect, and will not be elaborated herein.

[0084] In a tenth aspect, a communication device is provided. The communication device includes: a processor and a transceiver. The transceiver is configured to receive a synchronization signal block and a system message. The processor is configured to determine a first symbol according to the synchronization signal block and the system message. The transceiver is further configured to receive a demodulation reference signal from a network device on the first symbol.

[0085] Specifically, the first symbol may be a symbol that is not occupied by the synchronization signal block and the system message among the symbols occupied by the data channel.

[0086] In a possible design, the number of the first symbols may be one. Correspondingly, the above one first symbol is located before or after the symbol occupied by the synchronization signal block in the time domain.

[0087] Further, the above one first symbol may be: the last symbol located before the symbol occupied by the synchronization signal block in the time domain. Alternatively, optionally, the above one first symbol may also be: the first symbol located after the symbol occupied by the synchronization signal block in the time domain.

[0088] In another possible design, the number of the first symbols is two. Correspondingly, one of the above two first symbols is located before the symbol occupied by the synchronization signal block in the time domain, and the other is located after the symbol occupied by the synchronization signal block in the time domain. Alternatively, optionally, both of the above two first symbols are located before the symbol occupied by the synchronization signal block in the time domain, and the above two first symbols are not consecutive. Or, both of the above two first symbols are located after the symbol occupied by the synchronization signal block in the time domain, and the above two first symbols are not consecutive.

[0089] Further, both of the above two first symbols are located before the symbol occupied by the synchronization signal block in the time domain, and the above two first symbols are not consecutive, which may include: the above two first symbols may be: the first symbol and the last symbol located before the symbol occupied by the synchronization signal block in the time domain, and the above two first symbols are not consecutive.

[0090] Further, both of the above two first symbols are located after the symbol occupied by the synchronization signal block in the time domain, and the above two first symbols are not consecutive, which may include: the above two first symbols may be: the first symbol and the last symbol located after the symbol occupied by the synchronization signal block in the time domain, and the above two first symbols are not consecutive.

[0091] Optionally, the communication device described in the tenth aspect may further include a memory, and the memory stores programs or instructions. When the processor executes the programs or instructions, the communication device described in the tenth aspect can perform the functions of the terminal device described in the second aspect.

[0092] It should be noted that the communication device described in the tenth aspect may be a terminal device, or a chip or chip system disposed in the terminal device. This application does not make any limitations in this regard.

[0093] For the technical effects of the communication device described in the tenth aspect, reference may be made to the technical effects of the method for transmitting reference signals described in the first aspect, which will not be elaborated herein.

[0094] In the eleventh aspect, a communication device is provided. The communication device includes: a processor and a transceiver. Among them, the processor is configured to determine some symbols in the symbols occupied by the synchronization signal block as the first symbols. Among them, the synchronization signal block and the data channel occupy the same symbols. The transceiver is configured to send a demodulation reference signal to the terminal device on the first symbols.

[0095] In a possible design, the number of the first symbols may be one. Correspondingly, the above-mentioned one first symbol may be any one of the symbols occupied by the synchronization signal block. Among them, the symbols occupied by the synchronization signal block are usually 4 consecutive symbols.

[0096] Further, the above-mentioned one first symbol may be: the second symbol or the third symbol in the symbols occupied by the synchronization signal block.

[0097] In another possible design, the number of the first symbols is two. Correspondingly, the above-mentioned two first symbols may be: any two non-consecutive symbols in the symbols occupied by the synchronization signal block, such as the first symbol and the third symbol, or the second symbol and the fourth symbol, or the first symbol and the fourth symbol.

[0098] Further, the above-mentioned two first symbols may be: the first symbol and the last symbol in the symbols occupied by the synchronization signal block.

[0099] In a possible design, the demodulation reference signal and the synchronization signal block may adopt a frequency division multiplexing method to jointly occupy the first symbols. Among them, the synchronization signal block usually occupies a part of the RBs near the carrier frequency. The demodulation reference signal may occupy the subcarriers other than those occupied by the synchronization signal block, such as the subcarriers with subcarrier indices greater than and / or less than the subcarrier indices occupied by the synchronization signal block.

[0100] Optionally, the communication device described in the eleventh aspect may further include a memory, and the memory stores programs or instructions. When the processor executes the programs or instructions, the communication device described in the eleventh aspect can perform the functions of the network device described in the third aspect.

[0101] It should be noted that the communication device described in the eleventh aspect may be a network device, or a chip or chip system disposed in the network device. This application does not make any limitations in this regard.

[0102] For the technical effect of the communication device described in the eleventh aspect, reference may be made to the technical effect of the method for transmitting reference signals described in the third aspect, which will not be elaborated herein.

[0103] In a twelfth aspect, a communication device is provided. The communication device includes: a processor and a transceiver. The transceiver is configured to receive a synchronization signal block and a system message. The processor is configured to determine a first symbol according to the synchronization signal block and the system message. The first symbol is a partial symbol among the symbols occupied by the synchronization signal block, and the synchronization signal block and the data channel occupy the same symbol. The transceiver is further configured to receive a demodulation reference signal from a network device on the first symbol.

[0104] In a possible design, the number of the first symbols may be one. Correspondingly, the above-mentioned one first symbol may be any one of the symbols occupied by the synchronization signal block. Usually, the symbols occupied by the synchronization signal block are 4 consecutive symbols.

[0105] Furthermore, the above-mentioned one first symbol may be: the second symbol or the third symbol among the symbols occupied by the synchronization signal block.

[0106] In another possible design, the number of the first symbols is two. Correspondingly, the above-mentioned two first symbols may be: any two non-consecutive symbols among the symbols occupied by the synchronization signal block, such as the first symbol and the third symbol, or the second symbol and the fourth symbol, or the first symbol and the fourth symbol.

[0107] Furthermore, the above-mentioned two first symbols may be: the first symbol and the last symbol among the symbols occupied by the synchronization signal block.

[0108] In a possible design, the demodulation reference signal and the synchronization signal block may adopt a frequency division multiplexing manner to jointly occupy the first symbol. Usually, the synchronization signal block occupies a part of the RBs near the carrier frequency, and the demodulation reference signal may occupy the subcarriers other than those occupied by the synchronization signal block, such as the subcarriers with subcarrier indices greater than and / or less than the subcarrier indices occupied by the synchronization signal block.

[0109] Optionally, the communication device described in the twelfth aspect may further include a memory storing programs or instructions. When the processor executes the programs or instructions, the communication device described in the twelfth aspect can perform the functions of the terminal device described in the fourth aspect.

[0110] It should be noted that the communication device described in the twelfth aspect may be a terminal device, or a chip or a chip system disposed in the terminal device, and the present application does not make any limitation thereto.

[0111] The technical effect of the communication device described in the twelfth aspect can refer to the technical effect of the reference signal transmission method described in the third aspect, which will not be elaborated here.

[0112] In a thirteenth aspect, a chip system is provided. The chip system includes a processor and an input / output port. The processor is configured to implement the processing functions involved in the first aspect to the fourth aspect, and the input / output port is configured to implement the transceiver functions involved in the first aspect to the fourth aspect.

[0113] In a possible design, the chip system further includes a memory, which is used to store program instructions and data for implementing the functions involved in the first aspect to the fourth aspect.

[0114] The chip system can be composed of chips or can include chips and other discrete devices.

[0115] In a fourteenth aspect, a communication system is provided. The system includes a network device and a terminal device.

[0116] In a fifteenth aspect, a computer-readable storage medium is provided, including: computer instructions are stored in the computer-readable storage medium; when the computer instructions run on a computer, the computer is caused to execute the reference signal transmission method according to any possible implementation manner in the first aspect to the fourth aspect.

[0117] In a sixteenth aspect, a computer program product including instructions is provided, including a computer program or instructions. When the computer program or instructions run on a computer, the computer is caused to execute the reference signal transmission method according to any possible implementation manner in the first aspect to the fourth aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0118] Figure 1 It is a schematic diagram of the architecture of the communication system provided by the embodiments of the present application;

[0119] Figure 2 It is a schematic diagram of the structure of the communication device provided by the embodiments of the present application Figure 1 ;

[0120] Figure 3 It is a schematic flowchart of the reference signal transmission method provided by the embodiments of the present application Figure 1 ;

[0121] Figure 4 It is a schematic diagram of the first reference signal transmission scenario provided by the embodiments of the present application;

[0122] Figure 5 It is a first example of DMRS configuration in the first reference signal transmission scenario provided by the embodiments of the present application;

[0123] Figure 6 Example 2 of DMRS configuration in Transmission Scenario 1 of the reference signal provided by the embodiments of the present application;

[0124] Figure 7 Example 3 of DMRS configuration in Transmission Scenario 1 of the reference signal provided by the embodiments of the present application;

[0125] Figure 8 Schematic diagram of Transmission Scenario 2 of the reference signal provided by the embodiments of the present application;

[0126] Figure 9 Example of DMRS configuration in Transmission Scenario 2 of the reference signal provided by the embodiments of the present application;

[0127] Figure 10 Schematic diagram of Transmission Scenario 3 of the reference signal provided by the embodiments of the present application;

[0128] Figure 11 Example 1 of DMRS configuration in Transmission Scenario 3 of the reference signal provided by the embodiments of the present application;

[0129] Figure 12 Example 2 of DMRS configuration in Transmission Scenario 3 of the reference signal provided by the embodiments of the present application;

[0130] Figure 13 Example 3 of DMRS configuration in Transmission Scenario 3 of the reference signal provided by the embodiments of the present application;

[0131] Figure 14 Schematic diagram of Transmission Scenario 4 of the reference signal provided by the embodiments of the present application;

[0132] Figure 15 Example of DMRS configuration in Transmission Scenario 4 of the reference signal provided by the embodiments of the present application;

[0133] Figure 16 Schematic diagram of Transmission Scenario 5 of the reference signal provided by the embodiments of the present application;

[0134] Figure 17 Example 1 of DMRS configuration in Transmission Scenario 5 of the reference signal provided by the embodiments of the present application;

[0135] Figure 18 Example 2 of DMRS configuration in Transmission Scenario 5 of the reference signal provided by the embodiments of the present application;

[0136] Figure 19 Example 3 of DMRS configuration in Transmission Scenario 5 of the reference signal provided by the embodiments of the present application;

[0137] Figure 20Example 4 of DMRS configuration in Transmission Scenario 5 of the reference signal provided by the embodiment of the present application;

[0138] Figure 21 Example 5 of DMRS configuration in Transmission Scenario 5 of the reference signal provided by the embodiment of the present application;

[0139] Figure 22 Schematic diagram of Transmission Scenario 6 of the reference signal provided by the embodiment of the present application;

[0140] Figure 23 Example 1 of DMRS configuration in Transmission Scenario 6 of the reference signal provided by the embodiment of the present application;

[0141] Figure 24 Example 2 of DMRS configuration in Transmission Scenario 6 of the reference signal provided by the embodiment of the present application;

[0142] Figure 25 Schematic diagram of Transmission Scenario 7 of the reference signal provided by the embodiment of the present application;

[0143] Figure 26 Example 1 of DMRS configuration in Transmission Scenario 7 of the reference signal provided by the embodiment of the present application;

[0144] Figure 27 Example 2 of DMRS configuration in Transmission Scenario 7 of the reference signal provided by the embodiment of the present application;

[0145] Figure 28 Example 3 of DMRS configuration in Transmission Scenario 7 of the reference signal provided by the embodiment of the present application;

[0146] Figure 29 Example 4 of DMRS configuration in Transmission Scenario 7 of the reference signal provided by the embodiment of the present application;

[0147] Figure 30 Example 5 of DMRS configuration in Transmission Scenario 7 of the reference signal provided by the embodiment of the present application;

[0148] Figure 31 Example 6 of DMRS configuration in Transmission Scenario 7 of the reference signal provided by the embodiment of the present application;

[0149] Figure 32 Example 7 of DMRS configuration in Transmission Scenario 7 of the reference signal provided by the embodiment of the present application;

[0150] Figure 33 Example 8 of DMRS configuration in Transmission Scenario 7 of the reference signal provided by the embodiment of the present application;

[0151] Figure 34Example 9 of DMRS configuration under transmission scenario 7 of the reference signal provided by the embodiments of the present application;

[0152] Figure 35 Example 10 of DMRS configuration under transmission scenario 7 of the reference signal provided by the embodiments of the present application;

[0153] Figure 36 Example 11 of DMRS configuration under transmission scenario 7 of the reference signal provided by the embodiments of the present application;

[0154] Figure 37 Example 12 of DMRS configuration under transmission scenario 7 of the reference signal provided by the embodiments of the present application;

[0155] Figure 38 Schematic diagram of transmission scenario 8 of the reference signal provided by the embodiments of the present application;

[0156] Figure 39 Example 1 of DMRS configuration under transmission scenario 8 of the reference signal provided by the embodiments of the present application;

[0157] Figure 40 Example 2 of DMRS configuration under transmission scenario 8 of the reference signal provided by the embodiments of the present application;

[0158] Figure 41 Example 3 of DMRS configuration under transmission scenario 8 of the reference signal provided by the embodiments of the present application;

[0159] Figure 42 Flow schematic of the reference signal transmission method provided by the embodiments of the present application Figure 2 ;

[0160] Figure 43 Schematic diagram of transmission scenario 9 of the reference signal provided by the embodiments of the present application;

[0161] Figure 44 Example 1 of DMRS configuration under transmission scenario 9 of the reference signal provided by the embodiments of the present application;

[0162] Figure 45 Example 2 of DMRS configuration under transmission scenario 9 of the reference signal provided by the embodiments of the present application;

[0163] Figure 46 Example 3 of DMRS configuration under transmission scenario 9 of the reference signal provided by the embodiments of the present application;

[0164] Figure 47 Example 4 of DMRS configuration under transmission scenario 9 of the reference signal provided by the embodiments of the present application;

[0165] Figure 48Example 5 of DMRS configuration for transmission scenario 9 of the reference signal provided by the embodiment of the present application;

[0166] Figure 49 Example 6 of DMRS configuration for transmission scenario 9 of the reference signal provided by the embodiment of the present application;

[0167] Figure 50 Example 7 of DMRS configuration for transmission scenario 9 of the reference signal provided by the embodiment of the present application;

[0168] Figure 51 Schematic diagram of transmission scenario 10 of the reference signal provided by the embodiment of the present application;

[0169] Figure 52 Example 1 of DMRS configuration for transmission scenario 10 of the reference signal provided by the embodiment of the present application;

[0170] Figure 53 Example 2 of DMRS configuration for transmission scenario 10 of the reference signal provided by the embodiment of the present application;

[0171] Figure 54 Example 3 of DMRS configuration for transmission scenario 10 of the reference signal provided by the embodiment of the present application;

[0172] Figure 55 Example 4 of DMRS configuration for transmission scenario 10 of the reference signal provided by the embodiment of the present application;

[0173] Figure 56 Example 5 of DMRS configuration for transmission scenario 10 of the reference signal provided by the embodiment of the present application;

[0174] Figure 57 Example 6 of DMRS configuration for transmission scenario 10 of the reference signal provided by the embodiment of the present application;

[0175] Figure 58 Example 7 of DMRS configuration for transmission scenario 10 of the reference signal provided by the embodiment of the present application;

[0176] Figure 59 Schematic diagram of transmission scenario 11 of the reference signal provided by the embodiment of the present application;

[0177] Figure 60 Example 1 of DMRS configuration for transmission scenario 11 of the reference signal provided by the embodiment of the present application;

[0178] Figure 61 Example 2 of DMRS configuration for transmission scenario 11 of the reference signal provided by the embodiment of the present application;

[0179] Figure 62This is Example 3 of the DMRS configuration for Transmission Scenario 11 of the reference signal provided by the embodiments of the present application;

[0180] Figure 63 This is Example 4 of the DMRS configuration for Transmission Scenario 11 of the reference signal provided by the embodiments of the present application;

[0181] Figure 64 This is Example 5 of the DMRS configuration for Transmission Scenario 11 of the reference signal provided by the embodiments of the present application;

[0182] Figure 65 This is Example 6 of the DMRS configuration for Transmission Scenario 11 of the reference signal provided by the embodiments of the present application;

[0183] Figure 66 This is Example 7 of the DMRS configuration for Transmission Scenario 11 of the reference signal provided by the embodiments of the present application;

[0184] Figure 67 This is a schematic diagram of the structure of the communication device provided by the embodiments of the present application Figure 2 。 Detailed implementation manners

[0185] Next, the technical solutions in the present application will be described with reference to the accompanying drawings.

[0186] The technical solutions of the embodiments of the present application can be applied to various unlicensed communication systems, such as NR-U systems, long term evolution-unlicensed (LTE-U) systems, wireless fidelity-unlicensed (WiFi-U) systems, vehicle to everything-unlicensed (V2X-U) systems, etc., as well as future unlicensed systems, such as 6th generation (6G) unlicensed systems, etc.

[0187] The present application will present various aspects, embodiments or features around a system that may include multiple devices, components, modules, etc. It should be understood and clear that each system may include additional devices, components, modules, etc., and / or may not include all the devices, components, modules, etc. discussed in conjunction with the accompanying drawings. In addition, combinations of these solutions can also be used.

[0188] In addition, in the embodiments of the present application, words such as "exemplarily", "for example", etc. are used to represent examples, illustrations or explanations. Any embodiment or design solution described as an "example" in the present application should not be construed as being more preferred or having more advantages than other embodiments or design solutions. Rather, the use of the word "example" is intended to present concepts in a specific manner.

[0189] In the embodiments of the present application, "information", "signal", "message", "channel", and "signalling" may sometimes be used interchangeably. It should be noted that when the differences are not emphasized, their intended meanings are the same. "Of", "corresponding", and "corresponding" may sometimes be used interchangeably. It should be noted that when the differences are not emphasized, their intended meanings are the same.

[0190] In the embodiments of the present application, sometimes subscripts such as W 1 may be miswritten as non-subscript forms such as W1. When the differences are not emphasized, their intended meanings are the same.

[0191] The network architecture and service scenarios described in the embodiments of the present application are for more clearly illustrating the technical solutions of the embodiments of the present application, and do not constitute a limitation on the technical solutions provided by the embodiments of the present application. Those of ordinary skill in the art can know that with the evolution of the network architecture and the emergence of new service scenarios, the technical solutions provided by the embodiments of the present application are equally applicable to similar technical problems.

[0192] In some scenarios of the embodiments of the present application Figure 1 the scenarios in the shown communication system are taken as examples for illustration. It should be noted that the solutions in the embodiments of the present application can also be applied to other mobile communication systems, and the corresponding names can also be replaced with the names of the corresponding functions in other mobile communication systems.

[0193] To facilitate the understanding of the embodiments of the present application, first Figure 1 the communication system shown in is taken as an example to detail the communication system applicable to the embodiments of the present application. Figure 1 The figure shows a schematic diagram of a communication system for the transmission method of reference signals applicable to the embodiments of the present application. Figure 1 This is a schematic diagram of the architecture of a communication system applicable to the transmission method of reference signals provided by the embodiments of the present application. As Figure 1 shown, the communication system includes a network device and a terminal device. Among them, the network device is used to send a demodulation reference signal to the terminal device on the first symbol. Among them, the first symbol is determined by the symbols occupied by the synchronization signal block, the system message, and the data channel respectively. The terminal device is used to receive the synchronization signal block and parse the system message to determine the first symbol, and to receive the demodulation reference signal from the network device on the first symbol.

[0194] Among them, the above network device is located on the network side of the above communication system and is a device with wireless transceiver functions or a chip or chip system that can be set in the device. The network device includes, but is not limited to: access points (APs) in a wireless fidelity (WiFi) system, such as home gateways, routers, servers, switches, bridges, etc., evolved Node B (eNB), radio network controller (RNC), Node B (NB), base station controller (BSC), base transceiver station (BTS), home base station (for example, home evolved Node B, or home Node B, HNB), baseband unit (BBU), wireless relay node, wireless backhaul node, transmission and reception point (TRP or transmission point, TP), etc. It can also be a 5G device, such as a gNB in a new radio (NR) system, or a transmission point (TRP or TP), one or a group of antenna panels (including multiple antenna panels) of a base station in a 5G system, or it can also be a network node that constitutes a gNB or a transmission point, such as a baseband unit (BBU), or a distributed unit (DU), a roadside unit (RSU) with base station functions, etc.

[0195] The above terminal device is a terminal with a wireless transceiver function for accessing the above communication system, or a chip or chip system that can be set in the terminal. The terminal device can also be referred to as a user device, access terminal, user unit, user station, mobile station, mobile terminal, remote station, remote terminal, mobile device, user terminal, terminal, wireless communication device, user agent or user device. The terminal device in the embodiments of the present application can be a mobile phone, a tablet computer (Pad), a computer with a wireless transceiver function, a virtual reality (VR) terminal device, an augmented reality (AR) terminal device, a wireless terminal in industrial control, a wireless terminal in self-driving, a wireless terminal in remote medical, a wireless terminal in smart grid, a wireless terminal in transportation safety, a wireless terminal in smart city, a wireless terminal in smart home, a vehicle-mounted terminal, an RSU with terminal functions, etc. The terminal device of the present application can also be an in-vehicle module, in-vehicle module group, in-vehicle component, in-vehicle chip or in-vehicle unit built in a vehicle as one or more components or units, and the vehicle can implement the reference signal transmission method provided by the present application through the built-in in-vehicle module, in-vehicle module group, in-vehicle component, in-vehicle chip or in-vehicle unit.

[0196] It should be noted that the reference signal transmission method provided in the embodiments of the present application can be used for Figure 1 any two nodes shown, such as between terminal devices, between network devices, and between a terminal device and a network device. For communication between terminal devices, if there is a network device, it is a scenario with network coverage; if there is no network device, it is a scenario without network coverage. In a scenario with network coverage, communication between terminal devices can be carried out using resources configured by the network device, and in a scenario without network coverage, communication between terminal devices can be carried out using pre-configured resources.

[0197] It should be understood that Figure 1 only a simplified schematic diagram for easy understanding is shown, and other network devices and / or other terminal devices may also be included in the communication system, Figure 1 which are not drawn in the figure.

[0198] Figure 2FIG. 0 is a schematic structural diagram of a communication device 200 that can be used to execute the reference signal transmission method provided in the embodiments of the present application. The communication device 200 may be a network device or a terminal device, or may be a chip applied to the network device or the terminal device, or other components having the functions of the network device or the terminal device. As Figure 2 shown, the communication device 200 may include a processor 201, a memory 202, and a transceiver 203. Among them, the processor 201 is coupled to the memory 202 and the transceiver 203, and may be connected through a communication bus, for example.

[0199] Next, the various components of the communication device 200 will be specifically introduced in conjunction with Figure 2 :

[0200] The processor 201 is the control center of the communication device 200, and may be a single processor or a collective term for multiple processing elements. For example, the processor 201 is one or more central processing units (CPUs), or may be an application specific integrated circuit (ASIC), or may be one or more integrated circuits configured to implement the embodiments of the present application, for example: one or more digital signal processors (DSPs), or one or more field programmable gate arrays (FPGAs).

[0201] Among them, the processor 201 may execute various functions of the communication device 200 by running or executing software programs stored in the memory 202 and calling data stored in the memory 202.

[0202] Exemplarily, if the communication device 200 is a network device, then referring to the following Figure 3 and Figure 42 , the processor 201 may be used to execute S301 and S4201.

[0203] Exemplarily, if the communication device 200 is a terminal device, then referring to the following Figure 3 and Figure 42 , the processor 201 may be used to parse the received synchronization signal block and system message to determine the first symbol.

[0204] It should be noted that the processor 201 may also execute the processing functions of the network device or the terminal device involved in various implementation manners of the following method embodiments. Specifically, reference may be made to the relevant descriptions of the following method embodiments, which will not be elaborated here.

[0205] In a specific implementation, as an example, the processor 201 may include one or more CPUs, such as Figure 2 CPU0 and CPU1 shown in

[0206] In a specific implementation, as an example, the communication device 200 may also include multiple processors, such as Figure 2 the processor 201 and the processor 204 shown in. Each of these processors may be a single-core processor (single-CPU) or a multi-core processor (multi-CPU). The processor here may refer to one or more communication devices, circuits, and / or processing cores for processing data (such as computer program instructions).

[0207] The memory 202 may be a read-only memory (ROM) or other types of static storage communication devices that can store static information and instructions, a random access memory (RAM) or other types of dynamic storage communication devices that can store information and instructions, or may also be an electrically erasable programmable read-only memory (EEPROM), a compact disc read-only memory (CD-ROM) or other optical disc storage, optical disc storage (including compact discs, laser discs, optical discs, digital versatile discs, Blu-ray discs, etc.), magnetic disk storage media or other magnetic storage communication devices, or any other medium that can be used to carry or store the desired program code in the form of instructions or data structures and can be accessed by a computer, but is not limited thereto. The memory 202 may exist independently or may be integrated with the processor 201.

[0208] Among them, the memory 202 is used to store the software program for executing the solution of this application and is controlled by the processor 201 to execute.

[0209] The transceiver 203 is used for communication with other communication devices. For example, if the communication device 200 is a terminal device, the transceiver 203 can be used for communication with a network device or with another terminal device. Another example is that if the communication device 200 is a network device, the transceiver 203 can be used for communication with a terminal device or with another network device. It should be understood that the transceiver 203 may include a receiver and a transmitter, where the receiver is used to implement the receiving function and the transmitter is used to implement the sending function.

[0210] Exemplarily, if the communication device 200 is a network device, then refer to the following Figure 3 and Figure 42, the transceiver 203 can be used to perform S302 and S303, or S4202 and S4203.

[0211] Exemplarily, if the communication device 200 is a terminal device, refer to the following Figure 3 and Figure 42 , the transceiver 203 can be used to perform functions such as receiving a synchronization signal block and a system message in S304 and S305, or S4204 and S4205, and receiving a demodulation reference signal on a determined first symbol.

[0212] It should be noted that the transceiver 203 can also perform the transmission function of the network device involved in various implementation manners of the following method embodiments, or the receiving function of the terminal device. Specifically, reference can be made to the relevant descriptions of the following method embodiments, which will not be elaborated here.

[0213] It should be noted that Figure 2 the structure of the communication device 200 shown in

[0214] does not constitute a limitation on the communication device. The actual communication device may include more or fewer components than shown in the figure, or combine certain components, or have different component arrangements. Figures 3 - 66 The following will specifically elaborate on the method for transmitting a reference signal provided in the embodiments of the present application in combination with

[0215] Figure 3 is a schematic flow chart of the method for transmitting a reference signal provided in the embodiments of the present application Figure 1 . The method for transmitting the reference signal can be applied to the communication between the network device and the terminal device shown in Figure 1 .

[0216] As shown in Figure 3 , the method for transmitting the reference signal includes the following steps:

[0217] S301, the network device determines a first symbol according to the symbols occupied by the synchronization signal block, the system message, and the data channel respectively.

[0218] That is to say, the first symbol is jointly determined by the symbols occupied by the synchronization signal block, the system message, and the data channel respectively, and the synchronization signal block, the system message, and the data channel are in one-to-one correspondence.

[0219] Specifically, the first symbol can be a symbol among the symbols occupied by the data channel that is not occupied by the synchronization signal block and the system message.

[0220] In a possible design method, the number of the first symbols can be one. Correspondingly, the above one first symbol is located before or after the symbol occupied by the synchronization signal block in the time domain.

[0221] Further, one of the above first symbols may be: the last symbol in the time domain before the symbol occupied by the synchronization signal block. Alternatively, optionally, one of the above first symbols may also be: the first symbol in the time domain after the symbol occupied by the synchronization signal block.

[0222] In another possible design method, the number of first symbols is two. Accordingly, one of the two first symbols is in the time domain before the symbol occupied by the synchronization signal block, and the other is in the time domain after the symbol occupied by the synchronization signal block. Alternatively, optionally, both of the two first symbols are in the time domain before the symbol occupied by the synchronization signal block, and the two first symbols are not consecutive. Or, both of the two first symbols are in the time domain after the symbol occupied by the synchronization signal block, and the two first symbols are not consecutive.

[0223] Further, both of the two first symbols are in the time domain before the symbol occupied by the synchronization signal block, and the two first symbols are not consecutive, which may include: the two first symbols may be: the first symbol and the last symbol in the time domain before the symbol occupied by the synchronization signal block, and the two first symbols are not consecutive.

[0224] Further, both of the two first symbols are in the time domain after the symbol occupied by the synchronization signal block, and the two first symbols are not consecutive, which may include: the two first symbols may be: the first symbol and the last symbol in the time domain after the symbol occupied by the synchronization signal block, and the two first symbols are not consecutive.

[0225] Next, taking the data channel as PDSCH and the system message as CORESET as an example, and combined with several scenarios, it is described in detail how to determine the first symbol, that is, the symbol occupied by DMRS.

[0226] Exemplarily, Figure 4 is a schematic diagram of Scenario 1 of the transmission method of the reference signal provided by the embodiment of the present application. As Figure 4As shown, the SSB and its corresponding PDSCH occupy the first half of the time slot, and the SSB occupies symbols 2 to 5, and the CORESET occupies 1 symbol, that is, symbol 0. In one possible implementation, the start symbol (S) of the PDSCH is symbol 0, that is, S = 0, and the symbol length (L) is 7 symbols, that is, L = 7. That is to say, when L = 7, the PDSCH and the CORESET jointly occupy symbol 0 in a frequency division multiplexing (FDM) manner. Alternatively, in another possible implementation, the start symbol of the PDSCH is symbol 1, that is, S = 1, and the symbol length is 6 symbols, that is, L = 6. That is to say, when L = 6, the PDSCH does not occupy symbol 0, and the CORESET occupies symbol 0. The embodiments of the present application do not make specific limitations on whether the PDSCH and the CORESET occupy the same symbol.

[0227] For Figure 4 Scenario 1 shown, the symbols not occupied by the SSB and the CORESET include symbol 1 and symbol 6. If the DMRS only needs to occupy 1 symbol, then as Figure 5 and Figure 6 shown, the DMRS can occupy symbol 1 or symbol 6, that is, the symbol occupied by the DMRS can be arbitrarily selected from the symbols not occupied by the SSB and the CORESET among the symbols occupied by the PDSCH. It is easy to understand that if the DMRS needs to occupy 2 symbols, then as Figure 7 shown, the DMRS needs to occupy symbol 1 and symbol 6.

[0228] Exemplarily, Figure 8 is a schematic diagram of Scenario 2 of the reference signal transmission method provided by the embodiments of the present application. As Figure 8As shown, the SSB and its corresponding PDSCH occupy the first half of the time slot, and the SSB occupies symbols 2 - 5. The CORESET occupies 2 symbols, namely symbols 0 and 1. In a possible implementation, the start symbol (S) of the PDSCH is symbol 0, i.e., S = 0, and the length of symbols (L) is 7 symbols, i.e., L = 7. That is to say, when L = 7, the PDSCH and the CORESET use frequency division multiplexing (FDM) to jointly occupy symbol 0. Alternatively, in another possible implementation, the start symbol of the PDSCH is symbol 1, i.e., S = 1, and the symbol length is 6 symbols, i.e., L = 6. That is to say, when L = 6, the PDSCH does not occupy symbol 0, the CORESET occupies symbol 0, and the PDSCH and the CORESET use frequency division multiplexing to jointly occupy symbol 1. The embodiments of the present application do not make specific limitations on whether the PDSCH and the CORESET occupy the same symbol.

[0229] For Figure 8 In the second scenario shown, the only symbol not occupied by the SSB and the CORESET is symbol 6. That is to say, the second scenario is only applicable to the case where the DMRS only needs to occupy 1 symbol. Then, as Figure 9 shown, the DMRS can only occupy symbol 6.

[0230] Exemplarily, Figure 10 is a schematic diagram of the third scenario of the reference signal transmission method provided by the embodiments of the present application. As Figure 10 shown, the SSB and its corresponding PDSCH occupy the second half of the time slot, and the SSB occupies symbols 9 - 12. The CORESET occupies 1 symbol, namely symbol 7. In a possible implementation, the start symbol (S) of the PDSCH is symbol 7, i.e., S = 7, and the length of symbols (L) is 7 symbols, i.e., L = 7. That is to say, when L = 7, the PDSCH and the CORESET use frequency division multiplexing (FDM) to share symbol 7. Alternatively, in another possible implementation, the start symbol of the PDSCH is symbol 8, i.e., S = 8, and the symbol length is 6 symbols, i.e., L = 6. That is to say, when L = 6, the PDSCH does not occupy symbol 7, and the CORESET occupies symbol 7. The embodiments of the present application do not make specific limitations on whether the PDSCH and the CORESET occupy the same symbol.

[0231] For Figure 10Scenario three shown in the figure. The symbols not occupied by SSB and CORESET include symbol 8 and symbol 13. If DMRS only needs to occupy 1 symbol, then as Figure 11 and Figure 12 shown, DMRS can occupy symbol 8 or symbol 13, that is, the symbol occupied by DMRS can be arbitrarily selected from the symbols not occupied by SSB and CORESET among the symbols occupied by PDSCH. It is easy to understand that if DMRS needs to occupy 2 symbols, then as Figure 13 shown, DMRS needs to occupy symbol 8 and symbol 13.

[0232] Exemplarily, Figure 14 is a schematic diagram of scenario four of the method for transmitting reference signals provided by an embodiment of the present application. As Figure 14 shown, SSB and its corresponding PDSCH occupy the second half of the time slot, and SSB occupies symbols 9 - 12, and CORESET occupies 2 symbols, that is, symbol 7 and symbol 8. In one possible implementation, the starting symbol of PDSCH is symbol 7, that is, S = 7, and the symbol length is 7 symbols, that is, L = 7. That is to say, when L = 7, PDSCH and CORESET use frequency division multiplexing to jointly occupy symbols 7 and 8. Or, in another possible implementation, the starting symbol of PDSCH is symbol 8, that is, S = 8, and the symbol length is 6 symbols, that is, L = 6. That is to say, when L = 6, PDSCH does not occupy symbol 7, CORESET occupies symbol 7, and PDSCH and CORESET use frequency division multiplexing to jointly occupy symbol 8. The embodiments of the present application do not make specific limitations on whether PDSCH and CORESET occupy the same symbol.

[0233] For Figure 14 the shown scenario four, the only symbol not occupied by SSB and CORESET is symbol 13, that is, scenario four is only applicable to the case where DMRS only needs to occupy 1 symbol, then as Figure 15 shown, DMRS can only occupy symbol 13.

[0234] Table 1 is a symbol configuration table of various DMRSs involved in the above scenarios one to four. Exemplarily, for Figure 4 the shown scenario one, Figure 5 the shown DMRS configuration can be any one of the DMRS configurations corresponding to indices 2 to 3 in Table 1, Figure 6 the shown DMRS configuration can be any one of the DMRS configurations corresponding to indices 11 to 12 in Table 1, Figure 7 the shown DMRS configuration can be any one of the DMRS configurations corresponding to indices 4 to 5 in Table 1.

[0235] Exemplarily, forFigure 8 Scenario two shown Figure 9 The DMRS configuration shown can be any one of the DMRS configurations corresponding to indices 11 to 12 in Table 1.

[0236] Exemplarily, for Figure 10 Scenario three shown Figure 11 The DMRS configuration shown can be any one of the DMRS configurations corresponding to indices 6 to 7 in Table 1, Figure 12 The DMRS configuration shown can be any one of the DMRS configurations corresponding to indices 14 to 15 in Table 1, Figure 13 The DMRS configuration shown can be any one of the DMRS configurations corresponding to indices 8 to 9 in Table 1.

[0237] Exemplarily, for Figure 14 Scenario four shown Figure 15 The DMRS configuration shown can be any one of the DMRS configurations corresponding to indices 14 to 15 in Table 1.

[0238] It should be noted that for the above Scenarios one to four, the above SSB and its corresponding PDSCH occupy the first half of the time slot or the second half of the time slot, or can also be some symbols in the first half of the time slot or the second half of the time slot. For example, as shown in Table 1, for index 0, the SSB and its corresponding PDSCH occupy a total of 5 symbols from symbol 1 to symbol 5, and do not occupy symbol 0. Another example, as shown in Table 1, for index 10, the SSB and its corresponding PDSCH occupy a total of 5 symbols from symbol 2 to symbol 6, and do not occupy symbol 0 and symbol 1. Another example, as shown in Table 1, for index 13, the SSB and its corresponding PDSCH occupy a total of 5 symbols from symbol 9 to symbol 13, and do not occupy symbol 7 and symbol 8. It is easy to understand that the symbols not occupied by the SSB and its corresponding PDSCH can be occupied by the CORESET, that is, in this case, the PDSCH and the CORESET can adopt a time-division multiplexing method to occupy different symbols respectively.

[0239] Table 1

[0240] Index PDSCH Mapping Type S L Symbols Occupied by DMRS Slot Length 0 Type B 1 5 1 6 1 Type B 0 6 1 7 2 Type B 1 6 1 7 3 Type B 0 7 1 7 4 Type B 1 6 {1,6} 7 5 Type B 0 7 {1,6} 7 6 Type B 8 6 8 7 7 Type B 7 7 8 7 8 Type B 8 6 {8,13} 7 9 Type B 7 7 {8,13} 7 10 Type B 2 5 6 7 11 Type B 1 6 6 7 12 Type B 0 7 6 7 13 Type B 9 5 13 7 14 Type B 8 6 13 7 15 Type B 7 7 13 7

[0241] Exemplarily, Figure 16 It is a schematic diagram of Scenario five of the reference signal transmission method provided by the embodiments of the present application. As Figure 16As shown, the SSB and its corresponding PDSCH occupy the last 7 or 8 symbols in a time slot, i.e., symbols 7 - 13, or symbols 6 - 13, and the SSB occupies symbols 8 - 11, the CORESET occupies 1 symbol, i.e., symbol 6. In a possible implementation, the starting symbol of the PDSCH is symbol 6, i.e., S = 6, and the symbol length is 8 symbols, i.e., L = 8. That is to say, when L = 8, the PDSCH and the CORESET use frequency division multiplexing to jointly occupy symbol 6. Or, in another possible implementation, the starting symbol of the PDSCH is symbol 7, i.e., S = 7, and the symbol length is 7 symbols, i.e., L = 7. That is to say, when L = 7, the PDSCH does not occupy symbol 6, and the CORESET occupies symbol 6. The embodiments of the present application do not make specific limitations on whether the PDSCH and the CORESET occupy the same symbol.

[0242] For Figure 16 Scenario 5 shown, the symbols not occupied by the SSB and the CORESET include symbol 7, symbol 12, and symbol 13. If the DMRS only needs to occupy 1 symbol, then as Figures 17 - 19 shown, the DMRS can occupy symbol 7 or symbol 12 or symbol 13, that is, the symbol occupied by the DMRS can be arbitrarily selected from the symbols not occupied by the SSB and the CORESET among the symbols occupied by the PDSCH. It is easy to understand that if the DMRS needs to occupy 2 symbols, then as Figures 20 - 21 shown, the DMRS can occupy symbol 7 and symbol 12, or occupy symbol 7 and symbol 13, that is, for the 2 symbols occupied by the DMRS, one is before the symbol occupied by the SSB and the other is after the symbol occupied by the SSB.

[0243] Exemplarily, Figure 22 is a schematic diagram of Scenario 6 of the reference signal transmission method provided by the embodiments of the present application. As Figure 22 shown, the SSB and its corresponding PDSCH occupy the last 7 or 8 symbols in a time slot, i.e., symbols 7 - 13, or symbols 6 - 13, and the SSB occupies symbols 8 - 11, the CORESET occupies 2 symbols, i.e., symbol 6 and symbol 7. In a possible implementation, the starting symbol of the PDSCH is symbol 6, i.e., S = 6, and the symbol length is 8 symbols, i.e., L = 8. That is to say, when L = 8, the PDSCH and the CORESET use frequency division multiplexing to jointly occupy symbol 6. Or, in another possible implementation, the starting symbol of the PDSCH is symbol 7, i.e., S = 7, and the symbol length is 7 symbols, i.e., L = 7. That is to say, when L = 7, the PDSCH does not occupy symbol 6, and the CORESET occupies symbol 6. The embodiments of the present application do not make specific limitations on whether the PDSCH and the CORESET occupy the same symbol.

[0244] For Figure 22 For scenario six shown in the figure, the symbols not occupied by SSB and CORESET are only symbol 12 and symbol 13, and symbol 12 and symbol 13 are consecutive. That is, scenario six is only applicable to the case where DMRS only needs to occupy 1 symbol. Then, as Figures 23 to 24 shown in the figure, DMRS can occupy symbol 12 or symbol 13.

[0245] Table 2 is a symbol configuration table of various DMRSs involved in the above scenarios five to six. Exemplarily, for Figure 16 scenario five shown in the figure, Figure 17 the DMRS configuration shown can be any one of the DMRS configurations corresponding to indices 0 to 1 in Table 2, Figure 18 the DMRS configuration shown can be any one of the DMRS configurations corresponding to indices 2 to 3 in Table 2, Figure 19 the DMRS configuration shown can be any one of the DMRS configurations corresponding to indices 4 to 5 in Table 2. Exemplarily, for Figure 16 scenario five shown in the figure, Figure 20 the DMRS configuration shown can be any one of the DMRS configurations corresponding to indices 6 to 7 in Table 2, Figure 21 the DMRS configuration shown can be any one of the DMRS configurations corresponding to indices 8 to 9 in Table 2.

[0246] Exemplarily, for Figure 22 scenario six shown in the figure, Figure 23 the DMRS configuration shown can be any one of the DMRS configurations corresponding to indices 2 to 3 in Table 2, Figure 24 the DMRS configuration shown can be any one of the DMRS configurations corresponding to indices 4 to 5 in Table 2.

[0247] Table 2

[0248] Index PDSCH Mapping Type S L Symbols Occupied by DMRS Slot Length 0 Type B 7 7 7 8 1 Type B 6 8 7 8 2 Type B 7 7 12 8 3 Type B 6 8 12 8 4 Type B 7 7 13 8 5 Type B 6 8 13 8 6 Type B 7 7 {7,12} 8 7 Type B 6 8 {7,12} 8 8 Type B 7 7 {7,13} 8 9 Type B 6 8 {7,13} 8

[0249] Exemplarily, Figure 25 is a schematic diagram of scenario seven of the reference signal transmission method provided by an embodiment of the present application. As Figure 25As shown, the SSB and its corresponding PDSCH occupy the first 9 or 10 symbols in a time slot, that is, symbols 1 - symbol 9, or symbols 0 - symbol 9, and the SSB occupies symbols 2 - symbol 5, the CORESET occupies 1 symbol, that is, symbol 0. In a possible implementation, the starting symbol of the PDSCH is symbol 0, that is, S = 0, and the symbol length is 10 symbols, that is, L = 10. That is to say, when L = 10, the PDSCH and the CORESET jointly occupy symbol 0 in a frequency division multiplexing manner. Or, in another possible implementation, the starting symbol of the PDSCH is symbol 1, that is, S = 1, and the symbol length is 9 symbols, that is, L = 9. That is to say, when L = 9, the PDSCH does not occupy symbol 0, and the CORESET occupies symbol 0. The embodiments of the present application do not make specific limitations on whether the PDSCH and the CORESET occupy the same symbol.

[0250] For Figure 25 Scenario 7 shown, the symbols not occupied by the SSB and the CORESET include symbol 1, symbols 6 - symbol 9. If the DMRS only needs to occupy 1 symbol, then as Figures 26 - 30 shown, the DMRS can occupy any one of symbol 1, symbols 6 - symbol 9, that is, the symbol occupied by the DMRS can be selected from the symbols not occupied by the SSB and the CORESET among the symbols occupied by the PDSCH. It is easy to understand that if the DMRS needs to occupy 2 symbols, then as Figures 31 - 34 shown, the DMRS can occupy symbol 1 and symbol 6, or occupy symbol 1 and symbol 7, or occupy symbol 1 and symbol 8, or occupy symbol 1 and symbol 9, that is, for the 2 symbols occupied by the DMRS, one is before the symbol occupied by the SSB and one is after the symbol occupied by the SSB. Or, optionally, if the DMRS needs to occupy 2 symbols, then as Figures 35 - 37 shown, the DMRS can occupy symbol 6 and symbol 8, or occupy symbol 6 and symbol 9, or occupy symbol 7 and symbol 9, that is, both of the 2 symbols occupied by the DMRS can be after the symbol occupied by the SSB, and the 2 symbols are not consecutive.

[0251] Exemplarily, Figure 38 is a schematic diagram of Scenario 8 of the reference signal transmission method provided by the embodiments of the present application. As Figure 38As shown, the SSB and its corresponding PDSCH occupy the first 9 or 10 symbols in a time slot, i.e., symbols 1 - symbol 9, or symbols 0 - symbol 9, and the SSB occupies symbols 2 - symbol 5, the CORESET occupies 2 symbols, i.e., symbols 0 and symbol 1. In a possible implementation, the starting symbol of the PDSCH is symbol 0, i.e., S = 0, and the symbol length is 10 symbols, i.e., L = 10. That is to say, when L = 10, the PDSCH and the CORESET use frequency division multiplexing to jointly occupy symbols 0 and 1. Or, in another possible implementation, the starting symbol of the PDSCH is symbol 1, i.e., S = 1, and the symbol length is 9 symbols, i.e., L = 9. That is to say, when L = 9, the PDSCH does not occupy symbol 0, the CORESET occupies symbol 0, and the PDSCH and the CORESET jointly occupy symbol 1. The embodiments of the present application do not make specific limitations on whether the PDSCH occupies the same symbol as the CORESET.

[0252] For Figure 38 Scenario eight shown, the symbols not occupied by the SSB and the CORESET include symbols 6 - symbol 9, then as Figures 39 - 41 shown, the DMRS can occupy symbols 6 and 8, or occupy symbols 6 and 9, or occupy symbols 7 and 9, that is, the 2 symbols occupied by the DMRS are both after the symbols occupied by the SSB, and the 2 symbols are not consecutive.

[0253] Table 3 is the symbol configuration table of various DMRSs involved in Scenarios seven to eight above. Exemplarily, for Figure 25 Scenario seven shown, Figures 26 - 30 the DMRS configuration shown can be the DMRS configuration corresponding to index 2 or index 5 in Table 3, Figures 31 - 34 、 Figure 36 the DMRS configuration shown can be the DMRS configuration corresponding to index 15 or index 18 in Table 3.

[0254] Exemplarily, for Figure 38 Scenario eight shown, in view of the fact that the CORESET has occupied symbols 0 and 1, Figure 40 the DMRS configuration shown can be the configuration in the DMRS configuration corresponding to index 15 or index 18 in Table 3 that does not include symbol 1.

[0255] Table 3

[0256]

[0257] It should be noted that in view of the fact that the DMRS needs to occupy the symbols after the symbols occupied by the CORESET, in various configurations in Table 3, the configuration where the DMRS occupies symbol 1 is only applicable to Scenario seven and not applicable to Scenario eight. In addition,Figure 25 and Figure 38 The scenarios shown above are only illustrated by taking time slots with a symbol length of 10 as an example. Table 3 also includes time slots with other symbol lengths, which will not be elaborated here.

[0258] In the embodiments of this application, when there are two first symbols, in order to improve the accuracy of PDSCH channel estimation as much as possible, two symbols that are not occupied by SSB and CORESET and have a relatively large symbol deviation from each other can be preferentially selected from the symbols occupied by PDSCH as the first symbols. For example, one first symbol is before the symbol occupied by SSB, and the other first symbol is after the symbol occupied by SSB. Another example is that the two first symbols are respectively the first symbol and the last symbol in the PDSCH symbols after the symbol occupied by SSB. Still another example is that the two first symbols are respectively the first symbol and the last symbol in the PDSCH symbols before the symbol occupied by SSB. In other words, two symbols with a relatively small symbol deviation from each other are generally not selected as the first symbols. For example, for the scenarios of index 15 or index 18 in Table 3, the two configurations of {6,8} and {7,9} can also be selected. However, since the symbol deviation between the two symbols in these two configurations is relatively small, only 2 symbols, the accuracy of the PDSCH channel estimation result is poor. Therefore, the symbols in these two configurations are not determined as the first symbols and are not included in Table 3.

[0259] Similarly, when there is one first symbol, in order to improve the accuracy of PDSCH channel estimation as much as possible, a symbol that is not occupied by SSB and CORESET and is located in the middle of the symbols occupied by PDSCH can be preferentially selected from the symbols occupied by PDSCH as the first symbol. For example, the last symbol before the symbol occupied by SSB can be preferentially selected, or the first symbol after the symbol occupied by SSB can be preferentially selected as the first symbol.

[0260] S302, The network device sends the synchronization signal block, system message, and data channel to the terminal device on the symbols occupied by the synchronization signal block, system message, and data channel respectively.

[0261] S303, The network device sends the demodulation reference signal to the terminal device on the first symbol.

[0262] Exemplarily, the network device can send the SSB, CORESET, DMRS, and PDSCH to the terminal device on the downlink (DL) on the symbols occupied by the SSB, CORESET, DMRS, and PDSCH determined in S301. That is to say, the SSB, CORESET, DMRS, and PDSCH are sent in sequence according to the symbol order they occupy.

[0263] S304, The terminal device receives the synchronization signal block and parses the system message to determine the first symbol.

[0264] Exemplarily, the terminal device can receive and parse the SSB, obtain the symbols occupied by the system message, and receive and parse the system message on the symbols occupied by the system message, so as to obtain the position of the first symbol and the demodulation parameters of the data channel, such as the modulation & coding scheme (MCS). Among them, the position of the first symbol can refer to Table 1 - Table 3 above, which will not be elaborated here.

[0265] S305, The terminal device receives the demodulation reference signal from the network device on the first symbol.

[0266] Exemplarily, after obtaining the position of the first symbol, the terminal device can receive the DMRS on the first symbol and perform channel estimation on the data channel. Then, the terminal device performs demodulation and decoding on the data channel based on the channel estimation result and the demodulation parameters of the data channel, so as to obtain the user data.

[0267] In the transmission method of the reference signal provided by the embodiments of the present application, the network device can determine the first symbol according to the symbols occupied by the synchronization signal block, the system message, and the data channel respectively, and send the DMRS to the terminal device on the first symbol, which can solve the problem that when the symbols occupied by the data channel, since the symbols that could originally be occupied by the DMRS have all been occupied by the synchronization signal block and the system message, resulting in the inability to transmit the DMRS, and can improve the reliability of transmitting the DMRS.

[0268] Figures 3 - 41 The shown transmission methods of the reference signal all transmit the demodulation reference signal in a time - division multiplexing manner. In the embodiments of the present application, when the symbols occupied by the data channel have all been occupied by the SSB, the demodulation reference signal can also be transmitted in a frequency - division multiplexing manner, that is, the DMRS can occupy the sub - carriers not occupied by the SSB on some of the symbols occupied by the SSB for transmission.

[0269] Figure 42 It is a schematic flow chart of the transmission method of the reference signal provided by the embodiments of the present application Figure 2 。This transmission method of the reference signal can be applicable to Figure 1 the communication between the network device and the terminal device shown. As Figure 42 shown, this transmission method of the reference signal includes the following steps:

[0270] S4201, The network device determines a part of the symbols occupied by the synchronization signal block as the first symbol.

[0271] Among them, the synchronization signal block and the data channel occupy the same symbol.

[0272] In a possible design method, the number of the first symbols can be one. Accordingly, any one of the symbols occupied by the synchronization signal block can be the above-mentioned one first symbol. Among them, the symbols occupied by the synchronization signal block are usually 4 consecutive symbols.

[0273] Furthermore, the above-mentioned one first symbol can be: the second symbol or the third symbol among the symbols occupied by the synchronization signal block.

[0274] In another possible design method, the number of the first symbols is two. Accordingly, the above-mentioned two first symbols can be: any two non-consecutive symbols among the symbols occupied by the synchronization signal block, such as the first symbol and the third symbol, or the second symbol and the fourth symbol, or the first symbol and the fourth symbol.

[0275] Furthermore, the above-mentioned two first symbols can be: the first symbol and the last symbol among the symbols occupied by the synchronization signal block.

[0276] In a possible design method, the demodulation reference signal and the synchronization signal block can adopt a frequency division multiplexing method and jointly occupy the first symbol. Among them, the synchronization signal block usually occupies a part of the RBs near the carrier frequency, and the demodulation reference signal can occupy the subcarriers other than the subcarriers occupied by the synchronization signal block, such as the subcarriers with subcarrier indices greater than and / or less than the subcarrier indices occupied by the synchronization signal block.

[0277] The following takes the data channel as PDSCH and the system message as CORESET as an example, and combines several scenarios to detail how to determine the first symbol, that is, the symbol occupied by the DMRS.

[0278] Exemplarily, Figure 43 is a schematic diagram of Scenario 9 of the reference signal transmission method provided by the embodiments of the present application. As Figure 43 shown, the SSB and its corresponding PDSCH jointly occupy symbols 2 - 5, and the CORESET occupies 2 symbols, namely symbol 0 and symbol 1. Among them, the starting symbol of the PDSCH is symbol 2, that is, S = 2, and the symbol length is 4 symbols, that is, L = 4.

[0279] For Figure 43 the shown Scenario 9, if the DMRS only needs to occupy 1 symbol, then as Figures 44 - 47 shown, the DMRS can occupy any one of symbols 2 - 5. If the DMRS needs to occupy 2 symbols, then as Figures 48 - 50 shown, the DMRS can occupy symbol 2 and symbol 4, or occupy symbol 2 and symbol 5, or occupy symbol 3 and symbol 5.

[0280] Exemplarily, Figure 51 is a schematic diagram of Scenario 10 of the reference signal transmission method provided by an embodiment of the present application. As Figure 51 shown, the SSB and its corresponding PDSCH jointly occupy Symbols 8 - 11, and the CORESET occupies 1 symbol, i.e., Symbol 7. Among them, the starting symbol of the PDSCH is Symbol 8, i.e., S = 8, and the symbol length is 4 symbols, i.e., L = 4.

[0281] For Figure 51 the Scenario 10 shown, if the DMRS only needs to occupy 1 symbol, then as Figures 52 - 55 shown, the DMRS can occupy any one of Symbols 8 - 11. If the DMRS needs to occupy 2 symbols, then as Figures 56 - 58 shown, the DMRS can occupy Symbol 8 and Symbol 10, or occupy Symbol 8 and Symbol 11, or occupy Symbol 9 and Symbol 11.

[0282] Exemplarily, Figure 59 is a schematic diagram of Scenario 11 of the reference signal transmission method provided by an embodiment of the present application. As Figure 59 shown, the SSB and its corresponding PDSCH jointly occupy Symbols 9 - 12, and the CORESET occupies 2 symbols, i.e., Symbol 7 and Symbol 8. Among them, the starting symbol of the PDSCH is Symbol 9, i.e., S = 9, and the symbol length is 4 symbols, i.e., L = 4.

[0283] For Figure 59 the Scenario 11 shown, if the DMRS only needs to occupy 1 symbol, then as Figures 60 - 63 shown, the DMRS can occupy any one of Symbols 9 - 12. If the DMRS needs to occupy 2 symbols, then as Figures 64 - 66 shown, the DMRS can occupy Symbol 9 and Symbol 11, or occupy Symbol 9 and Symbol 12, or occupy Symbol 10 and Symbol 12.

[0284] S4202. The network device sends a synchronization signal block, a system message, and a data channel to the terminal device on the symbols occupied by the synchronization signal block, the system message, and the data channel respectively. The specific implementation can refer to S302 and will not be elaborated here.

[0285] S4203. The network device sends a demodulation reference signal to the terminal device on the first symbol.

[0286] It should be noted that in S303, since the symbols occupied by the first symbol, CORESET, and SSB are time-division multiplexed, the demodulation reference signal, CORESET, and SSB are transmitted on different symbols, that is, the demodulation reference signal, CORESET, and SSB are not transmitted simultaneously. In S4203, the first symbol is part of the symbols occupied by SSB, and the demodulation reference signal needs to be transmitted simultaneously with part of the content in SSB on different subcarriers of the same symbol.

[0287] Exemplarily, assume that the synchronization signal block and the data channel occupy symbols 2 to 5, and are used to transmit the primary synchronization signal (PSS), the first physical broadcast channel (PBCH), the secondary synchronization signal (SSS), and the second PBCH in sequence. Then the demodulation reference signal is transmitted together with the PSS on symbol 2 and together with the second PBCH on symbol 5.

[0288] S4204. The terminal device receives the synchronization signal block and parses the system message to determine the first symbol.

[0289] S4205. The terminal device receives the demodulation reference signal from the network device on the first symbol.

[0290] The implementation manners of S4204 - S4205 can refer to S304 - S305, which will not be elaborated here.

[0291] For the transmission method of the reference signal provided by the embodiments of the present application, when the data channel and the synchronization signal block occupy the same symbol, the network device can determine the part of the symbols occupied by the synchronization signal block as the first symbol, and transmit the demodulation reference signal and the synchronization signal block in a frequency-division multiplexing manner on the first symbol, which can solve the problem that all the symbols occupied by the data channel have been occupied by the synchronization signal block, resulting in no complete symbol available for transmitting the DMRS, and further resulting in the inability to transmit the DMRS, and can improve the reliability of transmitting the DMRS.

[0292] The above combines Figures 3 - 66 and details the transmission method of the reference signal provided by the embodiments of the present application. The following combines Figure 67 and details the communication device provided by the embodiments of the present application.

[0293] Figure 67 is the structural schematic Figure 2 of the communication device provided by the embodiments of the present application. This communication device is applicable to Figure 1 the communication system shown in Figure 3The functions of the network device in the method for transmitting the reference signal shown. For ease of explanation, Figure 67 only the main components of the communication device are shown.

[0294] As Figure 67 shown, the communication device 6700 includes: a processing module 6701 and a transceiver module 6702.

[0295] Among them, the processing module 6701 is used to determine the first symbol according to the symbols occupied by the synchronization signal block, the system message, and the data channel respectively. The transceiver module 6702 is used to send the demodulation reference signal to the terminal device on the first symbol.

[0296] Specifically, the first symbol may be the symbol among the symbols occupied by the data channel that is not occupied by the synchronization signal block and the system message.

[0297] In a possible design, the number of the first symbols may be one. Correspondingly, the above-mentioned one first symbol is located before or after the symbol occupied by the synchronization signal block in the time domain.

[0298] Furthermore, the above-mentioned one first symbol may be: the last symbol located before the symbol occupied by the synchronization signal block in the time domain. Or, optionally, the above-mentioned one first symbol may also be: the first symbol located after the symbol occupied by the synchronization signal block in the time domain.

[0299] In another possible design, the number of the first symbols is two. Correspondingly, one of the above-mentioned two first symbols is located before the symbol occupied by the synchronization signal block in the time domain, and the other is located after the symbol occupied by the synchronization signal block in the time domain. Or, optionally, the above-mentioned two first symbols are both located before the symbol occupied by the synchronization signal block in the time domain, and the above-mentioned two first symbols are not continuous. Or, the above-mentioned two first symbols are both located after the symbol occupied by the synchronization signal block in the time domain, and the above-mentioned two first symbols are not continuous.

[0300] Furthermore, the above-mentioned two first symbols are both located before the symbol occupied by the synchronization signal block in the time domain, and the above-mentioned two first symbols are not continuous, which may include: the above-mentioned two first symbols may be: the first symbol and the last symbol located before the symbol occupied by the synchronization signal block in the time domain, and the above-mentioned two first symbols are not continuous.

[0301] Furthermore, the above-mentioned two first symbols are both located after the symbol occupied by the synchronization signal block in the time domain, and the above-mentioned two first symbols are not continuous, which may include: the above-mentioned two first symbols may be: the first symbol and the last symbol located after the symbol occupied by the synchronization signal block in the time domain, and the above-mentioned two first symbols are not continuous.

[0302] Optionally, the communication device 6700 may further include a storage module ( Figure 67 not shown in the figure), which stores programs or instructions. When the processing module 6701 executes the programs or instructions, the communication device 6700 can perform the functions of the network device in the Figure 3 shown reference signal transmission method.

[0303] It should be noted that the communication device 6700 may be a network device, or a chip or chip system disposed in the network device. This application does not make any limitation thereto.

[0304] The technical effects of the communication device 6700 may refer to the technical effects of the Figure 3 shown reference signal transmission method, which will not be elaborated herein.

[0305] Optionally, the communication device 6700 may also be applicable to the Figure 1 shown communication system and perform the functions of the terminal device in the Figure 3 shown reference signal transmission method.

[0306] Among them, the transceiver module 6702 is used to receive the synchronization signal block and the system message. The processing module 6701 is used to determine the first symbol according to the synchronization signal block and the system message. The transceiver module 6702 is further used to receive the demodulation reference signal from the network device on the first symbol.

[0307] Specifically, the first symbol may be a symbol among the symbols occupied by the data channel that is not occupied by the synchronization signal block and the system message.

[0308] In a possible design, the number of the first symbols may be one. Correspondingly, the above one first symbol is located before or after the symbol occupied by the synchronization signal block in the time domain.

[0309] Furthermore, the above one first symbol may be: the last symbol located before the symbol occupied by the synchronization signal block in the time domain. Or, optionally, the above one first symbol may also be: the first symbol located after the symbol occupied by the synchronization signal block in the time domain.

[0310] In another possible design, the number of the first symbols is two. Correspondingly, one of the above two first symbols is located before the symbol occupied by the synchronization signal block in the time domain, and the other is located after the symbol occupied by the synchronization signal block in the time domain. Or, optionally, both of the above two first symbols are located before the symbol occupied by the synchronization signal block in the time domain, and the above two first symbols are not consecutive. Or, the above two first symbols are both located after the symbol occupied by the synchronization signal block in the time domain, and the above two first symbols are not consecutive.

[0311] Further, both of the above two first symbols are located before the symbols occupied by the synchronization signal block in the time domain, and the above two first symbols are not consecutive, which may include: the above two first symbols may be: the first symbol and the last symbol located before the symbols occupied by the synchronization signal block in the time domain, and the above two first symbols are not consecutive.

[0312] Further, both of the above two first symbols are located after the symbols occupied by the synchronization signal block in the time domain, and the above two first symbols are not consecutive, which may include: the above two first symbols may be: the first symbol and the last symbol located after the symbols occupied by the synchronization signal block in the time domain, and the above two first symbols are not consecutive.

[0313] Optionally, the communication device 6700 may further include a storage module ( Figure 67 not shown in the figure), and the storage module stores programs or instructions. When the processing module 6701 executes the programs or instructions, the communication device 6700 can perform Figure 3 the functions of the terminal device in the reference signal transmission method shown.

[0314] It should be noted that the communication device 6700 may be a terminal device, or a chip or chip system disposed in the terminal device, and the present application does not make any limitation thereto.

[0315] The technical effects of the communication device 6700 may refer to Figure 3 the technical effects of the reference signal transmission method shown, which will not be elaborated here.

[0316] In another possible design, the communication device 6700 is applicable to Figure 1 the communication system shown, and performs Figure 42 the functions of the network device in the reference signal transmission method shown.

[0317] Among them, the processing module 6701 is configured to determine some symbols in the symbols occupied by the synchronization signal block as the first symbols. Among them, the synchronization signal block occupies the same symbols as the data channel. The transceiver module 6702 is configured to send a demodulation reference signal to the terminal device on the first symbols.

[0318] In a possible design, the number of the first symbols may be one. Correspondingly, the above one first symbol may be any one of the symbols occupied by the synchronization signal block. Among them, the symbols occupied by the synchronization signal block are usually 4 consecutive symbols.

[0319] Further, the above one first symbol may be: the second symbol or the third symbol in the symbols occupied by the synchronization signal block.

[0320] In another possible design, the number of the first symbols is two. Accordingly, the above two first symbols may be any two non-consecutive symbols among the symbols occupied by the synchronization signal block, such as the first symbol and the third symbol, or the second symbol and the fourth symbol, or the first symbol and the fourth symbol.

[0321] Further, the above two first symbols may be the first symbol and the last symbol among the symbols occupied by the synchronization signal block.

[0322] In a possible design, the demodulation reference signal and the synchronization signal block may adopt a frequency division multiplexing manner and jointly occupy the first symbol. Among them, the synchronization signal block usually occupies a part of the RBs near the carrier frequency, and the demodulation reference signal may occupy other subcarriers outside the subcarriers occupied by the synchronization signal block, such as subcarriers with subcarrier indices greater than and / or less than the subcarrier indices occupied by the synchronization signal block.

[0323] Optionally, the communication device 6700 may further include a storage module ( Figure 67 not shown in the figure), and the storage module stores programs or instructions. When the processing module 6701 executes the programs or instructions, the communication device 6700 can perform Figure 42 the functions of the network device in the reference signal transmission method shown.

[0324] It should be noted that the communication device 6700 may be a network device, or a chip or a chip system disposed in the network device, and the present application does not make any limitation thereto.

[0325] The technical effects of the communication device 6700 may refer to Figure 42 the technical effects of the reference signal transmission method shown, and will not be elaborated here.

[0326] Optionally, the communication device 6700 may also be applicable to Figure 1 the communication system shown, and perform Figure 42 the functions of the terminal device in the reference signal transmission method shown.

[0327] Among them, the transceiver module 6702 is used to receive the synchronization signal block and the system message. The processing module 6701 is used to determine the first symbol according to the synchronization signal block and the system message. The first symbol is a part of the symbols occupied by the synchronization signal block, and the synchronization signal block and the data channel occupy the same symbols. The transceiver module 6702 is further used to receive the demodulation reference signal from the network device on the first symbol.

[0328] In a possible design, the number of the first symbols may be one. Accordingly, the above one first symbol may be any one of the symbols occupied by the synchronization signal block. Among them, the symbols occupied by the synchronization signal block are usually 4 consecutive symbols.

[0329] Further, one of the above first symbols may be: the second symbol or the third symbol among the symbols occupied by the synchronization signal block.

[0330] In another possible design, the number of first symbols is two. Accordingly, the two above-mentioned first symbols may be: any two non-consecutive symbols among the symbols occupied by the synchronization signal block, such as the first symbol and the third symbol, or the second symbol and the fourth symbol, or the first symbol and the fourth symbol.

[0331] Further, the two above-mentioned first symbols may be: the first symbol and the last symbol among the symbols occupied by the synchronization signal block.

[0332] In a possible design, the demodulation reference signal and the synchronization signal block may adopt a frequency division multiplexing method and jointly occupy the first symbol. Among them, the synchronization signal block usually occupies a part of the RBs near the carrier frequency, and the demodulation reference signal may occupy the subcarriers other than those occupied by the synchronization signal block, such as subcarriers with subcarrier indices greater than and / or less than the subcarrier indices occupied by the synchronization signal block.

[0333] Optionally, the communication device 6700 may further include a storage module ( Figure 67 not shown in the figure), and the storage module stores programs or instructions. When the processing module 6701 executes the program or instructions, the communication device 6700 can execute Figure 42 the functions of the terminal device in the reference signal transmission method shown.

[0334] It should be noted that the communication device 6700 may be a terminal device, or a chip or a chip system disposed in the terminal device, and the present application does not limit this.

[0335] The technical effects of the communication device 6700 may refer to Figure 42 the technical effects of the reference signal transmission method shown, and will not be elaborated here.

[0336] The embodiments of the present application provide a chip system. The chip system includes a processor and an input / output port. The processor is used to implement the processing functions involved in the above method embodiments, and the input / output port is used to implement the transceiver functions involved in the above method embodiments.

[0337] In a possible design, the chip system further includes a memory, and the memory is used to store program instructions and data for implementing the functions involved in the above method embodiments.

[0338] The chip system may be composed of chips, or may include chips and other discrete devices.

[0339] An embodiment of the present application provides a computer-readable storage medium, including: computer instructions are stored in the computer-readable storage medium; when the computer instructions run on a computer, the computer is caused to execute the reference signal transmission method described in the foregoing method embodiment.

[0340] An embodiment of the present application provides a computer program product containing instructions, including a computer program or instructions, when the computer program or instructions run on a computer, the computer is caused to execute the reference signal transmission method described in the foregoing method embodiment.

[0341] It should be understood that the processor in the embodiment of the present application may be a central processing unit (CPU), and the processor may also be other general-purpose processors, digital signal processors (DSPs), application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor or the processor may also be any conventional processor, etc.

[0342] It should also be understood that the memory in the embodiments of the present application may be a volatile memory or a non-volatile memory, or may include both volatile and non-volatile memories. Among them, the non-volatile memory may be a read-only memory (ROM), a programmable ROM (PROM), an erasable PROM (EPROM), an electrically erasable PROM (EEPROM), or a flash memory. The volatile memory may be a random access memory (RAM), which is used as an external cache. By way of example but not limitation, many forms of random access memory (RAM) are available, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchlink DRAM (SLDRAM), and direct rambus RAM (DR RAM).

[0343] The above embodiments can be implemented in whole or in part by software, hardware (such as circuits), firmware, or any combination thereof. When implemented using software, the above embodiments can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions or computer programs. When the computer instructions or computer programs are loaded or executed on a computer, the processes or functions described in the embodiments of the present application are generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center by wired (such as infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server or data center that contains one or more collections of available media. The available media can be magnetic media (such as floppy disks, hard disks, magnetic tapes), optical media (such as DVDs), or semiconductor media. The semiconductor media can be a solid-state drive.

[0344] It should be understood that the term "and / or" in this document is merely a description of the association relationship between associated objects, indicating that three relationships can exist. For example, A and / or B can represent: A exists alone, A and B exist simultaneously, and B exists alone. Here, A and B can be singular or plural. In addition, the character " / " in this document generally represents an "or" relationship between the associated objects before and after, but it may also represent an "and / or" relationship, which can be specifically understood by referring to the context.

[0345] In the present application, "at least one" means one or more, and "a plurality" means two or more. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single items or plural items. For example, at least one of a, b, or c can represent: a, b, c, a - b, a - c, b - c, or a - b - c, where a, b, and c can be single or multiple.

[0346] It should be understood that in various embodiments of the present application, the sequence numbers of the above processes do not imply the order of execution. The order of execution of each process should be determined by its function and internal logic, and should not constitute any limitation to the implementation process of the embodiments of the present application.

[0347] Those of ordinary skill in the art can realize that the units and algorithm steps of each example described in combination with the embodiments disclosed herein can be implemented by electronic hardware, or by a combination of computer software and electronic hardware. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Professional technicians can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of this application.

[0348] Those skilled in the art can clearly understand that for the convenience and brevity of description, the specific working processes of the systems, devices, and units described above can refer to the corresponding processes in the foregoing method embodiments, and will not be elaborated herein.

[0349] In the several embodiments provided in this application, it should be understood that the disclosed systems, devices, and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of the units is only a logical function division. In actual implementation, there may be other division methods. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the displayed or discussed couplings or direct couplings or communication connections to each other can be through some interfaces. The indirect couplings or communication connections of the devices or units can be electrical, mechanical, or other forms.

[0350] The units described as separate components may or may not be physically separated. The components shown as units may or may not be physical units, that is, they can be located in one place, or they can be distributed to multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0351] In addition, the functional units in each embodiment of this application can be integrated in a processing unit, or each unit can exist physically alone, or two or more units can be integrated in one unit.

[0352] When the above-mentioned functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art or a part of this technical solution can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in various embodiments of this application. The foregoing storage medium includes: various media that can store program codes, such as USB flash drives, mobile hard disks, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical discs.

[0353] The above is only the specific implementation manner of this application, but the protection scope of this application is not limited thereto. Any person skilled in the art within the technical scope disclosed by this application can easily think of changes or substitutions, which should all be covered within the protection scope of this application. Therefore, the protection scope of this application should be subject to the protection scope of the claims.

Claims

1. A method for transmitting a reference signal, characterized in that, it includes: The network device sends a demodulation reference signal to the terminal device on the first symbol; wherein, the first symbol is determined by the symbols occupied by the synchronization signal block, the system message, and the data channel respectively, and the first symbol is the symbol among the symbols occupied by the data channel that is not occupied by the synchronization signal block and the system message; The number of the first symbols is two; One of the two first symbols is located before the symbol occupied by the synchronization signal block in the time domain, and the other is located after the symbol occupied by the synchronization signal block in the time domain; or, The two first symbols are: the first symbol and the last symbol located before the symbol occupied by the synchronization signal block in the time domain, and the two first symbols are not continuous; or, The two first symbols are: the first symbol and the last symbol located after the symbol occupied by the synchronization signal block in the time domain, and the two first symbols are not continuous.

2. The method for transmitting a reference signal according to claim 1, characterized in that, The number of the first symbols is one, and the one first symbol is located before or after the symbol occupied by the synchronization signal block in the time domain.

3. The method for transmitting a reference signal according to claim 2, characterized in that, The one first symbol is: the last symbol located before the symbol occupied by the synchronization signal block in the time domain.

4. The method for transmitting a reference signal according to claim 2, characterized in that, The one first symbol is: the first symbol located after the symbol occupied by the synchronization signal block in the time domain.

5. A method for transmitting a reference signal, characterized in that, it includes: The terminal device receives the synchronization signal block and parses the system message to determine the first symbol; The terminal device receives the demodulation reference signal from the network device on the first symbol; wherein, the synchronization signal block and the system message are used to indicate that: the first symbol is the symbol among the symbols occupied by the data channel that is not occupied by the synchronization signal block and the system message; The number of the first symbols is two; One of the two first symbols is located before the symbol occupied by the synchronization signal block in the time domain, and the other is located after the symbol occupied by the synchronization signal block in the time domain; or, The two first symbols are: the first symbol and the last symbol located before the symbol occupied by the synchronization signal block in the time domain, and the two first symbols are not continuous; or, The two first symbols are: the first symbol and the last symbol located after the symbol occupied by the synchronization signal block in the time domain, and the two first symbols are not continuous.

6. The method for transmitting a reference signal according to claim 5, characterized in that, The number of the first symbols is one, and the one first symbol is located before or after the symbol occupied by the synchronization signal block in the time domain.

7. The method for transmitting a reference signal according to claim 6, characterized in that, The one first symbol is: the last symbol located before the symbol occupied by the synchronization signal block in the time domain.

8. The transmission method of the reference signal according to claim 6, characterized in that, the first symbol is: the first symbol in the time domain after the symbol occupied by the synchronization signal block.

9. A communication device, characterized in that, comprising: a processing module and a transceiver module; wherein, the processing module is configured to determine a first symbol according to the symbols occupied by the synchronization signal block, the system message, and the data channel respectively, and the first symbol is the symbol among the symbols occupied by the data channel that is not occupied by the synchronization signal block and the system message; the transceiver module is configured to transmit a demodulation reference signal to the terminal device on the first symbol; the number of the first symbols is two; one of the two first symbols is in the time domain before the symbol occupied by the synchronization signal block, and the other is in the time domain after the symbol occupied by the synchronization signal block; or, the two first symbols are: the first symbol and the last symbol in the time domain before the symbol occupied by the synchronization signal block, and the two first symbols are not consecutive; or, the two first symbols are: the first symbol and the last symbol in the time domain after the symbol occupied by the synchronization signal block, and the two first symbols are not consecutive.

10. The communication device according to claim 9, characterized in that, the number of the first symbols is one, and the one first symbol is in the time domain before or after the symbol occupied by the synchronization signal block.

11. The communication device according to claim 10, characterized in that, the one first symbol is: the last symbol in the time domain before the symbol occupied by the synchronization signal block.

12. The communication device according to claim 10, characterized in that, the one first symbol is: the first symbol in the time domain after the symbol occupied by the synchronization signal block.

13. A communication device, characterized in that, comprising: a processing module and a transceiver module; wherein, the transceiver module is configured to receive the synchronization signal block and the system message; the synchronization signal block and the system message are used to indicate that: the first symbol is the symbol among the symbols occupied by the data channel that is not occupied by the synchronization signal block and the system message; the processing module is configured to determine the first symbol according to the synchronization signal block and the system message; the transceiver module is further configured to receive a demodulation reference signal from the network device on the first symbol; the number of the first symbols is two; one of the two first symbols is in the time domain before the symbol occupied by the synchronization signal block, and the other is in the time domain after the symbol occupied by the synchronization signal block; or, the two first symbols are: the first symbol and the last symbol in the time domain before the symbol occupied by the synchronization signal block, and the two first symbols are not consecutive; or, the two first symbols are: the first symbol and the last symbol in the time domain after the symbol occupied by the synchronization signal block, and the two first symbols are not consecutive.

14. The communication device according to claim 13, characterized in that, The number of the first symbols is one, and the one first symbol is located before or after the symbol occupied by the synchronization signal block in the time domain.

15. The communication device according to claim 14, wherein, the one first symbol is: the last symbol located before the symbol occupied by the synchronization signal block in the time domain.

16. The communication device according to claim 14, wherein, the one first symbol is: the first symbol located after the symbol occupied by the synchronization signal block in the time domain.

17. A readable storage medium, wherein, the readable storage medium includes a program or instructions, and when the program or instructions are run on a computer, the computer is caused to execute the method for transmitting a reference signal according to any one of claims 1-4, 5-8.

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