Display device and method for manufacturing the display device

Abstract

A display device and a method of manufacturing the display device are provided. The display device includes a substrate, which includes a main display region, a component region, and a peripheral region. The component region includes a transmissive region, and the peripheral region is disposed outside the main display region. The display device also includes a main thin-film transistor disposed in the main display region, a main organic light-emitting diode disposed in the main display region and connected to the main thin-film transistor, an auxiliary thin-film transistor disposed in the component region, an auxiliary organic light-emitting diode disposed in the component region and connected to the auxiliary thin-film transistor, and a lower metal layer disposed in the component region between the substrate and the auxiliary thin-film transistor and having an undercut structure.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2020-0081067, filed on July 1, 2020, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] Exemplary embodiments of this disclosure relate to a display device and a method of manufacturing the display device, and more specifically, to a display device having improved reliability and a method of manufacturing the display device. Background Technology

[0003] Recently, the use of display devices has diversified. In addition, display devices have become thinner and lighter, thus expanding their applications.

[0004] As display devices are used for a variety of purposes, there are various methods for designing the shape of display devices, and the number of functions associated with display devices has increased. Summary of the Invention

[0005] Exemplary embodiments of this disclosure include a display device and a method of manufacturing such a display device, wherein a display area is enlarged such that an image is displayed in an area in which components as electronic elements are arranged.

[0006] According to an exemplary embodiment of the present disclosure, a display device includes a substrate comprising a main display region, a component region, and a peripheral region. The component region includes a transmissive region, and the peripheral region is disposed outside the main display region. The display device further includes: a main thin-film transistor disposed in the main display region; a main organic light-emitting diode disposed in the main display region and connected to the main thin-film transistor; an auxiliary thin-film transistor disposed in the component region; an auxiliary organic light-emitting diode disposed in the component region and connected to the auxiliary thin-film transistor; and a lower metal layer disposed in the component region between the substrate and the auxiliary thin-film transistor and having an undercut structure.

[0007] In an exemplary embodiment, the lower metal layer includes a first metal layer having a first thickness in the thickness direction of the display device and a second metal layer having a second thickness in the thickness direction of the display device. The second thickness is greater than the first thickness.

[0008] In an exemplary embodiment, the first thickness is approximately to approximately And the second thickness is approximately to approximately

[0009] In an exemplary embodiment, the lower metal layer includes a first hole corresponding to the transmission region.

[0010] In an exemplary embodiment, the second metal layer has an undercut structure.

[0011] In an exemplary embodiment, the first metal layer includes at least one of Ti, Cr, ITO, IZO, ZnO, In2O3, IGO, and AZO.

[0012] In an exemplary embodiment, the second metal layer includes Mo.

[0013] In an exemplary embodiment, the lower metal layer is disposed directly on the upper surface of the substrate.

[0014] In an exemplary embodiment, the lower metal layer and the auxiliary thin-film transistor are at least partially stacked on top of each other.

[0015] In an exemplary embodiment, the display device further includes an encapsulation substrate disposed above the substrate.

[0016] In an exemplary embodiment, the display device further includes components disposed below the substrate in the component region.

[0017] In an exemplary embodiment, the components include an imaging device or a sensor.

[0018] According to an exemplary embodiment of the present disclosure, a display device includes a substrate, the substrate including a main display region, a component region, and a peripheral region. The component region includes a transmissive region, and the peripheral region is disposed outside the main display region. The display device further includes: a main thin-film transistor disposed in the main display region; a main organic light-emitting diode disposed in the main display region and connected to the main thin-film transistor; an auxiliary thin-film transistor disposed in the component region; an auxiliary organic light-emitting diode disposed in the component region and connected to the auxiliary thin-film transistor; a lower metal layer disposed in the component region between the substrate and the auxiliary thin-film transistor; and a metal layer disposed on the lower metal layer and having an undercut structure.

[0019] In an exemplary embodiment, the display device further includes an auxiliary storage capacitor disposed in the component region. The auxiliary thin-film transistor includes an auxiliary gate electrode, and the auxiliary storage capacitor includes an auxiliary lower electrode and an auxiliary upper electrode.

[0020] In an exemplary embodiment, the metal layer includes a first metal layer and a second metal layer disposed on the first metal layer and having an undercut structure.

[0021] In an exemplary embodiment, the metal layer and the auxiliary gate electrode are arranged on the same layer.

[0022] In an exemplary embodiment, the metal layer and the auxiliary upper electrode are arranged on the same layer.

[0023] According to exemplary embodiments of the present disclosure, a method of manufacturing a display device includes forming a lower metal layer on an upper surface of a substrate. The substrate includes a main display region, a component region, and a peripheral region. The component region includes a transmissive region, and the peripheral region is disposed outside the main display region. A lower metal layer is formed in the component region, and the lower metal layer includes a first metal layer and a second metal layer. The method further includes the steps of: forming a conductive material layer on the substrate in the main display region and on the lower metal layer in the component region; forming a pixel electrode by removing at least a portion of the conductive material layer and removing the second metal layer from the transmissive region; and forming an organic functional layer, a counter electrode, and an upper layer on the entire upper surface of the substrate. The organic functional layer, the counter electrode, and the upper layer cover the pixel electrode and the first metal layer. The method further includes irradiating a lower surface of the substrate opposite the upper surface of the substrate in the transmissive region with a laser beam.

[0024] In an exemplary embodiment, the steps of forming a pixel electrode by removing at least a portion of the conductive material layer and removing the second metal layer from the transmission region include removing at least a portion of the conductive material layer by wet etching and removing the second metal layer from the transmission region.

[0025] In an exemplary embodiment, the method further includes forming an undercut structure in a second metal layer by wet etching.

[0026] In an exemplary embodiment, the step of forming a lower metal layer including a first metal layer and a second metal layer includes: forming a first metal layer having a first thickness in the thickness direction of the display device; and forming a second metal layer having a second thickness in the thickness direction of the display device. The second thickness is greater than the first thickness.

[0027] In an exemplary embodiment, the first thickness is approximately to approximately And the second thickness is approximately to approximately

[0028] In an exemplary embodiment, the first metal layer includes at least one of Ti, Cr, ITO, IZO, ZnO, In2O3, IGO, and AZO.

[0029] In an exemplary embodiment, the second metal layer includes Mo.

[0030] In an exemplary embodiment, the lower metal layer is formed directly on the upper surface of the substrate.

[0031] In an exemplary embodiment, the first metal layer, organic functional layer, counter electrode, and upper layer formed on the upper surface of the substrate in the transmission region are removed by irradiating the lower surface of the substrate opposite to the upper surface of the substrate in the transmission region with a laser beam.

[0032] In an exemplary embodiment, the lower metal layer includes a first hole corresponding to the transmission region.

[0033] In an exemplary embodiment, the method further includes: forming a main thin-film transistor on the substrate in the main display region and forming an auxiliary thin-film transistor on the lower metal layer in the component region after forming a lower metal layer on the upper surface of the substrate in the component region and before forming a conductive material layer on the substrate in the main display region and the lower metal layer in the component region.

[0034] In an exemplary embodiment, the lower metal layer and the auxiliary thin-film transistor are at least partially stacked on top of each other.

[0035] In an exemplary embodiment, a component is further disposed on the lower surface of the substrate in the component region, and the component includes an imaging device or a sensor. Attached Figure Description

[0036] The above and other aspects and features of this disclosure will become more apparent from the detailed description of exemplary embodiments thereof with reference to the accompanying drawings.

[0037] Figure 1 This is a schematic perspective view of a display device according to an exemplary embodiment.

[0038] Figure 2 This is a schematic cross-sectional view of a display device according to an exemplary embodiment.

[0039] Figure 3 This is a schematic plan view of a display device according to an exemplary embodiment.

[0040] Figure 4 and Figure 5 This is an equivalent circuit diagram of a pixel that can be included in a display device according to an exemplary embodiment.

[0041] Figure 6 This is a schematic layout of the pixel arrangement structure in the main display area of ​​a display device according to an exemplary embodiment.

[0042] Figure 7 and Figure 8 This is a schematic layout of the pixel arrangement structure in the component area of ​​a display device according to an exemplary embodiment.

[0043] Figure 9 This is a schematic cross-sectional view of a display device according to an exemplary embodiment.

[0044] Figure 10 and Figure 11 This is a schematic cross-sectional view of a display device according to an exemplary embodiment.

[0045] Figure 12This is a schematic cross-sectional view of a display device according to an exemplary embodiment.

[0046] Figure 13 This is a schematic cross-sectional view of a display device according to an exemplary embodiment.

[0047] Figures 14 to 19 This is a schematic cross-sectional view illustrating a method for manufacturing a display device according to an exemplary embodiment. Detailed Implementation

[0048] Exemplary embodiments of the present disclosure will be described more fully below with reference to the accompanying drawings. Throughout the drawings, the same reference numerals may refer to the same elements.

[0049] As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. Throughout the disclosure, the expression “at least one of a, b, and c” means only a, only b, only c, both a and b, both a and c, both b and c, all of a, b, and c, or variations thereof.

[0050] It will be understood that the terms “first,” “second,” “third,” etc., are used herein to distinguish one element from another, and the elements are not limited by these terms. Thus, a “first” element in an exemplary embodiment may be described as a “second” element in another exemplary embodiment.

[0051] As used herein, unless the context clearly indicates otherwise, the singular expressions “a (kind)” and “the (represented)” are also intended to include the plural forms.

[0052] It will also be understood that the term “comprising” and / or variations thereof as used herein indicates the presence of the stated features or components, but does not preclude the presence or addition of one or more other features or components.

[0053] It will be understood that when a component, such as a membrane, region, layer, or element, is referred to as being "on," "connected to," "bonded to," or "adjacent to" another component, the component may be directly on, directly connected to, directly bonded to, or adjacent to the other component, or there may be intermediate components present. It will also be understood that when a component is referred to as being "between two components," the component may be the only component between the two components, or there may be one or more intermediate components. It will also be understood that when a component is referred to as "covering" another component, the component may be the only component covering the other component, or one or more intermediate components may also cover the other component. Other terms used to describe relationships between components should be interpreted in the same manner.

[0054] In this specification, the expression "A and / or B" may mean A, B, or A and B. Additionally, in this specification, the expression "at least one of A and B" may mean A, B, or A and B.

[0055] In the exemplary embodiments described below, "a line extending in a first direction or a second direction" means not only a line extending in a linear shape, but also a line extending in a zigzag shape or a circular shape in the first direction or the second direction.

[0056] In the exemplary embodiments described below, the term "planar" refers to the shape of an object when viewed from below, and the term "section" refers to the shape of an object when viewed from a lateral perspective as a vertically cut section. In the exemplary embodiments described below, when a portion is referred to as "overlay," the portion may be overlaid "planarly" or "sectionally."

[0057] It should be understood that, unless the context clearly indicates otherwise, the description of a feature or aspect within each exemplary embodiment should generally be considered applicable to other similar features or aspects in other exemplary embodiments.

[0058] For ease of description, spatial relative terms such as “below,” “under,” “below,” “below,” “above,” “above,” etc., may be used herein to describe the relationship of one element or feature to another (or other) element or feature as shown in the accompanying drawings. It will be understood that, in addition to the orientations depicted in the drawings, the spatial relative terms are intended to cover different orientations of the device in use or operation. For example, if the device in the drawings is flipped, an element described as “below,” “below,” or “below” other elements or features will subsequently be positioned “above” other elements or features. Thus, the exemplary terms “below” and “below” can cover both above and below orientations.

[0059] Here, when two or more elements or values ​​are described as substantially the same or approximately equal to each other, it will be understood that the elements or values ​​are the same, the elements or values ​​are equal to each other within measurement error, or if they are measurably unequal, then as those skilled in the art will understand, they are sufficiently close in value to be functionally equal to each other. For example, the term “approximately” as used herein includes the stated value and, taking into account the measurement in question and the error associated with the measurement of the specific quantity (i.e., the limitations of the measurement system), means within an acceptable deviation of the specific value as determined by those skilled in the art. For example, “approximately” could mean within one or more standard deviations as understood by those skilled in the art. Furthermore, it will be understood that although a parameter may be described herein as having “approximately” a certain value, according to exemplary embodiments, as those skilled in the art will understand, the parameter may be exactly a certain value or approximately a certain value within measurement error.

[0060] It will also be understood that when two components or directions are described as extending substantially parallel or perpendicular to each other, as will be understood by one of ordinary skill in the art, the two components or directions extend exactly parallel or perpendicular to each other, or extend approximately parallel or perpendicular to each other within measurement error.

[0061] Figure 1 This is a schematic perspective view of a display device 1 according to an exemplary embodiment.

[0062] Reference Figure 1 The display device 1 may include a display area DA and a peripheral area DPA disposed outside the display area DA. The display area DA may include a component area CA and a main display area MDA that at least partially surrounds the component area CA. For example, each of the component area CA and the main display area MDA may display an image individually or together. The peripheral area DPA may include a non-display area in which no display elements are disposed and no images are displayed. The display area DA may be completely surrounded by the peripheral area DPA.

[0063] Figure 1 A component region CA is shown located within the main display region MDA. However, this disclosure is not limited thereto. For example, according to an exemplary embodiment, the display device 1 may include two or more component regions CA. The two or more component regions CA may have different shapes and sizes from each other. When viewed from a perspective substantially perpendicular to the upper surface of the display device 1, the component region CA may have various shapes, such as circular shapes, elliptical shapes, polygonal shapes including quadrilateral shapes, star shapes, rhombus shapes, etc. Figure 1The diagram shows a component region CA arranged at the upper center side (+y direction) of the main display area MDA, which has a substantially quadrilateral shape when viewed from a direction substantially perpendicular to the upper surface of the display device 1. However, this disclosure is not limited thereto. For example, according to an exemplary embodiment, the component region CA may be arranged on one side of the main display area MDA having a quadrilateral shape, wherein this side includes, for example, the upper right side or the upper left side.

[0064] Display device 1 can provide an image by using a plurality of primary sub-pixels Pm arranged in the main display area MDA and a plurality of auxiliary sub-pixels Pa arranged in the component area CA.

[0065] See below for reference. Figure 2 As described, component 40, as an electronic element, can be arranged below substrate 100 in component region CA. Component 40 can correspond to component region CA. For example, the size of component region CA can be determined based on the size of component 40. Component 40 can correspond to a camera using infrared or visible light and can include a capturing device. Optionally, component 40 can include, for example, a solar cell, a flash device, an illuminance sensor, a proximity sensor, an iris sensor, etc. Optionally, component 40 can have the function of receiving sound. However, component 40 is not limited thereto. Component 40 can be an electronic circuit, and therefore, component 40 can also be referred to as an electronic circuit component. To prevent limitations on the function of component 40 as much as possible, component region CA can include a transmission region TA through which light and / or sound can pass, with light and / or sound output from component 40 to the outside of display device 1 or traveling from the outside of display device 1 toward component 40. In the case of the display device 1 according to the exemplary embodiment, when light is transmitted through the component region CA, the transmittance can be about 10% or more, more specifically, about 40% or more, about 25% or more, about 50% or more, about 85% or more, or about 90% or more.

[0066] The display area DA, including the main display area MDA and the component area CA (including the transmission area TA), as well as the peripheral area DPA, can be included on the substrate 100.

[0067] Multiple auxiliary subpixels Pa can be arranged in the component region CA. These auxiliary subpixels Pa can emit light to provide a specific image. The image displayed in the component region CA can correspond to an auxiliary image, which may have a lower resolution than the image displayed in the main display region MDA. For example, where the component region CA includes a transmission region TA through which light and / or sound can be transmitted and the subpixels are not arranged in the transmission region TA, the number of auxiliary subpixels Pa arranged per unit area in the component region CA can be less than the number of main subpixels Pm arranged per unit area in the main display region MDA.

[0068] Figure 2 This is a schematic cross-sectional view of a display device 1 according to an exemplary embodiment.

[0069] Reference Figure 2 The display device 1 may include a display panel 10 and a component 40 stacked with the display panel 10. In an exemplary embodiment, a cover window protecting the display panel 10 may be further arranged above the display panel 10.

[0070] The display panel 10 may include a component area CA and a main display area MDA. The component area CA is an area superimposed on the component 40, and the main image is displayed in the main display area MDA. The display panel 10 may include a substrate 100, a display layer DISL disposed above the substrate 100, and a protective member PB disposed below the substrate 100.

[0071] The display layer DISL may include a circuit layer PCL, a display element layer EDL, and an encapsulation component ENCM (such as an encapsulation substrate). The circuit layer PCL includes a main thin-film transistor (TFT) and an auxiliary thin-film transistor (TFT'). The display element layer EDL includes a main organic light-emitting diode (OLED) and an auxiliary organic light-emitting diode (OLED') as display elements. A main insulating layer (also known as an "inorganic insulating layer") IL may be disposed in the display layer DISL, and an auxiliary insulating layer IL' may be disposed between the substrate 100 and the display layer DISL.

[0072] The substrate 100 may include an insulating material, such as glass, quartz, or polymer resin. The substrate 100 may include a rigid substrate or a flexible substrate, and the flexible substrate may be bent (or flexible), folded (or foldable), or rolled (or rollable).

[0073] The main thin-film transistor (TFT) and the main organic light-emitting diode (OLED) connected to the main TFT can be arranged in the main display area MDA of the display panel 10 to realize the main sub-pixel Pm. The auxiliary thin-film transistor (TFT) and the auxiliary organic light-emitting diode (OLED) connected to the auxiliary TFT can be arranged in the component area CA of the display panel 10 to realize the auxiliary sub-pixel Pa. The component area CA in which the auxiliary sub-pixel Pa is arranged can be referred to as the auxiliary display area.

[0074] The component region CA may include a transmissive region TA in which no display element is disposed. The transmissive region TA is an area through which light / signals emitted from or incident into the component 40 can pass, and the component 40 is arranged corresponding to the component region CA. The auxiliary display region and the transmissive region TA may be arranged alternately in the component region CA.

[0075] When the display element layer EDL is encapsulated by a packaging substrate, the packaging substrate may be arranged facing the substrate 100, with the display element layer EDL disposed between the packaging substrate and the substrate 100. The packaging substrate and the display element layer EDL may have a gap between them. The packaging substrate may include glass. A sealant, including glass frit, may be disposed between the substrate 100 and the packaging substrate, and the sealant may be disposed in the peripheral region DPA described above. The sealant disposed in the peripheral region DPA may surround the display region DA and prevent water or other substances from penetrating through the side surfaces of the display region DA.

[0076] The display element layer (EDL) may be covered by a packaging substrate or a thin-film encapsulation layer. In an exemplary embodiment, the thin-film encapsulation layer may include at least one inorganic encapsulation layer and at least one organic encapsulation layer. For example, the thin-film encapsulation layer may include a first inorganic encapsulation layer, a second inorganic encapsulation layer, and an organic encapsulation layer disposed between the first inorganic encapsulation layer and the second inorganic encapsulation layer.

[0077] The protective member PB can be bonded beneath the substrate 100 and can support and protect the substrate 100. The protective member PB may include an opening PB_OP corresponding to the component region CA. When the protective member PB includes an opening PB_OP, the light transmittance of the component region CA can be increased. The protective member PB may include, for example, polyethylene terephthalate (PET) or polyimide (PI).

[0078] The component region CA can have an area larger than the area in which the component 40 is arranged. Therefore, in an exemplary embodiment, the area of ​​the opening PB_OP provided in the protective member PB may not correspond to the area of ​​the component region CA.

[0079] Multiple components 40 may be arranged in the component area CA. The multiple components 40 may have different functions from each other. For example, the multiple components 40 may include at least two of a camera (imaging device), a solar cell, a flash device, a proximity sensor, an illumination sensor, and an iris sensor. However, the multiple components are not limited to this.

[0080] Figure 3 This is a schematic plan view of a display device 1 according to an exemplary embodiment.

[0081] Reference Figure 3 Various components included in the display device 1 can be arranged above the substrate 100. The substrate 100 may include a display area DA and a peripheral area DPA surrounding the display area DA. The display area DA may include a main display area MDA in which a main image is displayed and a component area CA in which an auxiliary image is displayed, wherein the component area CA includes a transmissive area TA. The auxiliary image may form a regular image with the main image, or it may be an image separate from the main image.

[0082] Multiple primary subpixels Pm can be arranged in the main display area MDA. Each of the primary subpixels Pm can be implemented as a display element such as a primary organic light-emitting diode (OLED). Each primary subpixel Pm can emit light, for example, red, green, blue, or white light. The main display area MDA can be covered by encapsulation components and protected from external materials, moisture, etc.

[0083] As described above, the component region CA can be located on one side of the main display region MDA, or it can be arranged in the display region DA and surrounded by the main display region MDA. Multiple auxiliary sub-pixels Pa can be arranged in the component region CA. Each of the multiple auxiliary sub-pixels Pa can be implemented as a display element such as an auxiliary organic light-emitting diode (OLED). Each auxiliary sub-pixel Pa can emit light, for example, red, green, blue, or white light. The component region CA can be covered by an encapsulation component and protected from external materials, moisture, etc.

[0084] The component region CA may include a transmission region TA. The transmission region TA may surround multiple auxiliary sub-pixels Pa. Alternatively, the transmission region TA may form a grid shape with the multiple auxiliary sub-pixels Pa.

[0085] Because the component area CA includes the transmission area TA, the resolution of the component area CA can be lower than the resolution of the main display area MDA. For example, the resolution of the component area CA can be approximately 1 / 2, 3 / 8, 1 / 3, 1 / 4, 2 / 9, 1 / 8, 1 / 9, or 1 / 16 of the resolution of the main display area MDA. For example, the resolution of the main display area MDA can be approximately 400 PPI or higher, and the resolution of the component area CA can be approximately 200 PPI or approximately 100 PPI.

[0086] Each of the pixel circuits driving the main sub-pixel Pm and the auxiliary sub-pixel Pa can be electrically connected to external circuitry arranged in the peripheral region DPA. The first scan drive circuit SDRV1, the second scan drive circuit SDRV2, the terminal portion PAD, the drive voltage supply line 11, and the common voltage supply line 13 can be arranged in the peripheral region DPA.

[0087] The first scan driving circuit SDRV1 can apply a scan signal to each of the pixel circuits driving the main sub-pixel Pm and the auxiliary sub-pixel Pa via the scan line SL. The first scan driving circuit SDRV1 can apply an emission control signal to each pixel circuit via the emission control line EL. The second scan driving circuit SDRV2 can be located on the opposite side of the first scan driving circuit SDRV1 based on the main display area MDA, and can be substantially parallel to the first scan driving circuit SDRV1. One or more pixel circuits of the main sub-pixel Pm of the main display area MDA can be electrically connected to the first scan driving circuit SDRV1, and other pixel circuits can be electrically connected to the second scan driving circuit SDRV2. One or more pixel circuits of the auxiliary sub-pixel Pa of the component area CA can be electrically connected to the first scan driving circuit SDRV1, and other pixel circuits can be electrically connected to the second scan driving circuit SDRV2. In an exemplary embodiment, the second scan driving circuit SDRV2 may be omitted.

[0088] The terminal portion PAD may be disposed on one side of the substrate 100. In an exemplary embodiment, the terminal portion PAD is not covered by an insulating layer and may be exposed for connection to the display circuit board 30. The display driver 32 may be disposed on the display circuit board 30.

[0089] The display driver 32 can generate control signals to be transmitted to the first scan drive circuit SDRV1 and the second scan drive circuit SDRV2. The display driver 32 can generate data signals, and the generated data signals can be transmitted to the pixel circuits of the main sub-pixel Pm and the auxiliary sub-pixel Pa through the fan-out line FW and the data line DL connected to the fan-out line FW.

[0090] The display driver 32 can drive voltage ELVDD (see...) Figure 4 and Figure 5 ) is supplied to drive voltage supply line 11, and the common voltage ELVSS (see Figure 4 and Figure 5 The driving voltage ELVDD can be applied to the pixel circuits of the main sub-pixel Pm and the auxiliary sub-pixel Pa through the driving voltage line PL connected to the driving voltage supply line 11, and the common voltage ELVSS can be applied to the counter electrode of the display element through the common voltage supply line 13.

[0091] The drive voltage supply line 11 can be disposed below the main display area MDA and can extend in the x direction. The common voltage supply line 13 can have a ring shape with an open side and can partially surround the main display area MDA.

[0092] Figure 4 and Figure 5 This is an equivalent circuit diagram of sub-pixels Pm and Pa that may be included in display device 1 according to an exemplary embodiment.

[0093] Reference Figure 4 The pixel circuit PC can be connected to an organic light-emitting diode (OLED) to enable sub-pixel emission. The pixel circuit PC may include a driving thin-film transistor (TFT) T1, a switching TFT T2, and a storage capacitor Cst. The switching TFT T2 can be connected to a scan line SL and a data line DL, and can transmit a data signal Dm provided via the data line DL to the driving TFT T1 in response to a scan signal Sn provided via the scan line SL.

[0094] The storage capacitor Cst can be connected to the switching thin-film transistor T2 and the drive voltage line PL, and can store the voltage corresponding to the difference between the voltage received from the switching thin-film transistor T2 and the drive voltage ELVDD supplied to the drive voltage line PL.

[0095] The driving thin-film transistor T1 can be connected to the driving voltage line PL and the storage capacitor Cst, and the driving current flowing from the driving voltage line PL through the organic light-emitting diode (OLED) can be controlled according to the voltage value stored in the storage capacitor Cst. The OLED can emit light with a certain brightness based on the driving current.

[0096] Reference Figure 4 The pixel circuit PC is described as including two thin-film transistors and a storage capacitor. However, this disclosure is not limited thereto.

[0097] Reference Figure 5The pixel circuit PC may include a driving thin-film transistor T1, a switching thin-film transistor T2, a compensation thin-film transistor T3, a first initialization thin-film transistor T4, an operation control thin-film transistor T5, an emission control thin-film transistor T6, a second initialization thin-film transistor T7, and a storage capacitor Cst.

[0098] Figure 5 The illustration shows a case where each pixel circuit PC includes signal lines SL, SL-1, SL+1, EL, and DL, an initialization voltage line VL, and a drive voltage line PL. However, the disclosure is not limited thereto. For example, according to an exemplary embodiment, at least one of the signal lines SL, SL-1, SL+1, EL, and DL and the initialization voltage line VL may be shared by adjacent pixel circuit PCs.

[0099] The drain electrode of the driving thin-film transistor T1 can be electrically connected to the organic light-emitting diode (OLED) via the emitter control thin-film transistor T6. The driving thin-film transistor T1 can receive the data signal Dm according to the switching operation of the switching thin-film transistor T2 and supply the driving current to the OLED.

[0100] The gate electrode of the switching thin-film transistor T2 can be connected to the scan line SL, and the source electrode of the switching thin-film transistor T2 can be connected to the data line DL. The drain electrode of the switching thin-film transistor T2 can be connected to the source electrode of the driving thin-film transistor T1, and can be connected to the driving voltage line PL by operating the control thin-film transistor T5.

[0101] The switching thin-film transistor T2 can be turned on in response to the scan signal Sn transmitted through the scan line SL, and can perform a switching operation to transmit the data signal Dm transmitted through the data line DL to the source electrode of the driving thin-film transistor T1.

[0102] The gate electrode of the compensation thin-film transistor T3 can be connected to the scan line SL. The source electrode of the compensation thin-film transistor T3 can be connected to the drain electrode of the driving thin-film transistor T1, and can be connected to the pixel electrode of the organic light-emitting diode (OLED) via the emission control thin-film transistor T6. The drain electrode of the compensation thin-film transistor T3 can be connected to any electrode of the storage capacitor Cst, the source electrode of the first initialization thin-film transistor T4, and the gate electrode of the driving thin-film transistor T1. The compensation thin-film transistor T3 can be turned on in response to the scan signal Sn transmitted through the scan line SL, thereby connecting the gate electrode of the driving thin-film transistor T1 to the drain electrode of the driving thin-film transistor T1, thus enabling the driving thin-film transistor T1 to be diode-connected.

[0103] The gate electrode of the first initialization thin-film transistor T4 can be connected to the previous scan line SL-1. The drain electrode of the first initialization thin-film transistor T4 can be connected to the initialization voltage line VL. The source electrode of the first initialization thin-film transistor T4 can be connected to any electrode of the storage capacitor Cst, the drain electrode of the compensation thin-film transistor T3, and the gate electrode of the driving thin-film transistor T1. The first initialization thin-film transistor T4 can be turned on in response to the previous scan signal Sn-1 received through the previous scan line SL-1, and can perform an initialization operation to initialize the voltage of the gate electrode of the driving thin-film transistor T1 by transmitting the initialization voltage Vint to the gate electrode of the driving thin-film transistor T1.

[0104] The gate electrode of the operational control thin-film transistor T5 can be connected to the emitter control line EL. The source electrode of the operational control thin-film transistor T5 can be connected to the drive voltage line PL. The drain electrode of the operational control thin-film transistor T5 can be connected to the source electrode of the driving thin-film transistor T1 and the drain electrode of the switching thin-film transistor T2.

[0105] The gate electrode of the emitter control thin-film transistor T6 can be connected to the emitter control line EL. The source electrode of the emitter control thin-film transistor T6 can be connected to the drain electrode of the driving thin-film transistor T1 and the source electrode of the compensation thin-film transistor T3. The drain electrode of the emitter control thin-film transistor T6 can be electrically connected to the pixel electrode of the organic light-emitting diode (OLED). The operation control thin-film transistor T5 and the emitter control thin-film transistor T6 can be simultaneously turned on in response to the emitter control signal En received through the emitter control line EL, so that the driving voltage ELVDD can be transmitted to the OLED and the driving current can flow in the OLED.

[0106] The gate electrode of the second initialization thin-film transistor T7 can be connected to the next scan line SL+1. The source electrode of the second initialization thin-film transistor T7 can be connected to the pixel electrode of the organic light-emitting diode (OLED). The drain electrode of the second initialization thin-film transistor T7 can be connected to the initialization voltage line VL. The second initialization thin-film transistor T7 can be turned on in response to the next scan signal Sn+1 received through the next scan line SL+1, and can initialize the pixel electrode of the organic light-emitting diode (OLED).

[0107] Figure 5 The illustration shows a case where the first initialization thin-film transistor T4 and the second initialization thin-film transistor T7 are connected to the previous scan line SL-1 and the next scan line SL+1, respectively. However, this disclosure is not limited thereto. For example, according to an exemplary embodiment, both the first initialization thin-film transistor T4 and the second initialization thin-film transistor T7 can be connected to the previous scan line SL-1 and driven according to the previous scan signal Sn-1.

[0108] The other electrode of the storage capacitor Cst can be connected to the drive voltage line PL. One electrode of the storage capacitor Cst can also be connected to the gate electrode of the driving thin-film transistor T1, the drain electrode of the compensation thin-film transistor T3, and the source electrode of the first initialization thin-film transistor T4.

[0109] The counter electrode (e.g., cathode) of an organic light-emitting diode (OLED) can receive a common voltage ELVSS. An OLED can emit light by receiving a drive current from a driving thin-film transistor T1.

[0110] Pixel circuit PC is not limited to reference Figure 5 The number of thin-film transistors and storage capacitors and the circuit design described can be modified in various ways according to the exemplary embodiments. The pixel circuits PC used to drive the main sub-pixel Pm and the auxiliary sub-pixel Pa can be the same as or different from each other.

[0111] Figure 6 This is a schematic layout of the pixel arrangement structure in the main display area MDA according to an exemplary embodiment.

[0112] Multiple master subpixels Pm can be arranged in the main display area MDA. In this specification, a subpixel represents the emission region of the smallest unit used to realize an image. When an organic light-emitting diode is implemented as a display element, the emission region can be defined by an opening in the pixel-defining layer. This aspect will be described further below.

[0113] like Figure 6 As shown, the principal sub-pixel Pm arranged in the main display area MDA can be PENTILE TM Structural arrangement. The red sub-pixel Pr, green sub-pixel Pg, and blue sub-pixel Pb can respectively realize red, green, and blue.

[0114] Multiple red subpixels Pr and multiple blue subpixels Pb can be alternately arranged in the first row 1N. Multiple green subpixels Pg can be arranged in the second row 2N adjacent to the first row 1N, spaced apart from the multiple red subpixels Pr and multiple blue subpixels Pb. Multiple blue subpixels Pb and multiple red subpixels Pr can be alternately arranged in the third row 3N adjacent to the second row 2N. Multiple green subpixels Pg can be arranged in the fourth row 4N adjacent to the third row 3N, spaced apart from the multiple blue subpixels Pb and multiple red subpixels Pr. This arrangement of pixels can be repeated up to the Nth row. Here, the size of the blue subpixels Pb and red subpixels Pr can be larger than the size of the green subpixels Pg.

[0115] Multiple red sub-pixels Pr and multiple blue sub-pixels Pb arranged in the first row 1N can be arranged offset from multiple green sub-pixels Pg arranged in the second row 2N. Therefore, multiple red sub-pixels Pr and multiple blue sub-pixels Pb can be alternately arranged in the first column 1M, multiple green sub-pixels Pg can be arranged in the second column 2M adjacent to the first column 1M to be spaced apart from the multiple red sub-pixels Pr and multiple blue sub-pixels Pb, multiple blue sub-pixels Pb and multiple red sub-pixels Pr can be alternately arranged in the third column 3M adjacent to the second column 2M, and multiple green sub-pixels Pg can be arranged in the fourth column 4M adjacent to the third column 3M to be spaced apart from the multiple blue sub-pixels Pb and multiple red sub-pixels Pr. This arrangement of pixels can be repeated up to the Mth column.

[0116] According to an exemplary embodiment, the red sub-pixel Pr can be arranged at the first and third vertices of a virtual square VS with the center point of the green sub-pixel Pg as its center point, wherein the first and third vertices face each other, and the blue sub-pixel Pb can be arranged at the second and fourth vertices, which are the other vertices of the virtual square VS. Here, the virtual square VS can be modified in various ways to include rectangular, rhomboid, square, etc.

[0117] This pixel arrangement structure can be called a pentiline. TM Matrix structure or Pentile TM The structure allows for the application of rendering operations that represent colors by sharing adjacent pixels, thereby achieving high resolution using a small number of pixels.

[0118] Figure 6 Multiple principal sub-pixels Pm are shown in PENTILE TM Matrix structure arrangement. However, this disclosure is not limited thereto. For example, according to an exemplary embodiment, multiple principal sub-pixels Pm can be arranged in various shapes (such as stripe structures, mosaic arrangements, triangular arrangements, etc.).

[0119] Figure 7 and Figure 8 This is a schematic layout of the pixel arrangement structure in the component region CA according to an exemplary embodiment.

[0120] Reference Figure 7 Multiple auxiliary subpixels Pa can be arranged in the component region CA. Each of the multiple auxiliary subpixels Pa can emit any one of red, green, blue, and white light.

[0121] The component region CA may have a pixel group PG including at least one auxiliary sub-pixel Pa and a transmission region TA. The pixel group PG and the transmission region TA may be arranged alternately in the x and y directions. For example, the pixel group PG and the transmission region TA may be arranged in a grid shape. In this case, the component region CA may have multiple pixel groups PG and multiple transmission regions TA.

[0122] A pixel group PG can be defined as a group of subpixels generated by grouping multiple auxiliary subpixels Pa into predetermined units. For example, as... Figure 7 As shown, a pixel group PG can include PENTILE TM The structure consists of eight auxiliary sub-pixels Pa. For example, a pixel group PG may include two red sub-pixels Pr, four green sub-pixels Pg, and two blue sub-pixels Pb.

[0123] Within the component region CA, basic units U, comprising a certain number of pixel groups PG and a certain number of transmission regions TA, can be repeatedly arranged in the x and y directions. Figure 7 In this design, a basic unit U may include two pixel groups PG within a square shape and two transmissive regions TA arranged adjacent to the pixel groups PG. The basic unit U is obtained by dividing a repeating shape, and it does not imply that the components included in the basic unit U are separate from other components included in another basic unit.

[0124] Reference Figure 6 and Figure 7 A corresponding unit U' with the same area as the basic unit U can be set in the main display area MDA. In this case, the number of main sub-pixels Pm included in the corresponding unit U' can be greater than the number of auxiliary sub-pixels Pa included in the basic unit U. For example, the basic unit U may include 16 auxiliary sub-pixels Pa, and the corresponding unit U' may include 32 main sub-pixels Pm. Therefore, the number of auxiliary sub-pixels Pa and the number of main sub-pixels Pm arranged in the same area can have a ratio of 1:2.

[0125] like Figure 7 As shown, when the auxiliary sub-pixel Pa is PENTILE TM When the pixel arrangement is such that the resolution of the auxiliary sub-pixels Pa corresponds to half the resolution of the primary sub-pixels arranged in the main display area MDA, the pixel arrangement structure can be called a 1 / 2 pentile. TM Structure. The number and arrangement of auxiliary subpixels Pa within pixel group PG can be designed to vary according to the resolution of component region CA.

[0126] Reference Figure 8The pixel arrangement structure of the component region CA can correspond to 1 / 4 PENTILE TM Structure. According to an exemplary embodiment, although the 8 auxiliary sub-pixels Pa of pixel group PG can be pentiles TM The structural arrangement is as follows, but the basic unit U may consist of only one pixel group PG, and the other areas of the basic unit U may be occupied by the transmissive region TA. Therefore, the number of auxiliary sub-pixels Pa and the number of main sub-pixels Pm arranged in the same area can have a ratio of 1:4. In this case, a pixel group PG can be surrounded by the transmissive region TA.

[0127] Figure 9 This is a schematic cross-sectional view of a display device 1 according to an exemplary embodiment. Figure 10 and Figure 11 This is a schematic cross-sectional view of a display device 1 according to an exemplary embodiment. Figure 9 This is a schematic cross-sectional view of a portion of a display device 1 according to an exemplary embodiment, which schematically shows the main display area MDA and the component area CA. Figure 10 yes Figure 9 An enlarged sectional view of region A, and Figure 11 yes Figure 9 An enlarged sectional view of region B.

[0128] Reference Figure 9 The display device 1 may include a main display area MDA and a component area CA. A main sub-pixel Pm may be arranged in the main display area MDA, and an auxiliary sub-pixel Pa may be arranged in the component area CA. The component area CA may include a transmissive area TA.

[0129] A main pixel circuit PC, including a main thin-film transistor (TFT) and a main storage capacitor Cst, and a main organic light-emitting diode (OLED) serving as a display element connected to the main pixel circuit PC, can be arranged in the main display area MDA. An auxiliary pixel circuit PC', including an auxiliary thin-film transistor 'TFT' and an auxiliary storage capacitor 'Cst', and an auxiliary organic light-emitting diode 'OLED' serving as a display element connected to the auxiliary pixel circuit PC', can be arranged in the component area CA.

[0130] According to exemplary embodiments, examples in which organic light-emitting diodes (OLEDs) and OLED' are used as display elements are described. However, this disclosure is not limited thereto. For example, according to exemplary embodiments, inorganic light-emitting diodes or quantum dot light-emitting diodes can be used as display elements.

[0131] The following describes the stacked structure of the components included in the display device 1. The display device 1 may include a stacked substrate 100, a buffer layer 111, a circuit layer PCL, and a display element layer EDL. For example, the buffer layer 111, the circuit layer PCL, and the display element layer EDL may be disposed on the upper surface of the substrate 100.

[0132] As described above, substrate 100 may include insulating materials, such as glass, quartz, and polymer resins. Substrate 100 may include a rigid substrate or a flexible substrate, and the flexible substrate may be bent (or flexible), folded (or foldable), or rolled (or rollable).

[0133] A buffer layer 111 may be disposed on a substrate 100 to reduce or prevent the penetration of foreign materials or substances, moisture, etc., from beneath the substrate 100, and to provide a planarized surface on the substrate 100. The buffer layer 111 may include inorganic materials (such as oxides or nitrides), organic materials, or organic-inorganic composites, and may have a single-layer or multi-layer structure comprising both inorganic and organic materials. A barrier layer to prevent the penetration of foreign substances may also be included between the substrate 100 and the buffer layer 111. In an exemplary embodiment, the buffer layer 111 may include silicon oxide (SiO2). x ), silicon nitride (SiN) x ) and silicon oxynitride (SiO) x N y At least one of the following. The buffer layer 111 disposed in the component region CA may have an opening corresponding to the transmission region TA.

[0134] In the component region CA, the lower metal layer BML can be disposed between the substrate 100 and the buffer layer 111. The lower metal layer BML can also be disposed on the upper surface of the substrate 100 in the component region CA.

[0135] Reference Figure 10 and Figure 11 The lower metal layer BML may include a first metal layer 105a and a second metal layer 105b. The lower metal layer BML may be disposed above the substrate 100 and below the auxiliary thin-film transistor TFT', and may have an undercut structure U. For example, the second metal layer 105b of the lower metal layer BML may have an undercut structure U. The undercut structure U of the second metal layer 105b may be formed when the material used to form the pixel electrode is etched together with the second metal layer 105b disposed in the transmission region TA.

[0136] Referring to the second metal layer 105b, the undercut structure U can refer to the shape of the end of the second metal layer 105b facing the transmission region TA. For example, referring to the undercut structure U, the upper part of the end of the second metal layer 105b facing the transmission region TA can be configured to be farther away from the transmission region TA than the lower part of the end of the second metal layer 105b facing the transmission region TA, and as the end extends from the upper part to the lower part in the z-direction, the end of the second metal layer 105b can gradually become closer to the transmission region TA in the x-direction. For example, referring to the end of the second metal layer 105b facing the transmission region TA, the portion of the end of the second metal layer 105b that contacts the buffer layer 111 can be configured to be farther away from the transmission region TA than the portion of the end of the second metal layer 105b that contacts the first metal layer 105a, and as the end of the second metal layer 105b becomes closer to the first metal layer 105a in the z-direction, the end of the second metal layer 105b can become closer to the transmission region TA in the x-direction.

[0137] According to an exemplary embodiment, the lower metal layer BML can be directly disposed on the upper surface 100a of the substrate 100. For example, the first metal layer 105a of the lower metal layer BML can be directly disposed on the upper surface 100a of the substrate 100, and no intermediate layer or component is provided between the first metal layer 105a and the upper surface 100a of the substrate 100. For example, according to an exemplary embodiment, the first metal layer 105a can directly contact the upper surface 100a of the substrate 100. Alternatively, according to an exemplary embodiment, a buffer layer can be disposed between the lower metal layer BML and the substrate 100.

[0138] The first metal layer 105a of the lower metal layer (BML) may have a first thickness t1 extending in the z-direction (e.g., the thickness direction of the display device 1). For example, the first metal layer 105a may have a first thickness t1 in a direction that extends substantially perpendicularly from the upper surface 100a of the substrate 100. According to an exemplary embodiment, the first thickness t1 may be approximately to approximately According to an exemplary embodiment, the first thickness t1 can be approximately to approximately about to approximately For example, in an exemplary embodiment, the first thickness t1 can be approximately... to approximately

[0139] The second metal layer 105b of the lower metal layer BML may have a second thickness t2 extending in the z-direction (e.g., the thickness direction of the display device 1). For example, the second metal layer 105b may have a second thickness t2 in a direction that extends substantially perpendicularly from the upper surface 100a of the substrate 100. The second thickness t2 may be greater than the first thickness t1. According to an exemplary embodiment, the second thickness t2 may be approximately to approximately According to an exemplary embodiment, the second thickness t2 can be approximately to approximately about to approximately For example, in an exemplary embodiment, the second thickness t2 can be approximately... to approximately

[0140] The lower metal layer BML may include at least one of, for example, Al, Pt, Pd, Ag, Mg, Au, Ni, Nd, Ir, Cr, Ca, Mo, Ti, W, Cu, ITO, IZO, ZnO, In2O3, IGO, and AZO. For example, in an exemplary embodiment, the first metal layer 105a of the lower metal layer BML may include at least one of Ti, Cr, ITO, IZO, ZnO, In2O3, IGO, and AZO, and the second metal layer 105b may include Mo.

[0141] The lower metal layer BML disposed in the component region CA can be at least partially superimposed with the auxiliary pixel circuit PC' disposed in the component region CA. For example, the lower metal layer BML of the component region CA can correspond to the entire component region CA, except for the first hole H1 included in the lower metal layer BML in the region corresponding to the transmission region TA. In an exemplary embodiment, the shape and size of the transmission region TA can be defined according to the shape and size of the first hole H1 defined by the lower metal layer BML. The minimum width Wt of the transmission region TA can be the same as the width of the first hole H1 defined by the lower metal layer BML.

[0142] When manufacturing the display device 1 according to an exemplary embodiment of the present disclosure, it may be advantageous not to arrange the lower metal layer (BML) in the main display area (MDA). For example, when the lower metal layer (BML) is disposed on the entire surface or a large portion (e.g., including a portion of the main display area (MDA)) of the substrate 100, defects may occur in the process of crystallizing the semiconductor layer of the thin-film transistor using a laser beam.

[0143] The lower metal layer BML can be at least partially stacked with the auxiliary thin-film transistor TFT'. The lower metal layer BML can be disposed below the auxiliary thin-film transistor TFT' and can prevent the characteristics of the auxiliary thin-film transistor TFT' from being degraded due to light emitted from the component. Additionally, the lower metal layer BML can prevent diffraction of light emitted from or traveling toward the component through small gaps between the wiring connected to the auxiliary pixel circuit PC'. In an exemplary embodiment, the lower metal layer BML is not located in the transmission region TA.

[0144] The circuit layer PCL can be disposed above the buffer layer 111 and can include a main pixel circuit PC and an auxiliary pixel circuit PC', a first insulating layer 112, a second insulating layer 113, a third insulating layer 115, and a planarization layer 117. The main pixel circuit PC can include a main thin-film transistor TFT and a main storage capacitor Cst, and the auxiliary pixel circuit PC' can include an auxiliary thin-film transistor TFT' and an auxiliary storage capacitor Cst'.

[0145] The main thin-film transistor (TFT) and the auxiliary thin-film transistor (TFT') can be disposed above the buffer layer 111. The main thin-film transistor (TFT) may include a main semiconductor layer A1, a main gate electrode G1, a main source electrode S1, and a main drain electrode D1. The auxiliary thin-film transistor (TFT') may include an auxiliary semiconductor layer A2, an auxiliary gate electrode G2, an auxiliary source electrode S2, and an auxiliary drain electrode D2. The main thin-film transistor (TFT) can be connected to and drive the main organic light-emitting diode (OLED). The auxiliary thin-film transistor (TFT') can be connected to and drive the auxiliary organic light-emitting diode (OLED').

[0146] The main semiconductor layer A1 and the auxiliary semiconductor layer A2 may be disposed above the buffer layer 111 and may comprise polycrystalline silicon. According to an exemplary embodiment, the main semiconductor layer A1 and the auxiliary semiconductor layer A2 may comprise amorphous silicon. According to an exemplary embodiment, the main semiconductor layer A1 and the auxiliary semiconductor layer A2 may comprise oxides of at least one of, for example, In, Ga, Sn, Zr, V, Hf, Cd, Ge, Cr, Ti, and Zn. The main semiconductor layer A1 and the auxiliary semiconductor layer A2 may comprise a channel region and impurity-doped source and drain regions.

[0147] The auxiliary semiconductor layer A2 can be stacked with the lower metal layer BML, and the buffer layer 111 is disposed between the auxiliary semiconductor layer A2 and the lower metal layer BML. According to an exemplary embodiment, the width of the auxiliary semiconductor layer A2 can be smaller than the width of the lower metal layer BML, so that when viewed from a direction perpendicular to the substrate 100, the auxiliary semiconductor layer A2 can be completely stacked with the lower metal layer BML.

[0148] The first insulating layer 112 may cover the main semiconductor layer A1 and the auxiliary semiconductor layer A2. The first insulating layer 112 may include an inorganic insulating material, such as SiO2 or SiN. x SiO x N y For example, Al2O3, TiO2, Ta2O5, HfO2, or ZnO. The first insulating layer 112 may include a single layer or multiple layers containing the inorganic insulating material described above.

[0149] The main gate electrode G1 and the auxiliary gate electrode G2 can be disposed on the first insulating layer 112, and can be stacked with the main semiconductor layer A1 and the auxiliary semiconductor layer A2, respectively. The main gate electrode G1 and the auxiliary gate electrode G2 can include, for example, Mo, Al, Cu, Ti, etc., and can include a single layer or multiple layers.

[0150] The second insulating layer 113 may cover the main gate electrode G1 and the auxiliary gate electrode G2. The second insulating layer 113 may include inorganic insulating materials, such as SiO2 and SiN. x SiO x N y Examples include Al2O3, TiO2, Ta2O5, HfO2, or ZnO. The second insulating layer 113 may include a single layer or multiple layers containing the inorganic insulating material described above.

[0151] The main upper electrode CE2 of the main storage capacitor Cst and the auxiliary upper electrode CE2' of the auxiliary storage capacitor Cst' can be arranged above the second insulating layer 113.

[0152] The main upper electrode CE2 may be stacked in the main display area MDA with the main gate electrode G1 disposed below the main upper electrode CE2. The stacked main gate electrode G1 and main upper electrode CE2, as well as the second insulating layer 113 disposed between the main gate electrode G1 and the main upper electrode CE2, may be included in the main storage capacitor Cst. The main gate electrode G1 may be integrally disposed with the main lower electrode CE1 of the main storage capacitor Cst. According to an exemplary embodiment, the main storage capacitor Cst is not stacked with the main thin-film transistor TFT, and the main lower electrode CE1 of the main storage capacitor Cst may be a component separate from the main gate electrode G1 of the main thin-film transistor TFT.

[0153] The auxiliary upper electrode CE2' may be stacked in the component region CA with the auxiliary gate electrode G2 disposed below the auxiliary upper electrode CE2'. The auxiliary gate electrode G2 and the auxiliary upper electrode CE2' stacked on top of each other, as well as the second insulating layer 113 disposed between the auxiliary gate electrode G2 and the auxiliary upper electrode CE2', may be included in the auxiliary storage capacitor Cst'. The auxiliary gate electrode G2 may be integrally disposed with the auxiliary lower electrode CE1' of the auxiliary storage capacitor Cst'. According to an exemplary embodiment, the auxiliary storage capacitor Cst' is not stacked with the auxiliary thin film transistor TFT', and the auxiliary lower electrode CE1' of the auxiliary storage capacitor Cst' may be a component separate from the auxiliary gate electrode G2 of the auxiliary thin film transistor TFT'.

[0154] The main upper electrode CE2 and the auxiliary upper electrode CE2' may include, for example, Al, Pt, Pd, Ag, Mg, Au, Ni, Nd, Ir, Cr, Ca, Mo, Ti, W and / or Cu, and may include a single layer or multiple layers containing the materials described above.

[0155] The third insulating layer 115 may cover the main upper electrode CE2 and the auxiliary upper electrode CE2'. The third insulating layer 115 may include, for example, SiO2 or SiN. x SiO x N y Al2O3, TiO2, Ta2O5, HfO2, or ZnO. The third insulating layer 115 may include a single layer or multiple layers containing the inorganic insulating material described above.

[0156] When the first insulating layer 112, the second insulating layer 113, and the third insulating layer 115 are collectively referred to as the inorganic insulating layer IL, the inorganic insulating layer IL may have a second hole H2 corresponding to the transmission region TA. The second hole H2 may expose a portion of the upper surface 100a of the substrate 100. When the buffer layer 111 is arranged in the transmission region TA, the second hole H2 may expose a portion of the upper surface of the buffer layer 111. The second hole H2 may be formed by openings in the first insulating layer 112, the second insulating layer 113, and the third insulating layer 115 stacked on top of each other, wherein the openings of the first insulating layer 112, the second insulating layer 113, and the third insulating layer 115 correspond to the transmission region TA. The openings may be formed individually in separate processes or simultaneously in the same process. When the openings are formed in separate processes, the inner surface of the second hole H2 may not be smooth and may have a step difference with a stepped shape.

[0157] The main source electrode S1, the auxiliary source electrode S2, the main drain electrode D1, and the auxiliary drain electrode D2 can be disposed above the third insulating layer 115. The main source electrode S1, the auxiliary source electrode S2, the main drain electrode D1, and the auxiliary drain electrode D2 can comprise conductive materials such as Mo, Al, Cu, Ti, etc., and can comprise multilayers or single layers comprising the materials described above. For example, the main source electrode S1, the auxiliary source electrode S2, the main drain electrode D1, and the auxiliary drain electrode D2 can comprise a Ti / Al / Ti multilayer structure.

[0158] The planarization layer 117 may cover the main source electrode S1 and the auxiliary source electrode S2, as well as the main drain electrode D1 and the auxiliary drain electrode D2. The planarization layer 117 may have a planarized upper surface, such that the main pixel electrode 121 and the auxiliary pixel electrode 121' disposed above the planarization layer 117 may be substantially flat.

[0159] The planarization layer 117 may comprise organic or inorganic materials and may have a single-layer or multi-layer structure. The planarization layer 117 may comprise a first planarization layer 117a and a second planarization layer 117b. Therefore, conductive patterns (such as wiring) can be formed between the first planarization layer 117a and the second planarization layer 117b, resulting in high integration.

[0160] Planarization layer 117 may include, for example, benzocyclobutene (BCB), PI, hexamethyldisiloxane (HMDSO), polymethyl methacrylate (PMMA), or general polymers (such as polystyrene (PS), polymer derivatives with phenolic groups, acrylic polymers, imide polymers, aryl ether polymers, amide polymers, fluorinated polymers, p-xylene polymers, or vinyl alcohol polymers). Planarization layer 117 may include inorganic insulating materials, such as SiO2, SiN. x SiO x N y For example, Al2O3, TiO2, Ta2O5, HfO2, or ZnO. When the planarization layer 117 is formed, chemical mechanical polishing can be performed on the upper surface of the formed layer to provide a substantially flat upper surface.

[0161] The main organic light-emitting diode (OLED) and the auxiliary organic light-emitting diode (OLED') can be disposed on the second planarization layer 117b. The main pixel electrode 121 of the main organic light-emitting diode (OLED) and the auxiliary pixel electrode 121' of the auxiliary organic light-emitting diode (OLED') can be connected to the main pixel circuit PC and the auxiliary pixel circuit PC' through the main connection electrode CM and the auxiliary connection electrode CM' disposed on the first planarization layer 117a.

[0162] The main connecting electrode CM and the auxiliary connecting electrode CM' can be disposed between the first planarization layer 117a and the second planarization layer 117b. The main connecting electrode CM and the auxiliary connecting electrode CM' can include conductive materials such as Mo, Al, Cu, Ti, etc., and can include multiple layers or a single layer containing the conductive materials described above. For example, the main connecting electrode CM and the auxiliary connecting electrode CM' can include a Ti / Al / Ti multilayer structure.

[0163] The planarization layer 117 may have a third hole H3 corresponding to the transmission region TA. The third hole H3 may be stacked with the second hole H2. Figure 9 In an exemplary embodiment, the third hole H3 is shown to be larger than the second hole H2. According to the exemplary embodiment, the planarization layer 117 can cover the edge of the second hole H2 in the inorganic insulating layer IL; therefore, the area of ​​the third hole H3 can be smaller than the area of ​​the second hole H2.

[0164] The planarization layer 117 may have vias exposing either the main source electrode S1 or the main drain electrode D1 of the main thin-film transistor TFT, and the main pixel electrode 121 may be electrically connected to the main thin-film transistor TFT by contacting the main source electrode S1 or the main drain electrode D1 through the vias. Additionally, the planarization layer 117 may have vias exposing either the auxiliary source electrode S2 or the auxiliary drain electrode D2 of the auxiliary thin-film transistor TFT', and the auxiliary pixel electrode 121' may be electrically connected to the auxiliary thin-film transistor TFT' by contacting the auxiliary source electrode S2 or the auxiliary drain electrode D2 through the vias.

[0165] The main pixel electrode 121 can be arranged on the planarization layer 117 in the main display area MDA, and the auxiliary pixel electrode 121' can be arranged on the planarization layer 117 in the component area CA.

[0166] The main pixel electrode 121 and the auxiliary pixel electrode 121' may include conductive oxides, such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), or zinc aluminum oxide (AZO). The main pixel electrode 121 and the auxiliary pixel electrode 121' may include a reflective layer comprising, for example, Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, or compounds thereof. For example, the main pixel electrode 121 and the auxiliary pixel electrode 121' may have a structure in which layers comprising ITO, IZO, ZnO, or In2O3 are disposed above / below the reflective layer described above. In this case, the main pixel electrode 121 and the auxiliary pixel electrode 121' may have a stacked structure of ITO / Ag / ITO.

[0167] The pixel defining layer 119 may cover the edges of each of the main pixel electrode 121 and the auxiliary pixel electrode 121' above the planarization layer 117, and may include a first opening OP1 and a second opening OP2 that expose at least a portion of the main pixel electrode 121 and the auxiliary pixel electrode 121'. The emission regions of the main organic light-emitting diode OLED and the auxiliary organic light-emitting diode OLED' (i.e., the size and shape of the main sub-pixel Pm and the auxiliary sub-pixel Pa) may be defined according to the first opening OP1 and the second opening OP2.

[0168] The pixel defining layer 119 can increase the distance between the edges of the main pixel electrode 121 and the auxiliary pixel electrode 121' and the counter electrode 123 on the main pixel electrode 121 and the auxiliary pixel electrode 121'. As a result, it can prevent electric arcs and the like from occurring at the edges of the main pixel electrode 121 and the auxiliary pixel electrode 121'. The pixel defining layer 119 can be formed by using, for example, a spin coating method, by using an organic insulating material (such as PI, polyamide, acrylic resin, BCB, HMDSO, phenolic resin, etc.).

[0169] The pixel defining layer 119 may have a fourth hole H4 corresponding to the transmission region TA. The fourth hole H4 may be stacked with the second hole H2 and the third hole H3. Due to the presence of the second hole H2 to the fourth hole H4, the transmittance of the transmission region TA may be increased. A portion of the counter electrode 123, which will be described below, may be disposed on the inner surface of the second hole H2 to the fourth hole H4.

[0170] The main emitting layer 122b and the auxiliary emitting layer 122b', corresponding to the main pixel electrode 121 and the auxiliary pixel electrode 121' respectively, can be arranged in the first opening OP1 and the second opening OP2 of the pixel limiting layer 119. The main emitting layer 122b and the auxiliary emitting layer 122b' can include high molecular weight materials or low molecular weight materials, and can emit red light, green light, blue light or white light.

[0171] The organic functional layer 122e may be disposed above and / or below the main emission layer 122b and the auxiliary emission layer 122b'. The organic functional layer 122e may include a first functional layer 122a and / or a second functional layer 122c. According to an exemplary embodiment, the first functional layer 122a or the second functional layer 122c may be omitted.

[0172] The first functional layer 122a may be disposed below the main emitting layer 122b and the auxiliary emitting layer 122b'. The first functional layer 122a may comprise a single layer or multiple layers containing organic materials. The first functional layer 122a may comprise a hole transport layer (HTL) having a single-layer structure. Alternatively, the first functional layer 122a may comprise a hole injection layer (HIL) and an HTL. The first functional layer 122a may integrally correspond to the main organic light-emitting diode OLED included in the main display area MDA and the auxiliary organic light-emitting diode OLED' included in the component area CA.

[0173] The second functional layer 122c may be disposed above the main emitting layer 122b and the auxiliary emitting layer 122b'. The second functional layer 122c may comprise a single layer or multiple layers containing organic materials. The second functional layer 122c may comprise an electron transport layer (ETL) and / or an electron injection layer (EIL). The second functional layer 122c may integrally correspond to the main organic light-emitting diode OLED included in the main display area MDA and the auxiliary organic light-emitting diode OLED' included in the component area CA.

[0174] Counter electrode 123 may be disposed above the second functional layer 122c. Counter electrode 123 may comprise a conductive material having a low work function. For example, counter electrode 123 may comprise a (semi-)transparent layer comprising Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li, Ca, or alloys thereof. Alternatively, counter electrode 123 may further comprise a layer disposed on the (semi-)transparent layer comprising the material described above (such as ITO, IZO, ZnO, or In2O3, for example). Counter electrode 123 may integrally correspond to a main organic light-emitting diode (OLED) included in the main display region MDA and an auxiliary organic light-emitting diode (OLED') included in the component region CA.

[0175] The layer formed between the main pixel electrode 121 and the counter electrode 123 in the main display area MDA can be included in the main organic light-emitting diode OLED. The layer formed between the auxiliary pixel electrode 121' and the counter electrode 123 in the component area CA can be included in the auxiliary organic light-emitting diode OLED'.

[0176] An upper layer 150, comprising an organic material, can be formed above the counter electrode 123. The upper layer 150 can protect the counter electrode 123 and increase light extraction efficiency. The upper layer 150 can comprise an organic material having a higher refractive index than the organic material of the counter electrode 123. Alternatively, the upper layer 150 can comprise a stack of layers with different refractive indices. For example, the upper layer 150 can be formed by comprising a stack of a high refractive index layer, a low refractive index layer, and a high refractive index layer. Here, the refractive index of the high refractive index layer can be approximately equal to or higher than 1.7, and the refractive index of the low refractive index layer can be approximately equal to or lower than 1.3. The upper layer 150 can additionally comprise LiF. Alternatively, the upper layer 150 can additionally comprise, for example, SiO2 or SiN. x and SiO x N y At least one of them. According to an exemplary embodiment, the upper layer 150 may be omitted.

[0177] In an exemplary embodiment, the organic functional layer 122e, the counter electrode 123, and the upper layer 150 are not disposed in the transmission region TA. For example, the material included in the organic functional layer 122e, the counter electrode 123, and the upper layer 150 can be formed on the entire surface of the substrate 100, and then the organic functional layer 122e, the counter electrode 123, and the upper layer 150 formed at locations corresponding to the transmission region TA can be removed using a laser ablation operation. Therefore, in the exemplary embodiment, the organic functional layer 122e, the counter electrode 123, and the upper layer 150 are not disposed in the transmission region TA. Therefore, the transmittance in the transmission region TA can be significantly increased.

[0178] Figure 12 This is a schematic cross-sectional view of a display device 1 according to an exemplary embodiment. Figure 12 Exemplary embodiments and Figure 9 The difference in the exemplary embodiments is that: Figure 12 In an exemplary embodiment, a first metal layer 105a and a second metal layer 105b having an undercut structure U are included in a metal layer 105 disposed above a first insulating layer 112. Hereinafter, for ease of explanation, the description will primarily focus on the metal layer 105. Figure 9 The differences in exemplary embodiments, and with regard to the omission of further descriptions of elements and technical aspects, may be assumed to be at least similar to the corresponding elements and technical aspects already described elsewhere in this disclosure.

[0179] Reference Figure 12The metal layer 105, including the first metal layer 105a and the second metal layer 105b, can be disposed above the lower metal layer BML. The auxiliary pixel circuit PC' can include an auxiliary thin-film transistor TFT' and an auxiliary storage capacitor Cst'. The auxiliary thin-film transistor TFT' can include an auxiliary gate electrode G2, and the auxiliary storage capacitor Cst' can include an auxiliary lower electrode CE1' and an auxiliary upper electrode CE2'. In an exemplary embodiment, the metal layer 105 can be disposed adjacent to the auxiliary thin-film transistor TFT' in the x-direction and not disposed below the auxiliary thin-film transistor TFT' in the z-direction.

[0180] Metal layer 105, including first metal layer 105a and second metal layer 105b, can be disposed on the same layer as the auxiliary thin-film transistor TFT', and can have an undercut structure U. According to an exemplary embodiment, metal layer 105 can be disposed above first insulating layer 112. Metal layer 105 can be disposed on the same layer as the auxiliary gate electrode G2 of the auxiliary thin-film transistor TFT'. Although Figure 12 An exemplary embodiment in which the metal layer 105 and the auxiliary gate electrode G2 are spaced apart from each other is shown, but this disclosure is not limited thereto. For example, according to an exemplary embodiment, the metal layer 105 and the auxiliary gate electrode G2 may be integrally formed.

[0181] As described above, metal layer 105 may include a first metal layer 105a and a second metal layer 105b. The second metal layer 105b may be disposed above the first metal layer 105a and may have an undercut structure U. The second metal layer 105b may be thicker than the first metal layer 105a. For example, the first metal layer 105a may have approximately [missing information - likely a thickness or thickness]. to approximately The thickness, and the second metal layer 105b can have approximately to approximately The thickness.

[0182] Metal layer 105 may include, for example, Al, Pt, Pd, Ag, Mg, Au, Ni, Nd, Ir, Cr, Ca, Mo, Ti, W, Cu, ITO, IZO, ZnO, In2O3, IGO, or AZO. For example, the first metal layer 105a of metal layer 105 may include at least one of Ti, Cr, ITO, IZO, ZnO, In2O3, IGO, and AZO, and the second metal layer 105b may include Mo.

[0183] Figure 13 This is a schematic cross-sectional view of a display device 1 according to an exemplary embodiment. Figure 13 Exemplary embodiments and Figure 12 The difference in the exemplary embodiments is that: Figure 13In an exemplary embodiment, a first metal layer 105a and a second metal layer 105b having an undercut structure U are included in a metal layer 105 disposed above a second insulating layer 113. Hereinafter, for ease of explanation, the description will primarily focus on the metal layer 105. Figure 12 The differences in exemplary embodiments, and with regard to the omission of further descriptions of elements and technical aspects, may be assumed to be at least similar to the corresponding elements and technical aspects already described elsewhere in this disclosure.

[0184] Reference Figure 13 The metal layer 105, including the first metal layer 105a and the second metal layer 105b, can be disposed on the same layer as the auxiliary storage capacitor Cst', and can have an undercut structure U. According to an exemplary embodiment, the metal layer 105 can be disposed above the second insulating layer 113. The metal layer 105 can be disposed on the same layer as the auxiliary upper electrode CE2' of the auxiliary storage capacitor Cst'. Although Figure 13 An exemplary embodiment is shown in which the metal layer 105 and the auxiliary upper electrode CE2' are spaced apart from each other, but this disclosure is not limited thereto. For example, according to an exemplary embodiment, the metal layer 105 and the auxiliary upper electrode CE2' may be integrally disposed.

[0185] As described above, the metal layer 105 may include a first metal layer 105a and a second metal layer 105b. The second metal layer 105b may be disposed above the first metal layer 105a and may have an undercut structure U. The second metal layer 105b may be thicker than the first metal layer 105a.

[0186] Figures 14 to 19 This is a schematic cross-sectional view illustrating a method for manufacturing a display device 1 according to an exemplary embodiment. (Refer to...) Figures 14 to 19 The described method can correspond to the formation of a reference. Figures 9 to 11 The process of the described display device 1.

[0187] In the following text, refer to Figures 14 to 19 A method for manufacturing display device 1 is described.

[0188] A method for manufacturing a display device 1 according to an exemplary embodiment may include the following steps: providing a substrate 100, the substrate 100 including a main display area MDA, a component area CA including a transmissive area TA, and a peripheral area DPA outside the main display area MDA; forming a lower metal layer BML on the upper surface of the substrate 100 in the component area CA, the lower metal layer BML including a first metal layer 105a and a second metal layer 105b; forming on the upper surface of the substrate 100 in the main display area MDA and the lower metal layer BML in the component area CA A conductive material layer 121M is formed; a main pixel electrode 121 and an auxiliary pixel electrode 121' are formed by removing at least a portion of the conductive material layer 121M; a second metal layer 105b corresponding to the transmission region TA is removed; an organic functional layer 122e, a counter electrode 123, and an upper layer 150 are formed on the entire surface of the substrate 100 to cover the main pixel electrode 121, the auxiliary pixel electrode 121', and the first metal layer 105a; and a laser beam is used to irradiate the lower surface of the substrate 100, which is opposite to the upper surface of the substrate 100 in the transmission region TA.

[0189] Reference Figure 14 It can perform the provision of a substrate 100 including a main display area MDA, a component area CA including a transmissive area TA, and a peripheral area DPA outside the main display area MDA, and form a lower metal layer BML on the upper surface of the substrate 100 in the component area CA, the lower metal layer BML including a first metal layer 105a and a second metal layer 105b.

[0190] Forming a lower metal layer (BML) including a first metal layer 105a and a second metal layer 105b on the upper surface of a substrate 100 in the component region CA may include the following steps: forming a first metal layer 105a on the substrate 100 to have a first thickness t1 in the z-direction (e.g., the thickness direction of the display device 1), and forming a second metal layer 105b on the first metal layer 105a to have a second thickness t2 in the z-direction (e.g., the thickness direction of the display device 1). The second thickness t2 of the second metal layer 105b may be greater than the first thickness t1 of the first metal layer 105a. For example, the first thickness t1 may be approximately to approximately And the second thickness t2 can be approximately to approximately

[0191] After forming a lower metal layer BML including a first metal layer 105a and a second metal layer 105b on the upper surface of the substrate 100 in the component region CA, a main pixel circuit PC can be formed on the upper surface of the substrate 100 in the main display region MDA, and an auxiliary pixel circuit PC' can be formed on the lower metal layer BML in the component region CA.

[0192] The main pixel circuit PC may include a main thin-film transistor TFT and a main storage capacitor Cst, and the auxiliary pixel circuit PC' may include an auxiliary thin-film transistor TFT' and an auxiliary storage capacitor Cst'.

[0193] The lower metal layer BML and the auxiliary pixel circuit PC' disposed in the component region CA can be stacked on top of each other. The lower metal layer BML can be disposed below the auxiliary pixel circuit PC' and can prevent the characteristics of the auxiliary thin film transistor TFT' from being degraded due to light emitted from the component, etc.

[0194] A planarization layer 117 can be formed on the main pixel circuit PC and the auxiliary pixel circuit PC'. The planarization layer 117 can cover the main pixel circuit PC and the auxiliary pixel circuit PC'.

[0195] Reference Figure 15 After forming a main pixel circuit PC on the upper surface of the substrate 100 in the main display area MDA and forming an auxiliary pixel circuit PC' on the lower metal layer BML in the component area CA, a conductive material layer 121M can be formed on the upper surface of the substrate 100 in the main display area MDA and on the lower metal layer BML in the component area CA.

[0196] A conductive material layer 121M can be formed on the entire surface of the substrate 100. For example, the conductive material layer 121M can be formed on the planarization layer 117 in the main display region MDA and the component region CA, and the conductive material layer 121M can be formed on the second metal layer 105b of the lower metal layer BML in the transmission region TA. The conductive material layer 121M may include a reflective layer, wherein the reflective layer may include a conductive oxide (such as ITO, IZO, ZnO, In2O3, IGO, and AZO, for example), or Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, or Cr, or a mixture thereof.

[0197] Reference Figure 16 After forming a conductive material layer 121M on the upper surface of the substrate 100 in the main display area MDA and the lower metal layer BML in the component area CA, the main pixel electrode 121 and the auxiliary pixel electrode 121' can be formed by removing at least a portion of the conductive material layer 121M, and the second metal layer 105b disposed in the transmission area TA can be removed.

[0198] The step of forming the main pixel electrode 121 and the auxiliary pixel electrode 121' by removing at least a portion of the conductive material layer 121M and the second metal layer 105b corresponding to the transmission region TA may include forming the main pixel electrode 121 and the auxiliary pixel electrode 121' by etching the conductive material layer 121M formed on the entire surface of the substrate 100. For example, the main pixel electrode 121 and the auxiliary pixel electrode 121' may be formed by wet etching the conductive material layer 121M disposed in the main display region MDA and the component region CA.

[0199] When etching the conductive material layer 121M formed on the entire surface of the substrate 100, the second metal layer 105b formed in the transmission region TA can also be etched. The second metal layer 105b formed in the transmission region TA can be removed by wet etching. The undercut structure U can be formed in the second metal layer 105b by anisotropic etching. Because the second metal layer 105b disposed in the transmission region TA is removed by wet etching, the upper surface of the first metal layer 105a disposed below the second metal layer 105b in the transmission region TA is exposed to the outside.

[0200] Reference Figure 17 After forming the main pixel electrode 121 and the auxiliary pixel electrode 121' by removing at least a portion of the conductive material layer 121M and removing the second metal layer 105b corresponding to the transmission region TA, an organic functional layer 122e, a counter electrode 123 and an upper layer 150 can be formed on the entire surface of the substrate 100 to cover the main pixel electrode 121 and the auxiliary pixel electrode 121' as well as the first metal layer 105a.

[0201] The organic functional layer 122e, the counter electrode 123, and the upper layer 150 can integrally correspond to the main organic light-emitting diode (OLED) included in the main display region MDA and the auxiliary organic light-emitting diode (OLED) included in the component region CA. The organic functional layer 122e, the counter electrode 123, and the upper layer 150 can be formed on the upper surface of the first metal layer 105a in the transmission region TA, and this upper surface is exposed to the outside.

[0202] However, according to an exemplary embodiment, the materials included in the organic functional layer 122e, the counter electrode 123, and the upper layer 150 may be thinly formed or not formed on the inner surfaces of the inorganic insulating layer IL, the planarization layer 117, and the pixel defining layer 119 in the transmission region TA, and at least a portion of these materials are removed.

[0203] Reference Figure 18After forming an organic functional layer 122e, a counter electrode 123, and an upper layer 150 on the entire surface of the substrate 100 to cover the main pixel electrode 121 and the auxiliary pixel electrode 121' and the first metal layer 105a, the lower surface opposite to the upper surface of the substrate 100 corresponding to the transmission region TA can be irradiated with a laser beam.

[0204] When the organic functional layer 122e, the counter electrode 123, and the upper layer 150 are formed in the transmission region TA, the transmittance of the transmission region TA may decrease significantly. Therefore, in order to increase the transmittance of the transmission region TA, the organic functional layer 122e, the counter electrode 123, and the upper layer 150 formed on the upper surface of the first metal layer 105a formed in the transmission region TA can be removed. For example, the organic functional layer 122e, the counter electrode 123, and the upper layer 150 formed in the transmission region TA can be removed using a laser beam.

[0205] When the organic functional layer 122e, counter electrode 123 and upper layer 150 formed in the transmission region TA are removed by using a laser beam, only the counter electrode 123 and upper layer 150 can be removed, and the organic functional layer 122e can be left unremoved and remain, thus degrading the transmittance of the transmission region TA.

[0206] Additionally, when a portion of the conductive material layer 121M included in the pixel electrode is allowed to remain in the transmission region TA, and when the remaining conductive material layer 121M is used as a sacrificial layer and the organic functional layer 122e, counter electrode 123, and upper layer 150 formed in the transmission region TA are removed using a laser beam, a portion of the conductive material layer 121M may remain, and particles may be generated on the sidewall portion of the transmission region TA. For example, when the conductive material layer 121M includes Ag, Ag has a low melting point; therefore, a lower energy laser beam can be used, which will generate Ag particles.

[0207] The lower metal layer (BML) can be disposed in the component region (CA) excluding the transmissive region (TA). The lower metal layer (BML) can prevent the characteristics of the auxiliary thin-film transistor (TFT) from deteriorating due to light emitted from the component, etc., and can prevent light emitted from or traveling toward the component from diffracting through the small gaps between the wirings connected to the auxiliary pixel circuit (PC). However, when the lower metal layer (BML) has a small thickness, it may not sufficiently prevent the deterioration of the characteristics of the auxiliary thin-film transistor (TFT) and the diffracting of light through the small gaps between the wirings connected to the auxiliary pixel circuit (PC).

[0208] When the organic functional layer 122e, counter electrode 123 and upper layer 150 formed in the transmission region TA are removed by laser ablation using a sacrificial layer, the time period for applying the laser beam increases when the sacrificial layer has a large thickness.

[0209] According to exemplary embodiments of the present disclosure, the lower metal layer (BML) may include a first metal layer 105a and a second metal layer 105b, the first metal layer 105a and the second metal layer 105b comprising different materials from each other, wherein the second metal layer 105b has a greater thickness than the first metal layer 105a. Therefore, degradation of the thin-film transistor and diffraction of light between wirings can be prevented based on the lower metal layer (BML) formed in the component region CA, excluding the transmission region TA.

[0210] Furthermore, because the second metal layer 105b in the transmission region TA is etched along with the conductive material layer 121M, only the first metal layer 105a can remain in the transmission region TA. Therefore, by using the first metal layer 105a, which has a thickness smaller than that of the second metal layer 105b, as a sacrificial layer, the organic functional layer 122e, the counter electrode 123, and the upper layer 150 formed in the transmission region TA can be removed by irradiating the lower surface of the substrate 100 with a laser beam.

[0211] like Figure 19 As shown, since the first metal layer 105a formed in the transmission region TA can be removed by laser ablation, the organic functional layer 122e, the counter electrode 123, and the upper layer 150 formed on the first metal layer 105a can also be removed together. Because the organic functional layer 122e, the counter electrode 123, and the upper layer 150 formed in the transmission region TA can be removed, the transmittance of the transmission region TA can be increased.

[0212] Because the first metal layer 105a in the transmission region TA is removed, the first hole H1 can be defined in the lower metal layer BML in the component region CA. For example, the first hole H1 can be defined in the first metal layer 105a retained in the component region CA.

[0213] As described above, according to one or more exemplary embodiments of the present disclosure, a display device having a component area in a display area in which various types of components are arranged, and a method of manufacturing such a display device, can be implemented. However, the scope of the present disclosure is not limited thereto.

[0214] Although this disclosure has been specifically shown and described with reference to exemplary embodiments thereof, those skilled in the art will understand that various changes in form and detail may be made therein without departing from the spirit and scope of this disclosure as defined by the claims.

Claims

1. A display device, the display device comprising: The substrate includes a main display area, a component area, and a peripheral area, wherein the component area includes a transmissive area, and the peripheral area is arranged outside the main display area; The main thin-film transistor is arranged in the main display area; A main organic light-emitting diode is arranged in the main display area and connected to the main thin-film transistor; Auxiliary thin-film transistors are arranged in the component region; An auxiliary organic light-emitting diode is disposed in the component region and connected to the auxiliary thin-film transistor; and The lower metal layer, disposed in the component region between the substrate and the auxiliary thin-film transistor, comprises two layers in direct contact with each other and has an undercut structure.

2. The display device according to claim 1, wherein, The lower metal layer includes a first metal layer having a first thickness in the thickness direction of the display device and a second metal layer having a second thickness in the thickness direction of the display device. The second thickness is greater than the first thickness.

3. The display device according to claim 2, wherein, The first thickness is 200 Å to 400 Å, and the second thickness is 2500 Å to 3500 Å.

4. The display device according to claim 2, wherein, The lower metal layer includes a first hole corresponding to the transmission region.

5. The display device according to claim 2, wherein, The second metal layer has the undercut structure.

6. The display device according to claim 2, wherein, The first metal layer includes at least one of Ti, Cr, ITO, IZO, ZnO, In2O3, IGO, and AZO.

7. The display device according to claim 2, wherein, The second metal layer comprises Mo.

8. The display device according to claim 1, wherein, The lower metal layer is disposed directly on the upper surface of the substrate.

9. The display device according to claim 1, wherein, The lower metal layer and the auxiliary thin-film transistor are at least partially stacked on top of each other.

10. The display device according to claim 1, further comprising: An encapsulation substrate is disposed above the substrate.

11. The display device according to claim 1, further comprising: Components are arranged below the substrate in the component region.

12. The display device according to claim 11, wherein, The components include imaging devices or sensors.

13. A display device, the display device comprising: The substrate includes a main display area, a component area, and a peripheral area, wherein the component area includes a transmissive area, and the peripheral area is arranged outside the main display area; The main thin-film transistor is arranged in the main display area; A main organic light-emitting diode is arranged in the main display area and connected to the main thin-film transistor; Auxiliary thin-film transistors are arranged in the component region; An auxiliary organic light-emitting diode is disposed in the component region and connected to the auxiliary thin-film transistor; A lower metal layer is disposed in the component region between the substrate and the auxiliary thin-film transistor; and A metal layer, disposed on the lower metal layer, has an undercut structure, is disposed adjacent to the auxiliary thin-film transistor in the horizontal direction, and is not disposed below the auxiliary thin-film transistor in the thickness direction of the display device.

14. The display device according to claim 13, further comprising: Auxiliary storage capacitors are arranged in the component area. The auxiliary thin-film transistor includes an auxiliary gate electrode, and the auxiliary storage capacitor includes an auxiliary lower electrode and an auxiliary upper electrode.

15. The display device according to claim 14, wherein, The metal layer includes a first metal layer and a second metal layer disposed on the first metal layer and having the undercut structure.

16. The display device according to claim 15, wherein, The metal layer and the auxiliary gate electrode are arranged on the same layer.

17. The display device according to claim 15, wherein, The metal layer and the auxiliary upper electrode are arranged on the same layer.

18. A method for manufacturing a display device, the method comprising the following steps: A lower metal layer is formed on the upper surface of a substrate, wherein the substrate includes a main display area, a component area, and a peripheral area, wherein the component area includes a transmissive area, and the peripheral area is disposed outside the main display area, wherein the lower metal layer is formed in the component area, and the lower metal layer includes a first metal layer and a second metal layer that are in direct contact with each other. A conductive material layer is formed on the substrate in the main display area and on the lower metal layer in the component area; A pixel electrode is formed by removing at least a portion of the conductive material layer and the second metal layer is removed from the transmission region; An organic functional layer, a counter electrode, and an upper layer are formed on the entire upper surface of the substrate, wherein the organic functional layer, the counter electrode, and the upper layer cover the pixel electrode and the first metal layer; and A laser beam is used to irradiate the lower surface of the substrate, which is opposite the upper surface of the substrate, in the transmission region.

19. The method according to claim 18, wherein, The steps of forming a pixel electrode by removing at least a portion of the conductive material layer and removing the second metal layer from the transmissive region include: At least a portion of the conductive material layer is removed by wet etching, and the second metal layer is removed from the transmission region.

20. The method according to claim 19, further comprising: An undercut structure is formed in the second metal layer by the wet etching process.

21. The method according to claim 18, wherein, The step of forming the lower metal layer comprising the first metal layer and the second metal layer includes: A first metal layer having a first thickness is formed in the thickness direction of the display device; and A second metal layer having a second thickness is formed in the thickness direction of the display device. The second thickness is greater than the first thickness.

22. The method according to claim 21, wherein, The first thickness is 200 Å to 400 Å, and the second thickness is 2500 Å to 3500 Å.

23. The method according to claim 21, wherein, The first metal layer includes at least one of Ti, Cr, ITO, IZO, ZnO, In2O3, IGO, and AZO.

24. The method according to claim 21, wherein, The second metal layer comprises Mo.

25. The method according to claim 21, wherein, The lower metal layer is formed directly on the upper surface of the substrate.

26. The method according to claim 18, wherein, The first metal layer, the organic functional layer, the counter electrode, and the upper layer formed on the upper surface of the substrate in the transmission region are removed by irradiating the lower surface of the substrate opposite to the upper surface of the substrate in the transmission region with a laser beam.

27. The method according to claim 26, wherein, The lower metal layer includes a first hole corresponding to the transmission region.

28. The method according to claim 18, further comprising: After the lower metal layer is formed on the upper surface of the substrate in the component region and before the conductive material layer is formed on the substrate in the main display region and on the lower metal layer in the component region, a main thin-film transistor is formed on the substrate in the main display region and an auxiliary thin-film transistor is formed on the lower metal layer in the component region.

29. The method according to claim 28, wherein, The lower metal layer and the auxiliary thin-film transistor are at least partially stacked on top of each other.

30. The method according to claim 18, wherein, Components are further arranged on the lower surface of the substrate in the component region, and The components include imaging devices or sensors.

Images