Image generation using one or more neural networks

Abstract

Image generation using one or more neural networks is disclosed, specifically, apparatus, systems, and techniques for generating view-specific representations of objects or environments are presented. In at least one embodiment, one or more neural networks are used to generate one or more images based at least in part on two or more two-dimensional (2D) images having different reference frames.

Description

Technical Field

[0001] At least one embodiment relates to processing resources for performing and facilitating artificial intelligence. For example, at least one embodiment relates to a processor or computing system for training neural networks according to the various novel techniques described herein. Background Technology

[0002] Automation is being used to perform an ever-growing variety of tasks. In many cases, this automation relies on cameras and sensors to obtain information about its environment, which helps the automation determine its path of movement and avoid collisions. Existing systems typically utilize a fixed number and orientation of cameras and sensors that also provide depth information. The increasing variety of automation is accompanied by a growing variation in the number and placement of cameras and sensors, which may or may not provide depth information. This depth information will then require the development of custom systems for each type of automation. For many applications, such customization can be costly, or at least delay implementation and require additional maintenance and complexity. Such systems will also have to be updated for any changes in the cameras or sensors. Attached Figure Description

[0003] Various embodiments according to this disclosure will be described with reference to the accompanying drawings, in which:

[0004] Figure 1A , Figure 1B , Figure 1C , Figure 1D , Figure 1E and Figure 1F Images according to at least one embodiment are shown;

[0005] Figure 2 An automated system according to at least one embodiment is shown;

[0006] Figure 3 Components of an image view generator according to at least one embodiment are shown;

[0007] Figure 4A , Figure 4B , Figure 4C and Figure 4D Data of an image in a common reference frame according to at least one embodiment is shown;

[0008] Figure 5A and Figure 5B The process for generating an image view according to at least one embodiment is shown;

[0009] Figure 6A The inference and / or training logic according to at least one embodiment is illustrated;

[0010] Figure 6B The inference and / or training logic according to at least one embodiment is illustrated;

[0011] Figure 7 An example data center system according to at least one embodiment is shown;

[0012] Figure 8 A computer system according to at least one embodiment is shown;

[0013] Figure 9 A computer system according to at least one embodiment is shown;

[0014] Figure 10 A computer system according to at least one embodiment is shown;

[0015] Figure 11 A computer system according to at least one embodiment is shown;

[0016] Figure 12A A computer system according to at least one embodiment is shown;

[0017] Figure 12B A computer system according to at least one embodiment is shown;

[0018] Figure 12C A computer system according to at least one embodiment is shown;

[0019] Figure 12D A computer system according to at least one embodiment is shown;

[0020] Figure 12E and Figure 12F A shared programming model according to at least one embodiment is shown;

[0021] Figure 13 An exemplary integrated circuit and an associated graphics processor according to at least one embodiment are shown;

[0022] Figures 14A-14B An exemplary integrated circuit and an associated graphics processor according to at least one embodiment are shown;

[0023] Figures 15A-15B Additional exemplary graphics processor logic according to at least one embodiment is shown;

[0024] Figure 16 A computer system according to at least one embodiment is shown;

[0025] Figure 17A A parallel processor according to at least one embodiment is shown;

[0026] Figure 17BA partitioning unit according to at least one embodiment is shown;

[0027] Figure 17C A processing cluster according to at least one embodiment is shown;

[0028] Figure 17D A graphics multiprocessor according to at least one embodiment is shown;

[0029] Figure 18 A multi-graphics processing unit (GPU) system according to at least one embodiment is illustrated;

[0030] Figure 19 A graphics processor according to at least one embodiment is shown;

[0031] Figure 20 The microarchitecture of a processor according to at least one embodiment is shown;

[0032] Figure 21 A deep learning application processor according to at least one embodiment is shown;

[0033] Figure 22 An example neuromorphic processor according to at least one embodiment is shown;

[0034] Figure 23 and Figure 24 At least a portion of a graphics processor according to at least one embodiment is shown;

[0035] Figure 25 At least a portion of a graphics processor core according to at least one embodiment is shown;

[0036] Figures 26A-26B At least a portion of a graphics processor core according to at least one embodiment is shown;

[0037] Figure 27 A parallel processing unit (“PPU”) according to at least one embodiment is shown;

[0038] Figure 28 A general-purpose processing cluster (“GPC”) according to at least one embodiment is illustrated;

[0039] Figure 29 A memory partition unit of a parallel processing unit (“PPU”) according to at least one embodiment is shown;

[0040] Figure 30 A streaming multiprocessor according to at least one embodiment is illustrated;

[0041] Figure 31 This is an example data flow diagram for an advanced computing pipeline according to at least one embodiment;

[0042] Figure 32 This is a system diagram of an example system for training, adapting, instantiating, and deploying machine learning models in an advanced computing pipeline, according to at least one embodiment.

[0043] Figure 33A A data flow diagram illustrating a process for training a machine learning model according to at least one embodiment is shown;

[0044] Figure 33B This is an example illustration of a client-server architecture for enhancing annotation tools using a pre-trained annotation model, according to at least one embodiment.

[0045] Figure 34A An example of an autonomous vehicle according to at least one embodiment is shown;

[0046] Figure 34B According to at least one embodiment, it is shown that Figure 34A Examples of camera positions and field of view for autonomous vehicles;

[0047] Figure 34C A method for illustrating at least one embodiment is shown. Figure 34A An example system architecture for autonomous vehicles; and

[0048] Figure 34D The diagram illustrates a method for connecting to one or more cloud-based servers according to at least one embodiment. Figure 34A A system for communication between autonomous vehicles. Detailed Implementation

[0049] In at least one embodiment, information about a scene, object, or environment can be determined using one or more captured images of different views of the scene, object, or environment. In at least one embodiment, these images can be two-dimensional images captured by one or more cameras or sensors. In at least one embodiment, a device such as a camera assembly can include any or a variable number of cameras (or sensors or other image capturing elements) located and oriented in various positions. In at least one embodiment, these cameras can each capture a corresponding view, such as... Figure 1A , Figure 1B and Figure 1CThe captured images 100, 110, and 120 are shown. In at least one embodiment, these images each show a different two-dimensional view of the three-dimensional environment in which the device is located. In at least one embodiment, it may be desirable to use these two-dimensional images to determine three-dimensional information about the environment. In at least one embodiment, one or more neural networks may be used to process these images 100, 110, and 120 to generate at least one image 130 showing objects in the environment from a single or common coordinate system or reference frame. In at least one embodiment, one or more neural networks may utilize features of these images to also generate at least one image 140, which includes depth information inferred from these two-dimensional images and corresponds to this view in a single reference frame. In at least one embodiment, this depth information from the single reference frame can be used to generate a three-dimensional representation of the environment. In at least one embodiment, this may include a point cloud in a common coordinate system, wherein the positions of those points are determined by placing these two-dimensional images into the three-dimensional coordinate system. In at least one embodiment, this three-dimensional information can be used to generate one or more views of the environment, such as a top view 150, or a "bird's-eye view" showing the positions of different objects (e.g., vehicle 152) relative to the device or a set of cameras that captured these images. In at least one embodiment, such views can be provided to controllable or at least partially automated devices or systems, such as robots, unmanned aircraft, or autonomous vehicles.

[0050] In at least one embodiment, different types of cameras 206, 208, 212, or imaging sensors 210 may be present in the components of camera equipment 204 or automation system 202, such as those that may be included in or communicate with a device or system to be controlled by the automation system. In at least one embodiment, these cameras may be of any number or may vary depending on the equipment, components, or other such groupings. In at least one embodiment, this may include cameras and sensors with different resolutions, color depths, optical capabilities, and other such aspects. In at least one embodiment, one or more of these cameras or sensors may also provide three-dimensional data or depth information. In at least one embodiment, these cameras and sensors may be positioned at a variety of potential locations and orientations. In at least one embodiment, this may result in different cameras or sensors providing data in different coordinate systems or reference frames. In at least one embodiment, images (or video or other image data) captured by these images may be provided to image processing system 214. In at least one embodiment, the image processing system 214 may include one or more neural networks for analyzing these images and generating one or more images or representations. In at least one embodiment, these representations may reside in a single or common coordinate system or reference frame. In at least one embodiment, this can be achieved by determining the positions of these two-dimensional images in the common reference frame and subsequently inferring the projection of the features of these images into the three dimensions of the reference frame, as can be implemented using one or more neural networks 216. In at least one embodiment, calibration parameters such as known intrinsic and extrinsic parameters for each of these cameras and sensors 206, 208, 210, 212 can be used by these neural networks to place and project these points into the common reference frame. In at least one embodiment, camera intrinsic or extrinsic parameters represent the position of the camera in the three-dimensional scene, and may include rotation and translation, while camera intrinsic or extrinsic parameters may represent aspects such as the camera's optical center and focal length.

[0051] In at least one embodiment, the image or data generated in the reference frame may be provided to the control system 220 to determine actions to be taken by one or more controllable subsystems 220 of the automation system 202. In at least one embodiment, this may include determining the position of objects in the environment and determining one or more movements of the system to avoid or interact with one or more of those objects. In at least one embodiment, device data 224 may be used to enable the control system 220 to use the object position data to provide appropriate instructions to the controllable subsystems 220 to perform one or more tasks. In at least one embodiment, at least some of the image processing or control determination may be performed by a cloud server 280 or other such systems or services, as can be transmitted using at least one network 240 (e.g., wired or wireless network). In at least one embodiment, the cloud server may include a control application 284 capable of performing at least some of these tasks, such as a session manager for managing control sessions of the automation system 202, a device manager 290 for storing information for the automation system 202, an image processor 292 for processing image data from the automation system 202, and a control manager 288 for generating control instructions based on the captured and processed image data. In at least one embodiment, the cloud server 280 also stores device data 294 and user data 292 to support these and other such tasks. In at least one embodiment, the automation system 202 may not use the cloud server 280 for any of these specific tasks, but may submit data via the network 240 for other reasons (such as for logging, historical data storage, or troubleshooting).

[0052] In at least one embodiment, a key objective of the automated system (such as an autonomous vehicle) is to incorporate semantic representations extracted from raw sensor data into a single "bird's-eye view" coordinate frame for consumption by motion planning. In at least one embodiment, methods such as... Figure 3The illustrated end-to-end architecture 300 can generate a top-down or bird's-eye view representation of a scene given image data from any number of cameras or sensors. In at least one embodiment, this may include individually boosting each image into a frustum of features from each camera. In at least one embodiment, these frustums can then be placed or projected onto a rasterized bird's-eye view mesh. In at least one embodiment, training the entire camera assembly can allow learning not only how to represent images, but also how to fuse predictions from any or all available cameras into a single cohesive representation of the scene, while being robust to calibration errors. In at least one embodiment, the top-down view can be useful for tasks such as object segmentation and map segmentation. In at least one embodiment, such a representation inferred by a model (such as a deep learning model) enables the training of an end-to-end motion plan using expert driving trajectories.

[0053] In at least one embodiment, the neural network architecture 300 of the view generator 308 can be utilized, which includes two large network backbones, such as Figure 3As shown. In at least one embodiment, these backbones may include feature extractor networks, such as convolutional neural networks (CNNs), which can compute features from any number n input images 302, 304, 306, such as features that can be upsampled by a decoder to generate a mask or representation. In at least one embodiment, the first backbone may include a feature extractor network 310, which can operate individually on each image to characterize a point cloud generated from each input image 302. In at least one embodiment, a second backbone can operate on the point cloud once it has been projected onto a pillar in a reference frame. In at least one embodiment, the two networks may be joined by common layers as discussed elsewhere herein. In at least one embodiment, the first feature extractor network 310 can operate individually on each image and may utilize layers from the network, such as EfficientNet-BO, a model pre-trained on ImageNet for including a baseline. In at least one embodiment, ResNet or a similar network may be used instead of EfficientNet. In at least one embodiment, a second network, referred to herein as a bird's-eye view network, may utilize a combination of ResNet blocks. In at least one embodiment, after convolution with kernel 7 and stride 2, followed by batch normalization and ReLU or other activations, images 314 can be passed through the first three meta-layers of ResNet-18 to obtain one or more images 314 with a specific view, such as three different bird's-eye view representations at different resolutions x1, x2, and x3. In at least one embodiment, x3 can be scaled up by a factor of 4, concatenated with x1, a ResNet block applied, and finally upsampled by 2 to return to the resolution of the original input bird's-eye view pseudo-image. In at least one embodiment, a large number of trainable parameters may exist in the final network, such as 14.3 million trainable parameters.

[0054] In at least one embodiment, several hyperparameters may exist that determine the resolution of the model. In at least one embodiment, the hyperparameters may correspond to the size H x W of the input image. In at least one embodiment, the input image may be resized and cropped, such as resized to 128x352 pixels, where the eigenvalues ​​and intrinsic 316 stored for these cameras and sensors are transformed accordingly. In at least one embodiment, another important hyperparameter of this network is related to the size and resolution of the bird's-eye view grid X x Y. In at least one embodiment, bin (binary) may be set to both x and y from -50 meters to 50 meters, where the cells have a size of 0.5 meters x 0.5 meters. In at least one embodiment, the resulting grid may be 200x200. In at least one embodiment, the choice of D may determine the resolution of the depth predicted by the network. In at least one embodiment, the value of D may be constrained, for example, between 4.0 meters and 45.0 meters at intervals of 1.0 meters. In at least one embodiment, utilizing these hyperparameters and architecture design choices, the model's forward pass can run at 35 Hz on a Titan X GPU.

[0055] In at least one embodiment, such a system can be used to encode any camera array, which may correspond to a camera setup, into a single representation of a scene or environment. In at least one embodiment, this can be a “bird’s-eye view” obtained from a viewpoint above multiple objects in the environment, or a view corresponding to another defined viewpoint. In at least one embodiment, this can be performed using images of objects or the environment that consist only of two-dimensional data, or other types of captured data, although in at least one embodiment, one or more image or data types may include two-dimensional or three-dimensional data. In at least one embodiment, where a given two-dimensional camera and sensor do not provide depth information, such a method can overcome the difficulty of converting two-dimensional images from an arbitrary number of cameras into a single representation (such as a bird’s-eye view representation). In at least one embodiment, a characteristic point cloud can be generated, which comprises three-dimensional points in a coordinate frame local to each pixel of each camera. In at least one embodiment, these point clouds can then be accumulated in a world frame using the eigenvalues ​​and eigenvalues ​​of the respective cameras or sensors. In at least one embodiment, such a method can be scaled to an arbitrary number of cameras in any number of positions and orientations. In at least one embodiment, such a method enables the reasoning of the pose of a 3D structure for applications such as autonomous navigation or robotics using only two-dimensional camera or sensor data.

[0056] In at least one embodiment, a single representation of the scene can be generated from image data captured by any appropriate number of cameras. In at least one embodiment, for purposes of discussion, quantities in the reference frame coordinate system are specified using hat symbols. In at least one embodiment, images may have different dimensions, but for simplicity of explanation, at least some examples and discussions herein assume that images have the same dimensions. In at least one embodiment, the system has multiple cameras n, each camera providing an image for a single time point. In at least one embodiment, this results in receiving n images. Each image has an eigenvalue matrix. and eigenmatrix In at least one embodiment, an attempt is made to determine a reference coordinate frame (such as a bird's-eye view coordinate frame). The rasterized representation of the scene in the reference coordinates. In at least one embodiment, the eigenma and the eigenma together define the rasterized representation of the scene in the reference coordinates. A mapping to the local pixel coordinates (h, w, d) of each of the n cameras. In at least one embodiment, no access to any type of depth sensor or data is required during training or inference.

[0057] In at least one embodiment, the first stage of the deep learning model can operate on each image individually. In at least one embodiment, this allows each image to be lifted from a two-dimensional coordinate system to a three-dimensional reference frame or coordinate system shared across all cameras providing image data of the relevant object or environment. In at least one embodiment, the depth information associated with the individual pixels of these two-dimensional images will be blurred, and such a model can be used to generate representations for each pixel at any or all possible depths. In at least one embodiment, It is an image with non-intrinsic E and intrinsic I, and p i ∈X represents a pixel in the image with image coordinates (h,w). In at least one embodiment, each pixel is associated with a |D| point and pixel {(h,w,d)|d∈D} on a ray passing through the origin of this camera, where D is a set of discrete depths, such as that which can be defined by {d0+Δ,…,d0+|D|Δ}. In at least one embodiment, there are no learnable parameters in this transformation, where a large point cloud is generated for a given image of size D x H x W.

[0058] In at least one embodiment, the point cloud is defined within a desired reference frame, but not in any way conditional on the content of the image. In at least one embodiment, the dependency on content can be achieved by training the network f θ To model and infer the point cloud p i,d The context vector of each point in In at least one embodiment, the context vector is parameterized to match the attention concept and discrete deep inference. At each pixel, the network predicts the context for that pixel. and depth distribution In at least one embodiment, for p o The generated point at depth d can be represented by the following formula:

[0059]

[0060] In at least one embodiment, if this network is to predict the one-hot vector of l, then the vector from pixel p... i The context will only be non-zero at a single depth, as in pseudo-LiDAR. In at least one embodiment, if the network predicts a uniform distribution over depth, then the network will predict pixel p. i The same depth-independent representation. In at least one embodiment, the network can then be able to choose between placing the context from the image at a specific location in a single bird's-eye view representation and expanding that context across a spatial ray (where depth might be ambiguous). In at least one embodiment, the same representation can be used for each image generation function g that can be queried at any spatial location and returns a context vector. c : In at least one embodiment, in order to utilize discrete convolution, the system can instead discretize the space. In at least one embodiment, the spatial volume visible to a given camera can correspond to a cone.

[0061] In at least one embodiment, the initial network stage can generate a point cloud with n x H x W x D points, each point having an associated context vector of dimension C. In at least one embodiment, this point cloud differs fundamentally from a LiDAR point cloud in that the spatial density of the points is independent of semantics. In at least one embodiment, the point cloud can be transformed into a representation well-suited for efficient 2D convolutional neural networks (CNNs). In at least one embodiment, a pillar can be used to refer to a voxel with infinite height. In at least one embodiment, each point can be assigned to its nearest pillar and sum pooling is performed to create a C x H x W tensor, which can be processed by a standard CNN for bird's-eye view inference.

[0062] In at least one embodiment, such as Figures 4A to 4D The data for these steps can be visualized as shown. In at least one implementation, Figure 4AGraph 400 illustrates a representation of six two-dimensional images positioned or lifted into a single coordinate frame or reference frame. In at least one embodiment, this may include using camera eigenvalues ​​and eigenvalues ​​with a neural network to determine the appropriate placement of each of these images into this reference frame. In at least one embodiment, a cone-shaped point cloud is predicted for each image, such that the density depends only on the calibration of the respective camera and is independent of the semantics of the image. In at least one embodiment, in Figure 4A The union of point clouds from all six cameras is visualized in 3D. In at least one embodiment, a corresponding point cloud can then be generated to... Figure 4B The XY plane 420 is neutralized to Figure 4C Different projections of the projection in the XZ plane 440. In at least one embodiment, Figure 4D Figure 460 illustrates the result of projecting these features onto a common reference frame. In at least one embodiment, this corresponds to discretizing a first plane (such as the xy plane) of the reference frame and performing pooling on the features of all points in this point cloud within each grid cell. In at least one embodiment, height information may not be lost in this transformation, thus creating a large point cloud for a given image of size D x H x W.

[0063] In at least one embodiment, a method can be used to accelerate pooling. In at least one embodiment, efficiency may be important for training the model given the size of the generated point cloud (B x N x D x H x W for batch size B). In at least one embodiment, given a point cloud of N points, each point has a D-dimensional geometric location. right C-dimensional context and bin ID for encoding These points can be classified such that all points with the same bin ID are adjacent to each other. In at least one embodiment, pooling can then be performed by computing the cumulative sum of all context vectors in this point cloud and evaluating the difference between the cumulative sums at the endpoints of each bin ID. In at least one embodiment, this operation has an analytical gradient that can be efficiently computed to accelerate automatic differentiation, such as by using PyTorch's autograd.

[0064] In at least one embodiment, such a model can provide end-to-end cost graph learning for motion planning from camera input. In at least one embodiment, inference time planning can be achieved by projecting different trajectories, scoring the relative costs of those trajectories, and then performing an action based on the lowest-cost trajectory. In at least one embodiment, this is performed using a trajectory determination network 318, which is capable of inferring an optimal trajectory from a set of possible trajectories and outputting the corresponding trajectory data 320. In at least one embodiment, this can provide accurate end-to-end interpretable motion planning. In at least one embodiment, planning may involve predicting the distribution of the vehicle on the trajectory, as can be given by:

[0065] τ={τ i} K ={{x j ,y j ,t j}T}k

[0066] In at least one embodiment, this can be adjusted based on sensor observations p(τo). In at least one embodiment, the planning can be constructed as a classification of a set of K template trajectories. In at least one embodiment, to take advantage of the cost-volume nature of the planning problem, the distribution on the K template trajectories can be implemented to take a specified form, as can be given by the following equation:

[0067]

[0068] c(.o) is learned from the data by optimizing the log probability of the expert trajectory.

[0069] In at least one embodiment, for a label and given a ground truth trajectory, the nearest neighbor trajectory can be computed in the L2 distance from the template trajectory τ, and then trained using cross-entropy loss. In at least one embodiment, p(τ) i This definition of |o) enables the learning of an interpretable spatial cost function without defining a hard marginal loss. In at least one embodiment, a set of template trajectories can be determined using the K-means over all self-trajectories in the training set.

[0070] In at least one embodiment, training efficiency may be important for learning from data from a set of cameras (such as for the entire sensor rig). In at least one embodiment, cross-pillar pooling can be used instead of max pooling because both forward and backward propagation of cross-pillar pooling can be performed efficiently in such a system. In at least one embodiment, the cone pooling layer can handle the transformation of cones generated from n images into fixed-dimensional tensors independent of the number of cameras n.

[0071] In at least one embodiment, the eigenvalue matrices of a set of cameras can define the relative orientation of each of these cameras by arbitrarily selecting reference frames. In at least one embodiment, an affine transformation applied jointly to all eigenvalues ​​can result in a second valid reference frame. In at least one embodiment, because such a network can tune the eigenvalues ​​of these cameras, ground-based targets can be rotated and translated, simultaneously rotating and translating these eigenvalues. In at least one embodiment, at least one regularization that takes into account the three-dimensional structure of such a model can be utilized. In at least one embodiment, cameras can be randomly dropped from each mini-batch, thereby allowing the network to learn cross-sensor correlations.

[0072] In at least one embodiment, the CNN may be equipped with a three-dimensional structure upon initialization. In at least one embodiment, this structure may be important for performance. In at least one embodiment, the CNN may be trained to output bird's-eye view labels from images while leveraging inductive inference from an architecture with multiple cameras. In at least one embodiment, the CNN architecture may have an EfficientNet-BO backbone that extracts features independently on all images. In at least one embodiment, other types of backbones may be used, such as those corresponding to ResNet, DeepLab, or Gated Shape CNN (GCCNN) for semantic segmentation. In at least one embodiment, these representations may then be concatenated and bilinear interpolation performed to upsample them to... Tensors, such as those output by this model. In at least one embodiment, such a CNN can learn semantic 3D representations in a bird's-eye view frame under supervision.

[0073] In at least one embodiment, if cross-camera fusion is learned via a bird's-eye view CNN, the model can be trained to be robust to simple noise models that occur in applications such as autonomous vehicles, where intrigues may be biased or camera coloring. In at least one embodiment, dropping cameras during training can improve the model's performance. In at least one embodiment, dropping cameras or sensors can force such a model to learn correlations between images on different cameras. In at least one embodiment, training such a model with noisy intrigues can also lead to better test-time performance. In at least one embodiment, the importance of each camera for the performance of object segmentation in a new scene can be determined. In at least one embodiment, losing a camera for a new scene may mean that one or more areas of the camera or sensor component will not have sensor measurements, and therefore performance may be strictly capped by the performance of having a full sensor setup. In at least one embodiment, the importance of each camera can be measured, which can indicate where redundancy in the system may be most critical. In at least one embodiment, such a model can support various generalizations, such as those involving differences in available cameras or a different number of cameras than those used for training. In at least one embodiment, a network can also be trained such that it is resilient to common sources of sensor errors. In at least one embodiment, training with a large amount of noise in the eigenvalues ​​can cause the network to become more robust to eigenvalue noise at inference time. In at least one embodiment, randomly dropping cameras from each batch during training can increase robustness to sensor dropouts at inference time.

[0074] In at least one embodiment, the trainable model is able to use an appropriate cost function to assist in planning performance. In at least one embodiment, multiple possible paths or trajectories can be generated for the controllable device. In at least one embodiment, these generated trajectories can have desired lengths and spacings, such as trajectories approximately five seconds long with intervals of approximately 0.25 seconds. In at least one embodiment, a clustering method (such as k-means) can be fitted to all self-trajectories in the training set of the new scene to obtain one or more templates. In at least one embodiment, inference time can be measured regarding how well the network can predict the template closest to the ground-realistic trajectory under a metric (such as L2 metric). In at least one embodiment, this task may have significantly less supervision than the segmentation tasks previously discussed. However, in at least one embodiment, this task is an important experiment for autonomous driving because acquiring ground-realistic targets for such experiments can be several orders of magnitude cheaper than ground-realistic 3D bounding boxes, since expert driving is intuitive for most people. In at least one embodiment, this task can also be important for benchmarking performance of camera-based methods.

[0075] In at least one embodiment, this architecture can be trained to generate different representations, such as bird's-eye view representations, from any number of cameras or any camera components. In at least one embodiment, the model in this architecture can be robust to simple models with calibration noise. In at least one embodiment, such a model can also achieve end-to-end motion planning following a trajectory shooting paradigm. In at least one embodiment, the cost of each template trajectory is calculated and interpreted as a Boltzmann distribution over a set of templates. In at least one embodiment, the Argmax of this distribution can be selected based on the selected templates.

[0076] In at least one embodiment, such as Figure 5A As shown, a process 500 for generating images of an environment with a specific view can be performed. In at least one embodiment, a set of two-dimensional images, all captured at or near a single point in time, can be received 502. In at least one embodiment, these images represent views of the environment in different reference frames. In at least one embodiment, at least one of these cameras (or imaging sensors) may also include depth or three-dimensional data. In at least one embodiment, these images can be processed 504, such as by using a trained CNN, to extract a set of contextual or semantic image features. In at least one embodiment, these features can be any features representing the corresponding images determined by the CNN or another feature extractor. In at least one embodiment, these features can be used to generate 506 characteristic, cone-shaped point clouds in local reference frames for each camera. In at least one embodiment, these individual point clouds can be positioned 508 into a three-dimensional world reference frame, as can be utilized with various intrinsic and non-intrinsic features known to the respective cameras from which these images are received. In at least one embodiment, such placement can result in a single point cloud representing the three dimensions of this environment. In at least one embodiment, an image or dataset representing the determined viewpoint of the environment can be generated 510. In at least one embodiment, this involves projecting points in this public world reference frame relative to a specific origin onto a defined plane. In at least one embodiment, multiple images can be generated, such as those with different resolutions or those corresponding to different viewpoints. In at least one embodiment, 512 of these view images can then be provided for performing tasks related to this environment, such as controlling or navigating vehicles, robots, or devices. In at least one embodiment, projecting these point cones onto a reference plane can be useful for tasks such as motion planning, where a single cohesive representation is generated using two-dimensional image data from any number of cameras.

[0077] In at least one embodiment, such as Figure 5BAs shown, process 550 for generating a three-dimensional image can be performed. In at least one embodiment, one or more two-dimensional images are obtained, wherein at least some of these images may have different reference frames. In at least one embodiment, the positions of features of these images can be determined in a common reference frame. In at least one embodiment, one or more three-dimensional images can be generated at least in part based on the positions of these image features in this common reference frame.

[0078] Reasoning and training logic

[0079] Figure 6A Inference and / or training logic 615 is illustrated for performing inference and / or training operations associated with one or more embodiments. The following is in conjunction with... Figure 6A and / or Figure 6B Provide details about reasoning and / or training logic 615.

[0080] In at least one embodiment, the inference and / or training logic 615 may include, but is not limited to, a code and / or data memory 601 for storing forward and / or output weights and / or input / output data, and / or other parameters for configuring neurons or layers of a neural network being trained and / or used for inference in aspects of one or more embodiments. In at least one embodiment, the training logic 615 may include or be coupled to the code and / or data memory 601 to store graphical code or other software for controlling timing and / or sequence, wherein weight and / or other parameter information is loaded to configure the logic, including integer and / or floating-point units (collectively, arithmetic logic units (ALUs)). In at least one embodiment, code (such as graphical code) loads weight or other parameter information into the processor ALU based on the architecture of the neural network to which the code corresponds. In at least one embodiment, the code and / or data memory 601 stores weight parameters and / or input / output data for each layer of a neural network that is trained or used in conjunction with one or more embodiments during forward propagation of input / output data and / or weight parameters during training and / or inference using aspects of one or more embodiments. In at least one embodiment, any portion of the code and / or data memory 601 may be included together with other on-chip or off-chip data storage (including the processor's L1, L2, or L3 cache or system memory).

[0081] In at least one embodiment, any portion of the code and / or data memory 601 may be internal or external to one or more processors or other hardware logic devices or circuits. In at least one embodiment, the code and / or data memory 601 may be a cache memory, dynamic random-addressable memory (“DRAM”), static random-addressable memory (“SRAM”), non-volatile memory (e.g., flash memory), or other memory. In at least one embodiment, the choice of whether the code and / or data memory 601 is internal or external to the processor, for example, or including DRAM, SRAM, flash memory, or some other memory type, may depend on the available on-chip memory relative to off-chip memory, the latency requirements of the training and / or inference functions being performed, the batch size of data used in the inference and / or training of the neural network, or some combination of these factors.

[0082] In at least one embodiment, the inference and / or training logic 615 may include, but is not limited to, a code and / or data memory 605 for storing backward and / or output weights and / or input / output data corresponding to neurons or layers of a neural network trained and / or used for inference in one or more embodiments. In at least one embodiment, the code and / or data memory 605 stores weight parameters and / or input / output data for each layer of a neural network trained or used in conjunction with one or more embodiments during backward propagation of input / output data and / or weight parameters during training and / or inference in one or more embodiments. In at least one embodiment, the training logic 615 may include or be coupled to the code and / or data memory 605 to store graphical code or other software to control timing and / or order, wherein weight and / or other parameter information is loaded to configure logic, including integer and / or floating-point units (collectively referred to as Arithmetic Logic Units (ALUs)). In at least one embodiment, code (such as graphical code) loads weight or other parameter information into the processor ALU based on the architecture of the neural network to which the code corresponds. In at least one embodiment, any portion of the code and / or data storage 605 may be included together with other on-chip or off-chip data storage (including the processor's L1, L2, or L3 cache or system memory). In at least one embodiment, any portion of the code and / or data storage 605 may be internal or external to one or more processors or other hardware logic devices or circuits. In at least one embodiment, the code and / or data storage 605 may be cache memory, DRAM, SRAM, non-volatile memory (e.g., flash memory), or other memory. In at least one embodiment, the choice of whether the code and / or data storage 605 is internal or external to the processor, for example, or including DRAM, SRAM, flash memory, or some other storage type, may depend on the available on-chip memory relative to off-chip memory, the latency requirements of the training and / or inference functions being performed, the batch size of data used in the inference and / or training of the neural network, or some combination of these factors.

[0083] In at least one embodiment, code and / or data memory 601 and code and / or data memory 605 may be separate storage structures. In at least one embodiment, code and / or data memory 601 and code and / or data memory 605 may be the same storage structure. In at least one embodiment, code and / or data memory 601 and code and / or data memory 605 may be partially identical and partially separate storage structures. In at least one embodiment, any portion of code and / or data memory 601 and code and / or data memory 605 may be included together with other on-chip or off-chip data memory (including the processor's L1, L2, or L3 cache or system memory).

[0084] In at least one embodiment, the inference and / or training logic 615 may include, but is not limited to, one or more arithmetic logic units (“ALUs”) 610, including integer and / or floating-point units, at least in part based on or instructing to perform logical and / or mathematical operations, training and / or inference code (e.g., graphical code), the result of which may produce activations (e.g., output values ​​from layers or neurons within a neural network) stored in activation memory 620, said activations being functions of input / output and / or weight parameter data stored in code and / or data memory 601 and / or code and / or data memory 605. In at least one embodiment, the activation stored in activation memory 620 is generated based on linear algebraic and / or matrix-based mathematical operations performed by one or more ALUs 610 in response to execution instructions or other code, wherein weight values ​​stored in code and / or data memory 605 and / or code and / or data memory 601 are used as operands along with other values ​​such as bias values, gradient information, momentum values, or other parameters or hyperparameters, any or all of which may be stored in code and / or data memory 605 or code and / or data memory 601 or another memory on or off-chip.

[0085] In at least one embodiment, one or more ALUs 610 are included within one or more processors or other hardware logic devices or circuits, while in another embodiment, one or more ALUs 610 may be external to the processor or other hardware logic devices or circuits (e.g., coprocessors) that use them. In at least one embodiment, ALUs 610 may be included within an execution unit of a processor or otherwise included within a group of ALUs accessible by the execution unit of the processor, which may be within the same processor or distributed among different types of processors (e.g., central processing unit, graphics processing unit, fixed-function unit, etc.). In at least one embodiment, code and / or data memory 601, code and / or data memory 605, and activation memory 620 may be on the same processor or other hardware logic device or circuit, while in another embodiment, they may be in different processors or other hardware logic devices or circuits, or some combination of the same and different processors or other hardware logic devices or circuits. In at least one embodiment, any portion of activation memory 620 may be included together with other on-chip or off-chip data memory, including the processor's L1, L2, or L3 cache or system memory. In addition, inference and / or training code may be stored together with other code accessible to the processor or other hardware logic or circuitry, and may be acquired and / or processed using the processor’s fetch, decode, schedule, execute, retire and / or other logic circuitry.

[0086] In at least one embodiment, the active memory 620 may be a cache memory, DRAM, SRAM, non-volatile memory (e.g., flash memory), or other memory. In at least one embodiment, the active memory 620 may be wholly or partially located within or outside one or more processors or other logic circuits. In at least one embodiment, the selection of whether the active memory 620 is internal or external to the processor, for example, or including DRAM, SRAM, flash memory, or some other memory type, may depend on the available on-chip memory relative to off-chip memory, the latency requirements of the training and / or inference functions being performed, the batch size of data used in the inference and / or training of the neural network, or some combination of these factors. In at least one embodiment, Figure 6A The inference and / or training logic 615 shown can be used in conjunction with an application-specific integrated circuit (“ASIC”), such as those from Google. Processing unit, from Graphcore TM Inference processing unit (IPU), or from Intel Corporation (For example, a "lake tooth" processor). In at least one embodiment, Figure 6AThe inference and / or training logic 615 shown can be used in conjunction with central processing unit (“CPU”) hardware, graphics processing unit (“GPU”) hardware or other hardware such as field programmable gate array (“FPGA”)

[0087] Figure 6B An inference and / or training logic 615 according to at least one embodiment is illustrated. In at least one embodiment, the inference and / or training logic 615 may include, but is not limited to, hardware logic in which computational resources are dedicated or otherwise used specifically in conjunction with weight values ​​or other information corresponding to one or more neuron layers within a neural network. In at least one embodiment, Figure 6B The inference and / or training logic 615 shown can be used in conjunction with an application-specific integrated circuit (ASIC), such as those from Google. Processing unit, from Graphcore TM Inference processing unit (IPU), or from Intel Corporation (For example, a "Lake Crest" processor. In at least one embodiment, Figure 6B The inference and / or training logic 615 shown can be used in conjunction with central processing unit (CPU) hardware, graphics processing unit (GPU) hardware, or other hardware such as a field-programmable gate array (FPGA). In at least one embodiment, the inference and / or training logic 615 includes, but is not limited to, code and / or data memories 601 and 605, which can be used to store code (e.g., graphical code), weight values, and / or other information, including bias values, gradient information, momentum values, and / or other parameter or hyperparameter information. Figure 6B In at least one embodiment shown, each of code and / or data memory 601 and code and / or data memory 605 is associated with a dedicated computing resource (such as computing hardware 602 and computing hardware 606). In at least one embodiment, each of computing hardware 602 and computing hardware 606 includes one or more ALUs that perform mathematical functions (such as linear algebraic functions) on information stored in code and / or data memory 601 and code and / or data memory 605, respectively, and the results are stored in activation memory 620.

[0088] In at least one embodiment, each of the code and / or data memories 601 and 605 and the corresponding computing hardware 602 and 606 corresponds to a different layer of the neural network, such that the resulting activation from a “store / computation pair 601 / 602” of the code and / or data memories 601 and computing hardware 602 is provided as input to a “store / computation pair 605 / 606” of the code and / or data memories 605 and computing hardware 606 to reflect the conceptual organization of the neural network. In at least one embodiment, each of the storage / computation pairs 601 / 602 and 605 / 606 may correspond to more than one neural network layer. In at least one embodiment, additional memory / computation pairs (not shown) following or paralleling the storage / computation pairs 601 / 602 and 605 / 606 may be included in the inference and / or training logic 615.

[0089] Data Center

[0090] Figure 7 An example data center 700 in which at least one embodiment can be used is shown. In at least one embodiment, the data center 700 includes a data center infrastructure layer 710, a framework layer 720, a software layer 730, and an application layer 740.

[0091] In at least one embodiment, such as Figure 7 As shown, the data center infrastructure layer 710 may include a resource orchestrator 712, packet computing resources 714, and node computing resources (“nodes CR”) 716(1)-716(N), where “N” represents any complete positive integer. In at least one embodiment, nodes CR 716(1)-716(N) may include, but are not limited to, any number of central processing units (“CPUs”) or other processors (including accelerators, field-programmable gate arrays (FPGAs), graphics processors, etc.), memory devices (e.g., dynamic read-only memory), memory (e.g., solid-state or disk drives), network input / output (“NW I / O”) devices, network switches, virtual machines (“VMs”), power modules, and cooling modules, etc. In at least one embodiment, one or more nodes CR from nodes CR 716(1)-716(N) may be servers having one or more of the aforementioned computing resources.

[0092] In at least one embodiment, the grouped computing resource 714 may include individual groups of node CRs housed within one or more racks (not shown) or numerous racks housed within data centers in different geographical locations (also not shown). Individual groups of node CRs within the grouped computing resource 714 may include grouped computing, networking, memory, or storage resources that can be configured or allocated to support one or more workloads. In at least one embodiment, several node CRs, including CPUs or processors, may be grouped within one or more racks to provide computing resources to support one or more workloads. In at least one embodiment, the one or more racks may also include any combination of any number of power modules, cooling modules, and network switches.

[0093] In at least one embodiment, the resource coordinator 712 may configure or otherwise control one or more nodes CR716(1)-716(N) and / or grouped computing resources 714. In at least one embodiment, the resource orchestrator 712 may include a Software Design Infrastructure (“SDI”) management entity for a data center 700. In at least one embodiment, the resource coordinator may include hardware, software, or some combination thereof.

[0094] In at least one embodiment, such as Figure 7 As shown, framework layer 720 includes a job scheduler 722, a configuration manager 724, a resource manager 726, and a distributed file system 728. In at least one embodiment, framework layer 720 may include a framework of software 732 supporting software layer 730 and / or one or more applications 742 supporting application layer 740. In at least one embodiment, software 732 or application 742 may respectively include web-based service software or applications, such as those provided by Amazon Web Services, Google Cloud, and Microsoft Azure. In at least one embodiment, framework layer 720 may be, but is not limited to, a free and open-source software web application framework that can utilize distributed file system 728 for large-scale data processing (e.g., "big data"), such as Apache Spark. TM(Hereinafter referred to as "Spark"). In at least one embodiment, the job scheduler 722 may include a Spark driver for facilitating the scheduling of workloads supported by various layers of data center 700. In at least one embodiment, the configuration manager 724 may be able to configure different layers, such as software layer 730 and framework layer 720, which include Spark and distributed file system 728 for supporting large-scale data processing. In at least one embodiment, the resource manager 726 may be able to manage computing resources mapped to or allocated to clusters or groups of distributed file system 728 and job scheduler 722 to support distributed file system 728 and job scheduler 722. In at least one embodiment, clustered or grouped computing resources may include grouped computing resources 714 at data center infrastructure layer 710. In at least one embodiment, the resource manager 726 may coordinate with resource coordinator 712 to manage these mapped or allocated computing resources.

[0095] In at least one embodiment, the software 732 included in the software layer 730 may include software used by at least a portion of the nodes CR716(1)-716(N) of the framework layer 720, the grouped computing resources 714, and / or the distributed file system 728. One or more types of software may include, but are not limited to, internet web search software, email virus scanning software, database software, and streaming video content software.

[0096] In at least one embodiment, one or more applications 742 included in application layer 740 may include one or more types of applications used by at least a portion of nodes CR716(1)-716(N) of framework layer 720, grouped computing resources 714, and / or distributed file system 728. The one or more types of applications may include, but are not limited to, any number of genomics applications, cognitive computing and machine learning applications, including training or inference software, machine learning framework software (e.g., PyTorch, TensorFlow, Caffe, etc.), or other machine learning applications used in combination with one or more embodiments.

[0097] In at least one embodiment, any of the configuration manager 724, resource manager 726, and resource orchestrator 712 can implement any number and type of self-modification actions based on any amount and type of data acquired in any technically feasible manner. In at least one embodiment, the self-modification actions can protect the data center operator of data center 700 from making potentially poor configuration decisions and may prevent underutilization and / or poor performance of the data center.

[0098] In at least one embodiment, data center 700 may include tools, services, software, or other resources to train one or more machine learning models or to predict or infer information using one or more machine learning models according to one or more embodiments described herein. For example, in at least one embodiment, a machine learning model can be trained by calculating weight parameters according to a neural network architecture using the software and computing resources described above with respect to data center 700. In at least one embodiment, a trained machine learning model corresponding to one or more neural networks can be used to infer or predict information using the resources described above with respect to data center 700 by using weight parameters calculated via one or more training techniques described herein.

[0099] In at least one embodiment, the data center may use a CPU, application-specific integrated circuit (ASIC), GPU, FPGA, or other hardware to perform training and / or inference using the resources described above. Furthermore, one or more of the software and / or hardware resources described above may be configured to allow a user to train or perform services that infer information, such as image recognition, speech recognition, or other artificial intelligence services.

[0100] Inference and / or training logic 615 is used to perform inference and / or training operations associated with one or more embodiments. The following is in conjunction with... Figure 6A and / or Figure 6B Details are provided regarding the inference and / or training logic 615. In at least one embodiment, the inference and / or training logic 615 can be implemented in the system. Figure 7 The operation is used to infer or predict based at least in part on weight parameters calculated using the neural network training operations, neural network functions and / or architecture or neural network usage described herein.

[0101] Inference and / or training logic 615 is used to perform inference and / or training operations associated with one or more embodiments. In at least one embodiment, this logic may be used with components of these graphs to generate a three-dimensional image of the determined view based on two-dimensional images from any number of cameras.

[0102] Computer System

[0103] Figure 8This is a block diagram illustrating an exemplary computer system according to at least one embodiment. The computer system may be a system of interconnected devices and components, a system-on-a-chip (SOC), or some combination thereof 800 formed with a processor that may include an execution unit capable of executing instructions. In at least one embodiment, the computer system 800 may include, but is not limited to, components such as a processor 802, which employs an execution unit including logic that executes algorithms for processing data according to this disclosure (such as those described herein). In at least one embodiment, the computer system 800 may include a processor, such as those available from Intel Corporation, Santa Clara, California. Processor family, Xeon TM , XScale TM and / or StrongARM TM , Core TM or Nervana TM The system can use a microprocessor, but other systems (including PCs, engineering workstations, set-top boxes, etc.) with other microprocessors can also be used. In at least one embodiment, the computer system 800 can execute a version of the Windows operating system available from Microsoft Corporation of Redmond, Washington, but other operating systems (such as UNIX and Linux), embedded software, and / or graphical user interfaces can also be used.

[0104] The embodiments can be used in other devices, such as handheld devices and embedded applications. Some examples of handheld devices include cellular phones, Internet Protocol devices, digital cameras, personal digital assistants (“PDAs”), and handheld PCs. In at least one embodiment, the embedded application may include a microcontroller, a digital signal processor (“DSP”), a system-on-a-chip, a network computer (“NetPC”), a set-top box, a network hub, a wide area network (“WAN”) switch, or any other system that can execute one or more instructions according to at least one embodiment.

[0105] In at least one embodiment, computer system 800 may include, but is not limited to, processor 802, which may include, but is not limited to, one or more execution units 808 performing machine learning model training and / or inference according to the techniques described herein. In at least one embodiment, computer system 800 is a single-processor desktop or server system, but in another embodiment, computer system 800 may be a multiprocessor system. In at least one embodiment, processor 802 may include, but is not limited to, a Complex Instruction Set Computer (“CISC”) microprocessor, a Reduced Instruction Set Computing (“RISC”) microprocessor, a Very Long Instruction Word (“VLIW”) microprocessor, a processor implementing a combination of instruction sets, or any other processor device, such as a digital signal processor. In at least one embodiment, processor 802 may be coupled to processor bus 810, which may transmit data signals between processor 802 and other components in computer system 800.

[0106] In at least one embodiment, processor 802 may include, but is not limited to, a Level 1 (“L1”) internal cache memory (“cache”) 804. In at least one embodiment, processor 802 may have a single internal cache or multiple levels of internal caches. In at least one embodiment, the cache memory may reside outside of processor 802. Other embodiments may also include a combination of both internal and external caches, depending on the specific implementation and requirements. In at least one embodiment, register file 806 may store different types of data in various registers, including but not limited to integer registers, floating-point registers, status registers, and instruction pointer registers.

[0107] In at least one embodiment, execution unit 808 (including, but not limited to, logic for performing integer and floating-point operations) also resides in processor 802. In at least one embodiment, processor 802 may further include a microcode (“ucode”) read-only memory (“ROM”) storing microcode for certain macro instructions. In at least one embodiment, execution unit 808 may include logic for processing a packaged instruction set 809. In at least one embodiment, by including the packaged instruction set 809 and associated circuitry for executing instructions in the instruction set of general-purpose processor 802, operations used by many multimedia applications can be performed using packaged data in general-purpose processor 802. In one or more embodiments, many multimedia applications can be accelerated and executed more efficiently by performing operations on compressed data using the full width of the processor’s data bus, eliminating the need to transfer smaller data units across the processor’s data bus to perform one or more operations at a time.

[0108] In at least one embodiment, the execution unit 808 may also be used in a microcontroller, embedded processor, graphics device, DSP, and other types of logic circuitry. In at least one embodiment, the computer system 800 may include, but is not limited to, memory 820. In at least one embodiment, memory 820 may be implemented as a dynamic random access memory (“DRAM”) device, a static random access memory (“SRAM”) device, a flash memory device, or other memory device. In at least one embodiment, memory 820 may store instructions 819 and / or data 821 represented by data signals executable by processor 802.

[0109] In at least one embodiment, the system logic chip may be coupled to a processor bus 810 and a memory 820. In at least one embodiment, the system logic chip may include, but is not limited to, a memory controller hub (“MCH”) 816, and the processor 802 may communicate with the MCH 816 via the processor bus 810. In at least one embodiment, the MCH 816 may provide a high-bandwidth memory path 818 to the memory 820 for instruction and data storage, as well as for storage of graphics commands, data, and textures. In at least one embodiment, the MCH 816 may direct data signals between the processor 802, the memory 820, and other components in the computer system 800, and bridge data signals between the processor bus 810, the memory 820, and system I / O 822. In at least one embodiment, the system logic chip may provide a graphics port for coupling to a graphics controller. In at least one embodiment, the MCH 816 may be coupled to the memory 820 via the high-bandwidth memory path 818, and the graphics / video card 812 may be coupled to the MCH 816 via an Accelerated Graphics Port (“AGP”) interconnect 814.

[0110] In at least one embodiment, computer system 800 may use system I / O 822, which serves as a dedicated hub interface bus, to couple MCH 816 to I / O controller hub (“ICH”) 830. In at least one embodiment, ICH 830 may provide direct connectivity to some I / O devices via a local I / O bus. In at least one embodiment, the local I / O bus may include, but is not limited to, a high-speed I / O bus for connecting peripheral devices to memory 820, chipset, and processor 802. Examples may include, but are not limited to, an audio controller 829, a firmware hub (“flash BIOS”) 828, a wireless transceiver 826, data storage 824, a conventional I / O controller 823 including a user input and keyboard interface 825, a serial expansion port 827 (such as a universal serial bus (“USB”), and a network controller 834). Data storage 824 may include a hard disk drive, floppy disk drive, CD-ROM device, flash memory device, or other mass storage.

[0111] In at least one embodiment, Figure 8 One embodiment is shown that includes interconnected hardware devices or "chips," while in other embodiments, Figure 8 An exemplary system-on-a-chip (“SoC”) may be shown. In at least one embodiment, the device shown in FIG1c may be interconnected with a dedicated interconnect, a standardized interconnect (e.g., PCIe), or some combination thereof. In at least one embodiment, one or more components of the computer system 800 are interconnected using a Fast Compute Link (CXL) interconnect.

[0112] Inference and / or training logic 615 is used to perform inference and / or training operations associated with one or more embodiments. The following is in conjunction with... Figure 6A and / or Figure 6B Details are provided regarding the inference and / or training logic 615. In at least one embodiment, the inference and / or training logic 615 can be implemented in the system. Figure 8 The operation is used to infer or predict based at least in part on weight parameters calculated using the neural network training operations, neural network functions and / or architecture or neural network usage described herein.

[0113] Inference and / or training logic 615 is used to perform inference and / or training operations associated with one or more embodiments. In at least one embodiment, this logic may be used with components of these graphs to generate a three-dimensional image of the determined view based on two-dimensional images from any number of cameras.

[0114] Figure 9 This is a block diagram illustrating an electronic device 900 for utilizing a processor 910 according to at least one embodiment. In at least one embodiment, the electronic device 900 may be, for example, but not limited to, a laptop, tower server, rack server, blade server, laptop computer, desktop computer, tablet computer, mobile device, telephone, embedded computer, or any other suitable electronic device.

[0115] In at least one embodiment, system 900 may, but is not limited to, processor 910 communicatively coupled to any suitable number or type of components, peripherals, modules, or devices. In at least one embodiment, processor 910 is coupled using a bus or interface (such as an I2C bus), system management bus (“SMBus”), low pin count (LPC) bus, serial peripheral interface (“SPI”), high definition audio (“HDA”) bus, serial advanced technology accessory (“SATA”) bus, universal serial bus (“USB”) (versions 1, 2, 3), or universal asynchronous receiver / transmitter (“UART”) bus. In at least one embodiment, Figure 9One embodiment is shown that includes interconnected hardware devices or "chips," while in other embodiments, Figure 9 An exemplary system-on-chip (“SoC”) may be shown. In at least one embodiment, Figure 9 The device shown can be interconnected with a dedicated interconnect, a standardized interconnect (e.g., PCIe), or some combination thereof. In at least one embodiment, Figure 9 One or more components are interconnected using Computational Fast Link (CXL) interconnects.

[0116] In at least one embodiment, Figure 9 This may include a display 924, a touchscreen 925, a touchpad 930, a near-field communication unit (“NFC”) 945, a sensor hub 940, a thermal sensor 946, a fast chipset (“EC”) 935, a trusted platform module (“TPM”) 938, a BIOS / firmware / flash memory (“BIOS, FW flash”) 922, a DSP 960, a drive 920 (such as a solid-state drive (“SSD”) or a hard disk drive (“HDD”)), a wireless LAN unit (“WLAN”) 950, a Bluetooth unit 952, a wireless wide area network unit (“WWAN”) 956, a global positioning system (GPS) 955, a camera (“USB 3.0 camera”) 954 (such as a USB 3.0 camera), and / or a low-power double data rate (“LPDDR”) memory unit (“LPDDR3”) 915 implemented therein, for example, the LPDDR3 standard. These components may each be implemented in any suitable manner.

[0117] In at least one embodiment, other components may be communicatively coupled to processor 910 via the components discussed above. In at least one embodiment, accelerometer 941, ambient light sensor (“ALS”) 942, compass 943, and gyroscope 944 may be communicatively coupled to sensor hub 940. In at least one embodiment, thermal sensor 939, fan 937, keyboard 936, and touchpad 930 may be communicatively coupled to EC 935. In at least one embodiment, speaker 963, earphone 964, and microphone (“mic”) 965 may be communicatively coupled to audio unit (“audio codec and Class D amplifier”) 962, which in turn may be communicatively coupled to DSP 960. In at least one embodiment, audio unit 964 may include (e.g., but not limited to) audio encoder / decoder (“codec”) and Class D amplifier. In at least one embodiment, SIM card (“SIM”) 957 may be communicatively coupled to WWAN unit 956. In at least one embodiment, components such as WLAN unit 950, Bluetooth unit 952, and WWAN unit 956 can be implemented in a next-generation form factor (“NGFF”).

[0118] Inference and / or training logic 615 is used to perform inference and / or training operations associated with one or more embodiments. The following is in conjunction with... Figure 6A and / or Figure 6B Details are provided regarding the inference and / or training logic 615. In at least one embodiment, the inference and / or training logic 615 can be implemented in the system. Figure 9 The operation is used to infer or predict based at least in part on weight parameters calculated using the neural network training operations, neural network functions and / or architecture or neural network usage described herein.

[0119] Inference and / or training logic 615 is used to perform inference and / or training operations associated with one or more embodiments. In at least one embodiment, this logic may be used with components of these graphs to generate a three-dimensional image of the determined view based on two-dimensional images from any number of cameras.

[0120] Figure 10 A computer system 1000 according to at least one embodiment is shown. In at least one embodiment, the computer system 1000 is configured to implement the various processes and methods described throughout this disclosure.

[0121] In at least one embodiment, the computer system 1000 includes, but is not limited to, at least one central processing unit (“CPU”) 1002 connected to a communication bus 1010 implemented using any suitable protocol, such as PCI (“Peripheral Component Interconnect”), Fast Peripheral Component Interconnect (“PCI-Express”), AGP (“Accelerated Graphics Port”), HyperTransport, or any other bus or point-to-point communication protocol. In at least one embodiment, the computer system 1000 includes, but is not limited to, main memory 1004 and control logic (e.g., implemented in hardware, software, or a combination thereof), and data is stored in main memory 1004, which may take the form of random access memory (“RAM”). In at least one embodiment, a network interface subsystem (“network interface”) 1022 provides an interface to other computing devices and networks for receiving data from the computer system 1000 and transmitting data to other systems.

[0122] In at least one embodiment, the computer system 1000 includes, but is not limited to, an input device 1008, a parallel processing system 1012, and a display device 1006 that can be implemented using conventional cathode ray tubes (“CRTs”), liquid crystal displays (“LCDs”), light-emitting diodes (“LEDs”), plasma displays, or other suitable display technologies. In at least one embodiment, user input is received from the input device 1008, such as a keyboard, mouse, touchpad, microphone, etc. In at least one embodiment, each of the foregoing modules may reside on a single semiconductor platform to form a processing system.

[0123] Inference and / or training logic 615 is used to perform inference and / or training operations associated with one or more embodiments. The following is in conjunction with... Figure 6A and / or Figure 6B Details are provided regarding the inference and / or training logic 615. In at least one embodiment, the inference and / or training logic 615 can be... Figure 10 The system is used to infer or predict operations based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architecture or neural network usage as described herein.

[0124] Inference and / or training logic 615 is used to perform inference and / or training operations associated with one or more embodiments. In at least one embodiment, this logic may be used with components of these graphs to generate a three-dimensional image of the determined view based on two-dimensional images from any number of cameras.

[0125] Figure 11 A computer system 1100 according to at least one embodiment is illustrated. In at least one embodiment, the computer system 1100 includes, but is not limited to, a computer 1110 and a USB stick 1120. In at least one embodiment, the computer 1110 may include, but is not limited to, any number and type of processors (not shown) and memory (not shown). In at least one embodiment, the computer 1110 includes, but is not limited to, a server, a cloud example, a laptop computer, and a desktop computer.

[0126] In at least one embodiment, the USB stick 1120 includes, but is not limited to, a processing unit 1130, a USB interface 1140, and USB interface logic 1150. In at least one embodiment, the processing unit 1130 can be any instruction execution system, apparatus, or device capable of executing instructions. In at least one embodiment, the processing unit 1130 can include, but is not limited to, any number and type of processing units (not shown). In at least one embodiment, the processing unit 1130 includes an application-specific integrated circuit (“ASIC”) optimized for performing any amount and type of operations associated with machine learning. For example, in at least one embodiment, the processing unit 1130 is a tensor processing unit (“TPC”) optimized for performing machine learning inference operations. In at least one embodiment, the processing unit 1130 is a vision processing unit (“VPU”) optimized for performing machine vision and machine learning inference operations.

[0127] In at least one embodiment, the USB interface 1140 can be any type of USB connector or USB receptacle. For example, in at least one embodiment, the USB interface 1140 is a USB 3.0 Type-C receptacle for data and power. In at least one embodiment, the USB interface 1140 is a USB 3.0 Type-A connector. In at least one embodiment, the USB interface logic 1150 may include any amount and type of logic that enables the processing unit 1130 to interface with a device (e.g., computer 1110) via the USB connector 1140.

[0128] Inference and / or training logic 615 is used to perform inference and / or training operations associated with one or more embodiments. The following is in conjunction with... Figure 6A and / or Figure 6B Details are provided regarding the inference and / or training logic 615. In at least one embodiment, the inference and / or training logic 615 can be... Figure 11 The system is used to infer or predict operations based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architecture or neural network usage as described herein.

[0129] Inference and / or training logic 615 is used to perform inference and / or training operations associated with one or more embodiments. In at least one embodiment, this logic may be used with components of these graphs to generate a three-dimensional image of the determined view based on two-dimensional images from any number of cameras.

[0130] Figure 12AAn exemplary architecture is shown, in which multiple GPUs 1210-1213 are communicatively coupled to multiple multi-core processors 1205-1206 via high-speed links 1240-1243 (e.g., bus, point-to-point interconnect, etc.). In one embodiment, the high-speed links 1240-1243 support communication throughput of 4GB / s, 30GB / s, 80GB / s, or higher. Different interconnect protocols can be used, including but not limited to PCIe 4.0 or 5.0 and NVLink 2.0.

[0131] Furthermore, and in one embodiment, two or more GPUs among GPUs 1210-1213 are interconnected on high-speed links 1229-1230, which can be implemented using the same or different protocols / links as those used for high-speed links 1240-1243. Similarly, two or more of the multi-core processors 1205-1206 may be connected via high-speed link 1228, which may be a symmetric multiprocessor (SMP) bus operating at speeds of 20GB / s, 30GB / s, 120GB / s, or higher. Alternatively, Figure 12A All communication between the different system components shown can be achieved using the same protocol / link (e.g., via a common interconnect structure).

[0132] In one embodiment, each multi-core processor 1205-1206 is communicatively coupled to processor memories 1201-1202 via memory interconnects 1226-1227, and each GPU 1210-1213 is communicatively coupled to GPU memories 1220-1223 via GPU memory interconnects 1250-1253. Memory interconnects 1226-1227 and 1250-1253 may utilize the same or different memory access technologies. By way of example and not limitation, processor memories 1201-1202 and GPU memories 1220-1223 may be volatile memories, such as dynamic random access memory (DRAM) (including stacked DRAM), graphics DDR SDRAM (GDDR) (e.g., GDDR5, GDDR6), or high bandwidth memory (HBM), and / or may be non-volatile memories, such as 3D XPoint or Nano-RAM. In one embodiment, some portions of the processor memories 1201-1202 may be volatile memory, and another portion may be non-volatile memory (e.g., using a two-level memory (2LM) hierarchy).

[0133] As described below, although each processor 1205-1206 and GPU 1210-1213 can be physically coupled to specific memories 1201-1202 and 1220-1223 respectively, a unified memory architecture can be achieved, in which the same virtual system address space (also referred to as the "effective address" space) is distributed across the various physical memories. For example, processor memories 1201-1202 can each include 64GB of system memory address space, and GPU memories 1220-1223 can each include 32GB of system memory address space (resulting in a total of 256GB of addressable memory in this example).

[0134] Figure 12B Additional details are shown regarding the interconnection between a multi-core processor 1207 and a graphics acceleration module 1246 according to an exemplary embodiment. The graphics acceleration module 1246 may include one or more GPU chips integrated on a line card coupled to the processor 1207 via a high-speed link 1240. Alternatively, the graphics acceleration module 1246 may be integrated with the processor 1207 in the same package or on a single chip.

[0135] In at least one embodiment, the illustrated processor 1207 includes a plurality of cores 1260A-1260D, each core having a translational backstop buffer 1261A-1261D and one or more caches 1262A-1262D. In at least one embodiment, cores 1260A-1260D may include different other components (not shown) for executing instructions and processing data. Caches 1262A-1262D may include Level 1 (L1) and Level 2 (L2) caches. Additionally, one or more shared caches 1256 may be included in caches 1262A-1262D and shared by the set of cores 1260A-1260D. For example, one embodiment of processor 1207 includes 24 cores, each core having its own L1 cache, twelve shared L2 caches, and twelve shared L3 caches. In this embodiment, one or more L2 and L3 caches are shared by two adjacent cores. Processor 1207 and graphics acceleration module 1246 are connected to system memory 1214, which may include Figure 12A The processor memory 1201-1202.

[0136] Inter-core communication on the coherence bus 1264 maintains consistency for data and instructions stored in different caches 1262A-1262D, 1256 and system memory 1214. For example, each cache may have associated cache coherence logic / circuit to communicate via the coherence bus 1264 in response to the detection of a read or write to a specific cache line. In one implementation, a cache snooping protocol is implemented on the coherence bus 1264 to monitor cache accesses.

[0137] In one embodiment, proxy circuitry 1225 communicatively couples graphics acceleration module 1246 to coherence bus 1264, thereby allowing graphics acceleration module 1246 to participate in cache coherence protocols as a peer of cores 1260A-1260D. Specifically, interface 1235 provides connectivity to proxy circuitry 1225 via high-speed link 1240 (e.g., PCIe bus, NV link, etc.), and interface 1237 connects graphics acceleration module 1246 to link 1240.

[0138] In one implementation, the accelerator integrated circuit 1236 provides cache management, memory access, context management, and interrupt management services for multiple graphics processing engines 1231, 1232, and N of the graphics acceleration module 1246. The graphics processing engines 1231, 1232, and N may each include a separate graphics processing unit (GPU). Alternatively, the graphics processing engines 1231, 1232, and N may include different types of graphics processing engines within the GPU, such as graphics execution units, media processing engines (e.g., video encoders / decoders), samplers, and bit-block transfer engines. In at least one embodiment, the graphics acceleration module 1246 may be a GPU with multiple graphics processing engines 1231-1232, and N, or the graphics processing engines 1231-1232, and N may be separate GPUs integrated on a common package, line card, or chip.

[0139] In one embodiment, the accelerator integrated circuit 1236 includes a memory management unit (MMU) 1239 for performing various memory management functions, such as virtual-to-physical memory translation (also known as effective-to-real memory translation) and memory access protocols for accessing system memory 1214. The MMU 1239 may also include a translation backstop buffer (TLB) (not shown) for caching virtual / effective-to-physical / real address translations. In one implementation, cache 1238 stores commands and data for efficient access by graphics processing engines 1231-1232, N. In one embodiment, data stored in cache 1238 and graphics memories 1233-1234, M is consistent with core caches 1262A-1262D, 1256 and system memory 1214. As described above, this can be accomplished via proxy circuitry 1225 on behalf of cache 1238 and memories 1233-1234, M (e.g., sending updates related to modifications / accesses to cache lines on processor caches 1262A-1262D, 1256 to cache 1238, and receiving updates from cache 1238).

[0140] Register set 1245 stores context data for threads executed by graphics processing engines 1231-1232, N, and context management circuitry 1248 manages the thread context. For example, context management circuitry 1248 can perform save and restore operations to save and restore the context of different threads during context switching (e.g., saving the first thread and storing the second thread so that the graphics processing engine can execute the second thread). For example, during a context switch, context management circuitry 1248 can store the current register value to a designated area in memory (e.g., identified by the context pointer). It can then restore the register value upon returning to the context. In one embodiment, interrupt management circuitry 1247 receives and processes interrupts received from system devices.

[0141] In one embodiment, the virtual / effective address from graphics processing engine 1231 is translated by MMU 1239 into a real / physical address in system memory 1214. One embodiment of accelerator integrated circuit 1236 supports multiple (e.g., 4, 8, 16) graphics accelerator modules 1246 and / or other accelerator devices. Graphics accelerator module 1246 may be dedicated to a single application executing on processor 1207, or may be shared among multiple applications. In one embodiment, a virtualized graphics execution environment is presented, wherein the resources of graphics processing engines 1231-1232, N are shared with multiple applications or virtual machines (VMs). In at least one embodiment, resources may be subdivided into "slices" that are allocated to different VMs and / or applications based on processing requirements and priorities associated with the VMs and / or applications.

[0142] In at least one embodiment, the accelerator integrated circuit 1236 acts as a bridge for the system used in the graphics acceleration module 1246 and provides address translation and system memory caching services. Furthermore, the accelerator integrated circuit 1236 can provide virtualization facilities for the host processor to manage virtualization interrupts and memory management for the graphics processing engines 1231-1232, N.

[0143] Because the hardware resources of graphics processing engines 1231-1232, N are explicitly mapped to the real address space seen by the main processor 1207, any main processor can directly address these resources using valid address values. In one embodiment, one function of the accelerator integrated circuit 1236 is the physical separation of graphics processing engines 1231-1232, N, so that they appear as independent units to the system.

[0144] In at least one embodiment, one or more graphics memories 1233-1234, M are coupled to each of the graphics processing engines 1231-1232, N, respectively. Graphics memories 1233-1234, M store instructions and data processed by each of the graphics processing engines 1231-1232, N. Graphics memories 1233-1234, M may be volatile memories, such as DRAM (including stacked DRAM), GDDR memory (e.g., GDDR5, GDDR6), or HBM, and / or may be non-volatile memories, such as 3D XPoint or Nano-RAM.

[0145] In one embodiment, to reduce data traffic on link 1240, a biasing technique is used to ensure that the data stored in graphics memories 1233-1234, M is the data that will be most frequently used by graphics processing engines 1231-1232, N and preferably not used (at least infrequently) by cores 1260A-1260D. Similarly, the biasing mechanism attempts to preserve the data required by the cores (and preferably not graphics processing engines 1231-1232, N) and system memory 1214 within the core caches 1262A-1262D, 1256.

[0146] Figure 12C Another exemplary embodiment is shown in which the accelerator integrated circuit 1236 is integrated within the processor 1207. In at least this embodiment, the graphics processing engines 1231-1232, N communicate directly with the accelerator integrated circuit 1236 via interfaces 1237 and 1235 (which can also utilize any form of bus or interface protocol) on a high-speed link 1240. The accelerator integrated circuit 1236 can perform operations related to... Figure 12BThe operations described are the same, but given their close proximity to the coherence bus 1264 and caches 1262A-1262D, 1256, they may be performed with higher throughput. At least one embodiment supports different programming models, including a dedicated process programming model (without graphics acceleration module virtualization) and a shared programming model (with virtualization), which may include a programming model controlled by accelerator integrated circuit 1236 and a programming model controlled by graphics acceleration module 1246.

[0147] In at least one embodiment, graphics processing engines 1231-1232, N are dedicated to a single application or process within a single operating system. In at least one embodiment, a single application can aggregate requests from other applications to graphics processing engines 1231-1232, N, thereby providing virtualization within a VM / partition.

[0148] In at least one embodiment, graphics processing engines 1231-1232, N can be shared by multiple VM / application partitions. In at least one embodiment, the shared model can use a hypervisor to virtualize graphics processing engines 1231-1232, N to allow each operating system to access them. For a single-partition system without a hypervisor, graphics processing engines 1231-1232, N are owned by the operating system. In at least one embodiment, the operating system can virtualize graphics processing engines 1231-1232, N to provide access to each process or application.

[0149] In at least one embodiment, the graphics acceleration module 1246 or the separate graphics processing engines 1231-1232, N uses a process handle to select a processing element. In at least one embodiment, the processing element is stored in system memory 1214 and can be addressed using the effective address to physical address translation techniques described herein. In at least one embodiment, the process handle may be an implementation-specific value provided to the host process when registering its context with the graphics processing engines 1231-1232, N (i.e., invoking system software to add the process element to the process element linked list). In at least one embodiment, the lower 16 bits of the process handle may be an offset of the processing element within the process element linked list.

[0150] Figure 12DAn exemplary accelerator integrated chip 1290 is shown. As used herein, a “slice” includes a designated portion of the processing resources of the accelerator integrated circuit 1236. The application-effective address space 1282 within system memory 1214 stores processing elements 1283. In one embodiment, processing element 1283 is stored in response to a GPU call 1281 from an application 1280 executing on processor 1207. Processing element 1283 contains the processing state corresponding to application 1280. A job descriptor (WD) 1284 contained in processing element 1283 may be a single job requested by the application, or may contain pointers to job queues. In at least one embodiment, WD 1284 is a pointer to a job request queue in the application's address space 1282.

[0151] The graphics acceleration module 1246 and / or the individual graphics processing engines 1231-1232, N can be shared by all or a subset of processes in the system. In at least one embodiment, infrastructure for setting process states and sending WD1284 to the graphics acceleration module 1246 to initiate a job in the virtualization environment may be included.

[0152] In at least one embodiment, a dedicated process programming model is implementation-specific. In this model, a single process owns either the graphics acceleration module 1246 or a separate graphics processing engine 1231. Because the graphics acceleration module 1246 is owned by a single process, when the graphics acceleration module 1246 is allocated, the hypervisor initializes the accelerator integration circuit 1236 for owning the partition, and the operating system initializes the accelerator integration circuit 1236 for owning the process.

[0153] In operation, the WD retrieval unit 1291 in the accelerator integrated chip 1290 retrieves the next WD 1284, which includes instructions for tasks to be performed by one or more graphics processing engines of the graphics acceleration module 1246. Data from the WD 1284 may be stored in register 1245 and used by the MMU 1239, interrupt management circuitry 1247, and / or context management circuitry 1248, as illustrated. For example, one embodiment of the MMU 1239 includes segment / page walk circuitry for accessing segment / page tables 1286 within the OS virtual address space 1285. The interrupt management circuitry 1247 may handle interrupt events 1292 received from the graphics acceleration module 1246. When performing graphics operations, the effective address 1293 generated by the graphics processing engines 1231-1232, N is translated into a real address by the MMU 1239.

[0154] In one embodiment, the same register set 1245 is copied for each graphics processing engine 1231-1232, N, and / or graphics acceleration module 1246 and can be initialized by a hypervisor or operating system. Each of these copied registers can be included in the accelerator integration chip 1290. Exemplary registers that can be initialized by the hypervisor are shown in Table 1.

[0155] Table 1 – Supervisor Initialization Registers

[0156]

[0157]

[0158] Exemplary registers that can be initialized by the operating system are shown in Table 2.

[0159] Table 2 – Operating System Initialization Registers

[0160] 1 Process and thread identification 2 Valid Address (EA) Context Save / Restore Pointer 3 Virtual address (VA) accelerators utilize record pointers 4 Virtual address (VA) memory segment table pointer 5 Permission mask 6 Job descriptor

[0161] In one embodiment, each WD1284 is dedicated to a specific graphics acceleration module 1246 and / or graphics processing engine 1231-1232, N. It contains all the information required for the graphics processing engine 1231-1232, N to perform its work, or it may be a pointer to a memory location of a command queue that the application has set up to perform the work.

[0162] Figure 12E Additional details of an exemplary embodiment of the shared model are shown. This embodiment includes a hypervisor real address space 1298, in which a list of processing elements 1299 is stored. The hypervisor real address space 1298 is accessible via a hypervisor 1296, which virtualizes the graphics acceleration module engine of the operating system 1295.

[0163] In at least one embodiment, the shared programming model allows all or a subset of processes from all or a subset of partitions in the system to use the graphics acceleration module 1246. Two programming models exist for the graphics acceleration module 1246, shared by multiple processes and partitions: time-sliced ​​sharing and graphics-oriented sharing.

[0164] In this model, the hypervisor 1296 owns the graphics acceleration module 1246 and makes its functionality available to all operating systems 1295. To enable the graphics acceleration module 1246 to support the virtualization of the hypervisor 1296, the graphics acceleration module 1246 may comply with the following: 1) Application job requests must be autonomous (i.e., no state maintenance is required between jobs, or the graphics acceleration module 1246 must provide context saving and restoration mechanisms). Application job requests are guaranteed by the graphics acceleration module 1246 to be completed within a specified amount of time (including any transition failures), or the graphics acceleration module 1246 provides the ability to preemptively process jobs. When operating in a directed shared programming model, the graphics acceleration module 1246 must guarantee fairness between processes.

[0165] In at least one embodiment, application 1280 is required to make a system call to operating system 1295 using graphics acceleration module 1246 type, working descriptor (WD), authorization mask register (AMR) value, and context save / restore region pointer (CSRP). In at least one embodiment, the graphics acceleration module 1246 type describes the target acceleration function for the system call. In at least one embodiment, the graphics acceleration module 1246 type can be a system-specific value. In at least one embodiment, the WD is specifically formatted for graphics acceleration module 1246 and can be in the form of a graphics acceleration module 1246 command, a valid address pointer to a user-defined structure, a valid address pointer to a command queue, or any other data structure describing the work to be performed by graphics acceleration module 1246. In one embodiment, the AMR value is the AMR state for the current process. In at least one embodiment, the value passed to the operating system is similar to that of an application setting the AMR. If the accelerator integrated circuit 1236 and graphics acceleration module 1246 implementation do not support the User Authorization Mask Override Register (UAMOR), the operating system may apply the current UAMOR value to the AMR value before passing the AMR in the hypervisor call. The hypervisor 1296 may optionally apply a current privilege mask overwrite register (AMOR) value before placing the AMR into process element 1283. In at least one embodiment, CSRP is one of the registers 1245 that contains the effective address of a region in the effective address space 1282 of the application used by the graphics acceleration module 1246 to save and restore the context state. This pointer is optional if saving state between jobs is not required or when a job is preempted. In at least one embodiment, the context save / restore region may be fixed system memory.

[0166] Upon receiving a system call, operating system 1295 verifies that application 1280 has been registered and granted permission to use graphics acceleration module 1246. Operating system 1295 then invokes hypervisor 1296 with the information shown in Table 3.

[0167] Table 3 – Call parameters from OS to hypervisor

[0168] 1 Working Descriptor (WD) 2 Authority Mask Register (AMR) value (potentially masked) 3 Valid Address (EA) Context Save / Restore Region Pointer (CSRP) 4 Process ID (PID) and optional thread ID (TID) 5 Virtual address (VA) accelerators use record pointers (AURP). 6 Virtual address of the segment table pointer (SSTP) 7 Logical Interruption Service Number (LISN)

[0169] Upon receiving a call from the management program, the management program 1296 verifies that the operating system 1295 has been registered and granted permission to use the graphics acceleration module 1246. The management program 1296 then places the processing element 1283 into a linked list of processing elements of the corresponding graphics acceleration module 1246 type. The processing element may include the information shown in Table 4.

[0170] Table 4 – Processing Component Information

[0171] 1 Working Descriptor (WD) 2 Authority Mask Register (AMR) value (potentially masked). 3 Valid Address (EA) Context Save / Restore Region Pointer (CSRP) 4 Process ID (PID) and optional thread ID (TID) 5 Virtual address (VA) accelerators use record pointers (AURP). 6 Virtual address of the segment table pointer (SSTP) 7 7. Logical Interruption Service Number (LISN) 8 Interrupt vector table, exported from hypervisor call parameters 9 Status Register (SR) Value 10 Logical Partition ID (LPID) 11 Real Address (RA) management accelerator uses record pointers 12 Storage Descriptor Register (SDR)

[0172] In at least one embodiment, the management program initializes multiple accelerator integration chip 1290 registers 1245.

[0173] like Figure 12F As shown, in at least one embodiment, a unified memory is used, which is addressable via a common virtual memory address space for accessing physical processor memories 1201-1202 and GPU memories 1220-1223. In this implementation, operations performed on GPUs 1210-1213 utilize the same virtual / effective memory address space to access processor memories 1201-1202 and vice versa, thereby simplifying programmability. In one embodiment, a first portion of the virtual / effective address space is allocated to processor memory 1201, a second portion to second processor memory 1202, a third portion to GPU memory 1220, and so on. In at least one embodiment, the entire virtual / effective memory space (sometimes referred to as the effective address space) is thus distributed across each of processor memories 1201-1202 and GPU memories 1220-1223, thereby allowing any processor or GPU to access any physical memory with a virtual address mapped to that memory.

[0174] In one embodiment, the bias / coherence management circuitry 1294A-1294E within one or more MMUs 1239A-1239E ensures cache coherence between the caches of one or more host processors (e.g., 1205) and GPUs 1210-1213, and implements biasing techniques to indicate the physical memory in which certain types of data should be stored. While in Figure 12F Several examples of bias / coherence management circuits 1294A-1294E are shown, but the bias / coherence circuitry can be implemented within the MMU of one or more host processors 1205 and / or within the accelerator integrated circuit 1236.

[0175] One embodiment allows the GPU-attached memories 1220-1223 to be mapped as part of system memory and accessed using shared virtual memory (SVM) technology without suffering the performance drawbacks associated with system-wide cache coherence. In at least one embodiment, the ability to access the GPU-attached memories 1220-1223 as system memory without heavy cache coherence overhead provides a beneficial operating environment for GPU offloading. This arrangement allows the host processor 1205 software to set operands and access computation results without the overhead of traditional I / O DMA data copying. Such traditional copying involves all inefficient driver calls, interrupts, and memory-mapped I / O (MMIO) accesses compared to simple memory access. In at least one embodiment, the ability to access the GPU-attached memories 1220-1223 without cache coherence overhead can be critical for the execution time of offloaded computations. In cases with high streaming write traffic to memory, for example, cache coherence overhead can significantly reduce the effective write bandwidth seen by the GPUs 1210-1213. In at least one embodiment, the efficiency of operand setup, the efficiency of result access, and the efficiency of GPU computation can play a role in determining the effectiveness of GPU offloading.

[0176] In at least one embodiment, the selection of GPU bias and host processor bias is driven by a bias tracker data structure. For example, a bias table can be used, which may be a page-granular structure containing 1 or 2 bits per memory page attached to the GPU (i.e., controlled at the memory page granularity). In at least one embodiment, the bias table can be implemented in the inexpensive memory range of the GPU-attached memories 1220-1223, with or without a bias cache in GPUs 1210-1213 (e.g., for caching frequently / recently used entries in the bias table). Alternatively, the entire bias table can be maintained within the GPU.

[0177] In at least one embodiment, accessing the bias table entry associated with each access to the GPU-attached memory 1220-1223 before actually accessing the GPU memory causes the following operations: First, a local request from GPUs 1210-1213 to find its page in the GPU bias is directly forwarded to the corresponding GPU memory 1220-1223. A local request from the GPU to find its page in the host bias is forwarded to processor 1205 (e.g., via a high-speed link as discussed above). In one embodiment, a request from processor 1205 to find the requested page in the host processor completes the request like a normal memory read. Alternatively, the request to the GPU bias page can be forwarded to GPUs 1210-1213. In at least one embodiment, if the GPU is not currently using the page, then the GPU may then transfer the page to the host processor bias. In at least one embodiment, the page bias state can be changed by a software-based mechanism, a hardware-assisted software mechanism, or a purely hardware-based mechanism for a limited set of cases.

[0178] One mechanism for changing the bias state employs an API call (e.g., OpenCL), which in turn invokes the GPU's device driver, which then sends a message to the GPU (or enqueues a command descriptor) to guide it to change the bias state and, for some transitions, performs a cache flush operation in the host. In at least one embodiment, the cache flush operation is used for transitions from host processor 1205 bias to GPU bias, but not for the reverse transition.

[0179] In one embodiment, cache coherence is maintained by temporarily making GPU-biased pages unavailable to the host processor 1205 cache. To access these pages, the processor 1205 can request access from the GPU 1210, which may or may not immediately grant access. Therefore, to reduce communication between the processor 1205 and the GPU 1210, it is beneficial to ensure that the GPU-biased pages are those required by the GPU, not the host processor 1205, and vice versa.

[0180] The inference and / or training logic 615 is used to execute one or more implementations. The following is in conjunction with... Figure 6A and / or Figure 6B Provide details about reasoning and / or training logic 615.

[0181] Inference and / or training logic 615 is used to perform inference and / or training operations associated with one or more embodiments. In at least one embodiment, this logic may be used with components of these graphs to generate a three-dimensional image of the determined view based on two-dimensional images from any number of cameras.

[0182] Figure 13 Exemplary integrated circuits and associated graphics processors that can be fabricated using one or more IP cores according to different embodiments described herein are shown. In addition to those shown, at least one embodiment may include other logic and circuitry, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores.

[0183] Figure 13 This diagram illustrates a block diagram of an exemplary system-on-a-chip integrated circuit 1300 that can be fabricated using one or more IP cores, according to at least one embodiment. In at least one embodiment, the integrated circuit 1300 includes one or more application processors 1305 (e.g., CPUs), at least one graphics processor 1310, and may additionally include an image processor 1315 and / or a video processor 1320, any of which may be a modular IP core. In at least one embodiment, the integrated circuit 1300 includes peripheral or bus logic including a USB controller 1325, a UART controller 1330, an SPI / SDIO controller 1335, and an I2S / I2C controller 1340. In at least one embodiment, the integrated circuit 1300 may include a display device 1345 coupled to one or more of a High Definition Multimedia Interface (HDMI) controller 1350 and a Mobile Industry Processor Interface (MIPI) Display Interface 1355. In at least one embodiment, storage may be provided by a flash memory subsystem 1360 including flash memory and a flash memory controller. In at least one embodiment, a memory interface may be provided via a memory controller 1365 for accessing an SDRAM or SRAM memory device. In at least one embodiment, some integrated circuits additionally include an embedded security engine 1370.

[0184] Inference and / or training logic 615 is used to perform inference and / or training operations associated with one or more embodiments. The following is in conjunction with... Figure 6A and / or Figure 6B Details regarding inference and / or training logic 615 are provided. In at least one embodiment, inference and / or training logic 615 may be used in integrated circuit 1300 for inferring or predicting operations based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architecture, or neural network usage as described herein.

[0185] Inference and / or training logic 615 is used to perform inference and / or training operations associated with one or more embodiments. In at least one embodiment, this logic may be used with components of these graphs to generate a three-dimensional image of the determined view based on two-dimensional images from any number of cameras.

[0186] Figures 14A-14BExemplary integrated circuits and associated graphics processors that may be fabricated using one or more IP cores according to various embodiments described herein are illustrated. In addition to those shown, at least one embodiment may include other logic and circuitry, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores.

[0187] Figures 14A-14B This is a block diagram illustrating an exemplary graphics processor used within a SoC according to embodiments described herein. Figure 14A An exemplary graphics processor 1410, which can be manufactured using one or more IP cores according to at least one embodiment, is shown. Figure 14B An additional exemplary graphics processor 1440, which can be fabricated using one or more IP cores, is shown according to at least one embodiment. In at least one embodiment, Figure 14A The graphics processor 1410 is a low-power graphics processor core. In at least one embodiment, Figure 14B The graphics processor 1440 is a higher-performance graphics processor core. In at least one embodiment, each of the graphics processors 1410, 1440 may be... Figure 13 A variant of the 1310 graphics processor.

[0188] In at least one embodiment, the graphics processor 1410 includes a vertex processor 1405 and one or more fragment processors 1415A-1415N (e.g., 1415A, 1415B, 1415C, 1415D to 1415N-1 and 1415N). In at least one embodiment, the graphics processor 1410 may execute different shader programs via separate logic, such that the vertex processor 1405 is optimized to perform operations for a vertex shader program, while one or more fragment processors 1415A to 1415N perform fragment (e.g., pixel) shading operations for a fragment or pixel shader program. In at least one embodiment, the vertex processor 1405 performs the vertex processing stage of the 3D graphics pipeline and generates primitive and vertex data. In at least one embodiment, one or more fragment processors 1415A-1415N use the primitive and vertex data generated by the vertex processor 1405 to generate a frame buffer displayed on a display device. In at least one embodiment, the fragment processors 1415A-1415N are optimized to execute fragment shader programs as provided in the OpenGL API, which can be used to perform operations similar to those of pixel shader programs provided in the Direct 3D API.

[0189] In at least one embodiment, the graphics processor 1410 further includes one or more memory management units (MMUs) 1420A-1420B, one or more caches 1425A-1425B, and one or more circuit interconnects 1430A-1430B. In at least one embodiment, one or more MMUs 1420A-1420B provide virtual-to-physical address mapping for the graphics processor 1410, including vertex processors 1405 and / or fragment processors 1415A to 1415N, which can reference vertex or image / texture data stored in memory, in addition to vertex or image / texture data stored in one or more caches 1425A-1425B. In at least one embodiment, one or more MMUs 1420A-1420B may be synchronized with other MMUs within the system, including one or more MMUs associated with one or more application processors 1305, image processors 1315, and / or Figure 13 The video processor 1320 enables each processor 1305-1320 to participate in a shared or unified virtual memory system. In at least one embodiment, one or more circuit interconnects 1430A-1430B enable the graphics processor 1410 to interface with other IP cores within the SoC via the SoC's internal bus or via a direct connection.

[0190] In at least one embodiment, the graphics processor 1440 includes Figure 14A The graphics processor 1410 includes one or more MMUs 1420A-1420B, one or more caches 1425A-1425B, and one or more circuit interconnects 1430A-1430B. In at least one embodiment, the graphics processor 1440 includes one or more shader cores 1455A to 1455N (e.g., 1455A, 1455B, 1455C, 1455D, 1455E, 1455F to 1455N-1 and 1455N) that provide a unified shader core architecture, wherein a single core or type or core can execute all types of programmable shader code, including shader program code for implementing vertex shaders, fragment shaders, and / or compute shaders. In at least one embodiment, the number of shader cores may vary. In at least one embodiment, the graphics processor 1440 includes an inter-core task manager 1445, which acts as a thread dispatcher to dispatch execution threads to one or more shader cores 1455A-1455N and tiling units 1458 to accelerate tiling operations for tile-based reproduction, wherein rendering operations that subdivide a scene in image space, for example, to take advantage of local spatial coherence within the scene or optimize the use of internal caches.

[0191] Inference and / or training logic 615 is used to perform inference and / or training operations associated with one or more embodiments. The following is in conjunction with... Figure 6A and / or Figure 6B Details regarding inference and / or training logic 615 are provided. In at least one embodiment, inference and / or training logic 615 may be used in integrated circuits 14A and / or 14B for inferring or predicting operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network usage as described herein. Inference and / or training logic 615 is used to perform inference and / or training operations associated with one or more embodiments. In at least one embodiment, this logic may be used with components of these graphs to generate a three-dimensional image of a determined view based on two-dimensional images from any number of cameras.

[0192] Figures 15A-15B Additional exemplary graphics processor logic according to the embodiments described herein is shown. Figure 15A It is shown that in at least one embodiment, it may include in Figure 13 The graphics processor 1310 is located within the graphics processor and, in at least one embodiment, may be as follows: Figure 14B The graphics core 1500 is the unified shader core 1455A-1455N. Figure 15B A highly parallel general-purpose graphics processing unit 1530, suitable for deployment on a multi-chip module, is shown in at least one embodiment.

[0193] In at least one embodiment, the graphics core 1500 includes a shared instruction cache 1502, texture units 1518, and cache / shared memory 1520 shared for execution resources within the graphics core 1500. In at least one embodiment, the graphics core 1500 may include multiple slices 1501A-1501N or partitions for each core, and the graphics processor may include multiple examples of the graphics core 1500. Slices 1501A-1501N may include supporting logic including local instruction caches 1504A-1504N, thread schedulers 1506A-1506N, thread dispatchers 1508A-1508N, and register sets 1510A-1510N. In at least one embodiment, chip 1501A-1501N may include a set of additional functional units (AFU1512A-1512N), floating-point units (FPU1514A-1514N), integer arithmetic logic units (ALU1516-1516N), address calculation units (ACU1513A-1513N), double-precision floating-point units (DPFPU1515A-1515N), and matrix processing units (MPU1517A-1517N).

[0194] In at least one embodiment, the FPU 1514A-1514N can perform single-precision (32-bit) and half-precision (16-bit) floating-point operations, while the DPFPU 1515A-1515N performs double-precision (64-bit) floating-point operations. In at least one embodiment, the ALU 1516A-1516N is capable of performing variable-precision integer operations with 8-bit, 16-bit, and 32-bit precision, and can be configured for mixed-precision operations. In at least one embodiment, the MPU 1517A-1517N can also be configured for mixed-precision matrix operations, including half-precision floating-point and 8-bit integer operations. In at least one embodiment, the MPU 1517A-1517N can perform various matrix operations to accelerate machine learning application frameworks, including enabling support for accelerated generalized matrix-to-matrix multiplication (GEMM). In at least one embodiment, the AFU 1512A-1512N can perform additional logical operations not supported by floating-point or integer units, including trigonometric operations (e.g., sine, cosine, etc.).

[0195] Inference and / or training logic 615 is used to perform inference and / or training operations associated with one or more embodiments. The following is in conjunction with... Figure 6A and / or Figure 6B Details regarding inference and / or training logic 615 are provided. In at least one embodiment, inference and / or training logic 615 may be used in the graphics core 1500 to infer or predict operations based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architecture or neural network usage described herein.

[0196] Inference and / or training logic 615 is used to perform inference and / or training operations associated with one or more embodiments. In at least one embodiment, this logic may be used with components of these graphs to generate a three-dimensional image of the determined view based on two-dimensional images from any number of cameras.

[0197] Figure 15BA general-purpose processing unit (GPGPU) 1530 is illustrated in at least one embodiment. The GPGPU can be configured to enable highly parallel computational operations to be performed by a graphics processing unit array. In at least one embodiment, the GPGPU 1530 can be directly linked to other examples of the GPGPU 1530 to create a multi-GPU cluster to improve the training speed of deep neural networks. In at least one embodiment, the GPGPU 1530 includes a host interface 1532 for connection to a host processor. In at least one embodiment, the host interface 1532 is a PCI high-speed interface. In at least one embodiment, the host interface 1532 can be a vendor-specific communication interface or communication structure. In at least one embodiment, the GPGPU 1530 receives commands from the host processor and uses a global scheduler 1534 to allocate execution threads associated with those commands to a set of compute clusters 1536A-1536H. In at least one embodiment, compute clusters 1536A-1536H share a cache memory 1538. In at least one embodiment, the cache memory 1538 can act as a high-level cache of the cache memory within compute clusters 1536A-1536H.

[0198] In at least one embodiment, the GPGPU 1530 includes memories 1544A to 1544B coupled to computing clusters 1536A to 1536H via a collection of memory controllers 1542A to 1542B. In at least one embodiment, memories 1544A-1544B may include different types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory.

[0199] In at least one embodiment, computing clusters 1536A-1536H each include a set of graphics cores, such as Figure 15A The graphics core 1500 may include various types of integer and floating-point logic units that can perform computational operations within a precision range suitable for machine learning computations. For example, in at least one embodiment, at least one subset of floating-point units in each of the computing clusters 1536A-1536H may be configured to perform 16-bit or 32-bit floating-point operations, while different subsets of floating-point units may be configured to perform 64-bit floating-point operations.

[0200] In at least one embodiment, multiple instances of GPGPU 1530 may be configured to operate as a compute cluster. In at least one embodiment, the communication used for synchronization and data exchange by compute clusters 1536A-1536H varies across embodiments. In at least one embodiment, multiple instances of GPGPU 1530 communicate via host interface 1532. In at least one embodiment, GPGPU 1530 includes an I / O hub 1539 that couples GPGPU 1530 to GPU link 1540, which enables direct connection to other instances of GPGPU 1530. In at least one embodiment, GPU link 1540 is coupled to a dedicated GPU-to-GPU bridge that enables communication and synchronization among multiple instances of GPGPU 1530. In at least one embodiment, GPU link 1540 is coupled to a high-speed interconnect for transmitting and receiving data to and from other GPGPUs or parallel processors. In at least one embodiment, multiple instances of GPGPU 1530 reside in a separate data processing system and communicate via a network device accessible via host interface 1532. In at least one embodiment of the GPU, in addition to or as an alternative to host interface 1532, link 1540 may be configured to enable a connection to the host processor.

[0201] In at least one embodiment, the GPGPU 1530 can be configured to train a neural network. In at least one embodiment, the GPGPU 1530 can be used within an inference platform. In at least one embodiment where the GPGPU 1530 is used for inference, the GPGPU may contain fewer compute clusters 1536A-1536H compared to when the GPGPU is used to train a neural network. In at least one embodiment, the memory technology associated with memories 1544A-1544B can differ between the inference configuration and the training configuration, wherein a higher bandwidth memory technology is dedicated to the training configuration. In at least one embodiment, the inference configuration of the GPGPU 1530 can support inference-specific instructions. For example, in at least one embodiment, the inference configuration can provide support for one or more 8-bit integer dot product instructions, which can be used during inference operations against the deployed neural network.

[0202] Inference and / or training logic 615 is used to perform inference and / or training operations associated with one or more embodiments. The following is in conjunction with... Figure 6A and / or Figure 6B Details are provided regarding the inference and / or training logic 615. In at least one embodiment, the inference and / or training logic 615 may be used in the GPGPU 1530 to infer or predict operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architecture or neural network usage described herein.

[0203] Inference and / or training logic 615 is used to perform inference and / or training operations associated with one or more embodiments. In at least one embodiment, this logic may be used with components of these graphs to generate a three-dimensional image of the determined view based on two-dimensional images from any number of cameras.

[0204] Figure 16 This is a block diagram illustrating a computing system 1600 according to at least one embodiment. In at least one embodiment, the computing system 1600 includes a processing subsystem 1601 having one or more processors 1602 communicating via interconnect paths and a system memory 1604, the interconnect paths including a memory hub 1605. In at least one embodiment, the memory hub 1605 may be a separate component within a chipset assembly or may be integrated within one or more processors 1602. In at least one embodiment, the memory hub 1605 is coupled to an I / O subsystem 1611 via a communication link 1606. In at least one embodiment, the I / O subsystem 1611 includes an I / O hub 1607 enabling the computing system 1600 to receive input from one or more input devices 1608. In at least one embodiment, the I / O hub 1607 may enable a display controller, which may be included in one or more processors 1602, to provide output to one or more display devices 1610A. In at least one embodiment, one or more display devices 1610A coupled to the I / O hub 1607 may include local, internal, or embedded display devices.

[0205] In at least one embodiment, the processing subsystem 1601 includes one or more parallel processors 1612 coupled to the memory hub 1605 via a bus or other communication link 1613. In at least one embodiment, the communication link 1613 can be any number of standards-based communication link technologies or protocols, such as, but not limited to, PCI High Speed, or can be vendor-specific communication interfaces or communication structures. In at least one embodiment, the one or more parallel processors 1612 form a computationally focused parallel or vector processing system that may include a large number of processing units and / or processing clusters, such as many integrated core (MIC) processors. In at least one embodiment, the one or more parallel processors 1612 form a graphics processing subsystem that can output pixels to one of one or more display devices 1610A coupled via an I / O hub 1607. In at least one embodiment, the one or more parallel processors 1612 may also include a display controller and a display interface (not shown) to enable direct connection to one or more display devices 1610B.

[0206] In at least one embodiment, system storage unit 1614 may be connected to I / O hub 1607 to provide a storage mechanism for computing system 1600. In at least one embodiment, I / O switch 1616 may be used to provide an interface mechanism to enable connectivity between I / O hub 1607 and other components, such as network adapter 1618 and / or wireless network adapter 1619 which may be integrated into one or more platforms, and various other devices that may be added via one or more additional devices 1620. In at least one embodiment, network adapter 1618 may be an Ethernet adapter or another wired network adapter. In at least one embodiment, wireless network adapter 1619 may include one or more of Wi-Fi, Bluetooth, near field communication (NFC), or other network devices including one or more radios.

[0207] In at least one embodiment, the computing system 1600 may include other components not explicitly shown, including USB or other port connections, optical storage drives, video capture devices, etc., and may also be connected to the I / O hub 1607. In at least one embodiment, any suitable protocol (such as a PCI (Peripheral Component Interconnect) based protocol (e.g., PCI Fast)) or other bus or point-to-point communication interface and / or one or more protocols (such as NV Link High Speed ​​Interconnect) or interconnection protocols can be used to implement the connection. Figure 16 The communication paths that connect the various components in the system.

[0208] In at least one embodiment, one or more parallel processors 1612 combine circuitry optimized for graphics and video processing, including, for example, video output circuitry, and constitute a graphics processing unit (GPU). In at least one embodiment, one or more parallel processors 1612 combine into general-purpose processing optimized circuitry. In at least one embodiment, components of the computing system 1600 may be integrated with one or more other system elements on a single integrated circuit. For example, in at least one embodiment, one or more parallel processors 1612, a memory hub 1605, one or more processors 1602, and an I / O hub 1607 may be integrated into a system-on-a-chip (SoC) integrated circuit. In at least one embodiment, components of the computing system 1600 may be integrated into a single package to form a system-in-package (SIP) configuration. In at least one embodiment, at least a portion of the components of the computing system 1600 may be integrated into a multi-chip module (MCM) that can interconnect with other MCMs to a modular computing system.

[0209] Inference and / or training logic 615 is used to perform inference and / or training operations associated with one or more embodiments. The following is in conjunction with... Figure 6A and / or Figure 6BDetails regarding inference and / or training logic 615 are provided. In at least one embodiment, inference and / or training logic 615 may be used in system 1600 to infer or predict operations based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architecture or neural network usage described herein.

[0210] Inference and / or training logic 615 is used to perform inference and / or training operations associated with one or more embodiments. In at least one embodiment, this logic may be used with components of these graphs to generate a three-dimensional image of the determined view based on two-dimensional images from any number of cameras.

[0211] processor

[0212] Figure 17A A parallel processor 1700 according to at least one embodiment is illustrated. In at least one embodiment, different components of the parallel processor 1700 may be implemented using one or more integrated circuit devices, such as programmable processors, application-specific integrated circuits (ASICs), or field-programmable gate arrays (FPGAs). In at least one embodiment, the parallel processor 1700 shown is according to an exemplary embodiment. Figure 16 The variant of the 1612, which includes one or more parallel processors, is shown.

[0213] In at least one embodiment, the parallel processor 1700 includes a parallel processing unit 1702. In at least one embodiment, the parallel processing unit 1702 includes an I / O unit 1704 that allows communication with other devices (including other examples of the parallel processing unit 1702). In at least one embodiment, the I / O unit 1704 can be directly connected to other devices. In at least one embodiment, the I / O unit 1704 is connected to other devices via a hub or switch interface (such as a memory hub 1605). In at least one embodiment, the connection between the memory hub 1605 and the I / O unit 1704 forms a communication link 1613. In at least one embodiment, the I / O unit 1704 is connected to a host interface 1706 and a strut memory 1716, wherein the host interface 1706 receives commands to perform processing operations, and the strut memory 1716 receives commands to perform memory operations.

[0214] In at least one embodiment, when host interface 1706 receives a command buffer via I / O unit 1704, host interface 1706 can route work operations to execute those commands to front end 1708. In at least one embodiment, front end 1708 is coupled to scheduler 1710, which is configured to distribute commands or other work items to processing cluster array 1712. In at least one embodiment, scheduler 1710 ensures that processing cluster array 1712 is properly configured and in an active state before tasks are distributed to processing cluster array 1712. In at least one embodiment, scheduler 1710 is implemented via firmware logic executed on a microcontroller. In at least one embodiment, microcontroller-implemented scheduler 1710 can be configured to perform complex scheduling and work assignment operations at both coarse and fine granular levels, enabling rapid preemption and context switching of threads executing on processing array 1712. In at least one embodiment, host software can validate workloads for scheduling on processing array 1712 via one of a plurality of graphics processing doorbells. In at least one embodiment, the workload can then be automatically allocated across the processing array 1712 by the scheduler logic within the microcontroller, which includes the scheduler 1710.

[0215] In at least one embodiment, the processing cluster array 1712 may include up to "N" processing clusters (e.g., clusters 1714A, 1714B to 1714N). In at least one embodiment, each cluster 1714A-1714N of the processing cluster array 1712 may execute a large number of concurrent threads. In at least one embodiment, the scheduler 1710 may use different scheduling and / or work allocation algorithms to allocate work to the clusters 1714A-1714N of the processing cluster array 1712, and these scheduling and / or work allocation algorithms may vary depending on the workload generated for each type of program or computation. In at least one embodiment, scheduling may be handled dynamically by the scheduler 1710, or may be partially assisted by compiler logic during compilation of the program logic configured for execution by the processing cluster array 1712. In at least one embodiment, the different clusters 1714A-1714N of the processing cluster array 1712 may be assigned to process different types of programs or to perform different types of computations.

[0216] In at least one embodiment, the processing cluster array 1712 can be configured to perform different types of parallel processing operations. In at least one embodiment, the processing cluster array 1712 is configured to perform general-purpose parallel computing operations. For example, in at least one embodiment, the processing cluster array 1712 may include logic for performing processing tasks, including filtering video and / or audio data, performing modeling operations (including physical operations), and performing data transformations.

[0217] In at least one embodiment, the processing cluster array 1712 is configured to perform parallel graphics processing operations. In at least one embodiment, the processing cluster array 1712 may include additional logic for supporting the execution of such graphics processing operations, including but not limited to texture sampling logic for performing texture operations, as well as tessellation logic and other vertex processing logic. In at least one embodiment, the processing cluster array 1712 may be configured to execute graphics processing-related shader programs, such as, but not limited to, vertex shaders, tessellation shaders, geometry shaders, and pixel shaders. In at least one embodiment, the parallel processing unit 1702 may transfer data from system memory via I / O unit 1704 for processing. In at least one embodiment, during processing, the transferred data may be stored in on-chip memory (e.g., parallel processor memory 1722) and then written back to system memory.

[0218] In at least one embodiment, when the parallel processing unit 1702 is used to perform graphics processing, the scheduler 1710 can be configured to divide the processing workload into tasks of approximately equal size to better distribute graphics processing operations across multiple clusters 1714A-1714N of the processing cluster array 1712. In at least one embodiment, portions of the processing cluster array 1712 can be configured to perform different types of processing. For example, in at least one embodiment, a first portion can be configured to perform vertex shading and topology generation, a second portion can be configured to perform tessellation and geometry shading, and a third portion can be configured to perform pixel shading or other screen-space operations to produce a reproduced image for display. In at least one embodiment, intermediate data generated by one or more clusters 1714A-1714N can be stored in a buffer to allow intermediate data to be transferred between clusters 1714A-1714N for further processing.

[0219] In at least one embodiment, the processing cluster array 1712 may receive processing tasks to be executed via a scheduler 1710, which receives commands defining the processing tasks from a front end 1708. In at least one embodiment, the processing task may include an index of data to be processed, such as surface (patch) data, graph data, vertex data, and / or pixel data, as well as state parameters and commands defining how the data is processed (e.g., what program to execute). In at least one embodiment, the scheduler 1710 may be configured to retrieve the index corresponding to the task or may receive the index from the front end 1708. In at least one embodiment, the front end 1708 may be configured to ensure that the processing cluster array 1712 is configured to be active before the workload specified by an incoming command buffer (e.g., a batch buffer, a push buffer, etc.) is initiated.

[0220] In at least one embodiment, each of one or more examples of the parallel processing unit 1702 may be coupled to the parallel processor memory 1722. In at least one embodiment, the parallel processor memory 1722 may be accessed via a memory crossbar 1716, which may receive memory requests from the processing cluster array 1712 and the I / O unit 1704. In at least one embodiment, the memory crossbar 1716 may access the parallel processor memory 1722 via a memory interface 1718. In at least one embodiment, the memory interface 1718 may include a plurality of partition units (e.g., partition units 1720A, 1720B to 1720N), each partition unit being coupled to a portion (e.g., a memory cell) of the parallel processor memory 1722. In at least one embodiment, the number of partition units 1720A-1720N is configured to be equal to the number of memory units, such that the first partition unit 1720A has a corresponding first memory unit 1724A, the second partition unit 1720B has a corresponding memory unit 1724B, and the Nth partition unit 1720N has a corresponding Nth memory unit 1724N. In at least one embodiment, the number of partition units 1720A-1720N may not be equal to the number of storage devices.

[0221] In at least one embodiment, memory cells 1724A-1724N may include different types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory. In at least one embodiment, memory cells 1724A-1724N may also include 3D stacked memory, including but not limited to high bandwidth memory (HBM). In at least one embodiment, rendering targets (such as frame buffers or texture maps) may be stored across memory cells 1724A-1724N, allowing partitioning cells 1720A-1720N to write portions of each rendering target in parallel to efficiently utilize the available bandwidth of the parallel processor memory 1722. In at least one embodiment, a local example of the parallel processor memory 1722 may be excluded to facilitate a unified memory design that leverages system memory in conjunction with local cache memory.

[0222] In at least one embodiment, any of the clusters 1714A-1714N of the processing cluster array 1712 can process data to be written to any of the memory cells 1724A-1724N within the parallel processor memory 1722. In at least one embodiment, the memory crossbar 1716 can be configured to transfer the output of each cluster 1714A-1714N to any partition cell 1720A-1720N or to another cluster 1714A-1714N, which can perform additional processing operations on the output. In at least one embodiment, each cluster 1714A-1714N can communicate with the memory interface 1718 via the memory crossbar 1716 to read from or write to different external memory devices. In at least one embodiment, the memory crossover 1716 has a connection to a memory interface 1718 for communication with I / O unit 1704, and a local connection to parallel processor memory 1722, enabling processing units within different processing clusters 1714A-1714N to communicate with system memory or other memory that is not local to parallel processing unit 1702. In at least one embodiment, the memory crossover 1716 may use virtual channels to separate traffic flows between clusters 1714A-1714N and partition units 1720A-1720N.

[0223] In at least one embodiment, multiple instances of the parallel processing unit 1702 may be housed on a single add-in card, or multiple add-in cards may be interconnected. In at least one embodiment, different instances of the parallel processing unit 1702 may be configured to interoperate, even if the different instances have different numbers of processing units, different amounts of local parallel processor memory, and / or other configuration differences. For example, in at least one embodiment, some instances of the parallel processing unit 1702 may include higher precision floating-point units relative to other instances. In at least one embodiment, a system combining one or more instances of the parallel processing unit 1702 or the parallel processor 1700 can be implemented with various configurations and form factors, including but not limited to desktop, laptop, or handheld personal computers, servers, workstations, game consoles, and / or embedded systems.

[0224] Figure 17B This is a block diagram of a partitioning unit 1720 according to at least one embodiment. In at least one embodiment, the partitioning unit 1720 is... Figure 17AAn example of one of the partition units 1720A-1720N. In at least one embodiment, partition unit 1720 includes an L2 cache memory 1721, a frame buffer interface 1725, and a raster operation unit (“ROP”) 1726. The L2 cache memory 1721 is a read / write cache memory configured to perform load and store operations received from memory cross 1716 and ROP 1726. In at least one embodiment, read misses and urgent write-back requests are output from the L2 cache 1721 to the frame buffer interface 1725 for processing. In at least one embodiment, updates can also be sent to the frame buffer for processing via the frame buffer interface 1725. In at least one embodiment, the frame buffer interface 1725 interfaces with one of the memory cells in the parallel processor memory (such as memory cells 1724A-1724N of FIG. 17 (e.g., within parallel processor memory 1722)).

[0225] In at least one embodiment, the ROP1726 is a processing unit that performs raster operations (e.g., stenciling, z-testing, blending, etc.). In at least one embodiment, the ROP1726 then outputs processed graphics data stored in graphics memory. In at least one embodiment, the ROP1726 includes compression logic for compressing depth or color data written to memory and decompressing depth or color data read from memory. In at least one embodiment, the compression logic may be lossless compression logic utilizing one or more of a plurality of compression algorithms. The compression logic performed by the ROP1726 may vary based on the statistical characteristics of the data to be compressed. For example, in at least one embodiment, incremental color compression is performed on depth and color data per tile.

[0226] In at least one embodiment, ROP1726 is included in each processing cluster (e.g., Figure 17A The data is stored within clusters 1714A-1714N, rather than within partition units 1720. In at least one embodiment, read and write requests for pixel data are made via memory crossover 1716 instead of pixel fragment data transfer. In at least one embodiment, the processed graphics data can be displayed on a display device (e.g., [display device name]). Figure 16 On one or more display devices 1610, it is routed for further processing by processor 1602, or routed for... Figure 17A One of the processing entities within the parallel processor 1700 is further processed.

[0227] Figure 17C This is a block diagram of a processing cluster 1714 within a parallel processing unit according to at least one embodiment. In at least one embodiment, the processing cluster is... Figure 17AExamples of one of the processing clusters 1714A-1714N. In at least one embodiment, one or more of the processing clusters 1714 can be configured to execute a number of threads in parallel, where a "thread" refers to an example of a specific program executed on a specific dataset. In at least one embodiment, a Single Instruction Multiple Data (SIMD) instruction dispatch technique is used to support the parallel execution of a large number of threads without providing multiple independent instruction units. In at least one embodiment, a Single Instruction Multiple Thread (SIMT) technique is used to support the parallel execution of a large number of generally synchronous threads using a common instruction unit configured to dispatch instructions to a set of processing engines within each processing cluster.

[0228] In at least one embodiment, the operation of the processing cluster 1714 can be controlled via a pipeline manager 1732 that allocates processing tasks to the SIMT parallel processors. In at least one embodiment, the pipeline manager 1732... Figure 17A The scheduler 1710 receives instructions and manages the execution of those instructions via the graphics multiprocessor 1734 and / or texture unit 1736. In at least one embodiment, the graphics multiprocessor 1734 is an exemplary example of a SIMT parallel processor. However, in at least one embodiment, different types of SIMT parallel processors with different architectures may be included within the processing cluster 1714. In at least one embodiment, one or more examples of the graphics multiprocessor 1734 may be included within the processing cluster 1714. In at least one embodiment, the graphics multiprocessor 1734 can process data, and the data cross 1740 can be used to distribute the processed data to one of a plurality of possible destinations (including other shader units). In at least one embodiment, the pipeline manager 1732 can facilitate the distribution of processed data by specifying the destination of the processed data to be distributed to face-to-face with the data cross 1740.

[0229] In at least one embodiment, each graphics multiprocessor 1734 within the processing cluster 1714 may include a set of identical functional execution logic (e.g., arithmetic logic units, load-memory units, etc.). In at least one embodiment, the functional execution logic may be pipelined, wherein new instructions can be issued before previous instructions complete. In at least one embodiment, the functional execution logic supports different operations, including integer and floating-point arithmetic, comparison operations, Boolean operations, bit shifting, and computation of different algebraic functions. In at least one embodiment, the same functional unit hardware can be used to perform different operations, and any combination of functional units may exist.

[0230] In at least one embodiment, instructions transmitted to the processing cluster 1714 constitute a thread. In at least one embodiment, a group of threads executed across a set of parallel processing engines is a thread group. In at least one embodiment, the thread group executes programs on different input data. In at least one embodiment, each thread within the thread group can be assigned to a different processing engine within the graphics multiprocessor 1734. In at least one embodiment, the thread group can include fewer threads than the multiple processing engines within the graphics multiprocessor 1734. In at least one embodiment, when the thread group includes fewer threads than the multiple processing engines, one or more processing engines can be idle during the cycle in which the thread group is processed. In at least one embodiment, the thread group can also include more threads than the multiple processing engines within the graphics multiprocessor 1734. In at least one embodiment, when the thread group includes more threads than the multiple processing engines within the graphics multiprocessor 1734, processing can be performed on consecutive clock cycles. In at least one embodiment, multiple thread groups can be executed simultaneously on the graphics multiprocessor 1734.

[0231] In at least one embodiment, the graphics multiprocessor 1734 includes an internal cache memory for performing load and store operations. In at least one embodiment, the graphics multiprocessor 1734 may forgo the internal cache and use cache memory within the processing cluster 1714 (e.g., L1 cache 1748). In at least one embodiment, each graphics multiprocessor 1734 may also access partition units shared across all processing clusters 1714 and used for transferring data between threads (e.g., ...). Figure 17A The L2 cache is located within partition units 1720A-1720N. In at least one embodiment, the graphics multiprocessor 1734 can also access off-chip global memory, which may include one or more of local parallel processor memory and / or system memory. In at least one embodiment, any memory outside of the parallel processing unit 1702 can be used as global memory. In at least one embodiment, the processing cluster 1714 includes multiple instances of the graphics multiprocessor 1734 that can share common instructions and data, which may be stored in the L1 cache 1748.

[0232] In at least one embodiment, each processing cluster 1714 may include a memory management unit (“MMU”) 1745 configured to map virtual addresses to physical addresses. In at least one embodiment, one or more instances of the MMU 1745 may reside in Figure 17AThe memory interface 1718 is located within the MMU 1745. In at least one embodiment, the MMU 1745 includes a set of page table entries (PTEs) for mapping virtual addresses to physical addresses of tiles and optionally a cache line index. In at least one embodiment, the MMU 1745 may include an address translation lookahead buffer (TLB) or cache that may reside within the graphics multiprocessor 1734 or the L1 cache or processing cluster 1714. In at least one embodiment, physical addresses are processed to distribute surface data access locality, thereby allowing valid requests to be interleaved between partition units. In at least one embodiment, the cache line index can be used to determine whether a request for a cache line is a hit or a miss.

[0233] In at least one embodiment, the processing cluster 1714 may be configured such that each graphics multiprocessor 1734 is coupled to a texture unit 1736 to perform texture mapping operations, such as determining texture sample locations, reading texture data, and filtering texture data. In at least one embodiment, texture data is read from an internal texture L1 cache (not shown) or from an L1 cache within the graphics multiprocessor 1734, and texture data is retrieved from an L2 cache, local parallel processor memory, or system memory as needed. In at least one embodiment, each graphics multiprocessor 1734 outputs a processed task to a data cross 1740 to provide one or more processed tasks to another processing cluster 1714 for further processing, or stores one or more processed tasks in an L2 cache, local parallel processor memory, or system memory via a memory cross 1716. In at least one embodiment, a pre-ROP 1742 (pre-raster operation unit) is configured to receive data from the graphics multiprocessor 1734 and direct the data to a ROP unit, which may be located in a partitioned unit as described herein (e.g., Figure 17A In the partitioning units 1720A-1720N. In at least one embodiment, the pre-ROP1742 unit can perform optimization for color blending, organize pixel color data, and perform address translation.

[0234] Inference and / or training logic 615 is used to perform inference and / or training operations associated with one or more embodiments. The following is in conjunction with... Figure 6A and / or Figure 6B Details are provided regarding inference and / or training logic 615. In at least one embodiment, inference and / or training logic 615 may be used in a graphics processing cluster 1714 to infer or predict operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architecture or neural network usage described herein.

[0235] Inference and / or training logic 615 is used to perform inference and / or training operations associated with one or more embodiments. In at least one embodiment, this logic may be used with components of these graphs to generate a three-dimensional image of the determined view based on two-dimensional images from any number of cameras.

[0236] Figure 17D A graphics multiprocessor 1734 according to at least one embodiment is illustrated. In at least one embodiment, the graphics multiprocessor 1734 is coupled to a pipeline manager 1732 of a processing cluster 1714. In at least one embodiment, the graphics multiprocessor 1734 has an execution pipeline, including but not limited to an instruction cache 1752, an instruction unit 1754, an address mapping unit 1756, a register file 1758, one or more general-purpose graphics processing unit (GPGPU) cores 1762, and one or more load / store units 1766. The GPGPU cores 1762 and the load / store units 1766 are coupled to a cache memory 1772 and a shared memory 1770 via a memory and cache interconnect 1768.

[0237] In at least one embodiment, instruction cache 1752 receives a stream of instructions to be executed from pipeline manager 1732. In at least one embodiment, instructions are cached in instruction cache 1752 and dispatched for execution by instruction unit 1754. In at least one embodiment, instruction unit 1754 may dispatch instructions into thread groups (e.g., meridians), where each thread group is assigned to a different execution unit within one or more GPGPU cores 1762. In at least one embodiment, instructions can access any of the local, shared, or global address spaces by specifying an address within a unified address space. In at least one embodiment, address mapping unit 1756 can be used to translate addresses in the unified address space into different memory addresses accessible by load / store unit 1766. In at least one embodiment, register file 1758 provides a set of registers for the functional units of graphics multiprocessor 1734. In at least one embodiment, register file 1758 provides temporary storage for operands of data paths connected to the functional units of graphics processor 1734 (e.g., GPGPU core 1762, load / store unit 1766). In at least one embodiment, register file 1758 is partitioned between each functional unit such that each functional unit is assigned a dedicated portion of register file 1758. In at least one embodiment, register file 1758 is partitioned between different meridians executed by graphics multiprocessor 1734.

[0238] In at least one embodiment, each of the GPGPU cores 1762 may include a floating-point unit (FPU) and / or an integer arithmetic logic unit (ALU) for executing instructions of the graphics multiprocessor 1734. The GPGPU cores 1762 may be architecturally similar or architecturally different. In at least one embodiment, a first portion of the GPGPU core 1762 includes a single-precision FPU and an integer ALU, while a second portion of the GPGPU core includes a double-precision FPU. In at least one embodiment, the FPU may implement the IEEE 754-2008 standard for floating-point operations or implement variable-precision floating-point operations. In at least one embodiment, the graphics multiprocessor 1734 may also include one or more fixed-function or special-function units to perform specific functions such as copying rectangles or pixel blending operations. In at least one embodiment, one or more of the GPGPU cores may also include fixed-function or special-function logic.

[0239] In at least one embodiment, the GPGPU core 1762 includes SIMD logic capable of executing a single instruction on multiple datasets. In at least one embodiment, the GPGPU core 1762 can physically execute SIMD4, SIMD8, and SIMD16 instructions, and logically execute SIMD1, SIMD2, and SIMD32 instructions. In at least one embodiment, the SIMD instructions for the GPGPU core can be generated at compile time by a shader compiler, or automatically generated when executing a program written and compiled for a Single Program Multiple Data (SPMD) or SIMT architecture. In at least one embodiment, multiple threads of a program configured for a SIMT execution model can be executed via a single SIMD instruction. For example, in at least one embodiment, eight SIMD threads performing the same or similar operations can be executed in parallel via a single SIMD8 logic unit.

[0240] In at least one embodiment, the memory and cache interconnect 1768 is an interconnect network connecting each functional unit of the graphics multiprocessor 1734 to the register file 1758 and the shared memory 1770. In at least one embodiment, the memory and cache interconnect 1768 is a cross-connect that allows the load / store unit 1766 to perform load and store operations between the shared memory 1770 and the register file 1758. In at least one embodiment, the register file 1758 can operate at the same frequency as the GPGPU core 1762, thus data transfers between the GPGPU core 1762 and the register file 1758 have very low latency. In at least one embodiment, the shared memory 1770 can be used to implement communication between threads executing on functional units within the graphics multiprocessor 1734. In at least one embodiment, the cache memory 1772 can be used, for example, as a data cache memory to cache texture data transferred between functional units and texture units 1736. In at least one embodiment, the shared memory 1770 can also be used as a program-managed cache. In at least one embodiment, the thread executing on the GPGPU core 1762 can programmably store data in shared memory in addition to the data stored in the auto-cached memory 1772.

[0241] In at least one embodiment, a parallel processor or GPGPU, as described herein, is communicatively coupled to the host / processor core to accelerate graphics operations, machine learning operations, pattern analysis operations, and various general-purpose GPU (GPGPU) functions. In at least one embodiment, the GPU may be communicatively coupled to the host processor / core via a bus or other interconnect (e.g., a high-speed interconnect such as PCIe or NVLink). In at least one embodiment, the GPU may be integrated on the same package or chip as the core and communicatively coupled to the core via an internal processor bus / interconnect (i.e., within the package or chip). In at least one embodiment, regardless of how the GPU is connected, the processor core may assign work to the GPU in the form of a sequence of commands / instructions contained in a job descriptor. In at least one embodiment, the GPU then uses dedicated circuitry / logic to efficiently process these commands / instructions.

[0242] Inference and / or training logic 615 is used to perform inference and / or training operations associated with one or more embodiments. The following is in conjunction with... Figure 6A and / or Figure 6BDetails are provided regarding inference and / or training logic 615. In at least one embodiment, inference and / or training logic 615 may be used in a graphics multiprocessor 1734 to infer or predict operations based at least in part on weight parameters computed using neural network training operations, neural network functionality and / or architecture, or neural network usage as described herein.

[0243] Inference and / or training logic 615 is used to perform inference and / or training operations associated with one or more embodiments. In at least one embodiment, this logic may be used with components of these graphs to generate a three-dimensional image of the determined view based on two-dimensional images from any number of cameras.

[0244] Figure 18 A multi-GPU computing system 1800 according to at least one embodiment is illustrated. In at least one embodiment, the multi-GPU computing system 1800 may include a processor 1802 coupled to a plurality of general-purpose graphics processing units (GPGPUs) 1806A-D via a host interface switch 1804. In at least one embodiment, the host interface switch 1804 is a PCI Fast switch device that couples the processor 1802 to a PCI Fast bus, through which the processor 1802 communicates with the GPGPUs 1806A-D. The GPGPUs 1806A-D may be interconnected via a set of high-speed point-to-point GPU-to-GPU links 1816. In at least one embodiment, the GPU-to-GPU links 1816 are connected to each of the GPGPUs 1806A-D via dedicated GPU links. In at least one embodiment, the P2P GPU links 1816 enable direct communication between each of the GPGPUs 1806A-D without requiring communication on the host interface bus 1804 to which the processor 1802 is connected. In at least one embodiment, the host interface bus 1804 remains available for system memory access or other example communication with the multi-GPU computing system 1800, for example, via one or more network devices, through GPU-to-GPU traffic directed to the P2PGPU link 1816. While in at least one embodiment, the GPGPUs 1806A-D are connected to the processor 1802 via the host interface switch 1804, in at least one embodiment, the processor 1802 includes direct support for the P2PGPU link 1816 and can be directly connected to the GPGPUs 1806A-D.

[0245] Inference and / or training logic 615 is used to perform inference and / or training operations associated with one or more embodiments. The following is in conjunction with... Figure 6A and / or Figure 6BDetails are provided regarding inference and / or training logic 615. In at least one embodiment, inference and / or training logic 615 may be used in a multi-GPU computing system 1800 to infer or predict operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architecture or neural network usage described herein.

[0246] Inference and / or training logic 615 is used to perform inference and / or training operations associated with one or more embodiments. In at least one embodiment, this logic may be used with components of these graphs to generate a three-dimensional image of the determined view based on two-dimensional images from any number of cameras.

[0247] Figure 19 This is a block diagram of a graphics processor 1900 according to at least one embodiment. In at least one embodiment, the graphics processor 1900 includes a ring interconnect 1902, a pipeline front end 1904, a media engine 1937, and graphics cores 1980A-1980N. In at least one embodiment, the ring interconnect 1902 couples the graphics processor 1900 to other processing units, including other graphics processors or one or more general-purpose processor cores. In at least one embodiment, the graphics processor 1900 is one of many processors integrated within a multi-core processing system.

[0248] In at least one embodiment, the graphics processor 1900 receives batch commands via a ring interconnect 1902. In at least one embodiment, the incoming commands are interpreted by a command stream converter 1903 in a pipeline front-end 1904. In at least one embodiment, the graphics processor 1900 includes scalable execution logic for performing 3D geometry processing and media processing via one or more graphics cores 1980A-1980N. In at least one embodiment, for 3D geometry processing commands, the command stream converter 1903 supplies commands to the geometry pipeline 1936. In at least one embodiment, for at least some media processing commands, the command stream converter 1903 supplies commands to a video front-end 1934 coupled to a media engine 1937. In at least one embodiment, the media engine 1937 includes a video quality engine (VQE) 1930 for video and image post-processing and a multi-format encoding / decoding (MFX) engine 1933 for providing hardware-accelerated media data encoding and decoding. In at least one embodiment, the geometry pipeline 1936 and the media engine 1937 each generate execution threads for thread execution resources provided by at least one graphics core 1980A.

[0249] In at least one embodiment, the graphics processor 1900 includes scalable thread execution resources characterized by modular cores 1980A-1980N (sometimes referred to as core slices), each modular core having a plurality of sub-cores 1950A-1950N, 1960A-1960N (sometimes referred to as core sub-slices). In at least one embodiment, the graphics processor 1900 may have any number of graphics cores 1980A to 1980N. In at least one embodiment, the graphics processor 1900 includes a graphics core 1980A having at least a first sub-core 1950A and a second sub-core 1960A. In at least one embodiment, the graphics processor 1900 is a low-power processor (e.g., 1950A) having a single sub-core. In at least one embodiment, the graphics processor 1900 includes a plurality of graphics cores 1980A-1980N, each graphics core including a set of first sub-cores 1950A-1950N and a set of second sub-cores 1960A-1960N. In at least one embodiment, each of the first sub-cores 1950A-1950N includes at least a first set of execution units 1952A-1952N and media / texture samplers 1954A-1954N. In at least one embodiment, each of the second sub-cores 1960A-1960N includes at least a second set of execution units 1962A-1962N and samplers 1964A-1964N. In at least one embodiment, each sub-core 1950A-1950N and 1960A-1960N shares a set of shared resources 1970A-1970N. In at least one embodiment, the shared resources include a shared cache memory and pixel operation logic.

[0250] Inference and / or training logic 615 is used to perform inference and / or training operations associated with one or more embodiments. The following is in conjunction with... Figure 6A and / or Figure 6B Details are provided regarding the inference and / or training logic 615. In at least one embodiment, the inference and / or training logic 615 may be used in the graphics processor 1900 to infer or predict operations based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architecture or neural network usage described herein.

[0251] Inference and / or training logic 615 is used to perform inference and / or training operations associated with one or more embodiments. In at least one embodiment, this logic may be used with components of these graphs to generate a three-dimensional image of the determined view based on two-dimensional images from any number of cameras.

[0252] Figure 20This is a block diagram illustrating the microarchitecture of a processor 2000 that may include logic circuitry for executing instructions according to at least one embodiment. In at least one embodiment, the processor 2000 can execute instructions, including x86 instructions, ARM instructions, application-specific integrated circuit (ASIC) instructions, etc. In at least one embodiment, the processor 2000 may include registers for storing compressed data, such as the 64-bit wide MMX™ registers in a microprocessor implemented using MMX technology from Intel Corporation, Santa Clara, California. In at least one embodiment, the MMX registers, available in both integer and floating-point forms, can be operated on with compressed data elements accompanying Single Instruction, Multiple Data (“SIMD”) and Streaming SIMD Extensions (“SSE”) instructions. In at least one embodiment, 128-bit wide XMM registers involving SSE2, SSE3, SSE4, AVX, or more (collectively, “SSEx”) technologies can hold such compressed data operands. In at least one embodiment, the processor 2000 can execute instructions to accelerate machine learning or deep learning algorithms, training, or inference.

[0253] In at least one embodiment, processor 2000 includes an ordered front end (“front end”) 2001 for fetching instructions to be executed and preparing instructions for later use in the processor pipeline. In at least one embodiment, front end 2001 may include several units. In at least one embodiment, instruction prefetcher 2026 fetches instructions from memory and feeds the instructions to instruction decoder 2028, which then decodes or interprets the instructions. For example, in at least one embodiment, instruction decoder 2028 decodes the received instructions into one or more operations that the machine can execute, referred to as “microinstructions” or “microoperations” (also referred to as “microoperations” or “uops”). In at least one embodiment, instruction decoder 2028 parses the instructions into opcodes and corresponding data and control fields that the microarchitecture can use to perform operations according to at least one embodiment. In at least one embodiment, trace cache 2030 may assemble the decoded microoperations into an ordered sequence or trace of programs in microoperation queue 2034 for execution. In at least one embodiment, when the trace cache 2030 encounters a complex instruction, the microcode ROM 2032 provides the uop required to complete the operation.

[0254] In at least one embodiment, some instructions may be converted into a single micro-operation, while other instructions require several micro-operations to complete the full operation. In at least one embodiment, if more than four uops are required to complete an instruction, the instruction decoder 2028 may access the microcode ROM 2032 to execute the instruction. In at least one embodiment, instructions may be decoded into a small number of uops for processing at the instruction decoder 2028. In at least one embodiment, if multiple uops are required to complete an operation, the instruction may be stored within the microcode ROM 2032. In at least one embodiment, according to at least one embodiment, the trace cache 2030 references an entry point programmable logic array (“PLA”) to determine the correct microinstruction pointer for reading the microcode sequence to complete one or more instructions from the microcode ROM 2032. In at least one embodiment, after the microcode ROM 2032 has completed the ordering of the instruction uops, the machine front end 2001 may resume fetching uops from the trace cache 2030.

[0255] In at least one embodiment, the out-of-order execution engine (“out-of-order engine”) 2003 can prepare instructions for execution. In at least one embodiment, the out-of-order execution logic has several buffers to smooth and reorder the instruction stream to optimize performance as the instruction stream travels down the pipeline and is scheduled for execution. In at least one embodiment, the out-of-order execution engine 2003 includes, but is not limited to, an allocator / register renamer 2040, a memory micro-operation queue 2042, an integer / floating-point micro-operation queue 2044, a memory scheduler 2046, a fast scheduler 2002, a slow / general-purpose floating-point scheduler (“slow / general-purpose FP scheduler”) 2004, and a simple floating-point scheduler (“simple FP scheduler”) 2006. In at least one embodiment, the fast scheduler 2002, the slow / general-purpose floating-point scheduler 2004, and the simple floating-point scheduler 2006 are also collectively referred to herein as "uop schedulers 2002, 2004, 2006". In at least one embodiment, the allocator / register renamer 2040 allocates the machine buffers and resources required for each uop to be executed. In at least one embodiment, the allocator / register renamer 2040 renames logical registers to entries in the register file. In at least one embodiment, prior to the memory scheduler 2046 and the uop schedulers 2002, 2004, 2006, the allocator / register renamer 2040 also allocates an entry for each uop in one of two uop queues, memory uop queue 2042 for memory operations and integer / floating-point uop queue 2044 for non-memory operations. In at least one embodiment, the UOP schedulers 2002, 2004, and 2006 determine when a UOP is ready to execute and needs to complete its operation based on the readiness of the relevant input register operand sources and the availability of execution resources. In at least one embodiment, the fast scheduler 2002 of at least one embodiment can schedule on each half of the master clock cycle, while the slow / general-purpose floating-point scheduler 2004 and the simple floating-point scheduler 2006 can schedule once per master processor clock cycle. In at least one embodiment, the UOP schedulers 2002, 2004, and 2006 arbitrate the dispatch port to schedule the UOP for execution.

[0256] In at least one embodiment, the execution block 2011 includes, but is not limited to, an integer register file / bypass network 2008, a floating-point register file / bypass network (“FP register file / bypass network”) 2010, address generation units (“AGU”) 2012 and 2014, fast arithmetic logic units (ALU) (“fast ALU”) 2016 and 2018, a slow arithmetic logic unit (“slow ALU”) 2020, a floating-point ALU (“FP”) 2022, and a floating-point move unit (“FP move”) 2024. In at least one embodiment, the integer register file / bypass network 2008 and the floating-point register file / bypass network 2010 are also referred to herein as "register files 2008, 2010". In at least one embodiment, AGU 2012 and 2014, fast ALU 2016 and 2018, slow ALU 2020, floating-point ALU 2022 and floating-point movement unit 2024 are also referred to herein as "execution units 2012, 2014, 2016, 2018, 2020, 2022 and 2024". In at least one embodiment, the execution block b11 may include, but is not limited to, any number (including zero) and type of register files, bypass networks, address generation units and execution units in any combination.

[0257] In at least one embodiment, register files 2008 and 2010 may be arranged between uop schedulers 2002, 2004, and 2006 and execution units 2012, 2014, 2016, 2018, 2020, 2022, and 2024. In at least one embodiment, integer register file / bypass network 2008 performs integer operations. In at least one embodiment, floating-point register file / bypass network 2010 performs floating-point operations. In at least one embodiment, each of register files 2008 and 2010 may include, but is not limited to, a bypass network that can bypass or forward recently completed results that have not yet been written to the register file to a new dependent uop. In at least one embodiment, register files 2008 and 2010 may communicate data with each other. In at least one embodiment, integer register file / bypass network 2008 may include, but is not limited to, two separate register files, one for low-order 32-bit data and a second register file for high-order 32-bit data. In at least one embodiment, the floating-point register file / bypass network 2010 may include, but is not limited to, 128-bit wide entries, since floating-point instructions typically have operands with widths ranging from 64 to 128 bits.

[0258] In at least one embodiment, execution units 2012, 2014, 2016, 2018, 2020, 2022, and 2024 can execute instructions. In at least one embodiment, register files 2008 and 2010 store integer and floating-point data operation values ​​that the microinstructions need to execute. In at least one embodiment, processor 2000 may include, but is not limited to, any number and combination of execution units 2012, 2014, 2016, 2018, 2020, 2022, and 2024. In at least one embodiment, floating-point ALU 2022 and floating-point movement unit 2024 can perform floating-point, MMX, SIMD, AVX, and SSE or other operations, including dedicated machine learning instructions. In at least one embodiment, floating-point ALU 2022 may include, but is not limited to, a 64-bit multiplication-64-bit floating-point divider for performing division, square root, and remainder microops. In at least one embodiment, instructions involving floating-point values ​​can be processed using floating-point hardware. In at least one embodiment, ALU operations can be routed to the fast ALU 2016 or 2018. In at least one embodiment, the fast ALU 2016 or 2018 can perform fast operations with an effective latency of half a clock cycle. In at least one embodiment, most complex integer operations are routed to the slow ALU 2020, because the slow ALU 2020 can include, but is not limited to, integer execution hardware for operations with long latency types, such as multipliers, shifters, tagging logic, and branching. In at least one embodiment, memory load / store operations can be performed by the ALU 2012 or 2014. In at least one embodiment, the fast ALU 2016, fast ALU 2018, and slow ALU 2020 can perform integer operations on 64-bit data operands. In at least one embodiment, the fast ALU 2016, fast ALU 2018, and slow ALU 2020 can be implemented to support various data bit sizes, including 16, 32, 128, 256, etc. In at least one embodiment, the floating-point ALU 2022 and the floating-point movement unit 2024 can be implemented to support operand ranges with different bit widths. In at least one embodiment, the floating-point ALU 2022 and the floating-point movement unit 2024 can operate on 128-bit wide compressed data operands in conjunction with SIMD and multimedia instructions.

[0259] In at least one embodiment, the uop schedulers 2002, 2004, and 2006 dispatch dependent operations before the parent load completes execution. In at least one embodiment, since uops can be speculatively scheduled and executed in processor 2000, processor 2000 may also include logic for handling memory misses. In at least one embodiment, if a data load misses in the data cache, there may be dependent operations in flight through the pipeline that cause the scheduler to have temporarily incorrect data. In at least one embodiment, a replay mechanism tracks and re-executes instructions that use incorrect data. In at least one embodiment, dependent operations may need to be replayed, and independent operations may be allowed to complete. In at least one embodiment, the scheduler and replay mechanism of at least one embodiment of the processor may also be designed to capture instruction sequences for text string comparison operations.

[0260] In at least one embodiment, the term "register" may refer to an on-board processor storage location that can be used as part of an instruction for identifying operands. In at least one embodiment, the register may be one that is available from outside the processor (from the programmer's perspective). In at least one embodiment, the register may not be limited to a particular type of circuitry. Rather, in at least one embodiment, the register may store data, provide data, and perform the functions described herein. In at least one embodiment, the registers described herein may be implemented by circuitry within the processor using any number of different techniques, such as dedicated physical registers, dynamically allocated physical registers renamed using register renaming, combinations of dedicated and dynamically allocated physical registers, etc. In at least one embodiment, the integer register stores 32-bit integer data. The register file of at least one embodiment also includes eight multimedia SIMD registers for packing data.

[0261] Inference and / or training logic 615 is used to perform inference and / or training operations associated with one or more embodiments. The following is in conjunction with... Figure 6A and / or Figure 6B Details regarding inference and / or training logic 615 are provided. In at least one embodiment, part or all of the inference and / or training logic 615 may be incorporated into execution block 2011 and other memories or registers shown or not shown. For example, in at least one embodiment, the training and / or inference techniques described herein may use one or more of the ALUs shown in execution block 2011. Furthermore, weight parameters may be stored in on-chip or off-chip memories and / or registers (shown or not shown) that configure the ALUs of execution block 2011 to execute one or more machine learning algorithms, neural network architectures, use cases, or training techniques described herein.

[0262] Inference and / or training logic 615 is used to perform inference and / or training operations associated with one or more embodiments. In at least one embodiment, this logic may be used with components of these graphs to generate a three-dimensional image of the determined view based on two-dimensional images from any number of cameras.

[0263] Figure 21 A deep learning application processor 2100 according to at least one embodiment is illustrated. In at least one embodiment, the deep learning application processor 2100 uses instructions that, if executed by the deep learning application processor 2100, cause the deep learning application processor 2100 to perform some or all of the processes and techniques described herein. In at least one embodiment, the deep learning application processor 2100 is an application-specific integrated circuit (ASIC). In at least one embodiment, the application processor 2100 performs matrix multiplication operations "hard-wired" into hardware by executing one or more instructions or both. In at least one embodiment, the deep learning application processor 2100 includes, but is not limited to, processing clusters 2110(1)-2110(12), inter-chip links (“ICL”) 2120(1)-2120(12), inter-chip controllers (“ICC”) 2130(1)-2130(2), memory controllers (“Mem Ctrlrs”) 2142(1)-2142(4), high-bandwidth memory physical layers (“HBM PHY”) 2144(1)-2144(4), management controller central processing unit (“management controller CPU”) 2150, fast peripheral component interconnect controller and direct memory access block (“PCIe controller and DMA”) 2170, and sixteen-channel peripheral component interconnect fast port (“PCI high speed x16”) 2180.

[0264] In at least one embodiment, processing cluster 2110 can perform deep learning operations, including inference or prediction operations based on weight parameters that compute one or more training techniques, including those described herein. In at least one embodiment, each processing cluster 2110 can include, but is not limited to, any number and type of processors. In at least one embodiment, deep learning application processor 2100 can include any number and type of processing cluster 2100. In at least one embodiment, the inter-chip link 2120 is bidirectional. In at least one embodiment, the inter-chip link 2120 and the inter-chip controller 2130 enable multiple deep learning application processors 2100 to exchange information, including activation information generated by one or more machine learning algorithms embodied in one or more neural networks. In at least one embodiment, deep learning application processor 2100 can include any number (including zero) and type of ICL 2120 and ICC 2130.

[0265] In at least one embodiment, the HBM2 2140 provides a total of 32 gigabytes (GB) of memory. The HBM2 2140(i) is associated with both the memory controller 2142(i) and the HBM PHY 2144(i). In at least one embodiment, any number of HBM2 2140s can provide any type and total amount of high-bandwidth memory and can be associated with any number (including zero) and type of memory controller 2142 and HBM PHY 2144. In at least one embodiment, SPI, I2C, GPIO2160, PCIe controllers, and DMA2170 and / or PCIe2180 can be replaced with any number and type of blocks enabling any number and type of communication standards in any technically feasible manner.

[0266] Inference and / or training logic 615 is used to perform inference and / or training operations associated with one or more embodiments. The following is in conjunction with... Figure 6A and / or Figure 6B Details regarding the inference and / or training logic 615 are provided. In at least one embodiment, the deep learning application processor 2100 is used to train a machine learning model (such as a neural network) to predict or infer information provided to the deep learning application processor 2100. In at least one embodiment, the deep learning application processor 2100 is used to infer or predict information based on a trained machine learning model (e.g., a neural network) that has been trained by another processor or system or by the deep learning application processor 2100. In at least one embodiment, the processor 2100 may be used to perform one or more neural network use cases described herein.

[0267] Inference and / or training logic 615 is used to perform inference and / or training operations associated with one or more embodiments. In at least one embodiment, this logic may be used with components of these graphs to generate a three-dimensional image of the determined view based on two-dimensional images from any number of cameras.

[0268] Figure 22This is a block diagram of a neuromorphic processor 2200 according to at least one embodiment. In at least one embodiment, the neuromorphic processor 2200 may receive one or more inputs from a source external to the neuromorphic processor 2200. In at least one embodiment, these inputs may be transmitted to one or more neurons 2202 within the neuromorphic processor 2200. In at least one embodiment, the neurons 2202 and their components may be implemented using circuitry or logic including one or more arithmetic logic units (ALUs). In at least one embodiment, the neuromorphic processor 2200 may include, but is not limited to, thousands or millions of neuron examples 2202, but any suitable number of neurons 2202 may be used. In at least one embodiment, each example of neuron 2202 may include a neuron input 2204 and a neuron output 2206. In at least one embodiment, the neuron 2202 may generate an output that can be transmitted to the inputs of other examples of the neuron 2202. For example, in at least one embodiment, the neuron input 2204 and the neuron output 2206 may be interconnected via synapses 2208.

[0269] In at least one embodiment, neuron 2202 and synapse 2208 may be interconnected, such that neuromorphic processor 2200 operates to process or analyze information received by neuromorphic processor 2200. In at least one embodiment, neuron 2202 may transmit an output pulse (or “fire” or “spiking”) when the input received through neuron input 2204 exceeds a threshold. In at least one embodiment, neuron 2202 may sum or integrate the signal received at neuron input 2204. For example, in at least one embodiment, neuron 2202 may be implemented as a leak-integral firing neuron, wherein if the sum (referred to as “membrane potential”) exceeds a threshold, neuron 2202 may use a transfer function (such as a sigmoid or threshold function) to generate an output (or “fire”). In at least one embodiment, leak-integral firing neuron may sum the signal received at neuron input 2204 to the membrane potential and may also apply an attenuation factor (or leak) to reduce the membrane potential. In at least one embodiment, a leakage integral-activated neuron can be activated if multiple input signals exceeding a threshold are received sufficiently quickly at neuron input 2204 (i.e., before the membrane potential decays too low to activate). In at least one embodiment, neuron 2202 can be implemented using circuitry or logic that receives inputs, integrates the inputs into the membrane potential, and decays the membrane potential. In at least one embodiment, the inputs can be averaged, or any other suitable transfer function can be used. Furthermore, in at least one embodiment, neuron 2202 may include, but is not limited to, comparator circuitry or logic that generates an output spike at neuron output 2206 when the result of applying the transfer function to neuron input 2204 exceeds a threshold. In at least one embodiment, once neuron 2202 is activated, it can ignore previously received input information by, for example, resetting the membrane potential to 0 or another suitable default value. In at least one embodiment, once the membrane potential is reset to 0, neuron 2202 can resume normal operation after a suitable time period (or refractory period).

[0270] In at least one embodiment, neurons 2202 may be interconnected via synapses 2208. In at least one embodiment, synapses 2208 are operable to transmit signals from the output of a first neuron 2202 to the input of a second neuron 2202. In at least one embodiment, neurons 2202 may transmit information on more than one instance of synapses 2208. In at least one embodiment, one or more instances of neuron outputs 2206 may be connected via instances of synapses 2208 to instances of neuron inputs 2204 within the same neuron 2202. In at least one embodiment, an instance of neuron 2202 that generates an output to be transmitted on an instance of synapse 2208 may be referred to as a "presynaptic neuron" relative to that instance of synapse 2208. In at least one embodiment, an instance of neuron 2202 that receives input transmitted via an instance of synapse 2208 may be referred to as a "postsynaptic neuron" relative to that instance of synapse 2208. Because an instance of neuron 2202 can receive input from one or more instances of synapse 2208, and can also transmit output to one or more instances of synapse 2208, a single instance of neuron 2202 can therefore be both a "presynaptic neuron" and a "postsynaptic neuron," in at least one embodiment, relative to each instance 2208 of the synapse.

[0271] In at least one embodiment, neurons 2202 may be organized into one or more layers. Each example of neuron 2202 may have a neuron output 2206, which fan out to one or more neuron inputs 2204 via one or more synapses 2208. In at least one embodiment, the neuron output 2206 of neuron 2202 in first layer 2210 may be connected to the neuron input 2204 of neuron 2202 in second layer 2212. In at least one embodiment, layer 2210 may be referred to as a “feedforward layer.” In at least one embodiment, each example of neuron 2202 in the examples of first layer 2210 may fan out to each example of neuron 2202 in second layer 2212. In at least one embodiment, first layer 2210 may be referred to as a “fully connected feedforward layer.” In at least one embodiment, each example of neuron 2202 in the examples of second layer 2212 may fan out to fewer than all examples of neuron 2202 in third layer 2214. In at least one embodiment, second layer 2212 may be referred to as a “sparsely connected feedforward layer.” In at least one embodiment, neurons 2202 in the second layer 2212 may fan out to neurons 2202 in multiple other layers, including neurons 2202 fan out to (the same) second layer 2212. In at least one embodiment, the second layer 2212 may be referred to as a “regression layer.” In at least one embodiment, the neuromorphic processor 2200 may include, but is not limited to, any suitable combination of recurrent layers and feedforward layers, including, but not limited to, both sparsely connected feedforward layers and fully connected feedforward layers.

[0272] In at least one embodiment, the neuromorphic processor 2200 may include, but is not limited to, a reconfigurable interconnect architecture or dedicated hardwired interconnect for connecting synapses 2208 to neurons 2202. In at least one embodiment, the neuromorphic processor 2200 may include, but is not limited to, circuitry or logic that allows synapses to be assigned to different neurons 2202 as needed based on neural network topology and neuron fan-in / out. For example, in at least one embodiment, synapses 2208 may be connected to neurons 2202 using interconnect structures (such as on-chip networks) or having dedicated connections. In at least one embodiment, circuitry or logic may be used to implement synaptic interconnects and their components.

[0273] Inference and / or training logic 615 is used to perform inference and / or training operations associated with one or more embodiments. In at least one embodiment, this logic may be used with components of these graphs to generate a three-dimensional image of the determined view based on two-dimensional images from any number of cameras.

[0274] Figure 23This is a block diagram of a processing system according to at least one embodiment. In at least one embodiment, system 2300 includes one or more processors 2302 and one or more graphics processors 2308, and may be a single-processor desktop system, a multi-processor workstation system, or a server system having a large number of processors 2302 or processor cores 2307. In at least one embodiment, system 2300 is a processing platform incorporated within a system-on-a-chip (SoC) integrated circuit for use in mobile, handheld, or embedded devices.

[0275] In at least one embodiment, system 2300 may include or be integrated into a game console (including game and media consoles), mobile game console, handheld game console, or online game console in a server-based gaming platform. In at least one embodiment, system 2300 is a mobile phone, smartphone, tablet computing device, or mobile internet device. In at least one embodiment, processing system 2300 may also include a wearable device (such as a smartwatch, smart glasses, augmented reality, or virtual reality device), coupled to or integrated within the wearable device. In at least one embodiment, processing system 2300 is a television or set-top box device having one or more processors 2302 and a graphical interface generated by one or more graphics processors 2308.

[0276] In at least one embodiment, one or more processors 2302 each include one or more processor cores 2307 for processing instructions that, when executed, perform operations for system and user software. In at least one embodiment, each of the one or more processor cores 2307 is configured to process a particular instruction set 2309. In at least one embodiment, the instruction set 2309 may facilitate Complex Instruction Set Computing (CISC), Reduced Instruction Set Computing (RISC), or computation via Very Long Instruction Word (VLIW). In at least one embodiment, the processor cores 2307 may each process different instruction sets 2309, which may include instructions that facilitate emulation of other instruction sets. In at least one embodiment, the processor cores 2307 may also include other processing devices, such as digital signal processors (DSPs).

[0277] In at least one embodiment, processor 2302 includes cache memory 2304. In at least one embodiment, processor 2302 may have a single internal cache or multi-level internal caches. In at least one embodiment, the cache memory is shared among different components of processor 2302. In at least one embodiment, processor 2302 also uses an external cache (e.g., a Level 3 (L3) cache or a last-level cache (LLC)) (not shown), which can be shared among processor cores 2307 using known cache coherence techniques. In at least one embodiment, register file 2306 is additionally included in processor 2302, and processor 2302 may include different types of registers (e.g., integer registers, floating-point registers, status registers, and instruction pointer registers) for storing different types of data. In at least one embodiment, register file 2306 may include general-purpose registers or other registers.

[0278] In at least one embodiment, one or more processors 2302 are coupled to one or more interface buses 2310 to transmit communication signals, such as address, data, or control signals, between the processors 2302 and other components in the system 2300. In at least one embodiment, the interface bus 2310 may be a processor bus, such as a version of the Direct Media Interface (DMI) bus. In at least one embodiment, the interface 2310 is not limited to the DMI bus and may include one or more peripheral component interconnect buses (e.g., PCI, PCI High Speed), memory buses, or other types of interface buses. In at least one embodiment, the processor 2302 includes an integrated memory controller 2316 and a platform controller hub 2330. In at least one embodiment, the memory controller 2316 facilitates communication between memory devices and other components of the system 2300, while the platform controller hub (PCH) 2330 provides connectivity to I / O devices via a local I / O bus.

[0279] In at least one embodiment, memory device 2320 may be a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a flash memory device, a phase-change memory device, or some other memory device with performance suitable for use as process memory. In at least one embodiment, memory device 2320 may operate as system memory of system 2300 to store data 2322 and instructions 2321 for use when one or more processors 2302 execute an application or process. In at least one embodiment, memory controller 2316 is also coupled to an optional external graphics processor 2312, which may communicate with one or more graphics processors 2308 of processor 2302 to perform graphics and media operations. In at least one embodiment, display device 2311 may be connected to processor 2302. In at least one embodiment, display device 2311 may include one or more internal display devices, such as in a mobile electronic device or laptop device attached via a display interface (e.g., a display port, etc.) or an external display device. In at least one embodiment, the display device 2311 may include a head-mounted display device (HMD), such as a stereoscopic display device for virtual reality (VR) or augmented reality (AR) applications.

[0280] In at least one embodiment, the platform controller hub 2330 enables peripheral devices to connect to the memory device 2320 and the processor 2302 via a high-speed I / O bus. In at least one embodiment, the I / O peripheral devices include, but are not limited to, an audio controller 2346, a network controller 2334, a firmware interface 2328, a wireless transceiver 2326, a touch sensor 2325, and a data storage device 2324 (e.g., a hard disk drive, flash memory, etc.). In at least one embodiment, the data storage device 2324 may be connected via a storage interface (e.g., SATA) or via a peripheral bus (such as a peripheral component interconnect bus (e.g., PCI, PCI High Speed)). In at least one embodiment, the touch sensor 2325 may include a touchscreen sensor, a pressure sensor, or a fingerprint sensor. In at least one embodiment, the wireless transceiver 2326 may be a Wi-Fi transceiver, a Bluetooth transceiver, or a mobile network transceiver, such as a 3G, 4G, or LTE transceiver. In at least one embodiment, the firmware interface 2328 enables communication with the system firmware and may be, for example, a Unified Extensible Firmware Interface (UEFI). In at least one embodiment, network controller 2334 enables network connectivity to a wired network. In at least one embodiment, a high-performance network controller (not shown) is coupled to interface bus 2310. In at least one embodiment, audio controller 2346 is a multi-channel high-definition audio controller. In at least one embodiment, system 2300 includes an optional legacy I / O controller 2340 for coupling legacy (e.g., Personal System 2 (PS / 2)) devices to the system. In at least one embodiment, platform controller hub 2330 may also be connected to one or more Universal Serial Bus (USB) controllers 2342 to connect input devices, such as a keyboard and mouse combination 2343, a camera 2344, or other USB input devices.

[0281] In at least one embodiment, examples of the memory controller 2316 and platform controller hub 2330 may be integrated into a discrete external graphics processor (such as external graphics processor 2312). In at least one embodiment, the platform controller hub 2330 and / or the memory controller 2316 may be external to one or more processors 2302. For example, in at least one embodiment, system 2300 may include an external memory controller 2316 and platform controller hub 2330, which may be configured to communicate with a system chipset-based memory controller hub and peripheral controller hub of the processor 2302.

[0282] Inference and / or training logic 615 is used to perform inference and / or training operations associated with one or more embodiments. The following is in conjunction with... Figure 6A and / or Figure 6BDetails regarding inference and / or training logic 615 are provided. In at least one embodiment, some or all of the inference and / or training logic 615 may be incorporated into graphics processor 2300. For example, in at least one embodiment, the training and / or inference techniques described herein may use one or more ALUs implemented in graphics processor 2312. Furthermore, in at least one embodiment, the inference and / or training operations described herein may use, in addition to... Figure 6A Alternatively, it may be accomplished using logic other than that shown in 6B. In at least one embodiment, the weight parameters may be stored in on-chip or off-chip memory and / or registers (shown or not shown) that configure the ALU of the graphics processor 2300 to execute one or more machine learning algorithms, neural network architectures, use cases, or training techniques described herein.

[0283] Inference and / or training logic 615 is used to perform inference and / or training operations associated with one or more embodiments. In at least one embodiment, this logic may be used with components of these graphs to generate a three-dimensional image of the determined view based on two-dimensional images from any number of cameras.

[0284] Figure 24 This is a block diagram of a processor 2400 having one or more processor cores 2402A-2402N, an integrated memory controller 2414, and an integrated graphics processor 2408 according to at least one embodiment. In at least one embodiment, the processor 2400 may include up to and including additional cores 2402N, indicated by dashed boxes. In at least one embodiment, each of the processor cores 2402A-2402N includes one or more internal cache units 2404A-2404N. In at least one embodiment, each processor core may also access one or more shared cache units 2406.

[0285] In at least one embodiment, internal cache units 2404A-2404N and shared cache unit 2406 represent a cache memory hierarchy within processor 2400. In at least one embodiment, cache memory units 2404A-2404N may include at least one level of instruction and data cache within each processor core, and one or more levels of shared intermediate cache, such as Level 2 (L2), Level 3 (L3), Level 4 (L4), or other levels of cache, wherein the highest level of cache preceding external memory is classified as LLC. In at least one embodiment, cache coherence logic maintains coherence between different cache units 2406 and 2404A-2404N.

[0286] In at least one embodiment, the processor 2400 may further include a collection of one or more bus controller units 2416 and system agent cores 2410. In at least one embodiment, one or more bus controller units 2416 manage a set of peripheral buses, such as one or more PCI or PCI Fast buses. In at least one embodiment, the system agent core 2410 provides management functions for different processor components. In at least one embodiment, the system agent core 2410 includes one or more integrated memory controllers 2414 for managing access to different external memory devices (not shown).

[0287] In at least one embodiment, one or more of the processor cores 2402A-2402N include support for simultaneous multithreading. In at least one embodiment, the system agent core 2410 includes components for coordinating and operating the cores 2402A-2402N during multithreaded processing. In at least one embodiment, the system agent core 2410 may further include a power control unit (PCU) including logic and components for regulating one or more power states of the processor cores 2402A-2402N and the graphics processor 2408.

[0288] In at least one embodiment, processor 2400 further includes a graphics processor 2408 for performing graphics processing operations. In at least one embodiment, graphics processor 2408 is coupled to a shared cache unit 2406 and a system proxy core 2410 (including one or more integrated memory controllers 2414). In at least one embodiment, system proxy core 2410 further includes a display controller 2411 for driving graphics processor output to one or more coupled displays. In at least one embodiment, display controller 2411 may also be a separate module coupled to graphics processor 2408 via at least one interconnect, or it may be integrated within graphics processor 2408.

[0289] In at least one embodiment, a ring-based interconnect unit 2412 is used to couple internal components of the processor 2400. In at least one embodiment, alternative interconnect units, such as point-to-point interconnects, switched interconnects, or other technologies, may be used. In at least one embodiment, the graphics processor 2408 is coupled to the ring interconnect 2412 via I / O link 2413.

[0290] In at least one embodiment, I / O link 2413 represents at least one of a variety of I / O interconnects, including on-package I / O interconnects that facilitate communication between different processor components and high-performance embedded memory modules 2418 (such as eDRAM modules). In at least one embodiment, each of processor cores 2402A-2402N and graphics processor 2408 uses embedded memory module 2418 as a shared final-level cache.

[0291] In at least one embodiment, processor cores 2402A-2402N are homogeneous cores executing a common instruction set architecture. In at least one embodiment, processor cores 2402A-2402N are heterogeneous in terms of instruction set architecture (ISA), wherein one or more processor cores 2402A-2402N execute a common instruction set, while one or more other processor cores 2402A-2402N execute a subset of the common instruction set or a different instruction set. In at least one embodiment, processor cores 2402A-2402N are heterogeneous in terms of microarchitecture, wherein one or more cores with relatively high power consumption are coupled to one or more power cores with lower power consumption. In at least one embodiment, processor 2400 can be implemented on one or more chips or as a SoC integrated circuit.

[0292] Inference and / or training logic 615 is used to perform inference and / or training operations associated with one or more embodiments. The following is in conjunction with... Figure 6A and / or Figure 6B Details regarding the inference and / or training logic 615 are provided. In at least one embodiment, some or all of the inference and / or training logic 615 may be incorporated into the processor 2400. For example, in at least one embodiment, the training and / or inference techniques described herein may be used in the graphics processor 2312, one or more graphics cores 2402A-2402N, or... Figure 24 One or more ALUs embodied in other components. Furthermore, in at least one embodiment, the inference and / or training operations described herein can use, in addition to... Figure 6A Alternatively, it may be accomplished using logic other than that shown in 6B. In at least one embodiment, the weight parameters may be stored in on-chip or off-chip memory and / or registers (shown or not shown), which configure the ALU of the graphics processor 2400 to execute one or more machine learning algorithms, neural network architectures, use cases, or training techniques described herein.

[0293] Inference and / or training logic 615 is used to perform inference and / or training operations associated with one or more embodiments. In at least one embodiment, this logic may be used with components of these graphs to generate a three-dimensional image of the determined view based on two-dimensional images from any number of cameras.

[0294] Figure 25This is a block diagram of the hardware logic of a graphics processor core 2500 according to at least one embodiment described herein. In at least one embodiment, the graphics processor core 2500 is included within a graphics core array. In at least one embodiment, the graphics processor core 2500 (sometimes referred to as a core slice) may be one or more graphics cores within a modular graphics processor. In at least one embodiment, the graphics processor core 2500 is an example of a graphics core slice, and the graphics processor as described herein may include multiple graphics core slices based on target power and performance envelopes. In at least one embodiment, each graphics core 2500 may include a fixed-function block 2530 coupled to a plurality of sub-cores 2501A-2501F (also referred to as sub-slices), said plurality of sub-cores including modular blocks having general and fixed-function logic.

[0295] In at least one embodiment, the fixed-function block 2530 includes a geometry / fixed-function pipeline 2536 that can be shared by all sub-cores of the graphics processor 2500 (e.g., in a lower-performance and / or lower-power graphics processor implementation). In at least one embodiment, the geometry / fixed-function pipeline 2536 includes a 3D fixed-function pipeline, a video front-end unit, a thread generator and a thread dispatcher, and a unified return buffer manager that manages the unified return buffer.

[0296] In at least one embodiment, the fixed functional block 2530 also includes a graphics SoC interface 2537, a graphics microcontroller 2538, and a media pipeline 2539. In at least one embodiment, the graphics SoC interface 2537 provides an interface between the graphics core 2500 and other processor cores within the system-on-a-chip integrated circuit. In at least one embodiment, the graphics microcontroller 2538 is a programmable subprocessor configurable to manage different functions of the graphics processor 2500, including thread dispatch, scheduling, and preemption. In at least one embodiment, the media pipeline 2539 includes logic for facilitating the decoding, encoding, preprocessing, and / or post-processing of multimedia data, including image and video data. In at least one embodiment, the media pipeline 2539 implements media operations by requesting computation or sampling logic within subcores 2501-2501F.

[0297] In at least one embodiment, the SoC interface 2537 enables the graphics core 2500 to communicate with a general-purpose application processor core (e.g., a CPU) and / or other components within the SoC, including memory hierarchy elements such as shared final-level cache memory, system RAM, and / or embedded on-chip or packaged DRAM. In at least one embodiment, the SoC interface 2537 also enables communication with fixed-function devices within the SoC (such as camera imaging pipelines) and allows the use and / or implementation of global memory atomics that can be shared between the graphics core 2500 and the CPU within the SoC. In at least one embodiment, the SoC interface 2537 also enables power management control for the graphics core 2500 and enables interfacing between the clock domain of the graphics core 2500 and other clock domains within the SoC. In at least one embodiment, the SoC interface 2537 enables the reception of command buffers from a command stream converter and a global thread dispatcher configured to provide commands and instructions to each of one or more graphics cores within the graphics processor. In at least one embodiment, when a media operation is to be performed, commands and instructions can be dispatched to media pipeline 2539, or when a graphics processing operation is to be performed, commands and instructions can be dispatched to geometry and fixed-function pipelines (e.g., geometry and fixed-function pipeline 2536, geometry and fixed-function pipeline 2514).

[0298] In at least one embodiment, the graphics microcontroller 2538 can be configured to perform different scheduling and management tasks of the graphics core 2500. In at least one embodiment, the graphics microcontroller 2538 can perform graphics and / or compute workload scheduling on different graphics parallel engines within the execution unit (EU) arrays 2502A-2502F and 2504A-2504F within sub-cores 2501A-2501F. In at least one embodiment, host software executing on the CPU core of the SoC including the graphics core 2500 can submit a workload to one of a plurality of graphics processor doorbells, which invokes scheduling operations on the appropriate graphics engine. In at least one embodiment, the scheduling operation includes: determining which workload to run next; submitting the workload to a command stream converter; preempting existing workloads running on the engine; monitoring the progress of the workload; and notifying the host software when the workload is completed. In at least one embodiment, the graphics microcontroller 2538 may also facilitate low-power or idle states of the graphics core 2500, thereby providing the graphics core 2500 with the ability to save and restore registers within the graphics core 2500 across low-power state transitions, independent of the operating system and / or the graphics driver software on the system.

[0299] In at least one embodiment, the graphics core 2500 may have more or fewer sub-cores 2501A-2501F as shown, up to N modular sub-cores. In at least one embodiment, for each set of N sub-cores, the graphics core 2500 may further include shared functional logic 2510, shared and / or cache memory 2512, geometry / fixed-function pipeline 2514, and additional fixed-function logic 2516 for accelerating different graphics and computational processing operations. In at least one embodiment, the shared functional logic 2510 may include logic units (e.g., samplers, math and / or inter-thread communication logic) that can be shared by every N sub-cores within the graphics core 2500. In at least one embodiment, the fixed, shared, and / or cache memory 2512 may be the final-level cache of the N sub-cores 2501A-2501F within the graphics core 2500, and may also be used as shared memory accessible by multiple sub-cores. In at least one embodiment, the geometry / fixed function pipeline 2514 may be included within the fixed function block 2530 instead of the geometry / fixed function pipeline 2536 and may include the same or similar logic units.

[0300] In at least one embodiment, the graphics core 2500 includes additional fixed-function logic 2516, which may include different fixed-function acceleration logic for use by the graphics core 2500. In at least one embodiment, the additional fixed-function logic 2516 includes additional geometry pipelines for use only in positional shading. In positional shading only, at least two geometry pipelines exist, while in the full geometry pipeline and culling pipeline within the geometry / fixed-function pipelines 2516, 2536, the culling pipeline is an additional geometry pipeline that may be included within the additional fixed-function logic 2516. In at least one embodiment, the culling pipeline is a trimmed version of the full geometry pipeline. In at least one embodiment, the full pipeline and the culling pipeline execute different examples of the application, each with a separate context. In at least one embodiment, positional shading only may hide long culling runs of discarded triangles, allowing shading to be completed earlier in some examples. For example, in at least one embodiment, the culling pipeline logic within the additional fixed-function logic 2516 can execute the position shader in parallel with the main application and typically produces key results faster than the full pipeline because the culling pipeline extracts and colors the position attributes of vertices without performing rasterization and reproducing pixels to the frame buffer. In at least one embodiment, the culling pipeline can use the resulting key results to compute visibility information for all triangles, regardless of whether those triangles were culled. In at least one embodiment, the full pipeline (which may be referred to as the replay pipeline in this example) can consume visibility information to skip culled triangles, thus coloring only the visible triangles that are ultimately passed to the rasterization stage.

[0301] In at least one embodiment, for implementations including optimizations for machine learning training or inference, the additional fixed-function logic 2516 may also include machine learning acceleration logic, such as fixed-function matrix multiplication logic.

[0302] In at least one embodiment, each graphics subcore 2501A-2501F includes a set of execution resources that can be used to perform graphics, media, and computational operations in response to requests from the graphics pipeline, media pipeline, or shader program. In at least one embodiment, the graphics subcore 2501A-2501F includes multiple EU arrays 2502A-2502F, 2504A-2504F, thread scheduling and inter-thread communication (TD / IC) logic 2503A-2503F, 3D (e.g., texture) samplers 2505A-2505F, media samplers 2506A-2506F, shader processors 2507A-2507F, and shared local memory (SLM) 2508A-2508F. EU arrays 2502A-2502F and 2504A-2504F each include multiple execution units, which are general-purpose graphics processing units capable of performing floating-point and integer / fixed-point logic operations in services of graphics, media, or computational operations (including graphics, media, or computational shader programs). In at least one embodiment, TD / IC logic 2503A-2503F performs local thread scheduling and thread control operations for the execution units within the subcore and facilitates communication between threads executing on the execution units of the subcore. In at least one embodiment, 3D samplers 2505A-2505F can read textures or other 3D graphics-related data into memory. In at least one embodiment, the 3D samplers can read texture data differently based on the configured sample state and the texture format associated with a given texture. In at least one embodiment, media samplers 2506A-2506F can perform similar read operations based on the type and format associated with the media data. In at least one embodiment, each graphics subcore 2501A-2501F may alternately include a uniform 3D and media sampler. In at least one embodiment, threads executing on execution units within each subcore 2501A-2501F may utilize shared local memory 2508A-2508F within each subcore, enabling threads executing within a thread group to use a common pool of on-chip memory for execution.

[0303] Inference and / or training logic 615 is used to perform inference and / or training operations associated with one or more embodiments. The following is in conjunction with... Figure 6A and / or Figure 6BDetails regarding inference and / or training logic 615 are provided. In at least one embodiment, some or all of the inference and / or training logic 615 may be incorporated into graphics processor 2510. For example, in at least one embodiment, the training and / or inference techniques described herein may be used in graphics processor 2312, graphics microcontroller 2538, geometry and fixed-function pipelines 2514 and 2536, or Figure 24 One or more ALUs implemented in other logic within the [the system]. Furthermore, in at least one embodiment, the inference and / or training operations described herein can use, in addition to [other methods]... Figure 6A Alternatively, it may be accomplished using logic other than that shown in 6B. In at least one embodiment, the weight parameters may be stored in on-chip or off-chip memory and / or registers (shown or not shown), which configure the ALU of the graphics processor 2500 to execute one or more machine learning algorithms, neural network architectures, use cases, or training techniques described herein.

[0304] Inference and / or training logic 615 is used to perform inference and / or training operations associated with one or more embodiments. In at least one embodiment, this logic may be used with components of these graphs to generate a three-dimensional image of the determined view based on two-dimensional images from any number of cameras.

[0305] Figures 26A-26B The diagram illustrates thread execution logic 2600 of an array of processing elements including a graphics processor core, according to at least one embodiment. Figure 26A At least one embodiment is shown in which thread execution logic 2600 is used. Figure 26B Exemplary internal details of an execution unit according to at least one embodiment are shown.

[0306] like Figure 26AAs shown, in at least one embodiment, the thread execution logic 2600 includes a shader processor 2602, a thread dispatcher 2604, an instruction cache 2606, a scalable execution unit array including multiple execution units 2608A-2608N, one or more samplers 2610, a data cache 2612, and a data port 2614. In at least one embodiment, the scalable execution unit array can be dynamically expanded by enabling or disabling one or more execution units (e.g., any one of execution units 2608A, 2608B, 2608C, 2608D to 2608N-1 and 2608N) based on, for example, the computational requirements of the workload. In at least one embodiment, the scalable execution units are interconnected via an interconnect structure linking to each execution unit in the execution units. In at least one embodiment, the thread execution logic 2600 includes one or more connections to memory (such as system memory or cache memory) via one or more of the instruction cache 2606, data port 2614, sampler 2610, and execution units 2608A-2608N. In at least one embodiment, each execution unit (e.g., 2608A) is an independent programmable general-purpose computing unit capable of executing multiple concurrent hardware threads and processing multiple data elements in parallel for each thread. In at least one embodiment, the array of execution units 2608A-2608N is scalable to include any number of individual execution units.

[0307] In at least one embodiment, execution units 2608A-2608N are primarily used to execute shader programs. In at least one embodiment, shader processor 2602 can handle different shader programs and dispatch execution threads associated with the shader programs via thread dispatcher 2604. In at least one embodiment, thread dispatcher 2604 includes logic for arbitrating thread initiation requests from the graphics and media pipeline and instantiating the requested thread on one or more execution units 2608A-2608N. For example, in at least one embodiment, the geometry pipeline can dispatch vertex, tessellation, or geometry shaders to thread execution logic for processing. In at least one embodiment, thread dispatcher 2604 can also handle runtime thread generation requests from executing shader programs.

[0308] In at least one embodiment, execution units 2608A-2608N support an instruction set that includes native support for many standard 3D graphics shader instructions, enabling the execution of shader programs from graphics libraries (e.g., Direct3D and OpenGL) with minimal translation. In at least one embodiment, the execution units support vertex and geometry processing (e.g., vertex programs, geometry programs, vertex shaders), pixel processing (e.g., pixel shaders, fragment shaders), and general processing (e.g., computation and media shaders). In at least one embodiment, each of the execution units 2608A-2608N, comprising one or more arithmetic logic units (ALUs), is capable of multiple-issue single-instruction multiple-data (SIMD) execution, and multithreaded operation enables an efficient execution environment despite higher memory access latency. In at least one embodiment, each hardware thread within each execution unit has a dedicated high-bandwidth register file and associated independent thread states. In at least one embodiment, execution is multi-clockwise for pipelines capable of performing integer, single-precision and double-precision floating-point operations, SIMD branching capabilities, logical operations, a priori operations, and other miscellaneous operations. In at least one embodiment, while waiting for data from one of the memory or shared functions, dependency logic within the execution units 2608A-2608N causes the waiting thread to sleep until the requested data has been returned. In at least one embodiment, while the waiting thread sleeps, hardware resources can be dedicated to processing other threads. For example, in at least one embodiment, during the latency associated with vertex shader operations, the execution unit can perform operations for a pixel shader, fragment shader, or another type of shader program (containing different vertex shaders).

[0309] In at least one embodiment, each execution unit in execution units 2608A-2608N operates on an array of data elements. In at least one embodiment, the number of data elements is an "execution size" or the number of channels for instructions. In at least one embodiment, an execution channel is a logical unit for execution of data element access, masking, and flow control within an instruction. In at least one embodiment, multiple channels may be independent of multiple physical arithmetic logic units (ALUs) or floating-point units (FPUs) for a particular graphics processor. In at least one embodiment, execution units 2608A-2608N support both integer and floating-point data types.

[0310] In at least one embodiment, the execution unit instruction set includes SIMD instructions. In at least one embodiment, different data elements can be stored as compact data types in registers, and the execution unit will process different elements based on their data size. For example, in at least one embodiment, when operating on a 256-bit wide vector, the 256 bits of the vector are stored in registers, and the execution unit operates on the vector as four separate 64-bit compact data elements (four-word (QW) size data elements), eight separate 32-bit compact data elements (double-word (DW) size data elements), sixteen separate 16-bit compact data elements (word (W) size data elements), or 32 separate 8-bit data elements (byte (B) size data elements). However, in at least one embodiment, different vector widths and register sizes are possible.

[0311] In at least one embodiment, one or more execution units may be combined into fused execution units 2609A-2609N having common thread control logic (2607A-2607N) for fused EUs. In at least one embodiment, multiple EUs may be fused into an EU group. In at least one embodiment, each EU in the fused EU group may be configured to execute a separate SIMD hardware thread. The number of EUs in the fused EU group may vary depending on the embodiment. In at least one embodiment, different SIMD widths may be executed per EU, including but not limited to SIMD8, SIMD16, and SIMD32. In at least one embodiment, each fused graphics execution unit 2609A-2609N includes at least two execution units. For example, in at least one embodiment, fused execution unit 2609A includes a first EU 2608A, a second EU 2608B, and thread control logic 2607A shared by the first EU 2608A and the second EU 2608B. In at least one embodiment, thread control logic 2607A controls the threads executing on the fused graphics execution unit 2609A, thereby allowing each EU within the fused execution units 2609A-2609N to execute using a common instruction pointer register.

[0312] In at least one embodiment, one or more internal instruction caches (e.g., 2606) are included in the thread execution logic 2600 to cache thread instructions of the execution unit. In at least one embodiment, one or more data caches (e.g., 2612) are included to cache thread data during thread execution. In at least one embodiment, a sampler 2610 is included to provide texture sampling for 3D operations and media sampling for media operations. In at least one embodiment, the sampler 2610 includes dedicated texture or media sampling functions for processing texture or media data during a sampling process prior to providing sampled data to the execution unit.

[0313] In at least one embodiment, during execution, the graphics and media pipeline sends a thread initiation request to thread execution logic 2600 via thread generation and scheduling logic. In at least one embodiment, once a set of geometric objects has been processed and rasterized into pixel data, pixel processor logic (e.g., pixel shader logic, fragment shader logic, etc.) within shader processor 2602 is invoked to further compute output information and causes the results to be written to an output surface (e.g., color buffer, depth buffer, stencil buffer, etc.). In at least one embodiment, the pixel shader or fragment shader computes values ​​of different vertex attributes to be interpolated across rasterized objects. In at least one embodiment, the pixel processor logic within shader processor 2602 then executes a pixel or fragment shader program provided by an application programming interface (API). In at least one embodiment, to execute the shader program, shader processor 2602 dispatches threads to execution units (e.g., 2608A) via thread dispatcher 2604. In at least one embodiment, shader processor 2602 uses texture sampling logic in sampler 2610 to access texture data in a texture map stored in memory. In at least one embodiment, arithmetic operations on the texture data and the input geometry data are performed to calculate the pixel color data of each geometric segment, or to discard one or more pixels from further processing.

[0314] In at least one embodiment, data port 2614 provides a memory access mechanism for thread execution logic 2600 to output processed data to memory for further processing on the graphics processor output pipeline. In at least one embodiment, data port 2614 includes or is coupled to one or more cache memories (e.g., data cache 2612) to cache data for memory access via the data port.

[0315] like Figure 26BAs shown, in at least one embodiment, the graphics execution unit 2608 may include an instruction fetch unit 2637, a general-purpose register file array (GRF) 2624, an architecture register file array (ARF) 2626, a thread arbiter 2622, a send unit 2630, a branch unit 2632, a set of SIMD floating-point units (FPUs) 2634, and, in at least one embodiment, a set of dedicated integer SIMD ALUs 2635. In at least one embodiment, the GRF 2624 and ARF 2626 include a set of general-purpose register files and architecture register files associated with each concurrent hardware thread that may be active in the graphics execution unit 2608. In at least one embodiment, per-thread architecture state is maintained in the ARF 2626, while data used during thread execution is stored in the GRF 2624. In at least one embodiment, the execution state of each thread, including the instruction pointer for each thread, may be stored in thread-specific registers in the ARF 2626.

[0316] In at least one embodiment, the graphics execution unit 2608 has an architecture combining simultaneous multithreading (SMT) and fine-grained interleaved multithreading (IMT). In at least one embodiment, the architecture has a modular configuration that can be fine-tuned at design time based on a target number of simultaneous threads and the number of registers per execution unit, wherein execution unit resources are partitioned across logic used to execute multiple simultaneous threads.

[0317] In at least one embodiment, the graphics execution unit 2608 can jointly issue multiple instructions, each of which can be different. In at least one embodiment, the thread arbiter 2622 of the graphics execution unit thread 2608 can dispatch instructions to one of the sending unit 2630, the branching unit 2642, or the SIMD FPU 2634 for execution. In at least one embodiment, each execution thread can access 128 general-purpose registers within the GRF2624, each register capable of storing 32 bytes, accessible as a vector of SIMD8 elements as 32-bit data elements. In at least one embodiment, each execution unit thread accesses 4KB within the GRF2624, although embodiments are not limited thereto, and more or fewer register resources may be provided in other embodiments. In at least one embodiment, up to seven threads can execute concurrently, but the number of threads per execution unit may also vary depending on the embodiment. In at least one embodiment, where seven threads can access 4KB, the GRF2624 can store a total of 28KB. In at least one embodiment, flexible addressing modes allow registers to be addressed together to efficiently construct wider registers or data structures representing striped rectangular blocks.

[0318] In at least one embodiment, a "send" instruction executed via message sending unit 2630 is used to dispatch memory operations, sampler operations, and other long-latency system communications. In at least one embodiment, branch instructions are dispatched to dedicated branch unit 2632 to facilitate SIMD divergence and eventual convergence.

[0319] In at least one embodiment, the graphics execution unit 2608 includes one or more SIMD floating-point units (FPUs) 2634 for performing floating-point operations. In at least one embodiment, the FPUs 2634 also support integer computation. In at least one embodiment, one or more FPUs 2634 can perform up to M 32-bit floating-point (or integer) operations in SIMD, or up to 2M 16-bit integer or 16-bit floating-point operations in SIMD. In at least one embodiment, at least one of the FPUs provides extended mathematical capabilities to support high-throughput a priori mathematical functions and double-precision 64-bit floating-point operations. In at least one embodiment, a set of 8-bit integer SIMD ALUs 2635 are also present and can be specifically optimized to perform operations associated with machine learning computations.

[0320] In at least one embodiment, an array of multiple instances of the graphics execution unit 2608 may be instantiated in a grouping of graphics subcores (e.g., subslices). In at least one embodiment, the execution unit 2608 may execute instructions across multiple execution channels. In at least one embodiment, each thread executed on the graphics execution unit 2608 executes on a different channel.

[0321] Inference and / or training logic 615 is used to perform inference and / or training operations associated with one or more embodiments. The following is in conjunction with... Figure 6A and / or Figure 6B Details are provided regarding the inference and / or training logic 615. In at least one embodiment, some or all of the inference and / or training logic 615 may be incorporated into the execution logic 2600. Furthermore, in at least one embodiment, the inference and / or training operations described herein may use, in addition to... Figure 6A Alternatively, it may be accomplished using logic other than that shown in 6B. In at least one embodiment, the weight parameters may be stored in on-chip or off-chip memory and / or registers (shown or not shown), which configure the ALU of execution logic 2600 to execute one or more machine learning algorithms, neural network architectures, use cases, or training techniques described herein.

[0322] Inference and / or training logic 615 is used to perform inference and / or training operations associated with one or more embodiments. In at least one embodiment, this logic may be used with components of these graphs to generate a three-dimensional image of the determined view based on two-dimensional images from any number of cameras.

[0323] Figure 27 A parallel processing unit (“PPU”) 2700 according to at least one embodiment is illustrated. In at least one embodiment, the PPU 2700 is configured with machine-readable code that, if executed by the PPU 2700, causes the PPU 2700 to perform some or all of the processes and techniques described herein. In at least one embodiment, the PPU 2700 is a multi-threaded processor implemented on one or more integrated circuit devices and utilizes multi-threading as a latency-hiding technique for processing computer-readable instructions (also referred to as machine-readable instructions or simply instructions) on multiple threads in parallel. In at least one embodiment, a thread refers to an executing thread and is an example of a set of instructions configured to be executed by the PPU 2700. In at least one embodiment, the PPU 2700 is a graphics processing unit (“GPU”) configured to implement a graphics rendering pipeline for processing three-dimensional (“3D”) graphics data to generate two-dimensional (“2D”) image data for display on a display device (such as a liquid crystal display (“LCD”) device). In at least one embodiment, the PPU2700 is used to perform computations such as linear algebra operations and machine learning operations. Figure 27 An example parallel processor is shown for illustrative purposes only and should be interpreted as a non-limiting example of processor architectures considered within the scope of this disclosure, and any suitable processor may be employed to complement and / or replace them.

[0324] In at least one embodiment, one or more PPU2700s are configured to accelerate high-performance computing (“HPC”), data centers, and machine learning applications. In at least one embodiment, the PPU2700 is configured to accelerate deep learning systems and applications, including, but not limited to, the following non-limiting examples: autonomous vehicle platforms, deep learning, high-precision speech, image, and text recognition systems, intelligent video analytics, molecular simulation, drug discovery, disease diagnosis, weather forecasting, big data analytics, astronomy, molecular dynamics simulation, financial modeling, robotics, factory automation, real-time language translation, online search optimization, and personalized user recommendations.

[0325] In at least one embodiment, the PPU 2700 includes, but is not limited to: an input / output (“I / O”) unit 2706, a front-end unit 2710, a scheduler unit 2712, a job allocation unit 2714, a hub 2716, a crossbar (“Xbar”) 2720, one or more general-purpose processing clusters (“GPCs”) 2718, and one or more partitioning units (“memory partitioning units”) 2722. In at least one embodiment, the PPU 2700 is connected to a host processor or other PPU 2700 via one or more high-speed GPU interconnects (“GPU interconnects”) 2708. In at least one embodiment, the PPU 2700 is connected to a host processor or other peripheral device via an interconnect 2702. In at least one embodiment, the PPU 2700 is connected to local memory including one or more memory devices (“memory”) 2704. In at least one embodiment, the memory device 2704 includes, but is not limited to, one or more dynamic random access memory (“DRAM”) devices. In at least one embodiment, one or more DRAM devices are configured and / or configurable as a high-bandwidth memory (“HBM”) subsystem, wherein multiple DRAM dies are stacked within each device.

[0326] In at least one embodiment, the high-speed GPU interconnect 2708 may refer to a wire-based multi-channel communication link used by the system to scale and include one or more PPUs 2700 combined with one or more central processing units (“CPUs”), supporting cache coherency between the PPUs 2700 and the CPUs, and CPU control. In at least one embodiment, data and / or commands are transmitted by the high-speed GPU interconnect 2708 via hub 2716 to other units of the PPUs 2700 (such as one or more copy engines, video encoders, video decoders, power management units, and...). Figure 27 Other components not explicitly shown in the document) or from other units of the PPU2700 (such as one or more copy engines, video encoders, video decoders, power management units, and Figure 27 (Other components not explicitly shown in the text) are transmitted.

[0327] In at least one embodiment, the I / O unit 2706 is configured to send and receive data from the host processor via the system bus 2702. Figure 27Communication (e.g., commands, data) is not shown in the diagram. In at least one embodiment, I / O unit 2706 communicates directly with the main processor via system bus 2702 or through one or more intermediate devices (such as memory bridges). In at least one embodiment, I / O unit 2706 can communicate with one or more other processors (such as one or more PPUs 2700) via system bus 2702. In at least one embodiment, I / O unit 2706 implements a Peripheral Component Interconnect High-Speed ​​(“PCIe”) interface for communication on the PCIe bus. In at least one embodiment, I / O unit 2706 implements an interface for communication with external devices.

[0328] In at least one embodiment, I / O unit 2706 decodes data packets received via system bus 2702. In at least one embodiment, at least some data packets represent commands configured to cause PPU 2700 to perform different operations. In at least one embodiment, I / O unit 2706 transmits the decoded commands to different other units of PPU 2700, as specified by the command. In at least one embodiment, the commands are transmitted to front-end unit 2710 and / or to hub 2716 or other units of PPU 2700, such as one or more copy engines, video encoders, video decoders, power management units, etc. Figure 27 (Not explicitly shown). In at least one embodiment, I / O unit 2706 is configured to route communication between or among different logical units of PPU 2700.

[0329] In at least one embodiment, a program executed by the host processor encodes a command stream in a buffer that provides a workload to the PPU2700 for processing. In at least one embodiment, the workload includes instructions and data processed by those instructions. In at least one embodiment, the buffer is an area of ​​memory accessible (e.g., read / write) by the host processor and the PPU2700—the host interface unit can be configured to access the buffer in system memory connected to the system bus 2702 via memory requests sent via the system bus 2702 through the I / O unit 2706. In at least one embodiment, the host processor writes the command stream to the buffer and then issues a pointer to the start of the command stream to the PPU2700, such that the front-end unit 2710 receives pointers to one or more command streams and manages one or more command streams, reads commands from the command streams, and forwards the commands to the respective units of the PPU2700.

[0330] In at least one embodiment, front-end unit 2710 is coupled to scheduler unit 2712, which configures different GPCs 2718 to process tasks defined by one or more command streams. In at least one embodiment, scheduler unit 2712 is configured to track status information related to the different tasks managed by scheduler unit 2712, wherein the status information may indicate which GPC 2718 a task is assigned to, whether the task is active or inactive, the priority associated with the task, etc. In at least one embodiment, scheduler unit 2712 manages the execution of multiple tasks on one or more GPCs 2718.

[0331] In at least one embodiment, scheduler unit 2712 is coupled to job allocation unit 2714, which is configured to assign tasks for execution on GPC 2718. In at least one embodiment, job allocation unit 2714 tracks multiple scheduled tasks received from scheduler unit 2712, and manages a pending task pool and an active task pool for each GPC 2718. In at least one embodiment, the pending task pool includes multiple time slots (e.g., 32 time slots) containing tasks assigned to be processed by a particular GPC 2718; the active task pool may include multiple slots (e.g., 4 slots) for tasks actively processed by GPC 2718, such that when one of the GPCs 2718 completes the execution of a task, that task is evicted from the active task pool for GPC 2718, and one of the other tasks from the pending task pool is selected and scheduled for execution on GPC 2718. In at least one embodiment, if an active task is idle on GPC 2718, such as while waiting for data correlations to be resolved, the active task is evicted from GPC 2718 and returned to the pending task pool, while another task in the pending task pool is selected and scheduled for execution on GPC 2718.

[0332] In at least one embodiment, the work allocation unit 2714 communicates with one or more GPCs 2718 via XBar 2720. In at least one embodiment, XBar 2720 is an interconnect network that couples a plurality of units of PPU 2700 to other units of PPU 2700, and can be configured to couple the work allocation unit 2714 to a specific GPC 2718. In at least one embodiment, one or more other units of PPU 2700 may also be connected to XBar 2720 via hub 2716.

[0333] In at least one embodiment, tasks are managed by scheduler unit 2712 and dispatched to one of GPCs 2718 by job allocation unit 2714. GPCs 2718 are configured to process tasks and produce results. In at least one embodiment, results may be consumed by other tasks within GPCs 2718, routed to different GPCs 2718 via XBar 2720, or stored in memory 2704. In at least one embodiment, results may be written to memory 2704 via partitioning unit 2722, which implements a memory interface for reading and writing data to memory 2704. In at least one embodiment, results may be transferred to another PPU 2704 or CPU via high-speed GPU interconnect 2708. In at least one embodiment, PPU 2700 includes, but is not limited to, a number U of partitioning units 2722, equal to the number of individual and distinct storage devices 2704 coupled to PPU 2700. In at least one embodiment, the following will be combined with… Figure 29 The partition unit 2722 is described in more detail.

[0334] In at least one embodiment, the host processor executes a driver kernel that implements an application programming interface (“API”) that enables one or more applications executing on the host processor to schedule operations for execution on the PPU2700. In at least one embodiment, the PPU 2700 executes multiple computing applications simultaneously, and the PPU 2700 provides isolation, Quality of Service (“QoS”), and independent address spaces for the multiple computing applications. In at least one embodiment, application generation causes the driver kernel to generate instructions (e.g., in the form of API calls) for one or more tasks executed by the PPU2700 and for the driver kernel to output tasks to one or more streams processed by the PPU2700. In at least one embodiment, each task includes one or more sets of associated yarns, which may be referred to as warps. In at least one embodiment, the warps include multiple associated yarns (e.g., 32 yarns) that can be executed in parallel. In at least one embodiment, a cooperating thread may refer to multiple threads that include instructions for performing tasks and exchanging data via shared memory. In at least one embodiment, combined with... Figure 29 The threads and cooperating threads are described in more detail according to at least one embodiment.

[0335] Inference and / or training logic 615 is used to perform inference and / or training operations associated with one or more embodiments. The following is in conjunction with... Figure 6A and / or Figure 6BDetails regarding the inference and / or training logic 615 are provided. In at least one embodiment, a deep learning application processor is used to train a machine learning model (such as a neural network) to predict or infer information provided to the PPU2700. In at least one embodiment, the PPU2700 is used to infer or predict information based on a trained machine learning model (e.g., a neural network) that has been trained by another processor or system or by the PPU2700. In at least one embodiment, the PPU2700 can be used to perform one or more neural network use cases described herein.

[0336] Inference and / or training logic 615 is used to perform inference and / or training operations associated with one or more embodiments. In at least one embodiment, this logic may be used with components of these graphs to generate a three-dimensional image of the determined view based on two-dimensional images from any number of cameras.

[0337] Figure 28 A general-purpose processing cluster (“GPC”) 2800 according to at least one embodiment is illustrated. In at least one embodiment, the GPC 2800 is Figure 27 The GPC 2718. In at least one embodiment, each GPC 2800 includes, but is not limited to, multiple hardware units for processing tasks, and each GPC 2800 includes, but is not limited to, a pipeline manager 2802, a pre-raster operation unit (“PROP”) 2804, a raster engine 2808, a work assignment crossbar switch (“WDX”) 2816, a memory management unit (“MMU”) 2818, one or more data processing clusters (“DPC”) 2806, and any suitable combination of components.

[0338] In at least one embodiment, the operation of GPC 2800 is controlled by pipeline manager 2802. In at least one embodiment, pipeline manager 2802 manages the configuration of one or more DPCs 2806 for processing tasks assigned to GPC 2800. In at least one embodiment, pipeline manager 2802 configures at least one of one or more DPCs 2806 to implement at least a portion of the graphics rendering pipeline. In at least one embodiment, DPC 2806 is configured to execute vertex shader programs on programmable streaming multiprocessor (“SM”) 2814. In at least one embodiment, pipeline manager 2802 is configured to route packets received from the work allocation unit to appropriate logical units within GPC 2800; in at least one embodiment, some packets may be routed to fixed-function hardware units in PROP 2804 and / or raster engine 2808, while other packets may be routed to DPC 2806 for processing by primitive engine 2812 or SM 2814. In at least one embodiment, pipeline manager 2802 configures at least one DPC in DPC 2806 to implement a neural network model and / or computation pipeline.

[0339] In at least one embodiment, PROP unit 2804 is configured to route data generated by raster engine 2808 and DPC 2806 to raster operation (“ROP”) units in partition unit 2722, in conjunction with the above. Figure 27 More detailed description. In at least one embodiment, the PROP unit 2804 is configured to perform optimizations for color blending, organizing pixel data, performing address translation, etc. In at least one embodiment, the raster engine 2808 includes, but is not limited to, multiple fixed-function hardware units configured to perform different raster operations. In at least one embodiment, the raster engine 2808 includes, but is not limited to, a setup engine, a coarse raster engine, a culling engine, a clipping engine, a fine raster engine, a patch merging engine, and any suitable combination thereof. In at least one embodiment, the setup engine receives transformed vertices and generates plane equations associated with the geometric primitives defined by the vertices; the plane equations are transmitted to the coarse raster engine to generate coverage information for primitives (e.g., x, y coverage masks of patches); the output of the coarse raster engine is transmitted to the culling engine, in which fragments associated with primitives that fail the z-test are culled, and is transmitted to the clipping engine, in which fragments located outside the view frustum are clipped. In at least one embodiment, the fragments present after clipping and culling are passed to a fine raster engine to generate properties of the pixel fragments based on plane equations generated by the setting engine. In at least one embodiment, the output of the raster engine 2808 includes fragments that will be processed by any suitable entity, such as the fragment shader implemented within the DPC 2806.

[0340] In at least one embodiment, each DPC 2806 included in the GPC 2800 includes, but is not limited to, an M-pipeline controller (“MPC”) 2810; a primitive engine 2812; one or more SMs 2814; and any suitable combination thereof. In at least one embodiment, the MPC 2810 controls the operation of the DPC 2806, routing packets received from the pipeline manager 2802 to the appropriate units within the DPC 2806. In at least one embodiment, packets associated with vertices are routed to the primitive engine 2812, which is configured to retrieve vertex attributes associated with vertices from memory; conversely, packets associated with shader programs may be emitted to the SMs 2814.

[0341] In at least one embodiment, the SM2814 includes, but is not limited to, a programmable stream processor configured to process tasks represented by multiple threads. In at least one embodiment, the SM2814 is multithreaded and configured to concurrently execute multiple threads (e.g., 32 threads) from a specific thread group and implement a Single Instruction, Multiple Data (“SIMD”) architecture, wherein each thread in a group of threads (e.g., meridians) is configured to process different datasets based on the same instruction set. In at least one embodiment, all threads in the thread group execute the same instructions. In at least one embodiment, the SM2814 implements a Single Instruction, Multiple Thread (“SIMT”) architecture, wherein each thread in a group of threads is configured to process different data sets based on the same instruction set, but wherein individual threads in the group are allowed to fork during execution. In at least one embodiment, a program counter, call stack, and execution state are maintained for each meridian, thereby achieving concurrency between serial executions within a meridian when threads diverge within a meridian. In another embodiment, a program counter, call stack, and execution state are maintained for each individual thread, thereby achieving equal concurrency between all threads, within a meridian, and between meridians. In at least one embodiment, each individual thread maintains an execution state, and for better efficiency, threads executing the same instructions can be converged and executed in parallel. At least one embodiment of the SM2814 is described in more detail below.

[0342] In at least one embodiment, the MMU 2818 is integrated with the GPC 2800 and memory partitioning unit (e.g., Figure 27 The MMU 2818 provides an interface between the partition units 2722 and the physical address translation, memory protection, and memory request arbitration. In at least one embodiment, the MMU 2818 provides one or more translation back buffers (“TLBs”) for performing translations from virtual addresses to physical addresses in memory.

[0343] Inference and / or training logic 615 is used to perform inference and / or training operations associated with one or more embodiments. The following is in conjunction with... Figure 6A and / or Figure 6B Details regarding the inference and / or training logic 615 are provided. In at least one embodiment, a deep learning application processor is used to train a machine learning model (such as a neural network) to predict or infer information provided to the GPC2800. In at least one embodiment, the GPC2800 is used to infer or predict information based on a trained machine learning model (e.g., a neural network) that has been trained by another processor or system or by the GPC2800. In at least one embodiment, the GPC2800 can be used to perform one or more neural network use cases described herein.

[0344] Inference and / or training logic 615 is used to perform inference and / or training operations associated with one or more embodiments. In at least one embodiment, this logic may be used with components of these graphs to generate a three-dimensional image of the determined view based on two-dimensional images from any number of cameras.

[0345] Figure 29 A memory partitioning unit 2900 of a parallel processing unit (“PPU”) according to at least one embodiment is shown. In at least one embodiment, the memory partitioning unit 2900 includes, but is not limited to, a raster operation (“ROP”) unit 2902; a secondary (“L2”) cache 2904; a memory interface 2906; and any suitable combination thereof. In at least one embodiment, the memory interface 2906 is coupled to memory. In at least one embodiment, the memory interface 2906 may implement a 32, 64, 128, 1024-bit data bus or similar implementation for high-speed data transfer. In at least one embodiment, the PPU incorporates U memory interfaces 2906, one memory interface 2906 per pair of partitioning units 2900, wherein each pair of partitioning units 2900 is connected to a corresponding memory device. For example, in at least one embodiment, the PPU may be connected to up to Y memory devices, such as a high-bandwidth memory stack or graphics double data rate, version 5, synchronous dynamic random-access-free memory (“GDDR5 SDRAM”).

[0346] In at least one embodiment, the memory interface 2906 implements a high-bandwidth second-generation (“HBM2”) memory interface, and Y equals half U. In at least one embodiment, the HBM2 memory stack resides on the same physical package as the PPU, providing significant power and area savings compared to conventional GDDR5 SDRAM systems. In at least one embodiment, each HBM2 stack includes, but is not limited to, four memory dies, and Y equals 4, wherein each HBM2 stack includes two 128-bit channels per die, for a total of eight channels and a 1024-bit data bus width. In at least one embodiment, the memory supports Single Error Corrected Double Error Detection (“SECDED”) error correction code (“ECC”) to protect data. In at least one embodiment, ECC provides higher reliability for data corruption-sensitive computing applications.

[0347] In at least one embodiment, the PPU implements a multi-level memory hierarchy. In at least one embodiment, the memory partitioning unit 2900 supports unified memory to provide a single unified virtual address space for the central processing unit (“CPU”) and PPU memory, thereby enabling data sharing between virtual memory systems. In at least one embodiment, the frequency of PPU accesses to memory located on other processors is tracked to ensure that memory pages are moved to the physical memory of the PPU that accesses pages more frequently. In at least one embodiment, the high-speed GPU interconnect 2708 supports address translation services that allow the PPU to directly access the CPU's page tables and provide full access to the CPU's memory through the PPU.

[0348] In at least one embodiment, the replication engine transfers data between multiple PPUs or between a PPU and a CPU. In at least one embodiment, the replication engine may generate a page fault for an address not mapped to a page table, and the memory partitioning unit 2900 then serves the page fault, maps the address to the page table, after which the replication engine performs the transfer. In at least one embodiment, for multiple replication engine operations across multiple processors, memory is pinned (i.e., not pageable), thereby significantly reducing available memory. In at least one embodiment, in the event of a hardware page fault, the address can be passed to the replication engine regardless of whether the memory page resides, and the replication process is transparent.

[0349] According to at least one embodiment, from Figure 27Data from memory 2704 or other system memory is retrieved by memory partitioning unit 2900 and stored in L2 cache 2904, which is located on-chip and shared between different GPCs. In at least one embodiment, each memory partitioning unit 2900 includes, but is not limited to, at least a portion of the L2 cache associated with the corresponding memory device. In at least one embodiment, lower-level caches are implemented in different units within the GPC. In at least one embodiment, each SM2814 may implement a Level 1 (“L1”) cache, wherein the L1 cache is a private memory dedicated to a specific SM2814, and data from L2 cache 2904 is retrieved and stored in each L1 cache for processing in the functional units of the SM2814. In at least one embodiment, L2 cache 2904 is coupled to memory interface 2906 and XBar 2720.

[0350] In at least one embodiment, ROP unit 2902 performs pixel color-related raster operations, such as color compression, pixel blending, and more. In at least one embodiment, ROP unit 2902 performs depth testing in conjunction with raster engine 2808, receiving depth from the culling engine of raster engine 2808 for sample locations associated with pixel fragments. In at least one embodiment, depth is tested for a corresponding depth in a depth buffer for the sample location associated with the fragment. In at least one embodiment, if the fragment passes the depth test for the sample location, then ROP unit 2902 updates the depth buffer and emits the result of the depth test to raster engine 2808. It will be understood that the number of partition units 2900 may differ from the number of GPCs, and therefore, in at least one embodiment, each ROP unit 2902 may be coupled to each of the GPCs. In at least one embodiment, ROP unit 2902 tracks packets received from different GPCs and determines which one the results generated by ROP unit 2902 are routed to via XBar 2720.

[0351] Figure 30 A streaming multiprocessor (“SM”) 3000 according to at least one embodiment is illustrated. In at least one embodiment, the SM 3000 is Figure 28The SM 2814. In at least one embodiment, the SM 3000 includes, but is not limited to, an instruction cache 3002; one or more scheduler units 3004; a register file 3008; one or more processing units (“cores”) 3010; one or more special function units (“SFUs”) 3012; one or more load / store units (“LSUs”) 3014; an interconnect network 3016; a shared memory / Level 1 (“L1”) cache 3018; and any suitable combination thereof. In at least one embodiment, a work allocation unit assigns tasks for execution on a general-purpose processing cluster (“GPC”) of parallel processing units (“PPUs”), and each task is assigned to a specific data processing cluster (“DPC”) within the GPC, and if the task is associated with a shader program, the task is assigned to one of the SM 3000s. In at least one embodiment, a scheduler unit 3004 receives tasks from the work allocation unit and manages the instruction scheduling of one or more thread blocks assigned to the SM 3000. In at least one embodiment, scheduler unit 3004 schedules thread blocks for execution as meridians of parallel threads, wherein each thread block is assigned at least one meridian. In at least one embodiment, each meridian executes a line. In at least one embodiment, scheduler unit 3004 manages multiple different thread blocks, assigns meridians to different thread blocks, and then dispatches instructions from multiple different cooperative groups to various functional units (e.g., processing units 3010, SFU 3012, and LSU 3014) during each clock cycle.

[0352] In at least one embodiment, a cooperative group can refer to a programming model for organizing groups of threads that communicate, allowing developers to express the granularity at which threads are communicating, enabling richer and more efficient parallel decompositions. In at least one embodiment, a cooperative startup API supports synchronization between blocks of threads for the execution of parallel algorithms. In at least one embodiment, the application of a conventional programming model provides a single, simple construct for synchronizing cooperative threads: a barrier (e.g., the `syncthreads()` function) across all threads in a thread block. However, in at least one embodiment, programmers can define groups of threads at a granularity smaller than that of thread blocks and synchronize within those defined groups to achieve greater performance, design flexibility, and software reuse in the form of a collective, group-wide functional interface. In at least one embodiment, cooperative groups enable programmers to explicitly define thread groups and multi-block granularity at the sub-block level (i.e., down to a single thread) and perform collective operations such as synchronization on threads within the cooperative group. In at least one embodiment, the programming model supports clear composition across software boundaries, allowing libraries and utility functions to be safely synchronized within their local contexts without having to make assumptions about convergence. In at least one embodiment, the cooperative group primitives implement novel patterns of cooperative parallelism, including but not limited to producer-consumer parallelism, opportunistic parallelism, and global synchronization across the entire mesh across thread blocks.

[0353] In at least one embodiment, dispatch unit 3006 is configured to send instructions to one or more functional units, and scheduler unit 3004 includes, but is not limited to, two dispatch units 3006, which enable the dispatching of two different instructions from the same meridian during each clock cycle. In at least one embodiment, each scheduler unit 3004 includes a single dispatch unit 3006 or additional dispatch units 3006.

[0354] In at least one embodiment, each SM3000 includes, but is not limited to, a register file 3008 providing a set of registers for functional units of the SM3000. In at least one embodiment, the register file 3008 is partitioned between each functional unit such that each functional unit is allocated a dedicated portion of the register file 3008. In at least one embodiment, the register file 3008 is partitioned between different meridians executed by the SM3000, and the register file 3008 provides temporary storage for operands connected to data paths of functional units. In at least one embodiment, each SM3000 includes, but is not limited to, a plurality of L processing units 3010. In at least one embodiment, the SM3000 includes, but is not limited to, a large number (e.g., 128 or more) of different processing units 3010. In at least one embodiment, each processing unit 3010 includes, but is not limited to, a fully pipelined, single-precision, double-precision, and / or mixed-precision processing unit, which includes, but is not limited to, a floating-point arithmetic logic unit and an integer arithmetic logic unit. In at least one embodiment, the floating-point arithmetic logic unit implements the IEEE 754-2008 standard for floating-point arithmetic. In at least one embodiment, the processing unit 3010 includes, but is not limited to, 64 single-precision (32-bit) floating-point cores, 64 integer cores, 32 double-precision (64-bit) floating-point cores, and 8 tensor cores.

[0355] According to at least one embodiment, a tensor core is configured to perform matrix operations. In at least one embodiment, one or more tensor cores are included in the processing unit 3010. In at least one embodiment, the tensor cores are configured to perform deep learning matrix operations, such as convolution operations for neural network training and inference. In at least one embodiment, each tensor core operates on a 4x4 matrix and performs matrix multiplication and accumulation operations D = AX B + C, where A, B, C, and D are 4x4 matrices.

[0356] In at least one embodiment, matrix multiplication inputs A and B are 16-bit floating-point matrices, and accumulation matrices C and D are either 16-bit or 32-bit floating-point matrices. In at least one embodiment, the tensor kernel operates on 16-bit floating-point input data with 32-bit floating-point accumulation. In at least one embodiment, 16-bit floating-point multiplication uses 64 operations and results in a full-precision product, which is then accumulated with other intermediate multiplications using 32-bit floating-point addition for 4x4x4 matrix multiplication. In at least one embodiment, the tensor kernel is used to perform matrix operations on much larger two-dimensional or higher-dimensional matrices constructed from these smaller elements. In at least one embodiment, APIs such as the CUDA 9 C++ API expose specialized matrix loading, matrix multiplication and accumulation, and matrix storage operations for efficient use of the tensor kernel from CUDA-C++ programs. In at least one embodiment, at the CUDA level, the meridian-level interface assumes a 16x16 matrix spanning all 32 meridian threads.

[0357] In at least one embodiment, each SM3000 includes, but is not limited to, M SFU3012s performing special functions (e.g., attribute evaluation, inverse square root, etc.). In at least one embodiment, the SFU3012 includes, but is not limited to, a tree traversal unit configured to traverse a hierarchical tree data structure. In at least one embodiment, the SFU3012 includes, but is not limited to, a texture unit configured to perform texture map filtering operations. In at least one embodiment, the texture unit is configured to load a texture map (e.g., a 2D array of texture elements) from memory and sample the texture map to produce sampled texture values ​​for use by a shader program executed by the SM3000. In at least one embodiment, the texture map is stored in shared memory / L1 cache 3018. In at least one embodiment, according to at least one embodiment, the texture unit performs texture operations, such as filtering operations using mip maps (e.g., texture maps with different levels of detail). In at least one embodiment, each SM3000 includes, but is not limited to, two texture units.

[0358] In at least one embodiment, each SM3000 includes, but is not limited to, N LSUs3014 that implement load and store operations between the shared memory / L1 cache 3018 and the register file 3008. In at least one embodiment, each SM3000 includes, but is not limited to, an interconnect network 3016 that connects each of the functional units to the register file 3008 and connects the LSUs3014 to both the register file 3008 and the shared memory / L1 cache 3018. In at least one embodiment, the interconnect network 3016 is a crossbar switch that can be configured to connect any functional unit to any register in the register file 3008 and connect the LSUs3014 to memory locations in both the register file 3008 and the shared memory / L1 cache 3018.

[0359] In at least one embodiment, the shared memory / L1 cache 3018 is an array of on-chip memory that allows data storage and communication between the SM3000 and the primitive engine, as well as between threads within the SM3000. In at least one embodiment, the shared memory / L1 cache 3018 includes, but is not limited to, a storage capacity of 128KB and is located on the path from the SM3000 to the partition unit. In at least one embodiment, the shared memory / L1 cache 3018 is used for cache reads and writes. In at least one embodiment, one or more of the shared memory / L1 cache 3018, the L2 cache, and memory are backup storage.

[0360] In at least one embodiment, combining data caching and shared memory functionality into a single memory block provides improved performance for both types of memory access. In at least one embodiment, for example, if shared memory is configured to use half its capacity, the capacity is used by programs that do not use shared memory or can be used as a cache, while texture and load / store operations can use the remaining capacity. According to at least one embodiment, integration within the shared memory / L1 cache 3018 enables the shared memory / L1 cache 3018 to act as a high-throughput pipeline for streaming data, while providing high-bandwidth and low-latency access to frequently reused data. In at least one embodiment, when configured for general-purpose parallel computing, a simpler configuration can be used compared to graphics processing. In at least one embodiment, a fixed-function graphics processing unit is bypassed, thereby creating a much simpler programming model. In at least one embodiment, in a general-purpose parallel computing configuration, the work allocation unit directly allocates and assigns blocks of threads to the DPC. In at least one embodiment, threads within a block execute the same program, using unique thread IDs in the computation to ensure each thread produces a unique result. The SM3000 executes the program and performs the computation, a shared memory / L1 cache 3018 facilitates communication between threads, and an LSU 3014 is used to read from and write to global memory via the shared memory / L1 cache 3018 and memory partitioning units. In at least one embodiment, when configured for general-purpose parallel computing, the SM3000 can write to the scheduler unit 3004 to initiate commands for new work on the DPC.

[0361] In at least one embodiment, the PPU is included in or coupled thereto in a desktop computer, laptop computer, tablet computer, server, supercomputer, smartphone (e.g., wireless, handheld device), personal digital assistant (“PDA”), digital camera, vehicle, head-mounted display, handheld electronic device, etc. In at least one embodiment, the PPU is implemented on a single semiconductor substrate. In at least one embodiment, the PPU is included in a system-on-a-chip (“SoC”) together with one or more other devices (such as an additional PPU, memory, a reduced instruction set computer (“RISC”) CPU, a memory management unit (“MMU”), a digital-to-analog converter (“DAC”), etc.).

[0362] In at least one embodiment, the PPU may be included on a graphics card that includes one or more memory devices. The graphics card may be configured to interface with a PCIe slot on a desktop computer's motherboard. In at least one embodiment, the PPU may be an integrated graphics processing unit ("iGPU") included in a motherboard chipset.

[0363] Inference and / or training logic 615 is used to perform inference and / or training operations associated with one or more embodiments. The following is in conjunction with... Figure 6A and / or Figure 6B Details regarding the inference and / or training logic 615 are provided. In at least one embodiment, the deep learning application processor is used to train a machine learning model (such as a neural network) to predict or infer information provided to the SM3000. In at least one embodiment, the SM3000 is used to infer or predict information based on a trained machine learning model (e.g., a neural network) that has been trained by another processor or system or by the SM3000. In at least one embodiment, the SM3000 may be used to perform one or more neural network use cases described herein.

[0364] Inference and / or training logic 615 is used to perform inference and / or training operations associated with one or more embodiments. In at least one embodiment, this logic may be used with components of these graphs to generate a three-dimensional image of the determined view based on two-dimensional images from any number of cameras.

[0365] In at least one embodiment, a single semiconductor platform may refer to a unique integrated circuit or chip based on a single semiconductor. In at least one embodiment, a multi-chip module may be used with enhanced connectivity that simulates on-chip operation and represents a substantial improvement over implementations utilizing a conventional central processing unit (“CPU”) and bus. In at least one embodiment, different modules may also be located individually or in different combinations of semiconductor platforms, depending on the user’s wishes.

[0366] In at least one embodiment, a computer program in the form of machine-readable executable code or computer control logic algorithms is stored in main memory 1004 and / or secondary memory. If the computer program is executed by one or more processors, it enables system 1000 to perform different functions according to at least one embodiment. In at least one embodiment, memory 1004, storage devices, and / or any other storage devices are possible examples of computer-readable media. In at least one embodiment, secondary storage devices can refer to any suitable storage device or system, such as hard disk drives and / or removable storage drives, representing floppy disk drives, magnetic tape drives, compact disk drives, digital universal disc (“DVD”) drives, recording devices, universal serial bus (“USB”) flash memory, etc. In at least one embodiment, the architecture and / or functionality of different prior figures are implemented in the context of CPU 1002; parallel processing system 1012; integrated circuits capable of implementing at least a portion of the capabilities of two CPUs 1002; parallel processing system 1012; chipsets (e.g., a set of integrated circuits designed to operate and be sold as units performing related functions); and any suitable combination of one or more integrated circuits.

[0367] In at least one embodiment, the architecture and / or functionality of the different prior figures are implemented within the context of general-purpose computer systems, circuit board systems, game console systems dedicated to entertainment purposes, special-purpose systems, and more. In at least one embodiment, computer system 1000 may take the form of a desktop computer, laptop computer, tablet computer, server, supercomputer, smartphone (e.g., wireless handheld device), personal digital assistant (“PDA”), digital camera, vehicle, head-mounted display, handheld electronic device, mobile phone device, television, workstation, game console, embedded system, and / or any other type of logic.

[0368] In at least one embodiment, the parallel processing system 1012 includes, but is not limited to, multiple parallel processing units (“PPUs”) 1014 and associated memory 1016. In at least one embodiment, the PPUs 1014 are connected to a host processor or other peripheral device via an interconnect 1018 and a switch 1020 or multiplexer. In at least one embodiment, the parallel processing system 1012 distributes computational tasks across the PPUs 1014, and these computational tasks may be parallelizable—for example, as part of distributing computational tasks across multiple graphics processing units (“GPUs”) thread blocks. In at least one embodiment, memory is shared and accessible (e.g., for read and / or write access) across some or all of the PPUs 1014, although such shared memory may cause a performance penalty relative to the use of local memory and registers residing in the PPUs 1014. In at least one embodiment, the operation of the PPUs 1014 is synchronized using commands such as __syncthreads(), wherein all threads in a block (e.g., executed across multiple PPUs 1014) arrive at a certain point of execution of the code before continuing.

[0369] Virtualization computing platform

[0370] Embodiments of a virtualized computing platform for advanced computing, such as image inference and image processing, are disclosed. (Refer to...) Figure 31This is an example data flow diagram of process 3100 for generating and deploying an image processing and inference pipeline according to at least one embodiment. In at least one embodiment, process 3100 can be deployed for use with imaging equipment, processing equipment, genomics equipment, gene sequencing equipment, radiology equipment, and / or other equipment types at one or more facilities 3102, such as medical facilities, hospitals, medical institutions, clinics, research or diagnostic laboratories, etc. In at least one embodiment, process 3100 can be deployed to perform genomic analysis and inference on sequencing data. Examples of genomic analyses that can be performed using the systems and methods described herein include, but are not limited to, variant invocation, mutation detection, and gene expression quantification. Process 3100 can be executed within training system 3104 and / or deployment system 3106. In at least one embodiment, training system 3104 can be used to train, deploy, and implement machine learning models (e.g., neural networks, object detection algorithms, computer vision algorithms, etc.) for use in deployment system 3106. In at least one embodiment, deployment system 3106 can be configured to offload processing and computing resources between distributed computing environments to reduce infrastructure requirements at facility 3102. In at least one embodiment, deployment system 3106 may provide a streamlined platform for selecting, customizing, and implementing virtual instruments at facility 3102 for use with imaging devices (e.g., MRI, CT scans, X-rays, ultrasound, etc.) or sequencing devices. In at least one embodiment, the virtual instrument may include software-defined applications for performing one or more processing operations on imaging data generated by the imaging device, sequencing device, radiology device, and / or other device types. In at least one embodiment, one or more applications in the pipeline may use or invoke services of deployment system 3106 (e.g., inference, visualization, computation, AI, etc.) during application execution.

[0371] In at least one embodiment, some applications in the advanced processing and inference pipeline may use machine learning models or other AI to perform one or more processing steps. In at least one embodiment, the machine learning model may be trained at facility 3102 using data 3108 (such as imaging data) generated at facility 3102 (and stored on one or more Picture Archiving and Communication System (PACS) servers at facility 3102), or using imaging or sequencing data 3108 from another or more facilities (e.g., different hospitals, laboratories, clinics, etc.), or a combination thereof. In at least one embodiment, the training system 3104 may be used to provide applications, services, and / or other resources for generating jobs, deployable machine learning models, for deployment system 3106.

[0372] In at least one embodiment, the model registry 3124 may be supported by an object storage capable of supporting versioning and object metadata. In at least one embodiment, the object storage may be, for example, cloud storage (e.g., Figure 32 The cloud platform (3226)-compatible application programming interface (API) is accessed from within the cloud platform. In at least one embodiment, machine learning models in model registry 3124 can be uploaded, listed, modified, or deleted by the developer or partner of the system interacting with the API. In at least one embodiment, the API can provide access to methods that allow a user with appropriate credentials to associate a model with an application, enabling the model to be executed as part of the containerized instantiation of the application.

[0373] In at least one embodiment, training pipeline 3204 ( Figure 32 This may include a scenario where facility 3102 is training its own machine learning model or has an existing machine learning model that needs to be optimized or updated. In at least one embodiment, imaging data 3108 generated by one or more imaging devices, sequencing devices, and / or other device types may be received. In at least one embodiment, once the imaging data 3108 is received, AI-assisted annotation 3110 may be used to help generate annotations corresponding to the imaging data 3108 for use as ground-based data for machine learning models. In at least one embodiment, AI-assisted annotation 3110 may include one or more machine learning models (e.g., convolutional neural networks (CNNs)) that may be trained to generate annotations corresponding to certain types of imaging data 3108 (e.g., from certain devices) and / or certain types of anomalies in the imaging data 3108. In at least one embodiment, AI-assisted annotation 3110 may then be used directly or may be adjusted or fine-tuned using annotation tools (e.g., by researchers, clinicians, doctors, scientists, etc.) to generate ground-based data. In at least one embodiment, in some examples, labeled clinic data 3112 (e.g., annotations provided by clinicians, doctors, scientists, technicians, etc.) can be used as ground-based data for training a machine learning model. In at least one embodiment, AI-assisted annotations 3110, labeled clinic data 3112, or a combination thereof can be used as ground-based data for training a machine learning model. In at least one embodiment, the trained machine learning model can be referred to as output model 3116 and can be used by deployment system 3106, as described herein.

[0374] In at least one embodiment, training pipeline 3204 ( Figure 32This could include scenarios where facility 3102 requires a machine learning model to perform one or more processing tasks for one or more applications in deployment system 3106, but facility 3102 may not currently have such a machine learning model (or may not have an optimized, efficient, or effective model for such a purpose). In at least one embodiment, an existing machine learning model can be selected from model registry 3124. In at least one embodiment, model registry 3124 may include machine learning models trained to perform various inference tasks on imaging data. In at least one embodiment, the machine learning models in model registry 3124 may have already been trained on imaging data from facilities other than facility 3102 (e.g., remote facilities). In at least one embodiment, the machine learning models may have already been trained on imaging data from one location, two locations, or any number of locations. In at least one embodiment, when training on imaging data from a particular location, training may occur at that location, or at least in a manner that protects the confidentiality of the imaging data or restricts the off-site transmission of the imaging data (e.g., in compliance with HIPAA regulations, privacy regulations, etc.). In at least one embodiment, once the model has been trained or partially trained at one location, the machine learning model can be added to the model registry 3124. In at least one embodiment, the machine learning model can then be retrained or updated at any number of other facilities, and the retrained or updated model can be made available in the model registry 3124. In at least one embodiment, the machine learning model can then be selected from the model registry 3124—and referred to as output model 3116—and can be used in deployment system 3106 to perform one or more processing tasks for one or more applications of the deployment system.

[0375] In at least one embodiment, training pipeline 3204 ( Figure 32One scenario may include facility 3102, which requires a machine learning model to perform one or more processing tasks for one or more applications in deployment system 3106, but facility 3102 may not currently have such a machine learning model (or may not have an optimized, efficient, or effective model for such purposes). In at least one embodiment, the machine learning model selected from model registry 3124 may not be fine-tuned or optimized for the imaging data 3108 generated at facility 3102 due to population differences, genetic variation, robustness of training data used to train the machine learning model, anomalous diversity of training data, and / or other problems with the training data. In at least one embodiment, AI-assisted annotation 3110 may be used to help generate annotations corresponding to imaging data 3108, which is used as ground-based data for retraining or updating the machine learning model. In at least one embodiment, labeled clinic data 3112 (e.g., annotations provided by clinicians, doctors, scientists, etc.) may be used as ground-based data for training the machine learning model. In at least one embodiment, retraining or updating the machine learning model may be referred to as model training 3114. In at least one embodiment, model training 3114 (e.g., AI-assisted annotation 3110, labeled clinic data 3112, or a combination thereof) can be used as ground-based real-world data for retraining or updating the machine learning model. In at least one embodiment, the trained machine learning model can be referred to as output model 3116 and can be used by deployment system 3106, as described herein.

[0376] In at least one embodiment, deployment system 3106 may include software 3118, service 3120, hardware 3122, and / or other components, features, and functions. In at least one embodiment, deployment system 3106 may include a software "stack" such that software 3118 can be built on top of service 3120 and can use service 3120 to perform some or all of the processing tasks, and service 3120 and software 3118 can be built on top of hardware 3122 and use hardware 3122 to perform processing, storage, and / or other computational tasks of deployment system 3106. In at least one embodiment, software 3118 may include any number of different containers, each of which can perform an instantiation of an application. In at least one embodiment, each application can perform one or more processing tasks (e.g., inference, object detection, feature detection, segmentation, image enhancement, calibration, etc.) in high-level processing and inference pipelines. In at least one embodiment, for each type of imaging device (e.g., CT, MRI, X-ray, ultrasound, ultrasound examination, echocardiography, etc.), sequencing device, radiology device, genomics device, etc., any number of containers may exist that can perform data processing tasks relative to the imaging data 3108 (or other data types, such as those described herein) generated by the device. In at least one embodiment, the high-level processing and inference pipeline may be defined based on the selection of different containers desired or required for processing the imaging data 3108, in addition to receiving and configuring imaging data for use by each container and / or for use by facility 3102 after processing through the pipeline (e.g., converting the output back to available data types, such as Medical Digital Imaging and Communications (DICOM) data, Radiology Information System (RIS) data, Clinical Information System (CIS) data, Remote Procedure Call (RPC) data, data substantially conforming to a Representation State Transition (REST) ​​interface, data substantially conforming to a file-based interface, and / or raw data, for storage and display at facility 3102). In at least one embodiment, a combination of containers within software 3118 (e.g., a combination of containers that make up a pipeline) may be referred to as a virtual tool (as described in more detail herein), and the virtual tool may utilize service 3120 and hardware 3122 to perform some or all of the processing tasks of an application exemplified in the container.

[0377] In at least one embodiment, the data processing pipeline may receive input data (e.g., imaging data 3108) in DICOM, RIS, CIS, REST-compatible, RPC, raw, and / or other formats in response to an inference request (e.g., a request from a user (such as a clinician, physician, radiologist, etc.) of deployment system 3106). In at least one embodiment, the input data may represent one or more images, videos, and / or other data representations generated by one or more imaging devices, sequencing devices, radiology devices, genomics devices, and / or other device types. In at least one embodiment, the data may undergo preprocessing as part of the data processing pipeline to prepare the data for processing by one or more applications. In at least one embodiment, postprocessing may be performed on the output of one or more inference tasks or other processing tasks of the pipeline to prepare output data for the next application and / or to prepare output data for user transmission and / or use (e.g., in response to an inference request). In at least one embodiment, the inference task may be performed by one or more machine learning models, such as trained or deployed neural networks, which may include the output model 3116 of training system 3104.

[0378] In at least one embodiment, the tasks of the data processing pipeline can be encapsulated in one or more containers, each representing a discrete, fully functional instantiation of an application capable of referencing a machine learning model and a virtualized computing environment. In at least one embodiment, a container or application can be published to a private (e.g., restricted access) area of ​​a container registry (described in more detail herein), and trained or deployed models can be stored in a model registry 3124 and associated with one or more applications. In at least one embodiment, an image of the application (e.g., a container image) can be available in the container registry, and once selected by a user from the container registry for deployment in the pipeline, the image can be used to generate containers to provide instantiations of the application for use by the user's system.

[0379] In at least one embodiment, a developer (e.g., a software developer, clinician, physician, etc.) may develop, publish, and store an application (e.g., as a container) for performing image processing and / or inference on the provided data. In at least one embodiment, development, publication, and / or storage may be performed using a software development kit (SDK) associated with the system (e.g., to ensure that the developed application and / or container is compatible with the system). In at least one embodiment, at least some of the services 3120 may be utilized as a system (e.g., Figure 32The system 3200's SDK is used to test the developed application locally (e.g., at the first facility, on data from the first facility). In at least one embodiment, because DICOM objects can contain anywhere from one to hundreds of images or other data types, and due to variations in data, the developer can be responsible for managing (e.g., setting up construction, incorporating preprocessing into the application, etc.) the extraction and preparation of the input DICOM data. In at least one embodiment, once validated by the system 3200 (e.g., for accuracy, security, patient privacy, etc.), the application can be available in the container registry for users (e.g., hospitals, clinics, laboratories, healthcare providers, etc.) to select and / or implement to perform one or more processing tasks on data at the user's facility (e.g., a second facility).

[0380] In at least one embodiment, the developer can then share the application or container over the network for the system (e.g., Figure 32 The system 3200 allows for user access and use. In at least one embodiment, completed and validated applications or containers may be stored in a container registry, and associated machine learning models may be stored in a model registry 3124. In at least one embodiment, a requesting entity (e.g., a user at a medical facility) providing an inference or image processing request can browse the container registry and / or model registry 3124 of applications, select desired combinations of elements such as containers, datasets, machine learning models, etc., to include in the data processing pipeline, and submit an imaging processing request. In at least one embodiment, the request may include input data necessary to perform the request (and, in some examples, associated patient data), and / or may include the selection of one or more applications and / or machine learning models to be performed in the processing request. In at least one embodiment, the request may then be passed to one or more components of the deployment system 3106 (e.g., the cloud) to perform processing in the data processing pipeline. In at least one embodiment, the processing performed by the deployment system 3106 may include referencing the selected elements (e.g., applications, containers, models, etc.) from the container registry and / or model registry 3124. In at least one embodiment, once results are generated by the pipeline, they can be returned to the user for reference (e.g., for viewing in a suite of viewing applications running locally, on a field workstation, or on a terminal). In at least one embodiment, radiologists can receive results from a data processing pipeline that includes any number of applications and / or containers, where results may include the detection of abnormalities in X-rays, CT scans, MRIs, etc.

[0381] In at least one embodiment, service 3120 may be utilized to assist in processing or executing applications or containers in the pipeline. In at least one embodiment, service 3120 may include computing services, artificial intelligence (AI) services, visualization services, and / or other service types. In at least one embodiment, service 3120 may provide common functionality to one or more applications in software 3118, thus abstracting functionality into services that can be invoked or utilized by applications. In at least one embodiment, the functionality provided by service 3120 can operate dynamically and more efficiently, while also allowing applications to process data in parallel (e.g., using parallel computing platform 3230). Figure 32 To scale well. In at least one embodiment, service 3120 can be shared between and among different applications, rather than requiring each application sharing the same functionality provided by service 3120 to have a corresponding example of service 3120. In at least one embodiment, as a non-limiting example, the service may include an inference server or engine that can be used to perform detection or segmentation tasks. In at least one embodiment, a model training service may be included, which can provide machine learning model training and / or retraining capabilities. In at least one embodiment, a data augmentation service may be further included, which can provide GPU-accelerated data (e.g., DICOM, RIS, CIS, REST-compatible, RPC, raw, etc.) extraction, resizing, scaling, and / or other enhancements. In at least one embodiment, a visualization service may be used, which can add image rendering effects—such as ray tracing, rasterization, denoising, sharpening, etc.—to add realism to two-dimensional (2D) and / or three-dimensional (3D) models. In at least one embodiment, a virtual instrument service may be included that provides beamforming, segmentation, inference, imaging, and / or support for other applications within the virtual instrument pipeline.

[0382] In at least one embodiment, service 3120 includes an AI service (e.g., an inference service) that can be invoked (e.g., as an API call) to execute one or more machine learning models associated with an application for anomaly detection (e.g., tumors, growth abnormalities, scar formation, etc.), or their processing, as part of application execution. In at least one embodiment, another application includes one or more machine learning models for a segmentation task, which can be invoked according to the inference service to execute one or more machine learning models for performing processing operations associated with the segmentation task. In at least one embodiment, software 3118 implementing the high-level processing...

Claims

1. A processor, comprising: One or more circuits for using one or more neural networks to: Receive two or more two-dimensional 2D images captured by any number of cameras with different reference frames in the environment; Extracting semantic features from two or more 2D images; The semantic features are used to generate a frustum-shaped point cloud for each camera in a local reference frame, wherein the spatial density of points in the point cloud depends only on the calibration of the corresponding camera and is independent of the semantics of the corresponding 2D image. Locate individual point clouds in a 3D world reference frame using the camera position, focal length, or optical center of each camera; as well as One or more 3D images of the environment are generated from one or more viewpoints by projecting feature points into the 3D world reference frame, wherein different 3D images have different resolutions or correspond to different viewpoints.

2. The processor of claim 1, wherein the one or more neural networks include a feature extraction network for extracting a set of semantic features from the two or more 2D images to generate one or more 3D images.

3. The processor of claim 1, wherein the one or more neural networks are further configured to determine one or more trajectories for movement through the environment, based at least in part on one or more objects represented in the one or more 3D images.

4. A computer system, comprising: One or more processors for using one or more neural networks to: Receive two or more two-dimensional 2D images captured by any number of cameras with different reference frames in the environment; Extracting semantic features from two or more 2D images; The semantic features are used to generate a frustum-shaped point cloud for each camera in a local reference frame, wherein the spatial density of points in the point cloud depends only on the calibration of the corresponding camera and is independent of the semantics of the corresponding 2D image. Locate individual point clouds in a 3D world reference frame using the camera position, focal length, or optical center of each camera; as well as One or more 3D images of the environment are generated from one or more viewpoints by projecting feature points into the 3D world reference frame, wherein different 3D images have different resolutions or correspond to different viewpoints.

5. The system of claim 4, wherein the one or more neural networks include a feature extraction network for extracting a set of semantic features from the two or more 2D images to generate one or more 3D images.

6. The system of claim 4, wherein the one or more neural networks are further configured to determine one or more trajectories for movement through the environment, based at least in part on one or more objects represented in the one or more 3D images.

7. A computer-implemented method, comprising: Using one or more neural networks to: Receive two or more two-dimensional 2D images captured by any number of cameras with different reference frames in the environment; Extracting semantic features from two or more 2D images; The semantic features are used to generate a frustum-shaped point cloud for each camera in a local reference frame, wherein the spatial density of points in the point cloud depends only on the calibration of the corresponding camera and is independent of the semantics of the corresponding 2D image. Locate individual point clouds in a 3D world reference frame using the camera position, focal length, or optical center of each camera; as well as One or more 3D images of the environment are generated from one or more viewpoints by projecting feature points into the 3D world reference frame, wherein different 3D images have different resolutions or correspond to different viewpoints.

8. The method of claim 7, wherein the one or more neural networks include a feature extraction network for extracting a set of semantic features from the two or more 2D images to generate one or more 3D images.

9. The method of claim 7, wherein the one or more neural networks are further configured to determine one or more trajectories for movement through the environment, based at least in part on one or more objects represented in the one or more 3D images.

10. A non-transitory computer-readable medium having an instruction set stored thereon, the instruction set, if executed by one or more processors, causes the one or more processors to at least: Using one or more neural networks to: Receive two or more two-dimensional 2D images captured by any number of cameras with different reference frames in the environment; Extracting semantic features from two or more 2D images; The semantic features are used to generate a frustum-shaped point cloud for each camera in a local reference frame, wherein the spatial density of points in the point cloud depends only on the calibration of the corresponding camera and is independent of the semantics of the corresponding 2D image. Locate individual point clouds in a 3D world reference frame using the camera position, focal length, or optical center of each camera; as well as One or more 3D images of the environment are generated from one or more viewpoints by projecting feature points into the 3D world reference frame, wherein different 3D images have different resolutions or correspond to different viewpoints.

11. The non-transitory computer-readable medium of claim 10, wherein the one or more neural networks include a feature extraction network for extracting a set of semantic features from the two or more 2D images to generate one or more 3D images.

12. The non-transitory computer-readable medium of claim 10, wherein the one or more neural networks are further configured to determine one or more trajectories for movement through the environment, based at least in part on one or more objects represented in the one or more 3D images.

13. A control system, comprising: One or more processors for using one or more neural networks to: Receive two or more two-dimensional 2D images captured by any number of cameras with different reference frames in the environment; Extracting semantic features from two or more 2D images; The semantic features are used to generate a frustum-shaped point cloud for each camera in a local reference frame, wherein the spatial density of points in the point cloud depends only on the calibration of the corresponding camera and is independent of the semantics of the corresponding 2D image. Locate individual point clouds in a 3D world reference frame using the camera position, focal length, or optical center of each camera; as well as One or more 3D images of the environment are generated from one or more viewpoints by projecting feature points into the 3D world reference frame, wherein different 3D images have different resolutions or correspond to different viewpoints.

14. The control system of claim 13, wherein the one or more neural networks include a feature extraction network for extracting a set of semantic features from the two or more 2D images to generate one or more 3D images.

15. The control system of claim 13, wherein the one or more neural networks are further configured to determine one or more trajectories for movement through the environment, based at least in part on one or more objects represented in the one or more 3D images.

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