Active matrix substrate and its manufacturing method

Abstract

An active matrix substrate is provided, comprising a plurality of oxide semiconductor TFTs having top gate structures and different characteristics. The active matrix substrate includes a first TFT and a second TFT having an oxide semiconductor layer and a gate electrode disposed on the oxide semiconductor layer across a gate insulating layer. In the first TFT, at least a portion of a first region of the oxide semiconductor layer covered by the gate electrode across the gate insulating layer has a stacked structure comprising a high-mobility oxide semiconductor film having relatively high mobility and a low-mobility oxide semiconductor film disposed on the high-mobility oxide semiconductor film with a lower mobility than the high-mobility oxide semiconductor film. In the second TFT, the first region of the oxide semiconductor layer comprises one of the high-mobility oxide semiconductor film and the low-mobility oxide semiconductor film throughout its entirety, but does not include the other oxide semiconductor film.

Description

Technical Field

[0001] This invention relates to active matrix substrates and their manufacturing methods. Background Technology

[0002] Active matrix substrates used in liquid crystal display devices, organic electroluminescent (EL) display devices, etc., have: a display area having multiple pixels; and an area outside the display area (non-display area or bezel area). In the display area, each pixel has a switching element such as a thin film transistor (hereinafter referred to as "TFT"). As such switching elements, TFTs with an amorphous silicon film as the active layer (hereinafter referred to as "amorphous silicon TFT") and TFTs with a polycrystalline silicon film as the active layer (hereinafter referred to as "polycrystalline silicon TFT") have been widely used in the past.

[0003] As the active layer material for TFTs, oxide semiconductors have been proposed to replace amorphous silicon and polycrystalline silicon. This type of TFT is called an "oxide semiconductor TFT." Oxide semiconductors have higher mobility than amorphous silicon. Therefore, oxide semiconductor TFTs can operate at higher speeds than amorphous silicon TFTs.

[0004] TFTs are broadly classified into bottom-gate and top-gate structures. Currently, oxide semiconductor TFTs mostly employ bottom-gate structures, but the use of top-gate structures has also been proposed (e.g., Patent Document 1). In top-gate structures, the gate insulating layer can be thinned, thus achieving higher current supply performance.

[0005] In the non-display areas of an active matrix substrate, peripheral circuits such as driving circuits are sometimes formed monolithically. By forming the driving circuits monolithically, costs are reduced by miniaturizing the non-display area and simplifying the installation process. For example, in the non-display area, gate driver circuits are sometimes formed monolithically, while source driver circuits are mounted in a COG (Chip on Glass) manner.

[0006] In devices with high requirements for narrow bezels, such as smartphones, sometimes not only are gate drivers formed on a single chip, but also source-shared driving (SSD) circuits and other multiplexing circuits are formed on a single chip. An SSD circuit distributes video data from a single video signal line from each terminal of the source driver to multiple source wirings. By incorporating an SSD circuit, the area for configuring terminals and wiring in the non-display area (terminal / wiring formation area) can be narrowed. Furthermore, the number of outputs from the source driver is reduced, allowing for a smaller circuit size and thus lowering the cost of the driver IC.

[0007] Peripheral circuits such as driving circuits and SSD circuits include TFTs. In this specification, TFTs configured as switching elements in each pixel of the display area are referred to as "pixel TFTs" or "pixel transistors," and TFTs constituting peripheral circuits are referred to as "circuit TFTs" or "circuit transistors." In addition, TFTs constituting driving circuits within circuit TFTs are referred to as "TFTs for driving circuits," and TFTs constituting SSD circuits are referred to as "TFTs for SSD circuits."

[0008] In active matrix substrates where oxide semiconductor TFTs are used as pixel TFTs, from a manufacturing process point of view, it is preferable that the circuit TFTs also use the same oxide semiconductor film as the pixel TFTs and are formed using the same process. Therefore, the circuit TFTs and pixel TFTs typically have the same structure. The characteristics of these TFTs are also largely the same.

[0009] Existing technical documents

[0010] Patent documents

[0011] Patent Document 1: Japanese Patent Application Publication No. 2015-109315 Summary of the Invention

[0012] The problem the invention aims to solve

[0013] However, pixel TFTs and circuit TFTs require different characteristics. Furthermore, even within circuit TFTs, the required characteristics differ between TFTs used in driving circuits and TFTs used in SSD circuits. In recent years, the types of peripheral circuits monolithically formed on active matrix substrates have increased, leading to a further diversification of the performance requirements for circuit TFTs.

[0014] Furthermore, in organic EL display devices, a pixel circuit is provided within each pixel, comprising at least two types of pixel TFTs (referred to as "driving TFTs" and "selection TFTs") and capacitor elements. The selection TFT has the function of selecting a pixel by varying the voltage applied to the driving TFT. The driving TFT has the function of supplying the current required for light emission. Since the selection TFT and the driving TFT perform different functions, their required characteristics may also differ.

[0015] Thus, in an active matrix substrate with multiple TFTs for different purposes, in order for each TFT to have the characteristics required for its application, it is necessary to fabricate multiple oxide semiconductor TFTs with different characteristics separately.

[0016] The embodiments of the present invention were made in view of the above circumstances, and the object is to provide an active matrix substrate having a plurality of oxide semiconductor TFTs having top gate structures and different characteristics.

[0017] Solution for solving the problem

[0018] This specification discloses the active matrix substrate and the method for manufacturing the active matrix substrate as described in the following items.

[0019] [Project 1] An active matrix substrate has a display area comprising multiple pixel areas and a non-display area disposed around the display area, wherein the active matrix substrate comprises:

[0020] Substrate; and

[0021] Multiple oxide semiconductor TFTs are supported on the substrate and disposed in the display area or the non-display area. Each of the multiple oxide semiconductor TFTs has an oxide semiconductor layer and a gate electrode disposed on a portion of the oxide semiconductor layer through a gate insulating layer.

[0022] The aforementioned oxide semiconductor layer includes a first region covered by the aforementioned gate electrode, separated from the aforementioned gate insulating layer.

[0023] The aforementioned plurality of oxide semiconductor TFTs include a first TFT and a second TFT.

[0024] In the first TFT described above, at least a portion of the first region of the oxide semiconductor layer has a stacked structure comprising a high-mobility oxide semiconductor film having a relatively high mobility, and a low-mobility oxide semiconductor film disposed on the high-mobility oxide semiconductor film and having a relatively low mobility compared to the high-mobility oxide semiconductor film.

[0025] In the second TFT, the first region of the oxide semiconductor layer includes one of the high-mobility oxide semiconductor film and the low-mobility oxide semiconductor film over the entire range, but does not include the other oxide semiconductor film.

[0026] [Project 2] According to the active matrix substrate described in Project 1, wherein,

[0027] The first region in the second TFT includes the low-mobility oxide semiconductor film but does not include the high-mobility oxide semiconductor film.

[0028] [Project 3] According to the active matrix substrate described in Project 1, wherein,

[0029] The first region in the second TFT includes the high-mobility oxide semiconductor film, but does not include the low-mobility oxide semiconductor film.

[0030] [Project 4] The active matrix substrate according to any one of Projects 1 to 3, wherein,

[0031] Each of the aforementioned oxide semiconductor TFTs also has a source electrode and a drain electrode.

[0032] Each of the plurality of oxide semiconductor TFTs has an oxide semiconductor layer comprising a first contact region and a second contact region located on both sides of the first region, wherein the first contact region is electrically connected to the source electrode and the second contact region is electrically connected to the drain electrode.

[0033] [Project 5] According to the active matrix substrate described in Project 4, wherein,

[0034] In the first TFT, at least a portion of the first region has the stacked structure, and the first contact region and the second contact region contain the low-mobility oxide semiconductor film but do not contain the high-mobility oxide semiconductor film.

[0035] [Project 6] According to the active matrix substrate described in Project 5, wherein,

[0036] In the first TFT described above, the entire range of the first region of the oxide semiconductor layer has the aforementioned stacked structure.

[0037] [Project 7] According to the active matrix substrate described in Project 5, wherein,

[0038] In the first TFT, a portion of the first region of the oxide semiconductor layer has the stacked structure described above, and another portion contains the low-mobility oxide semiconductor film described above, but does not contain the high-mobility oxide semiconductor film described above.

[0039] [Project 8] The active matrix substrate according to any one of Projects 4 to 7

[0040] It also includes an interlayer insulating layer that covers the gate electrode, the gate insulating layer, and the oxide semiconductor layer in the plurality of oxide semiconductor TFTs.

[0041] The source electrode and the drain electrode of each of the first TFT and the second TFT are disposed on the interlayer insulating layer.

[0042] [Project 9] The active matrix substrate according to any one of Projects 4 to 7, wherein,

[0043] At least one of the source electrode and the drain electrode of the second TFT is disposed on the substrate side of the oxide semiconductor layer of the second TFT, separated by a lower insulating layer.

[0044] The first region in the second TFT described above includes the low-mobility oxide semiconductor film, but does not include the high-mobility oxide semiconductor film.

[0045] At least one of the first contact region and the second contact region in the second TFT has a stacked structure including the low-mobility oxide semiconductor film and a connection layer including the high-mobility oxide semiconductor film, and the connection layer is electrically connected to the at least one electrode in the opening of the lower insulating layer.

[0046] [Project 10] The active matrix substrate according to Project 9, wherein,

[0047] The aforementioned active matrix substrate also includes a pixel TFT disposed in each of the plurality of pixel regions.

[0048] The aforementioned pixel TFT is the second TFT mentioned above.

[0049] At least one of the aforementioned electrodes is the source electrode of the second TFT.

[0050] The drain electrode of the second TFT is disposed above the oxide semiconductor layer of the second TFT.

[0051] [Project 11] An active matrix substrate according to any one of Projects 4 to 10, wherein,

[0052] The aforementioned plurality of oxide semiconductor TFTs also include a third TFT.

[0053] In the first TFT described above, the first region, the first contact region, and the second contact region include the aforementioned stacked structure.

[0054] In the third TFT, at least a portion of the first region has the stacked structure, and the first contact region and the second contact region contain the low-mobility oxide semiconductor film but do not contain the high-mobility oxide semiconductor film.

[0055] [Project 12] According to the active matrix substrate described in Project 2, wherein,

[0056] The first region of the oxide semiconductor layer of the first TFT further includes, between the high-mobility oxide semiconductor film and the substrate, another oxide semiconductor film having a lower mobility than the high-mobility oxide semiconductor film.

[0057] The first region of the second TFT does not contain the other oxide semiconductor films mentioned above.

[0058] [Project 13] According to the active matrix substrate described in Project 3, wherein,

[0059] The first region of the oxide semiconductor layer of the first TFT and the second TFT further includes another oxide semiconductor film having a lower mobility than the high mobility oxide semiconductor film between the high mobility oxide semiconductor film and the substrate.

[0060] [Item 14] The active matrix substrate according to Item 2 also includes:

[0061] Pixel TFTs, which are disposed in each of the plurality of pixel regions; and

[0062] Peripheral circuitry is located in the aforementioned non-display area.

[0063] The aforementioned peripheral circuitry includes the aforementioned first TFT.

[0064] The aforementioned pixel TFT is the second TFT mentioned above.

[0065] [Project 15] The active matrix substrate described in Project 2

[0066] It also includes gate drive circuitry and SSD circuitry configured in the aforementioned non-display area.

[0067] The aforementioned SSD circuit includes the aforementioned first TFT.

[0068] The gate driving circuit described above includes the second TFT.

[0069] [Project 16] According to the active matrix substrate described in Project 2, wherein,

[0070] Each of the aforementioned pixel regions has a pixel circuit that includes a selection TFT, a driving TFT, and a capacitor element.

[0071] The TFT selected above is the first TFT mentioned above.

[0072] The aforementioned driving TFT is the second TFT mentioned above.

[0073] [Item 17] The active matrix substrate according to Item 2 also includes:

[0074] A pixel circuit, disposed in each of the plurality of pixel regions, and including a selection TFT, a driving TFT, and a capacitor element; and

[0075] The gate driving circuit is configured in the aforementioned non-display area.

[0076] The aforementioned gate driving circuit includes the aforementioned first TFT.

[0077] The aforementioned driving TFT is the second TFT mentioned above.

[0078] [Project 18] An active matrix substrate according to any one of Projects 1 to 17, wherein,

[0079] Both the aforementioned low-mobility oxide semiconductor film and the aforementioned high-mobility oxide semiconductor film contain In and / or Sn.

[0080] The combined atomic ratio of In and Sn relative to all metal elements in the aforementioned high-mobility oxide semiconductor film is greater than the combined atomic ratio of In and Sn relative to all metal elements in the aforementioned low-mobility oxide semiconductor film.

[0081] [Project 19] An active matrix substrate according to any one of Projects 1 to 17, wherein,

[0082] The high-mobility oxide semiconductor film contains Sn, while the low-mobility oxide semiconductor film does not contain Sn, or contains Sn at a lower concentration than the high-mobility oxide semiconductor film.

[0083] [Project 20] A method for manufacturing an active matrix substrate, comprising a substrate and a plurality of oxide semiconductor TFTs supported on the substrate, wherein the plurality of oxide semiconductor TFTs include a first TFT formed in a first TFT formation region and a second TFT formed in a second TFT formation region, and the method for manufacturing the active matrix substrate includes:

[0084] In process (A), a high-mobility oxide semiconductor film is formed on the substrate in each of the first TFT forming region and the second TFT forming region.

[0085] In step (B), the high mobility oxide semiconductor film is patterned to remove at least a portion of the portion of the high mobility oxide semiconductor film located in the second TFT formation region.

[0086] Step (C): After step (B), in each TFT forming region of the first TFT forming region and the second TFT forming region, a low mobility oxide semiconductor film with a lower mobility than the high mobility oxide semiconductor film is formed in such a way as to cover the high mobility oxide semiconductor film.

[0087] In process (D), the low-mobility oxide semiconductor film is patterned, or the high-mobility oxide semiconductor film and the low-mobility oxide semiconductor film are patterned, thereby forming a first oxide semiconductor layer having a stacked portion including the high-mobility oxide semiconductor film and the low-mobility oxide semiconductor film in the first TFT forming region, and forming a second oxide semiconductor layer having a first portion including the low-mobility oxide semiconductor film and not including the high-mobility oxide semiconductor film in the second TFT forming region; and

[0088] In step (E), a gate insulating layer and a gate electrode are formed, wherein, in the first TFT forming region, the gate electrode is disposed on at least a portion of the stacked portion of the first oxide semiconductor layer with the gate insulating layer in between, and in the second TFT forming region, the gate electrode is disposed on the first portion of the second oxide semiconductor layer with the gate insulating layer in between.

[0089] [Project 21] An active matrix substrate according to any one of Projects 1 to 17, wherein,

[0090] Both the aforementioned low-mobility oxide semiconductor film and the aforementioned high-mobility oxide semiconductor film contain In-Ga-Zn-O semiconductors.

[0091] The atomic ratio of In to all metal elements in the aforementioned high-mobility oxide semiconductor film is higher than that in the aforementioned low-mobility oxide semiconductor film.

[0092] [Item 22] According to the active matrix substrate described in Item 21, wherein,

[0093] The In-Ga-Zn-O semiconductor in the aforementioned low-mobility oxide semiconductor film and / or the aforementioned high-mobility oxide semiconductor film contains a crystalline portion.

[0094] [Item 23] The method for manufacturing an active matrix substrate according to Item 20, wherein,

[0095] In the above-described process (D), in the first TFT formation region, the upper layer formed on both sides of the stacked portion further includes the first oxide semiconductor layer comprising the low-mobility oxide semiconductor film and not comprising the high-mobility oxide semiconductor film.

[0096] The manufacturing method further includes a step of forming a source electrode and a drain electrode in the first TFT forming region that are electrically connected to the upper portion of the first oxide semiconductor layer.

[0097] [Item 24] The manufacturing method of the active matrix substrate according to Item 20, wherein,

[0098] The manufacturing method described above further includes, prior to step (A):

[0099] In the second TFT forming region described above, a process of forming a source electrode on the substrate is performed;

[0100] The process of forming a lower insulating layer covering the source electrode in the first TFT forming region and the second TFT forming region; and

[0101] In the second TFT forming region described above, the process of forming an opening in the lower insulating layer that exposes a portion of the source electrode is described above.

[0102] The above-described process (B) includes the process of forming a connection layer comprising the above-described high-mobility oxide semiconductor film in the above-described second TFT forming region and in contact with the above-described source electrode within the above-described opening.

[0103] The second oxide semiconductor layer includes the aforementioned interconnect layer and the aforementioned low-mobility oxide semiconductor film covering the interconnect layer.

[0104] Invention Effects

[0105] According to one embodiment of the present invention, an active matrix substrate is provided, which includes a plurality of oxide semiconductor TFTs having top gate structures and different characteristics. Furthermore, according to another embodiment of the present invention, a method for manufacturing an active matrix substrate capable of separately fabricating a plurality of oxide semiconductor TFTs with different characteristics using the same oxide semiconductor film is provided. Attached Figure Description

[0106] Figure 1 This is a schematic diagram showing an example of the planar structure of the active matrix substrate 1000 of the first embodiment.

[0107] Figure 2 This is a cross-sectional view illustrating the first TFT 100 and the second TFT 200 formed on the active matrix substrate 1000.

[0108] Figure 3 This is a diagram illustrating the Vg-Id characteristics of TFT100 and TFT200.

[0109] Figure 4 This is a cross-sectional view showing another example of an active matrix substrate 1000.

[0110] Figure 5A This is a cross-sectional view showing the manufacturing method of the active matrix substrate 1000.

[0111] Figure 5B This is a cross-sectional view showing the manufacturing method of the active matrix substrate 1000.

[0112] Figure 5C This is a cross-sectional view showing the manufacturing method of the active matrix substrate 1000.

[0113] Figure 5D This is a cross-sectional view showing the manufacturing method of the active matrix substrate 1000.

[0114] Figure 5E This is a cross-sectional view showing the manufacturing method of the active matrix substrate 1000.

[0115] Figure 5F This is a cross-sectional view showing the manufacturing method of the active matrix substrate 1000.

[0116] Figure 5G This is a cross-sectional view showing the manufacturing method of the active matrix substrate 1000.

[0117] Figure 5H This is a cross-sectional view showing the manufacturing method of the active matrix substrate 1000.

[0118] Figure 5I This is a cross-sectional view showing the manufacturing method of the active matrix substrate 1000.

[0119] Figure 5J This is a cross-sectional view showing the manufacturing method of the active matrix substrate 1000.

[0120] Figure 5K This is a cross-sectional view showing the manufacturing method of the active matrix substrate 1000.

[0121] Figure 5L This is a cross-sectional view showing the manufacturing method of the active matrix substrate 1000.

[0122] Figure 5M This is a cross-sectional view showing the manufacturing method of the active matrix substrate 1000.

[0123] Figure 5NThis is a cross-sectional view showing the manufacturing method of the active matrix substrate 1000.

[0124] Figure 6 This is a schematic cross-sectional view of the active matrix substrate 1000.

[0125] Figure 7A This is a cross-sectional view used to illustrate another example of the first TFT100.

[0126] Figure 7B This is a cross-sectional view used to illustrate another example of the first TFT100.

[0127] Figure 7C This is a cross-sectional view showing another example of an active matrix substrate 1000.

[0128] Figure 8 This is a schematic cross-sectional view of the active matrix substrate 1001 in Modified Example 1.

[0129] Figure 9A This is a cross-sectional view showing the manufacturing method of the active matrix substrate 1001.

[0130] Figure 9B This is a cross-sectional view showing the manufacturing method of the active matrix substrate 1001.

[0131] Figure 9C This is a cross-sectional view showing the manufacturing method of the active matrix substrate 1001.

[0132] Figure 9D This is a cross-sectional view showing the manufacturing method of the active matrix substrate 1001.

[0133] Figure 10A This is a schematic cross-sectional view showing the first TFT 101 and the second TFT 200 of the active matrix substrate 1002 in Modified Example 2.

[0134] Figure 10B This is a schematic top view of TFT101.

[0135] Figure 11A This is a cross-sectional view showing another example of TFT101.

[0136] Figure 11B This is a cross-sectional view showing another example of TFT101.

[0137] Figure 12 This is a cross-sectional view showing another example of the active matrix substrate 1002.

[0138] Figure 13A This is a cross-sectional view showing the manufacturing method of the active matrix substrate 1002.

[0139] Figure 13BThis is a cross-sectional view showing the manufacturing method of the active matrix substrate 1002.

[0140] Figure 13C This is a cross-sectional view showing the manufacturing method of the active matrix substrate 1002.

[0141] Figure 13D This is a cross-sectional view showing the manufacturing method of the active matrix substrate 1002.

[0142] Figure 13E This is a cross-sectional view showing the manufacturing method of the active matrix substrate 1002.

[0143] Figure 13F This is a cross-sectional view showing the manufacturing method of the active matrix substrate 1002.

[0144] Figure 14A This is a schematic cross-sectional view showing the first TFT 100 and the second TFT 300 of the active matrix substrate 1003 in Modified Example 3.

[0145] Figure 14B This is a cross-sectional view showing another example of the active matrix substrate 1003 of Modified Example 3.

[0146] Figure 15 This is a diagram illustrating the Vg-Id characteristics of TFT100 and TFT300.

[0147] Figure 16 This is a cross-sectional view showing another example of the active matrix substrate 1003.

[0148] Figure 17 This is a diagram illustrating the shift register circuit in a gate drive circuit.

[0149] Figure 18 This is a diagram illustrating a unit shift register circuit SR.

[0150] Figure 19 This is a diagram illustrating an SSD circuit.

[0151] Figure 20 This is a schematic diagram showing an example of the planar structure of the active matrix substrate 2000 according to the second embodiment.

[0152] Figure 21 This is a diagram illustrating a pixel circuit.

[0153] Figure 22 This is a cross-sectional view showing the first TFT 100 and the second TFT 200 in the active matrix substrate 2000.

[0154] Figure 23 This is a diagram illustrating the Vg-Id characteristics of the first TFT100 and the second TFT200.

[0155] Explanation of reference numerals in the attached figures

[0156] 1 substrate

[0157] 2A, 2B, 2C Lower conductive layer

[0158] 4A, 4B, 4C Oxide Semiconductor Layers

[0159] 4Ac, 4Bc, 4Cc Region 1

[0160] 4As, 4Bs, 4Cs First contact area

[0161] 4Ad, 4Bd, 4Cd Second contact area

[0162] 5A, 5B, 5C gate insulating layers

[0163] 7A, 7B, 7C gate electrodes

[0164] 8A, 8B, 8C source electrodes

[0165] 9A, 9B, 9C Drain electrodes

[0166] 10 interlayer insulation layers

[0167] 11 Inorganic insulating layer

[0168] 12 Organic Insulation Layer

[0169] 17 Dielectric layer

[0170] 41 High-mobility oxide semiconductor films

[0171] 41a Connection Layer

[0172] 42 Low-mobility oxide semiconductor films

[0173] p1 Lower layer

[0174] p2 Upper layer

[0175] pa layer

[0176] CE common electrode

[0177] PE pixel electrode

[0178] DR display area

[0179] FR Non-display area

[0180] TL touch wiring

[0181] GL gate bus

[0182] SL source bus

[0183] 1000, 1001, 1002, 1003, 2000 Active matrix substrates Detailed Implementation

[0184] As mentioned above, the characteristics required for a TFT disposed on an active matrix substrate differ depending on its application. Hereinafter, taking an active matrix substrate used in a liquid crystal display device as an example, an example of preferred TFT characteristics will be described.

[0185] In SSD circuit TFTs, a relatively large on-current is required, necessitating a high current driving force. If a TFT with a low current driving force is used, it may be difficult to charge the source bus within a predetermined time. Furthermore, increasing the TFT channel width to ensure the desired current driving force would increase the TFT size, potentially preventing the achievement of a narrow bezel. Therefore, in SSD circuit TFTs, it is preferable to lower the threshold voltage to further increase the on-current. For example, SSD circuit TFTs may possess depletion characteristics with a negative threshold voltage.

[0186] In contrast, in TFTs used in drive circuits such as gate drivers, it is preferable to shift the threshold voltage of the TFT in the SSD circuit in a more positive direction than that of the TFT in the SSD circuit to reduce the cutoff leakage current. A large cutoff leakage current can lead to increased power consumption, malfunctions in the drive circuit, and other issues. TFTs used in drive circuits can, for example, have enhancement characteristics that provide a positive threshold voltage.

[0187] Furthermore, for the pixel TFTs used in liquid crystal display devices, TFTs with low cutoff leakage current are preferred. Pixel TFTs can have either depletion characteristics or enhancement characteristics.

[0188] Furthermore, in the active matrix substrate used in organic EL display devices, a pixel circuit comprising at least a driving TFT and a selection TFT is provided within each pixel. Preferably, the driving TFT has enhancement characteristics. Additionally, for proper multi-grayscale display, the Vg (gate voltage) - Id (drain current) characteristic of the driving TFT is preferably relatively flat (i.e., not steep). Therefore, a large subthreshold coefficient (S-value) is required for the driving TFT. To increase the threshold voltage in the positive direction and increase the S-value, for example, an oxide semiconductor with low mobility can be used. On the other hand, a high mobility (i.e., large on-current) is preferred for the selection TFT. The threshold voltage of the selection TFT can be negative (depletion characteristic). Furthermore, the S-value in the selection TFT can be small. Instead, a small S-value and high switching speed are required.

[0189] Furthermore, the applications and required characteristics of TFTs are not limited to the examples mentioned above and are diverse.

[0190] However, it is difficult to form multiple TFTs with different characteristics using the same oxide semiconductor film. For example, while TFTs for SSD circuits and pixel TFTs preferably use oxide semiconductors with high mobility, the threshold voltage of the TFT tends to shift negatively with the increase of the mobility of oxide semiconductors, and there is a tendency to develop depletion characteristics. Therefore, sometimes high-mobility oxide semiconductors are not suitable for TFTs used in driving circuits. On the other hand, in order to obtain enhanced characteristics, TFTs for driving circuits preferably use oxide semiconductors with relatively low mobility. However, in TFTs with enhanced characteristics, it is difficult to further increase the conduction current, so they may not be suitable for other peripheral circuits such as SSD circuits.

[0191] Based on the above insights, the inventors of this invention have discovered a method for separately fabricating multiple top-gate TFTs that utilize the same oxide semiconductor film but have different characteristics.

[0192] (First Embodiment)

[0193] Hereinafter, with reference to the accompanying drawings, the active matrix substrate of the first embodiment will be described as an example of an active matrix substrate used in a liquid crystal display device.

[0194] <Basic Structure of Active Matrix Substrate 1000>

[0195] Figure 1 This is a schematic diagram showing an example of the planar structure of the active matrix substrate 1000 of this embodiment.

[0196] The active matrix substrate 1000 has a display area DR and an area outside the display area DR (non-display area or bezel area) FR. The display area DR includes pixel areas PIX arranged in a matrix. Pixel areas PIX (sometimes simply referred to as "pixels") are areas corresponding to pixels of the display device. The non-display area FR is an area located around the display area DR that does not contribute to the display.

[0197] In the non-display area FR, for example, gate drivers and multiplexing circuits that function as SSD circuits are integrally (monolithically) disposed. Source drivers are, for example, mounted on the active matrix substrate 1000.

[0198] In the display area DR, multiple gate buses GL extending in the row direction (x-direction) and multiple source buses SL extending in the column direction (y-direction) are formed. Each pixel area PIX is defined, for example, by the gate buses GL and the source buses SL. The gate buses GL are connected to the terminals of the gate drivers, respectively. The source buses SL are connected to the terminals of the source drivers, respectively.

[0199] Each pixel region (PIX) has a pixel transistor (pixel TFT) Tp and a pixel electrode PE. The gate electrode of the pixel transistor Tp is electrically connected to the corresponding gate bus GL, and the source electrode is electrically connected to the corresponding source bus SL. The drain electrode is electrically connected to the pixel electrode PE. When the active matrix substrate 1000 is applied to a display device with a lateral electric field mode such as FFS (Fringe Field Switching) mode, although not shown, an electrode (shared electrode) shared by multiple pixels is provided in the active matrix substrate 1000.

[0200] Multiple circuit TFTs constituting peripheral circuits are formed in the non-display area of ​​the active matrix substrate 1000. The circuit TFTs include TFTs for driving circuits constituting gate drivers, TFTs for SSD circuits constituting SSD circuits, etc.

[0201] <TFT Structure in Active Matrix Substrate 1000>

[0202] Next, the structure of the multiple top-gate TFTs included in the active matrix substrate 1000 will be described.

[0203] The characteristics of a top-gate TFT with an oxide semiconductor layer as the active layer can be varied, for example, depending on the structure of the region in the oxide semiconductor layer covered by the gate electrode through the gate insulating layer. In this specification, the region in the oxide semiconductor layer covered by the gate electrode through the gate insulating layer is referred to as the "first region". The first region includes the region where the channel is formed. Furthermore, the structure of the first region in the oxide semiconductor layer is sometimes referred to as the "active layer structure".

[0204] In this embodiment, the active matrix substrate 1000 includes a plurality of oxide semiconductor TFTs having a top gate structure. The plurality of oxide semiconductor TFTs include at least one first TFT and one second TFT having mutually different active layer structures. The active layers of the first TFT and the second TFT are formed using the same oxide semiconductor film (in this case, a high-mobility oxide semiconductor film).

[0205] In the first TFT, at least a portion of the first region of the oxide semiconductor layer has a stacked structure comprising a high-mobility oxide semiconductor film and a low-mobility oxide semiconductor film disposed on the high-mobility oxide semiconductor film. Here, "high-mobility oxide semiconductor film" refers to an oxide semiconductor film having a relatively high mobility, and "low-mobility oxide semiconductor film" refers to an oxide semiconductor film having a relatively low mobility (i.e., lower than that of the high-mobility oxide semiconductor film). On the other hand, in the second TFT, the entire extent of the first region of the oxide semiconductor layer includes one of the aforementioned high-mobility oxide semiconductor film and low-mobility oxide semiconductor film, but excludes the other.

[0206] The first TFT and the second TFT have different active layer structures, and therefore can have different characteristics. For example, the mobility of the first region of the second TFT is lower than that of the first TFT, so the second TFT can have a threshold voltage that shifts the threshold voltage of the first TFT in the positive direction.

[0207] In this specification, the portion of the oxide semiconductor layer having a stacked structure comprising a high-mobility oxide semiconductor film and a low-mobility oxide semiconductor film is referred to as "stack portion p1". Furthermore, the portion of the oxide semiconductor layer comprising a high-mobility oxide semiconductor film but not a low-mobility oxide semiconductor film is referred to as "lower layer p1", and the portion of the oxide semiconductor layer comprising a low-mobility oxide semiconductor film but not a high-mobility oxide semiconductor film is referred to as "upper layer p2". Lower layer p1 may have a monolayer structure consisting only of a high-mobility oxide semiconductor film, or it may also include other semiconductor films. Similarly, upper layer p2 may consist only of a low-mobility oxide semiconductor film, or it may also include other semiconductor films.

[0208] The structure of each TFT will now be described in more detail with reference to the accompanying drawings.

[0209] Figure 2 This is a cross-sectional view illustrating the first TFT 100 and the second TFT 200 formed on the active matrix substrate 1000. Here, an example is given where TFT 100 is used as a circuit TFT requiring current driving force (e.g., a TFT for an SSD circuit) and TFT 200 is used as a pixel TFT or a TFT for a driving circuit. The active matrix substrate 1000 can have multiple first TFTs 100 and multiple second TFTs 200, but only a single first TFT 100 and a single second TFT 200 are illustrated for explanation.

[0210] TFT100 and 200 are top-gate TFTs supported on substrate 1 and having an active layer containing an oxide semiconductor film.

[0211] TFT100 includes: an oxide semiconductor layer 4A disposed on a substrate 1; a gate insulating layer 5A covering the oxide semiconductor layer 4A; a gate electrode 7A disposed on the gate insulating layer 5A; and a source electrode 8A and a drain electrode 9A. The gate electrode 7A is disposed such that it covers a portion of the oxide semiconductor layer 4A through the gate insulating layer 5A.

[0212] The oxide semiconductor layer 4A includes: a first region 4Ac covered by a gate electrode 7A through a gate insulating layer 5A; and a region not covered by the gate electrode 7A when viewed from the normal direction of the substrate 1 (hereinafter referred to as the "second region").

[0213] The entire extent of the first region 4Ac in the oxide semiconductor layer 4A is a stacked portion pa having a stacked structure comprising a high-mobility oxide semiconductor film 41 and a low-mobility oxide semiconductor film 42 disposed on the high-mobility oxide semiconductor film 41.

[0214] The second region of the oxide semiconductor layer 4A can be a low-resistivity region with a lower resistivity than the first region 4Ac. This low-resistivity region can be formed, for example, by using the gate electrode 7A as a mask to perform a low-resistivity treatment on the oxide semiconductor layer 4A.

[0215] When viewed from the normal direction of substrate 1, the second region (low-resistance region) includes a first contact region 4As and a second contact region 4Ad disposed on both sides of the first region 4Ac, respectively. The first contact region 4As is the region electrically connected to the source electrode 8A, and the second contact region 4Ad is the region electrically connected to the drain electrode 9A. The first contact region 4As and the second contact region 4Ad may also be a stacked portion pa. For example, as shown, the entire extent of the oxide semiconductor layer 4A may include a high-mobility oxide semiconductor film 41 and a low-mobility oxide semiconductor film 42. Furthermore, in this example, the first region 4Ac of the oxide semiconductor layer 4A is a stacked portion pa throughout its entire extent, but it is sufficient if at least a portion of the first region 4Ac of the oxide semiconductor layer 4A is a stacked portion pa. As described later, a portion of the first region 4Ac or the second region may also have a lower layer p1 or an upper layer p2.

[0216] The gate insulating layer 5A may also cover the first region 4Ac but not the first contact region 4As and the second contact region 4Ad. In the illustrated example, the gate insulating layer 5A is formed only in the region that overlaps with the gate electrode 7A when viewed from the normal direction of the substrate 1. The edge of the gate insulating layer 5A is aligned with the edge of the gate electrode 7A.

[0217] The gate electrode 7A is disposed on the gate insulating layer 5A in such a way that it overlaps with the first region 4Ac when viewed from the normal direction of the substrate 1 and does not overlap with the first contact region 4As and the second contact region 4Ad.

[0218] The oxide semiconductor layer 4A, the gate insulating layer 5A, and the gate electrode 7A are covered by the interlayer insulating layer 10. The interlayer insulating layer 10 may also be in contact with a portion of the upper surface of the oxide semiconductor layers 4A and 4B.

[0219] The source electrode 8A and drain electrode 9A are disposed, for example, on the interlayer insulating layer 10. In this example, the interlayer insulating layer 10 has: a first opening 10As that exposes a first contact region 4As of the oxide semiconductor layer 4A; and a second opening 10Ad that exposes a portion of the second contact region 4Ad. The source electrode 8A is disposed on the interlayer insulating layer 10 and within the first opening 10As, and is connected to the first contact region 4As within the first opening 10As. The drain electrode 9A is disposed on the interlayer insulating layer 10 and within the second opening 10Ad, and is connected to the second contact region 4Ad within the second opening 10Ad.

[0220] The TFT 100 may also have a lower conductive layer 2A on the substrate 1 side of the oxide semiconductor layer 4A, which functions as a light-shielding layer. The lower conductive layer 2A is covered by a lower insulating layer 3. The oxide semiconductor layer 4A of the TFT 100 is disposed on the lower insulating layer 3. The lower conductive layer 2A may be configured to overlap with at least a first region 4Ac in the oxide semiconductor layer 4A when viewed from the normal direction of the substrate 1. This can suppress the degradation of the characteristics of the oxide semiconductor layer 4A caused by light (backlight light) from the substrate 1 side. Furthermore, the lower conductive layer 2A may be in an electrically floating state or fixed at a GND potential (0V). Alternatively, the lower conductive layer 2A may function as a lower gate electrode (dual-gate structure) by electrically connecting the lower conductive layer 2A to the gate electrode 7A via a connection portion not shown. This can further improve the conduction current of the TFT 100. The TFT 100 with a dual-gate structure is suitable for SSD circuits, for example.

[0221] On the other hand, TFT200, like TFT100, has: an oxide semiconductor layer 4B; a gate electrode 7B disposed on a portion of the oxide semiconductor layer 4B with respect to a gate insulating layer 5B; and a source electrode 8B and a drain electrode 9B. TFT200 may also have a lower conductive layer 2B on the substrate 1 side of the oxide semiconductor layer 4B, which functions as a light-shielding layer.

[0222] The oxide semiconductor layer 4B, like the oxide semiconductor layer 4A, includes a first region 4Bc that overlaps with the gate electrode 7A when viewed from the normal direction of the substrate 1, and a second region that does not overlap with the gate electrode 7A. The second region may be a low-resistivity region with a lower resistivity than the first region 4Ac.

[0223] Furthermore, when viewed from the normal direction of the substrate 1, the oxide semiconductor layer 4B includes a first contact region 4Bs and a second contact region 4Bd respectively disposed on both sides of the first region 4Bc. The first contact region 4Bs and the second contact region 4Bd are disposed in the second region (low resistance region). The first contact region 4Bs is electrically connected to the source electrode 8B, and the second contact region 4Bd is electrically connected to the drain electrode 9B.

[0224] In TFT 200, the first region 4Bc of the oxide semiconductor layer 4B is an upper layer p2 that includes a low-mobility oxide semiconductor film 42 but not a high-mobility oxide semiconductor film 41. In the illustrated example, the entire extent of the oxide semiconductor layer 4B (including the first contact region 4Bs and the second contact region 4Bd) is the upper layer p2. Furthermore, in this embodiment, as long as the first region 4Bc in the oxide semiconductor layer 4B is the upper layer p2 over its entire extent, as will be described later, the second region (e.g., the contact region) of the oxide semiconductor layer 4B may also include a high-mobility oxide semiconductor film 41.

[0225] Except for the structure of the oxide semiconductor layer 4B, TFT200 can have the same structure as TFT100. However, the planar shape, size, channel length, and channel width of each layer of TFT100 and TFT200 can also be different from each other.

[0226] Using TFT200 as Figure 1 In the case of the pixel transistor Tp (pixel TFT) shown, the gate electrode 7B is electrically connected to the corresponding gate bus GL. The gate electrode 7B can be integrally formed with the corresponding gate bus GL using the same conductive film. The source electrode 8B is electrically connected to the corresponding source bus SL. The source electrode 8B can be integrally formed with the corresponding source bus SL using the same conductive film. The drain electrode 9B is electrically connected to the corresponding pixel electrode PE.

[0227] The low-mobility oxide semiconductor film 42 of the oxide semiconductor layers 4A and 4B of TFT100 and TFT200 is formed from the same oxide semiconductor film. Alternatively, the gate insulating layers 5A and 5B of each TFT can be formed from the same insulating film, the gate electrodes 7A and 7B can be formed from the same conductive film (conductive film for gate), and the source electrodes 8A and 8B and the drain electrodes 9A and 9B can be formed from the same conductive film (conductive film for source). Therefore, TFT100 and TFT200 can be manufactured using a common process.

[0228] The structures of TFT100 and TFT200 are not limited to Figure 2 The structure shown is as follows. For example, the source electrode and / or drain electrode may be disposed on the substrate side closer to the oxide semiconductor layer. As described later, the source electrode 8B of the TFT 200 may be formed using the same conductive film as the lower conductive layer 2B, and the oxide semiconductor layer 4B may be connected to the source electrode 8B within the opening formed in the lower insulating layer 3.

[0229] <Effect>

[0230] According to this embodiment, TFT100 and TFT200, which use a common oxide semiconductor film (in this case, a low-mobility oxide semiconductor film 42) and have different characteristics, can be fabricated separately.

[0231] Figure 3 This is a graph illustrating the Vg-Id characteristics of TFT100 and TFT200. The horizontal axis of the graph represents the gate electrode potential (gate-drain voltage) Vdg, which is based on the drain electrode potential, and the vertical axis represents the drain current Id.

[0232] according to Figure 3 It is known that TFT200 has a higher threshold voltage than TFT100. This can be attributed to the fact that in TFT200, the first region 4Bc (channel region) of the oxide semiconductor layer 4B does not contain the high-mobility oxide semiconductor film 41. Therefore, compared with the oxide semiconductor layer 4A which contains the high-mobility oxide semiconductor film 41, the overall mobility of the first region is lower, and the threshold voltage is shifted in the positive direction.

[0233] TFT100 is suitable for applications such as SSD circuits and other circuit TFTs. TFT100 has a higher mobility than TFT200 and excellent current driving force (conduction current). In addition, it can achieve short-channel configuration, which can reduce circuit area.

[0234] TFT200 has a low cutoff leakage current, making it suitable for use as a pixel TFT. Pixel TFTs can exhibit enhancement characteristics with a positive threshold voltage or depletion characteristics with a negative threshold voltage. Furthermore, when TFT200 exhibits enhancement characteristics, it can be used as a circuit TFT, such as a TFT for drive circuits. This helps suppress circuit malfunctions and reduce yield. Moreover, TFT200 can also be used as a TFT for inspection or ESD protection.

[0235] Alternatively, TFT100 and TFT200 can be mixed in the driving circuit. For example, the high-mobility TFT100 can be used as at least one of the multiple TFTs included in the gate driving circuit, referred to as an "output transistor (also called a buffer transistor)" (see reference). Figure 18 (described later) TFT, TFT200 can be used as any other TFT.

[0236] Table 1 illustrates preferred characteristics of TFTs used in pixel TFT driving circuits and SSD circuits in liquid crystal display devices. The characteristics and numerical ranges listed in Table 1 are illustrative and do not limit the characteristics of each TFT.

[0237] [Table 1]

[0238]

[0239] <High-mobility oxide semiconductor film 41 and low-mobility oxide semiconductor film 42>

[0240] There are no particular limitations on the composition, thickness, crystal structure, or formation method of each oxide semiconductor film. The high-mobility oxide semiconductor film 41 and the low-mobility oxide semiconductor film 42 can be either single-layer films or stacked films containing multiple oxide semiconductor films. As long as the mobility of the high-mobility oxide semiconductor film 41 (or the overall mobility of the stacked film if the high-mobility oxide semiconductor film 41 is a stacked film) is higher than the mobility of the low-mobility oxide semiconductor film 42, it is acceptable.

[0241] The compositions of the high-mobility oxide semiconductor film 41 and the low-mobility oxide semiconductor film 42 can be different. "Different compositions" means that the types or proportions of metal elements contained in each layer are different. For example, the high-mobility oxide semiconductor film 41 and the low-mobility oxide semiconductor film 42 may each contain In and / or Sn, and the combined atomic ratio of In and Sn relative to all metal elements in the high-mobility oxide semiconductor film 41 is greater than the combined atomic ratio of In and Sn relative to all metal elements in the low-mobility oxide semiconductor film 42.

[0242] For example, both the high-mobility oxide semiconductor film 41 and the low-mobility oxide semiconductor film 42 can be In-Ga-Zn-O based oxide semiconductor layers, with the proportion of In atoms in the low-mobility oxide semiconductor film 42 being less than that in the high-mobility oxide semiconductor film 41. Alternatively, the proportion of Ga atoms in the low-mobility oxide semiconductor film 42 can also be greater than that in the high-mobility oxide semiconductor film 41.

[0243] Alternatively, the high-mobility oxide semiconductor film 41 may contain Sn, while the low-mobility oxide semiconductor film 42 may not contain Sn. Alternatively, the low-mobility oxide semiconductor film 42 may contain Sn at a lower concentration than the high-mobility oxide semiconductor film 41. That is, the atomic ratio of Sn to all metal elements in the low-mobility oxide semiconductor film 42 may be less than the atomic ratio of Sn to all metal elements in the high-mobility oxide semiconductor film 41.

[0244] For example, an In-Ga-Zn-O semiconductor film (In:Ga:Zn = 1:1:1, etc.) can be used as the low-mobility oxide semiconductor film 42. For example, an In-Ga-Zn-O semiconductor film (In:Ga:Zn = 5:1:4, etc.), an In-Sn-Zn-O semiconductor film, an In-Al-Sn-Zn-O semiconductor film, an In-W-Zn-O semiconductor film, an In-Sn-O semiconductor film, an In-Zn-O semiconductor film, an In-Ga-Sn-O semiconductor film, an In-Sn-Ti-Zn-O semiconductor film, etc., can be used as the high-mobility oxide semiconductor film 41.

[0245] Furthermore, the low-mobility oxide semiconductor film 42 and the high-mobility oxide semiconductor film 41 may also have different crystal structures. For example, one of these oxide semiconductor films may be an amorphous oxide semiconductor film, and the other may be a crystalline oxide semiconductor film containing crystalline portions.

[0246] Furthermore, even when the ratio of each metal element is the same, the mobility of the oxide semiconductor film can be varied by different film formation methods or conditions. For example, the atmosphere inside the cavity (e.g., the flow ratio of oxygen to Ar supplied to the cavity) can be different when forming the oxide semiconductor film by sputtering. Specifically, when forming the low-mobility oxide semiconductor film 42, the flow ratio of oxygen to Ar can be set to be large (e.g., 80%), and when forming the high-mobility oxide semiconductor film 41, the flow ratio of oxygen to Ar can be set to be smaller (e.g., 20%) than when forming the low-mobility oxide semiconductor film 42.

[0247] The thicknesses of the low-mobility oxide semiconductor film 42 and the high-mobility oxide semiconductor film 41 can be approximately the same or different. The high-mobility oxide semiconductor film 41 can be thinner than the low-mobility oxide semiconductor film 42. By thinning the high-mobility oxide semiconductor film 41, the threshold voltage of the TFT using the high-mobility oxide semiconductor film 41 can be set to near 0V. This results in a TFT that not only has enhanced characteristics but also high on-state current. The thickness of the high-mobility oxide semiconductor film 41 can, for example, be 5 nm or more and 30 nm or less. The thickness of the low-mobility oxide semiconductor film 42 can, for example, be 20 nm or more and 100 nm or less.

[0248] The oxide semiconductor layers 4A and 4B may also include oxide semiconductor films other than the high-mobility oxide semiconductor film 41 and the low-mobility oxide semiconductor film 42. For example, they may also be, such as Figure 4 As shown, the oxide semiconductor layer 4A of TFT100 further includes another oxide semiconductor film 43 with a lower mobility than the high-mobility oxide semiconductor film 41 between the high-mobility oxide semiconductor film 41 and the substrate 1. The oxide semiconductor layer 4B of TFT200 does not include this other oxide semiconductor film 43. For example, a low-mobility oxide semiconductor film having the same composition as the low-mobility oxide semiconductor film 42 can be used as the other oxide semiconductor film 43. The thickness of the oxide semiconductor film 43 can be, for example, 5 nm or more and 30 nm or less.

[0249] <Manufacturing Method of Active Matrix Substrate 1000>

[0250] Figures 5A to 5N and Figure 6 These are cross-sectional views illustrating the manufacturing method of the active matrix substrate 1000.

[0251] Here, we will take an active matrix substrate used in an embedded touch panel type liquid crystal display device in FFS mode as an example for explanation. This active matrix substrate not only has pixel electrodes and common electrodes, but also multiple electrodes for touch sensors (hereinafter referred to as "touch sensor electrodes") and multiple wirings for driving and / or detecting touch sensors (hereinafter referred to as "touch wirings").

[0252] In this example, a first circuit transistor Tc1 and a second circuit transistor Tc2 constituting a peripheral circuit are formed in the non-display area FR of the active matrix substrate 1000, and a pixel transistor Tp is formed in each pixel region PIX in the display area DR. The first circuit transistor Tc1 is a first TFT, for example, used in an SSD circuit. The second circuit transistor Tc2 is a second TFT, for example, used in a driving circuit. The pixel transistor Tp is a second TFT. Furthermore, the uses of each TFT are not limited to the illustrated example. In the following description, the area where the first circuit transistor Tc1 is formed is referred to as "TFT forming area Rc1", the area where the second circuit transistor Tc2 is formed is referred to as "TFT forming area Rc2", and the area where the pixel transistor is formed is referred to as "TFT forming area Rp".

[0253] STEP 1: Formation of the lower conductive layer Figure 5A )

[0254] On substrate 1, a lower conductive film (thickness: for example, 50 nm to 500 nm) is formed by sputtering. Next, the lower conductive film is patterned using a known photolithography process. Thus, as... Figure 5A As shown, a lower conductive layer 2A is formed in the TFT forming region Rc1, and a lower conductive layer 2B is formed in the TFT forming regions Rc2 and Rp.

[0255] As substrate 1, transparent and insulating substrates such as glass substrates, silicon substrates, and heat-resistant plastic substrates (resin substrates) can be used.

[0256] The material of the lower conductive film is not particularly limited, and films containing metals such as aluminum (Al), tungsten (W), molybdenum (Mo), tantalum (Ta), chromium (Cr), titanium (Ti), and copper (Cu), or their alloys, or metal nitrides, can be used. Alternatively, a laminated film formed by stacking multiple films can also be used.

[0257] Here, a single-layer film containing a metal film (including an alloy film) of Cu or Al is used as the lower conductive film. Alternatively, a multilayer film with a metal film containing Cu or Al as the uppermost layer can also be used.

[0258] STEP 2: Formation of the lower insulating layer 3 Figure 5B )

[0259] Next, as Figure 5B As shown, a lower insulating layer 3 (thickness: for example, 200nm or more and 600nm or less) is formed in such a way as to cover the lower conductive layers 2A and 2B.

[0260] The lower insulating layer 3 is formed, for example, by a CVD method. As the lower insulating layer 3, silicon oxide (SiOx) layers, silicon nitride (SiNx) layers, silicon oxynitride (SiOxNy; x>y) layers, and silicon oxynitride (SiNxOy; x>y) layers can be appropriately used. The lower insulating layer 3 can be a single layer or have a stacked structure. For example, to prevent impurities from diffusing from the substrate 1, a silicon nitride (SiNx) layer or a silicon oxynitride layer can be formed on the substrate side (lower layer), and to ensure insulation, a silicon oxide (SiO2) layer or a silicon oxynitride layer can be formed on top of it (upper layer).

[0261] STEP 3: Formation of high-mobility oxide semiconductor film 41 Figure 5C )

[0262] Next, as Figure 5C As shown, a high-mobility oxide semiconductor film 41 is formed on the lower insulating layer 3.

[0263] The high-mobility oxide semiconductor film 41 can be formed, for example, by sputtering. Here, an In-Ga-Zn-O semiconductor film (e.g., In:Ga:Zn = 5:1:4) with a thickness of 10 nm is formed as the high-mobility oxide semiconductor film 41. Alternatively, an In-Sn-Zn-O semiconductor film (e.g., In2O3-SnO2-ZnO) containing Sn or the like can be formed with a thickness of 10 nm.

[0264] In this process, a multilayer film including a high-mobility oxide semiconductor film 41 can also be formed. For example, a multilayer film can be formed with another oxide semiconductor film with a lower mobility than the high-mobility oxide semiconductor film 41 as the lower layer and the high-mobility oxide semiconductor film 41 as the upper layer. Thus, a multilayer film can be obtained. Figure 4 The TFT structure shown.

[0265] STEP 4: Patterning of high-mobility oxide semiconductor film 41 Figure 5D )

[0266] Next, the high-mobility oxide semiconductor film 41 is patterned. This removes portions of the high-mobility oxide semiconductor film 41 located in the TFT formation regions Rc2 and Rp. The portion of the high-mobility oxide semiconductor film 41 located in the TFT formation region Rc1 remains. The high-mobility oxide semiconductor film 41 remaining in the TFT formation region Rc1 can have a larger size than the portion that forms the oxide semiconductor layer.

[0267] The patterning of the high-mobility oxide semiconductor film 41 can be performed by dry etching or wet etching. In the case of wet etching, if the high-mobility oxide semiconductor film 41 is an In-Ga-Zn-O semiconductor film, a PAN-based etchant or an oxalic acid-based etchant can be used; if it is an In-Sn-Zn-O semiconductor film, an oxalic acid-based etchant can be used.

[0268] •STEP5: Formation of low-mobility oxide semiconductor film 42 ( Figure 5E )

[0269] Next, as Figure 5E As shown, a low-mobility oxide semiconductor film 42 is formed by covering the lower insulating layer 3 and the patterned high-mobility oxide semiconductor film 41. Here, an In-Ga-Zn-O semiconductor film (e.g., In:Ga:Zn = 1:1:1 or 4:2:4) with a thickness of 40 nm is formed as the low-mobility oxide semiconductor film 42.

[0270] • STEP 6: Patterning of high-mobility oxide semiconductor film 41 and low-mobility oxide semiconductor film 42 ( Figure 5F )

[0271] Next, the stacked film comprising a high-mobility oxide semiconductor film 41 and a low-mobility oxide semiconductor film 42 is patterned. Thus, as... Figure 5F As shown, an oxide semiconductor layer 4A with a stacked structure including a high-mobility oxide semiconductor film 41 and a low-mobility oxide semiconductor film 42 is formed in the TFT formation region Rc1. An oxide semiconductor layer 4B including a low-mobility oxide semiconductor film 42 and not including a high-mobility oxide semiconductor film 41 is formed in the TFT formation regions Rc2 and Rp.

[0272] Patterning of the stacked films can be performed by dry etching or wet etching. In the case of wet etching, if both the high-mobility oxide semiconductor film 41 and the low-mobility oxide semiconductor film 42 are In-Ga-Zn-O based semiconductor films, a PAN-based etchant or an oxalic acid-based etchant can be used. If the high-mobility oxide semiconductor film 41 is an In-Sn-Zn-O based semiconductor film and the low-mobility oxide semiconductor film 42 is an In-Ga-Zn-O based semiconductor film, an oxalic acid-based etchant can be used. Thus, both the high-mobility oxide semiconductor film 41 and the low-mobility oxide semiconductor film 42 can be etched simultaneously. In this case, in the oxide semiconductor layer 4A, the side surface of the high-mobility oxide semiconductor film 41 is aligned with the side surface of the low-mobility oxide semiconductor film 42.

[0273] Annealing of the high-mobility oxide semiconductor film 41 and the low-mobility oxide semiconductor film 42 can also be performed before or after patterning.

[0274] STEP 7: Formation of gate insulating film 50 and gate conductive film 70 ( Figure 5G )

[0275] Next, as Figure 5G As shown, a gate insulating film 50 and a gate conductive film 70 (thickness: for example, 50 nm or more and 500 nm or less) are sequentially formed on a portion of the oxide semiconductor layers 4A and 4B.

[0276] An insulating film identical to the lower insulating layer 3 (exemplified as the lower insulating layer 3) can be used as the gate insulating film 50. Here, a silicon oxide (SiO2) film is formed as the gate insulating film 50. When an oxide film such as a silicon oxide film is used as the gate insulating film, the oxidation defects generated in the channel region of the oxide semiconductor layers 4A and 4B can be reduced by the oxide film, thus suppressing the low resistance of the channel region.

[0277] For example, metals such as molybdenum (Mo), tungsten (W), aluminum (Al), copper (Cu), titanium (Ti), and tantalum (Ta), or their alloys, can be used as the gate conductive film 70. The gate conductive film 70 can also have a stacked structure comprising multiple layers formed of different conductive materials. Here, a Cu / Cu alloy stacked film with a Cu alloy film as the lower layer and a Cu film as the upper layer is used as the gate conductive film. Alternatively, a Cu / Ti stacked film or a Cu / Mo stacked film can be used.

[0278] • STEP 8: Formation of gate insulating layers 5A and 5B and gate electrodes 7A and 7B ( Figure 5H )

[0279] Next, as Figure 5H As shown, gate insulating layers 5A and 5B and gate electrodes 7A and 7B are formed.

[0280] First, the conductive film 70 for the gate is patterned using a known photolithography process. As a result, a gate electrode 7A is formed in the TFT formation region Rc1, and gate electrodes 7B are formed in the TFT formation regions Rc2 and Rp, respectively. Although not shown, a gate bus is also formed using the conductive film 70. The portions of the oxide semiconductor layers 4A and 4B that overlap with the gate electrodes 7A and 7B when viewed from the normal direction of the substrate 1 become the first regions 4Ac and 4Bc, respectively, containing the channel region.

[0281] Next, the gate insulating film 50 is patterned using the resist mask used for patterning the gate conductive film 70, or by using the gate electrodes 7A and 7B as a mask, to form gate insulating layers 5A and 5B. According to this method, when viewed from the normal direction of the substrate 1, the sides of the gate electrodes 7A and 7B are aligned with the sides of the gate insulating layers 5A and 5B, respectively. However, depending on the etching conditions of each film, misalignment may occur. For example, if the gate electrodes 7A and 7B are over-etched, the sides of the gate electrodes 7A and 7B may be significantly offset from the sides of the resist mask. Subsequently, when dry etching of the gate insulating film 50 is performed using the resist mask, when viewed from the normal direction of the substrate 1, the sides of the gate electrodes 7A and 7B may sometimes be located inside the sides of the gate insulating layers 5A and 5B (see reference). Figure 7C ).

[0282] Alternatively, after patterning the gate insulating film 50, the gate conductive film can be formed and patterned.

[0283] After forming the gate electrodes 7A and 7B, the oxide semiconductor layers 4A and 4B can also undergo a low-resistivity treatment. For example, plasma treatment can be performed as a low-resistivity treatment. As a result, when viewed from the normal direction of the main surface of the substrate 1, the regions (exposed regions) in the oxide semiconductor layers 4A and 4B that do not overlap with the gate electrodes 7A and 7B and the gate insulating layers 5A and 5B become low-resistivity regions with lower resistivity than the regions (including channel regions) that overlap with the gate electrodes 7A and 7B and the gate insulating layers 5A and 5B. The low-resistivity regions can be conductive regions (e.g., sheet resistance: 200 Ω / □ or less). In this embodiment, an oxide semiconductor layer 4A and 4B is obtained that includes a first region 4Ac and 4Bc that overlaps with the gate electrodes 7A and 7B when viewed from the normal direction of the substrate 1, and a low-resistivity region located on both sides of the first region with a resistivity lower than that of the first region 4Ac and 4Bc. Furthermore, the method of low-resistivity treatment is not limited to plasma treatment.

[0284] STEP 9: Formation of interlayer insulation layer 10 ( Figure 5I )

[0285] Next, an interlayer insulating layer 10 is formed, covering oxide semiconductor layers 4A and 4B, gate insulating layers 5A and 5B, and gate electrodes 7A and 7B. Then, the interlayer insulating layer 10 is patterned using a known photolithography process. Thus, as... Figure 5IAs shown, in the TFT forming region Rc1, a first opening 10As and a second opening 10Ad, which are part of the low resistance region of the oxide semiconductor layer 4A, are formed in the interlayer insulating layer 10. In the TFT forming regions Rc2 and Rp, a first opening 10Bs and a second opening 10Bd, which are part of the low resistance region of the oxide semiconductor layer 4B, are formed in the interlayer insulating layer 10.

[0286] Inorganic insulating layers such as silicon oxide films, silicon nitride films, silicon oxynitride films, and silicon oxynitride films can be formed as single layers or stacked layers as interlayer insulating layers 10. The thickness of the inorganic insulating layer can be 100 nm or more and 500 nm or less. When an insulating film such as a silicon nitride film that reduces the oxide semiconductor is used to form the interlayer insulating layer 10, the resistivity of the regions in the oxide semiconductor layers 4A and 4B that are in contact with the interlayer insulating layer 10 (in this case, low-resistance regions) can be maintained at a low level, which is therefore preferred. Here, for example, a SiNx layer (thickness: 300 nm) is formed by CVD as the interlayer insulating layer 10.

[0287] When an insulating layer capable of reducing oxide semiconductors (e.g., a hydrogen-donating layer such as a silicon nitride layer) is used as the interlayer insulating layer 10, even without the aforementioned low-resistance treatment, the portions of oxide semiconductor layers 4A and 4B that are in contact with the interlayer insulating layer 10 can be made to have lower resistance than the portions that are not in contact with the interlayer insulating layer 10.

[0288] • STEP 10: Formation of source electrodes 8A and 8B and drain electrodes 9A and 9B ( Figure 5J )

[0289] Next, a source conductive film (thickness: for example, 50 nm to 500 nm) is formed on the interlayer insulating layer 10, and the source conductive film is patterned. Thus, as shown... Figure 5J As shown, source electrodes 8A and 8B and drain electrodes 9A and 9B are formed. Although not shown, a source bus is also formed from the conductive film of the source. Thus, the first circuit transistor Tc1 and the second circuit transistor Tc2 are formed in the TFT forming regions Rc1 and Rc2 of the non-display area FR, respectively. In addition, the pixel transistor Tp is formed in the TFT forming region Rp of each pixel area PIX.

[0290] Source electrodes 8A and 8B are respectively disposed on the interlayer insulating layer 10 and within the openings 10As and 10Bs, and are connected to the first contact regions 4As and 4Bs of the oxide semiconductor layers 4A and 4B within the openings 10As and 10Bs. Drain electrodes 9A and 9B are respectively disposed on the interlayer insulating layer 10 and within the openings 10Ad and 10Bd, and are connected to the second contact regions 4Ad and 4Bd of the oxide semiconductor layers 4A and 4B within the openings 10Ad and 10Bd.

[0291] As the conductive film for the source electrode, elements selected from aluminum (Al), chromium (Cr), copper (Cu), tantalum (Ta), titanium (Ti), molybdenum (Mo), or tungsten (W), or alloys composed of these elements, can be used. For example, a three-layer structure of titanium film-aluminum film-titanium film, a three-layer structure of molybdenum film-aluminum film-molybdenum film, etc., can be used. Furthermore, the conductive film for the source electrode is not limited to a three-layer structure, but can also have a single-layer or two-layer structure, or a stacked structure of four or more layers. Here, a stacked film with a Ti film (thickness: 15-70 nm) as the lower layer and a Cu film (thickness: 50-400 nm) as the upper layer is used. When a stacked film with an ohmic conductive film such as a Ti film as the lowermost layer is used, the contact resistance with the oxide semiconductor layers 4A and 4B can be reduced more effectively.

[0292] • STEP 11: Formation of inorganic insulating layer 11 and organic insulating layer 12 ( Figure 5K )

[0293] Next, as Figure 5K As shown, an inorganic insulating layer 11 (thickness: for example, 100 nm or more and 500 nm or less) and an organic insulating layer 12 (thickness: for example, 1 to 4 μm, preferably 2 to 3 μm) are sequentially formed to cover the interlayer insulating layer 10, the source electrodes 8A and 8B, and the drain electrodes 9A and 9B.

[0294] Next, in each pixel region (PIX), an opening 12p is formed in the organic insulating layer 12, exposing a portion of the inorganic insulating layer 11. Then, using the organic insulating layer 12 as a mask, the inorganic insulating layer 11 is etched, forming an opening 11p in the inorganic insulating layer 11 that exposes the drain electrode 9B. This forms a pixel contact hole CHp including openings 11p and 12p.

[0295] The same inorganic insulating film as the interlayer insulating layer 10 can be used as the inorganic insulating layer 11. Here, for example, a SiNx layer (thickness: 300 nm) is formed by CVD as the inorganic insulating layer 11. The organic insulating layer 12 can be, for example, an organic insulating film containing a photosensitive resin material (e.g., an acrylic resin film).

[0296] • STEP 12: Formation of pixel electrode PE and wiring TL ( Figure 5L)

[0297] Next, a first transparent conductive film (thickness: 20–300 nm) and a conductive film for touch wiring (thickness: for example, 200 nm) are formed on the organic insulating layer 12. Then, for example, the first transparent conductive film and the conductive film for touch wiring are patterned using a hydrogen peroxide-based etching solution containing a fluorine compound. Thus, as shown... Figure 5L As shown, touch wiring TL and a laminated film 20 containing pixel electrodes PE are formed at intervals between each other.

[0298] The touch wiring TL has a stacked structure comprising a lower layer 18 formed of a first transparent conductive film and an upper layer 19 formed of a conductive film for touch wiring.

[0299] The laminate 20 includes a pixel electrode PE and a conductive layer 22 located on the pixel electrode PE and formed by a conductive film for touch wiring. The pixel electrode PE is electrically connected to the drain electrode 9B of the pixel TFT within the pixel contact hole CHp.

[0300] In this embodiment, when viewed from the normal direction of the substrate 1, the lower layer 18 and the upper layer 19 are aligned with each other, and the pixel electrode PE and the conductive layer 22 are aligned with each other.

[0301] As the first transparent conductive film, metal oxides such as indium-zinc oxide, indium-tin oxide (ITO), and ZnO can be used.

[0302] The same conductive film used for the gate or source electrode can be used as the conductive film for touch wiring. The conductive film for touch wiring can also be a metal film with a single-layer or stacked structure based on Cu or Al (thickness: 50-500 nm).

[0303] STEP 13: Patterning of conductive layer 22 ( Figure 5M )

[0304] like Figure 5M As shown, the conductive layer 22 is patterned to obtain the first electrode 21. The patterning of the conductive layer 22 is performed under conditions where the pixel electrode PE is not etched, but only the conductive layer 22 is etched. Here, for example, a hydrogen peroxide-based etchant that does not contain fluorine compounds is used for wet etching of the conductive layer 22.

[0305] The first electrode 21 is formed using the method described above, which has the following advantages.

[0306] If only a first transparent conductive film (e.g., indium tin oxide (ITO)) is formed on the organic insulating layer 12 and within the pixel contact hole CHp, and then patterned, pinholes are easily formed within the pixel contact hole CHp due to the thinness of the first transparent conductive film. When a pinhole forms in the first transparent conductive film within the pixel contact hole CHp, the surface of the drain electrode DE will be exposed through the pinhole and may be damaged. Therefore, in this embodiment, while a touch wiring conductive film is formed on the first transparent conductive film, both the first transparent conductive film and the touch wiring conductive film are patterned simultaneously to form a laminated film 20 including the pixel electrode PE. This reduces the likelihood of pinholes forming in the first transparent conductive film (pixel electrode PE). Furthermore, even if pinholes do form, the surface of the drain electrode DE is protected because it is covered by the touch wiring conductive film, thus suppressing the increase in contact resistance at the pixel contact portion caused by pinholes. Furthermore, the portion of the conductive film (conductive layer 22) covering the entire pixel electrode PE, located outside the pixel contact area (i.e., the portion located in the area that contributes to display), is then removed to form the first electrode 21. This suppresses the decrease in pixel aperture ratio caused by the use of the conductive film for touch wiring.

[0307] STEP 14: Formation of dielectric layer 17 Figure 5N )

[0308] Next, as Figure 5N As shown, a dielectric layer 17 (thickness: 50-500 nm) is formed to cover the touch wiring TL, the pixel electrode PE, and the first electrode 21. Then, the dielectric layer 17 is patterned to form a touch contact hole CHt that exposes a portion of the upper layer 19 of the touch wiring TL.

[0309] The material of the dielectric layer 17 can be the same as the material exemplified as the inorganic insulating layer 11. Here, for example, a SiN film is formed by CVD as the dielectric layer 17.

[0310] • STEP 15: Formation of the common electrode CE ( Figure 6 )

[0311] Next, a second transparent conductive film (thickness: 20-300 nm) is formed on the dielectric layer 17 and within the touch contact hole CHt, and the second transparent conductive film is patterned. This forms a common electrode CE comprising multiple segments, each functioning as a touch sensor electrode TX. Each touch sensor electrode TX is connected to a corresponding touch wiring TL within the touch contact hole CHt. Thus, the active matrix substrate 1000 is manufactured.

[0312] The manufacturing method of the active matrix substrate 1000 in this embodiment is not limited to the method described above. Alternatively, in STEP 4, a lower layer of the oxide semiconductor layer 4A may be formed by etching the high-mobility oxide semiconductor film 41, and in STEP 6, only the low-mobility oxide semiconductor film 42 may be etched. For example, if the high-mobility oxide semiconductor film 41 is an oxide semiconductor film containing Sn, and the low-mobility oxide semiconductor film 42 is an oxide semiconductor film not containing Sn, then the low-mobility oxide semiconductor film 42 can be selectively etched only by using a PAN-based etching solution. In the case where the low-mobility oxide semiconductor film 42 and the high-mobility oxide semiconductor film 41 are etched separately, the side surfaces of the high-mobility oxide semiconductor film 41 and the low-mobility oxide semiconductor film 42 may not be aligned in the oxide semiconductor layer 4A. For example, it may be as follows... Figure 7A As illustrated, the width of the low-mobility oxide semiconductor film 42 is smaller than the width of the high-mobility oxide semiconductor film 41, and when viewed from the normal direction of the substrate 1, the low-mobility oxide semiconductor film 42 is located inside the upper surface of the high-mobility oxide semiconductor film 41. Therefore, the area of ​​the portion of the surface of the high-mobility oxide semiconductor film 41 exposed from the low-mobility oxide semiconductor film 42 becomes larger, and thus, through the low-resistivity treatment, the resistivity of the low-resistivity region of the oxide semiconductor layer 4A can be further reduced. Alternatively, it could be as follows... Figure 7B As illustrated, the width of the low-mobility oxide semiconductor film 42 is greater than the width of the high-mobility oxide semiconductor film 41, and the low-mobility oxide semiconductor film 42 covers the upper surface and side surfaces of the high-mobility oxide semiconductor film 41. By making the size of the high-mobility oxide semiconductor film 41 smaller than the size of the low-mobility oxide semiconductor film 42, depletion of the TFT 100 is less likely to occur.

[0313] The structure of the active matrix substrate 1000 is not limited to Figure 6 The structure shown is sufficient as long as the pixel electrode PE and the common electrode CE are positioned opposite each other with the dielectric layer 17 in between. Here, an example is shown where the common electrode CE is positioned on the pixel electrode PE with the dielectric layer 17 in between, but the common electrode CE can also be positioned on the substrate 1 side of the pixel electrode PE.

[0314] Furthermore, this description uses an active matrix substrate used in an embedded touch panel type liquid crystal display device as an example; however, the active matrix substrate of this embodiment can also be used in liquid crystal display devices without a built-in touch panel. In this case, the touch wiring TL, touch electrode TX, and first electrode 21 may not be formed, or only the first electrode 21 may be formed.

[0315] <Variation Example 1>

[0316] In the second TFT of this embodiment, at least one of the source electrode and drain electrode may be disposed on the substrate side of the oxide semiconductor layer, separated by a lower insulating layer. In this case, at least one of the first contact region and the second contact region of the second TFT may also have a connection layer comprising a high-mobility oxide semiconductor film on the substrate side of the low-mobility oxide semiconductor film. The connection layer is electrically connected to the source electrode or the drain electrode within the opening of the lower insulating layer. This reduces the contact resistance between the oxide semiconductor layer and the source electrode or the drain electrode.

[0317] The following describes the active matrix substrate of Modified Example 1 using an active matrix substrate with a structure (referred to as "lower source wiring structure") having a source bus SL located on the side of the active layer closer to substrate 1 than the gate bus GL and the pixel TFT.

[0318] In an active matrix substrate with a lower source wiring structure, the insulating layer between the source bus and the gate bus can be thickened, thereby reducing parasitic capacitance generated at the intersections of these buses. Additionally, the capacitance generated between the source bus and the common electrode can also be reduced. Regarding the lower source wiring structure, for example, it is described in the applicant's International Publication No. 2015 / 186619. For reference, the entire disclosure of International Publication No. 2015 / 186619 is incorporated herein by reference.

[0319] Figure 8 This is a schematic cross-sectional view showing the first TFT 100 and the second TFT 201 in the active matrix substrate 1001 of Modified Example 1 of this embodiment. Here, an example is described in which the first TFT 100 is used for circuit TFTs such as SSD circuit TFTs and the second TFT 201 is used for pixel TFTs.

[0320] The active matrix substrate 1001 has a lower source wiring structure. The following mainly describes the differences from the active matrix substrate 1000; descriptions of the same structures are omitted.

[0321] In the active matrix substrate 1001, the source electrode 8B and source bus SL (not shown) of the second TFT 201, which serves as a pixel TFT, are formed in the same layer as the lower conductive layer 2B (i.e., formed using the same conductive film). The source electrode 8B is electrically connected to the source bus SL. The source electrode 8B may be part of the source bus SL. The drain electrode 9B may be disposed on the interlayer insulating layer 10. The first contact region 4Bs of the oxide semiconductor layer 4B is electrically connected to the source electrode 8B (or the source bus SL) within the opening 3s formed in the lower insulating layer 3. This structure can be obtained by forming the opening 3s by adding a patterning process to the lower insulating layer 3 after the formation of the lower insulating layer 3 and before the formation of the high-mobility oxide semiconductor film 41.

[0322] In the illustrated example, the first contact region 4Bs of the second TFT 201 has a stacked portion pa, which includes a connection layer 41a comprising a high-mobility oxide semiconductor film 41 and a low-mobility oxide semiconductor film 42. Within the opening 3s, the high-mobility oxide semiconductor film 41 is electrically connected to the source electrode 8B via the connection layer 41a comprising the high-mobility oxide semiconductor film 41. By providing the high-mobility connection layer 41a, the contact resistance between the oxide semiconductor layer 4B and the source bus SL can be reduced.

[0323] The first TFT100 can have the same Figure 2 The first TFT 100 shown has the same structure. That is, similar to the active matrix substrate 1000, the source electrodes 8A and 8B and the drain electrodes 9A and 9B are all disposed on the interlayer insulating layer 10. Although not shown, the active matrix substrate 1001 may also have Figure 2 The second TFT200 shown is, for example, a TFT used in a driving circuit.

[0324] Furthermore, the source electrodes 8A and 8B and drain electrodes 9A and 9B of the first TFT100 and the second TFT200, as well as the drain electrode 9B of the second TFT201, can be formed in the same layer as the lower conductive layers 2A and 2B as needed.

[0325] Figures 9A to 9DThis is a cross-sectional view illustrating the manufacturing method of the active matrix substrate 1001. Here, an example is shown where a first circuit transistor Tc1 and a second circuit transistor Tc2 are formed in the non-display area FR, and a pixel transistor Tp is formed in each pixel region PIX in the display area DR. The first circuit transistor Tc1 is a first TFT 100, for example, used in an SSD circuit. The second circuit transistor Tc2 is a second TFT 200, for example, used in a driving circuit. The pixel transistor Tp is a second TFT 201. The regions where the first circuit transistor Tc1, the second circuit transistor Tc2, and the pixel transistor Tp are formed are designated as TFT forming regions Rc1, Rc2, and Rp, respectively. Hereinafter, the differences from the manufacturing method of the active matrix substrate 1000 will be mainly explained; descriptions of the same processes will be omitted.

[0326] First, such as Figure 9A As shown, a lower conductive film is formed and patterned on substrate 1, thereby forming a lower conductive layer 2A in TFT formation region Rc1 and a lower conductive layer 2B in TFT formation region Rc2. Additionally, in TFT formation region Rp, the lower conductive layer 2B and source electrode 8B (or source bus SL) are formed using the lower conductive film.

[0327] Next, as Figure 9B As shown, a lower insulating layer 3 is formed to cover the lower conductive layers 2A and 2B and the source electrode 8B. Then, the lower insulating layer 3 is patterned, and an opening 3s is provided in the TFT formation region Rp to expose a portion of the lower source electrode 8B.

[0328] Next, as Figure 9C As shown, a high-mobility oxide semiconductor film 41 is formed and patterned. This leaves the portion of the high-mobility oxide semiconductor film 41 located in the TFT formation region Rc1 intact, while the portion located in the TFT formation region Rc2 is removed. Furthermore, a connection layer 41a is formed from the high-mobility oxide semiconductor film 41 in the TFT formation region Rp. The connection layer 41a is disposed within the opening 3p and on the lower insulating layer 3, and is connected to the source electrode 8B within the opening 3p.

[0329] Next, as Figure 9D As shown, a low-mobility oxide semiconductor film 42 is formed, and the high-mobility oxide semiconductor film 41 and the low-mobility oxide semiconductor film 42 are patterned.

[0330] Therefore, an oxide semiconductor layer 4A having a high-mobility oxide semiconductor film 41 and a low-mobility oxide semiconductor film 42 is formed in the TFT formation region Rc1. In the TFT formation region Rc2, the low-mobility oxide semiconductor film 42 is patterned to form an oxide semiconductor layer 4B containing the low-mobility oxide semiconductor film 42 but not the high-mobility oxide semiconductor film 41. In the TFT formation region Rp, the low-mobility oxide semiconductor film 42 is disposed to cover the interconnect layer 41a, thereby forming an oxide semiconductor layer 4B containing the interconnect layer 41a and the low-mobility oxide semiconductor film 42. The first contact region 4Bs of the oxide semiconductor layer 4B becomes the stacked portion pa containing the interconnect layer 41a and the low-mobility oxide semiconductor film 42, and the portion that becomes the first region becomes the upper layer portion p2 containing the low-mobility oxide semiconductor film 42 but not the high-mobility oxide semiconductor film 41.

[0331] Although not shown, the subsequent processes are the same as those for the active matrix substrate 1000. However, in the TFT formation region Rp, the first opening 10Bs is not formed in the interlayer insulating layer 10, and the source electrode is not formed on the interlayer insulating layer 10.

[0332] Furthermore, while the above description uses an active matrix substrate with a lower source wiring structure as an example, this modification can also be applied to active matrix substrates without a lower source wiring structure. For example, the active layer structure of the second TFT of this modification can also be applied to a circuit TFT connected to wiring formed in the same layer as the lower conductive layer.

[0333] <Variation Example 2>

[0334] Figure 10A This is a schematic cross-sectional view showing the first TFT 101 and the second TFT 200 in the active matrix substrate 1002 of Modified Example 2 of this embodiment. Figure 10B This is a schematic top view of TFT101. Figure 10A The cross-section of TFT101 shown is Figure 10B The cross section of the Xa-Xa' line.

[0335] The first TFT 101 of the active matrix substrate 1002 has an active layer structure including a stacked portion p1 and an upper layer portion p2, which differs from the active matrix substrate 1000 of the aforementioned embodiment. Furthermore, the second TFT 200 has a structure similar to... Figure 2 The TFT200 shown has the same active layer structure.

[0336] In TFT 101, the oxide semiconductor layer 4A has: an upper layer p2, which includes a low-mobility oxide semiconductor film 42 and does not include a high-mobility oxide semiconductor film 41; and a stacked layer p2, which includes a high-mobility oxide semiconductor film 41 and a low-mobility oxide semiconductor film 42. At least a portion of the first region 4Ac of the oxide semiconductor layer 4A is the stacked layer p2. The first contact region 4As and the second contact region 4Ad are both the upper layer p2.

[0337] In the illustrated example, the high-mobility oxide semiconductor film 41 is configured to be located in at least a portion of the first region 4Ac. The low-mobility oxide semiconductor film 42 is configured to be larger than the high-mobility oxide semiconductor film 41, covering the upper surface and side surfaces of the high-mobility oxide semiconductor film 41. Here, the entire side surface of the high-mobility oxide semiconductor film 41 is covered by the low-mobility oxide semiconductor film 42. Alternatively, a portion of the high-mobility oxide semiconductor film 41 may not be covered by the low-mobility oxide semiconductor film 42. The structure in the oxide semiconductor layer 4A other than the active layer is the same as that of the TFT 100 in the aforementioned embodiment.

[0338] According to this modified example, in the oxide semiconductor layer 4A, by configuring a high-mobility oxide semiconductor film 41 in the portion that forms the channel, and making the size of the high-mobility oxide semiconductor film 41 smaller than the size of the low-mobility oxide semiconductor film 42, it is possible to ensure high mobility and suppress depletion of the TFT 101.

[0339] In TFT101, it is possible to... Figure 11A As illustrated, the high-mobility oxide semiconductor film 41 is disposed only in a portion of the first region 4Ac. That is, the first region 4Ac may include a stacked portion p1 and an upper portion p2. In this case, the width of the channel length direction of the high-mobility oxide semiconductor film 41 may be smaller than the width of the first region 4Ac (i.e., the width of the gate electrode 7A). Alternatively, it may be as follows: Figure 11B As shown, the width of the channel length direction of the high mobility oxide semiconductor film 41 is the same as or greater than the width of the first region 4Ac (i.e., the width of the gate electrode 7A), and the entire range of the first region 4Ac is the stacked portion pa.

[0340] Figure 12 This is a cross-sectional view showing another active matrix substrate 1002 of this modified example. (See diagram below.) Figure 12As shown, the active matrix substrate 1002 may have at least three TFTs 100, 101, and 200 with different active layer structures. Furthermore, in this specification, when the active matrix substrate has two first TFTs (or two second TFTs) with different active layer structures, one of them is sometimes referred to as the "third TFT".

[0341] Next, the manufacturing method of the active matrix substrate 1002 of this modified example will be described.

[0342] Figures 13A to 13F These are process cross-sectional views illustrating an example of the manufacturing method of the active matrix substrate 1002 in this modified example. Here, an example is shown where a first circuit transistor Tc1 and a second circuit transistor Tc2 are formed in the non-display area FR, and a pixel transistor Tp is formed in each pixel region PIX in the display area DR. The first circuit transistor Tc1 is a first TFT 101, for example, used in an SSD circuit. The second circuit transistor Tc2 is a second TFT 200, for example, used in a driving circuit. The pixel transistor Tp is the second TFT 200. The regions where the first circuit transistor Tc1, the second circuit transistor Tc2, and the pixel transistor Tp are formed are designated as TFT forming regions Rc1, Rc2, and Rp, respectively. Hereinafter, the differences from the manufacturing method of the active matrix substrate 1000 will be mainly explained; descriptions of the same processes will be omitted.

[0343] First, the lower conductive layers 2A and 2B and the lower insulating layer 3 are formed using the same method as the active matrix substrate 1000. Next, as... Figure 13A As shown, a high-mobility oxide semiconductor film 41 is formed and patterned on the lower insulating layer 3. Therefore, in the TFT formation region Rc1, the high-mobility oxide semiconductor film 41 is disposed only in a portion of the region that becomes the oxide semiconductor layer (active layer). The portions of the high-mobility oxide semiconductor film 41 located in the TFT formation regions Rc2 and Rp are removed.

[0344] Next, as Figure 13B As shown, a low-mobility oxide semiconductor film 42 is formed such that it covers a high-mobility oxide semiconductor film 41 and a lower insulating layer 3. Then, as... Figure 13C As shown, a low-mobility oxide semiconductor film 42 is patterned. Thus, in the TFT formation region Rc1, an oxide semiconductor layer 4A is obtained, comprising a high-mobility oxide semiconductor film 41 and a low-mobility oxide semiconductor film 42 covering the upper and side surfaces of the high-mobility oxide semiconductor film 41. In the TFT formation regions Rc2 and Rp, an oxide semiconductor layer 4B is obtained, comprising the low-mobility oxide semiconductor film 42 but not the high-mobility oxide semiconductor film 41.

[0345] Next, as Figures 13D to 13F As shown, gate insulating layers 5A and 5B, gate electrodes 7A and 7B, interlayer insulating layer 10, source electrodes 8A and 8B, and drain electrodes 9A and 9B are formed using the same method as the active matrix substrate 1000. Thus, a first circuit transistor Tc1 is formed in the TFT formation region Rc1, and a second circuit transistor Tc2 is formed in the TFT formation region Rc2. Furthermore, a pixel transistor Tp is formed in the TFT formation region Rp of each pixel region.

[0346] <Variation Example 3>

[0347] In the active matrix substrate of Modified Example 3, the first region of the second TFT has a lower layer p1 that includes a high-mobility oxide semiconductor film 41 but does not include a low-mobility oxide semiconductor film 42, which is different from the active matrix substrate 1000.

[0348] Figure 14A This is a schematic cross-sectional view of the first TFT 100 and the second TFT 300 in the active matrix substrate 1003 of Modified Example 3. Hereinafter, regarding the configuration of the active matrix substrate 1003, only the differences from those of the active matrix substrate 1000 will be described, and descriptions of the same configurations will be omitted.

[0349] TFT100 has the same characteristics as Figure 2 The TFT100 shown has the same structure.

[0350] Similar to TFT100, TFT300 has: an oxide semiconductor layer 4C; a gate electrode 7C disposed on a portion of the oxide semiconductor layer 4C with respect to a gate insulating layer 5C; and a source electrode 8C and a drain electrode 9C. TFT300 may also have a lower conductive layer 2C on the substrate 1 side of the oxide semiconductor layer 4C.

[0351] The oxide semiconductor layer 4C has a lower layer p1 that includes a high-mobility oxide semiconductor film 41 but does not include a low-mobility oxide semiconductor film 42. As shown, the entire extent of the oxide semiconductor layer 4C may include the high-mobility oxide semiconductor film 41 but not the low-mobility oxide semiconductor film 42. Furthermore, in this modified example, as long as the first region 4Cc of the oxide semiconductor layer 4C is the lower layer p1 over its entire extent, the second region may include the low-mobility oxide semiconductor film 42.

[0352] The oxide semiconductor layers 4A and 4C may also further comprise oxide semiconductor films other than the high-mobility oxide semiconductor film 41 and the low-mobility oxide semiconductor film 42. For example, such as Figure 14BAs shown, oxide semiconductor layers 4A and 4C may further include other oxide semiconductor films 43 with lower mobility than the high-mobility oxide semiconductor film 41 between the high-mobility oxide semiconductor film 41 and the substrate 1. For example, a low-mobility oxide semiconductor film having the same composition as the low-mobility oxide semiconductor film 42 can be used as the other oxide semiconductor film 43. The thickness of the other oxide semiconductor film 43 can be similar to that of the high-mobility oxide semiconductor film 42. Figure 4 The examples shown are similar, for instance, those above 5nm and below 30nm.

[0353] Figure 15 This is a graph illustrating the Vg-Id characteristics of TFT100 and TFT300. The horizontal axis of the graph represents the gate-drain voltage Vg, and the vertical axis represents the drain current Id.

[0354] Depend on Figure 15 It is known that TFT300 has a lower threshold voltage than TFT100. This can be attributed to the fact that in TFT300, the first region 4Cc of the oxide semiconductor layer 4C does not contain the low-mobility oxide semiconductor film 42. Therefore, compared with the oxide semiconductor layer 4A which contains the low-mobility oxide semiconductor film 42, the overall mobility of the first region is higher, and the threshold voltage is shifted in the negative direction.

[0355] TFT100 can also be used as a TFT for driving circuits, and TFT300 can be used as a TFT for SSD circuits. Using TFT300 in, for example, SSD circuits can increase the on-state current, which is advantageous. TFT300 can also have a depletion characteristic with a negative threshold voltage. Therefore, the on-state current of TFT300 can be further increased.

[0356] Alternatively, TFT100 and TFT300 can be mixed in the driving circuit. For example, TFT300 can be used as the output transistor in the gate driving circuit, and TFT100 can be used as other transistors.

[0357] Figure 16 This is a cross-sectional view showing another active matrix substrate 1003 of this modified example. (See diagram below.) Figure 16 As shown, the active matrix substrate 1003 may have at least three TFTs 100, 200, and 300 with different active layer structures.

[0358] <Structure and Operation of Gate Drive Circuit>

[0359] The circuit configuration and operation of a gate driver monolithically formed on an active matrix substrate are described. The gate driver includes a shift register. The shift register contains multiple unit shift register circuits connected in multiple stages.

[0360] Figure 17This is a diagram illustrating a shift register circuit.

[0361] The shift register circuit has multiple unit shift register circuits SR1 to SRz (z: an integer greater than or equal to 2) (hereinafter collectively referred to as "unit shift register circuits SR"). Each unit shift register circuit SR has a set terminal S for receiving a set signal, an output terminal Z for outputting an output signal, a reset terminal R for receiving a reset signal, and clock input terminals CK1 and CK2 for receiving clock signals GCK1 and GCK2. In unit shift register circuit SRα (α≥2), the set terminal S is input to the output signal of the previous unit shift register circuit SR. The set terminal S of the first-stage unit shift register circuit SR1 is input to the gate start pulse signal GSP. In addition, each unit shift register circuit SR outputs its output signal to the corresponding gate bus GL located in the display area. The reset terminal R is input to the output signal of the next-stage unit shift register circuit. The reset terminal R of the last-stage unit shift register circuit SRz is input to the clear signal.

[0362] Two clock input terminals, GCK1 and GCK2, are provided as two-phase clock signals. One clock input terminal receives clock signal GCK1, and the other clock input terminal receives clock signal GCK2. The clock signals input to the clock input terminals are configured to alternate between adjacent stages.

[0363] Figure 18 This diagram illustrates an example of a unit shift register circuit SR. In this example, the unit shift register circuit SR includes four TFTs 31-34 and a capacitor section Cap.

[0364] TFT31 is the input transistor. The gate and drain of TFT31 are connected to the set terminal, and the source of TFT31 is connected to the gate of TFT34. TFT34 is the output transistor. The drain of TFT34 is connected to the clock input terminal CK1, and the source is connected to the output terminal Z. That is, TFT34 acts as a transmission gate, allowing or blocking the clock signal input to the clock input terminal CK1.

[0365] The capacitor Cap is connected between the gate and source of the TFT34, which serves as the output transistor. In this specification, the node connected to the gate of the TFT34 is referred to as "node netA", and the node connected to the output terminal Z is referred to as "node Z". One electrode of the capacitor Cap is connected to the gate of the TFT34 and node netA, and the other electrode is connected to the source of the TFT34 and node Z.

[0366] TFT32 is positioned between the Low power input terminal and node netA. TFT32 is a pull-down transistor used to lower the potential of node netA. The gate of TFT32 is connected to the reset terminal, the drain is connected to node netA, and the source is connected to the Low power input terminal.

[0367] Node Z is connected to TFT33. The gate of TFT33 is connected to the clock signal input terminal CK2, the drain is connected to node Z, and the source is connected to the Low power input terminal.

[0368] In this embodiment, the second TFT can be used as TFTs 31 to 34. Alternatively, at least TFT 34, which serves as the output transistor, can use the first TFT, which has a high current driving force (high mobility), while the other TFTs can use the second TFT. Thus, two types of TFTs with different characteristics can be mixed within the driving circuit depending on the application. Furthermore, regardless of their TFT structure, TFTs 31 to 34 preferably have enhancement characteristics.

[0369] Furthermore, the configuration of the driving circuit is not limited to the configuration shown in the figure. For example, a unit shift register circuit may have five or more TFTs, including an output transistor.

[0370] <SSD Circuit Structure and Operation>

[0371] The circuit configuration and operation of an SSD with a monolithic ground plane formed on an active matrix substrate are explained.

[0372] Figure 19 It is a diagram used to illustrate the structure and operation of SSD circuitry.

[0373] An SSD circuit 600 is configured between the source driver SD and the display area DR. The SSD circuit 600 includes multiple SSD unit circuits 500(1) to 500(i) (i is an integer of 2 or more) (sometimes collectively referred to as "SSD unit circuits 500") and control signal lines SW1 to SWn (n is an integer of 2 or more, here n=3). The SSD circuit 600 and the source driver SD are controlled by a control circuit located in the non-display area FR. The control signal lines SW1 to SWn are connected to the control circuit.

[0374] The output terminals V(1) to V(i) (hereinafter, sometimes collectively referred to as "V terminals") of the source driver SD are each connected to any one of the multiple video signal lines DO(1) to DO(i) (sometimes collectively referred to as "video signal lines DO"). Each of the n grouped source buses SL corresponds to one video signal line DO. Between the video signal lines DO and the grouped source buses SL, an SSD unit circuit 500 is provided on a per-video signal-line basis. The SSD unit circuit 500 distributes video data from one video signal line DO to the n source buses SL.

[0375] In this embodiment, the Nth video signal line among the multiple video signal lines DO(1) to DO(i) is set as DO(N) (N is an integer from 1 to i), and the SSD unit circuit 500 and the source bus SL corresponding to the video signal line DO(N) are set as 500(N), SL(N-1) to SL(Nn), respectively. The source buses SL(N-1) to SL(Nn) can, for example, correspond to R, G, and B pixels (i.e., n = 3).

[0376] Each SSD unit circuit 500(N) has at least n (3 in this case) thin film transistors (TFTs for SSD circuits) 40(1) to 40(n) (sometimes collectively referred to as "TFTs for SSD circuits 40").

[0377] The SSD circuit uses TFT40 as a selection switch. The gate electrode of TFT40 is electrically connected to one of the n control signal lines SW1 to SWn. The source electrode of TFT40 is electrically connected to the branch line of the video signal line DO(N). The drain electrode of TFT40 is connected to one of the source buses SL(N-1) to SL(N-3).

[0378] A selection signal (control signal) is supplied to the gate electrode of the TFT 40 in the SSD circuit from one of the control signal lines SW1 to SW3. The control signal specifies the on-time of the selection switch within the same group and is synchronized with the time-series signal output from the source driver SD. The SSD unit circuit 500(N) writes the data potential obtained by time-division multiplexing the output of the video signal line DO(N) into multiple source buses SL(N-1) to SL(Nn) in a time sequence (time-division driving). As a result, the number of V terminals of the source driver SD can be reduced, and therefore, the area of ​​the non-display area FR can be further reduced (narrow bezel).

[0379] In this embodiment, the TFT 40 used in the SSD circuit can be a TFT with a higher mobility than other circuit TFTs or pixel TFTs, i.e., a higher current driving force. For example, a first TFT or a third TFT with high mobility can be suitable for use as the TFT 40 in the SSD circuit. The first TFT 100 may also have depletion characteristics.

[0380] Furthermore, the configuration of the SSD circuit is not limited to the configuration shown in the figure. The configuration and operation of the SSD circuit are disclosed in, for example, Japanese Patent Application Publication No. 2008-225036, Japanese Patent Application Publication No. 2006-119404, and International Patent Application Publication No. 2011 / 118079. In this specification, for reference, the entire contents of Japanese Patent Application Publication No. 2008-225036, Japanese Patent Application Publication No. 2006-119404, and International Patent Application Publication No. 2011 / 118079 are cited.

[0381] (Second Implementation)

[0382] In the active matrix substrate of the second embodiment, each pixel region includes multiple TFTs with different active layer structures, which differs from the aforementioned embodiments. Hereinafter, the active matrix substrate of this embodiment will be described using an active matrix substrate used in an organic EL display device as an example. Furthermore, the following mainly describes the differences from the active matrix substrate of the first embodiment; descriptions of the same structures are omitted.

[0383] Figure 20 This is a schematic diagram showing an example of the planar structure of the active matrix substrate 2000 of this embodiment.

[0384] The active matrix substrate 2000 has multiple pixel regions (PIX) arranged in a matrix. The multiple pixel regions typically include pixel regions corresponding to red pixels that display red, green pixels that display green, and blue pixels that display blue.

[0385] Each pixel region in a multi-pixel PIX includes a substrate 1 and pixel circuitry disposed on the substrate 1. Figure 20 (Not shown in the image). Figure 21 An example of a pixel circuit is shown below.

[0386] Figure 21 The pixel circuit 700 shown includes a driving TFT 71, a selection TFT 72, and a capacitor element (holding capacitor) 73. The driving TFT 71 and the selection TFT 72 are oxide semiconductor TFTs supported on the substrate 1.

[0387] The gate electrode of the selected TFT 72 is connected to the gate bus GL. The source electrode of the selected TFT 72 is connected to the source bus SL. The drain electrode of the selected TFT 72 is connected to the gate electrode of the driving TFT 71 and the capacitor element 73. The source electrode of the driving TFT 71 is connected to the current supply line CL. The drain electrode of the driving TFT 71 is connected to the OLED (organic light-emitting diode) 80 formed on the active matrix substrate 2000.

[0388] When a conduction signal is supplied from the gate bus GL to the gate electrode of the selection TFT 72, the selection TFT 72 becomes active. Therefore, the signal voltage from the source bus SL (corresponding to the desired luminance of the OLED 80) is applied to the gate electrodes of the capacitor element 73 and the driving TFT 71 via the selection TFT 72. When the driving TFT 71 becomes active due to the signal voltage, current from the current supply line CL flows to the OLED 80 via the driving TFT 71, causing the OLED 80 to emit light.

[0389] According to this embodiment, multiple oxide semiconductor TFTs (here, driving TFT 71 and selection TFT 72) with different required characteristics can be fabricated separately within the pixel circuit 700. Specifically, the first TFT can be used as the selection TFT 72, and the second TFT, which has a lower mobility than the selection TFT 72 (causing the threshold voltage to shift in the positive direction), can be used as the driving TFT 71.

[0390] Figure 22 This is a cross-sectional view showing the first TFT 100 and the second TFT 200 in the active matrix substrate 2000. Here, an example is shown in which the second TFT 200 is used as a driving TFT 71 for the pixel circuit 700, the first TFT 100 is used as a selection TFT 72, and the second TFT 200 is used as a driving circuit TFT.

[0391] Structure and reference of TFT100 and TFT200 Figure 2 The structure described above is the same. However, when applied to a top-emitting organic EL display device, the lower conductive layers 2A and 2B, which serve as light-shielding layers, may not be formed in each TFT. Alternatively, in the first TFT 100, the lower conductive layer 2A may function as a lower gate electrode (dual-gate structure), and the lower conductive layer 2B may not be provided in the second TFT 200.

[0392] A planarization layer 75 is provided on the driving TFT 71 and the selection TFT 72. A pixel electrode PE is provided on the planarization layer 75. The drain electrode 9B of the driving TFT 71 is electrically connected to the pixel electrode PE. Furthermore, in the case of an organic EL display device using a color filter method, a color filter layer (not shown) is also provided between the planarization layer 75 and the inorganic insulating layer 11. Between adjacent pixel areas, a bank (not shown) formed of insulating material is provided on the planarization layer 75 and the pixel electrode PE. In addition, although not shown, an organic EL layer is disposed on the pixel electrode PE, and an upper electrode is provided on the organic EL layer. For example, the pixel electrode PE functions as an anode, and the upper electrode functions as a cathode.

[0393] Furthermore, the composition of pixel circuits is not limited to... Figure 21 The configuration is illustrated. Each pixel circuit may also have more than three TFTs. In this case, at least the second TFT 200 is used as the driving TFT 71, and the other TFTs may be either the first TFT 100 or the second TFT 200, depending on the application.

[0394] In this embodiment, it can also be referred to as follows. Figure 8 As explained, one or both of the source and drain electrodes of the first TFT 100 and / or the second TFT are formed within the same layer as the lower conductive layer. In this case, the contact resistance can also be reduced by configuring a high-mobility oxide semiconductor film 41 at the connection portion of the oxide semiconductor layer 4B of the second TFT 200 and the electrode located within the same layer as the lower conductive layer. This structure is suitable, for example, for use in active matrix substrates having a lower source wiring structure.

[0395] The composition and thickness of the high-mobility oxide semiconductor film 41 and the low-mobility oxide semiconductor film 42 can be the same as in the aforementioned embodiments. However, in this embodiment, it is preferable that the second TFT 200, used as the driving TFT 71, has a large S-value (i.e., the VI characteristic is flat). Therefore, the low-mobility oxide semiconductor film 42 can also have a lower mobility than in the aforementioned embodiments. In addition, by increasing the channel length L of the driving TFT 71, the S-value can be further increased.

[0396] Although not shown, a gate driving circuit can also be monolithically formed in the non-display area of ​​the active matrix substrate 2000. In this case, the second TFT 200 can be used as a TFT for the driving circuit. TFTs with different characteristics can also be mixed and matched in the gate driving circuit depending on the application. For example, at least the output transistor can use the first TFT 100, while other driving circuit TFTs can use the second TFT 200.

[0397] Figure 23 This is a graph illustrating the Vg-Id characteristics of the first TFT100 and the second TFT200 in this embodiment. The horizontal axis of the graph represents the potential of the gate electrode (gate-drain voltage) Vg, which is based on the potential of the drain electrode, and the vertical axis represents the drain current Id.

[0398] according to Figure 23 It can be seen that the threshold voltage of the second TFT 200 is shifted in the positive direction compared to the threshold voltage of the first TFT 100. In this example, the second TFT 200 has an enhancement characteristic with a positive threshold voltage, while the first TFT 100 has a depletion characteristic with a negative threshold voltage. Furthermore, the VI characteristic of the second TFT 200 is smoother than that of the first TFT 100. That is, the S-value of the second TFT 200 is larger than that of the first TFT 100. Moreover, the sign and magnitude of the threshold voltage of each TFT, the tilt of the VI characteristic, etc., are not limited to the example shown.

[0399] Because the second TFT 200 has a large S-value, it is suitable for use as a driving TFT in pixel circuits. This allows for appropriate multi-grayscale display. Furthermore, as shown in the figure, when the second TFT 200 has enhanced characteristics, it can be used in some circuit TFTs, such as driving circuit TFTs. This helps suppress circuit malfunctions and reduce yield.

[0400] On the other hand, the first TFT100 has a high current driving force (conduction current). Furthermore, it allows for short-channel operation, reducing circuit area. The first TFT100 is suitable, for example, as a selection TFT for pixel circuits. Therefore, it can be applied to high-frequency or high-definition models. Additionally, the first TFT100 can also be used as an output transistor in a gate drive circuit.

[0401] Table 2 illustrates preferred characteristics of the TFTs for driving and selecting pixel circuits in an organic EL display device, as well as the TFTs for driving circuits. The characteristics and numerical ranges listed in Table 2 are illustrative and do not limit the characteristics of each TFT.

[0402] [Table 2]

[0403]

[0404] <Oxide Semiconductor>

[0405] In this embodiment, the oxide semiconductor included in the oxide semiconductor layer of each TFT can be an amorphous oxide semiconductor or a crystalline oxide semiconductor having a crystalline portion. Examples of crystalline oxide semiconductors include polycrystalline oxide semiconductors, microcrystalline oxide semiconductors, and crystalline oxide semiconductors whose c-axis is oriented substantially perpendicular to the layer.

[0406] The oxide semiconductor layer can have a stacked structure of two or more layers. When the oxide semiconductor layer has a stacked structure, it can include an amorphous oxide semiconductor layer and a crystalline oxide semiconductor layer. Alternatively, it can include multiple crystalline oxide semiconductor layers with different crystal structures. Additionally, it can include multiple amorphous oxide semiconductor layers. When the oxide semiconductor layer has a two-layer structure including an upper layer and a lower layer, the bandgap of the oxide semiconductor layer located on the gate electrode side (the lower layer if it's a bottom-gate structure, and the upper layer if it's a top-gate structure) can be smaller than the bandgap of the oxide semiconductor layer located on the opposite side of the gate electrode (the upper layer if it's a bottom-gate structure, and the lower layer if it's a top-gate structure). However, when the difference in bandgap between these layers is relatively small, the bandgap of the oxide semiconductor layer located on the gate electrode side can also be larger than the bandgap of the oxide semiconductor layer located on the opposite side of the gate electrode.

[0407] Materials, structures, film-forming methods, and compositions of oxide semiconductor layers with stacked structures for amorphous oxide semiconductors and the aforementioned crystalline oxide semiconductors are described, for example, in Japanese Patent Application Publication No. 2014-007399. For reference, the entire disclosure of Japanese Patent Application Publication No. 2014-007399 is incorporated herein by reference.

[0408] The oxide semiconductor layer may, for example, contain at least one metal element selected from In, Ga, and Zn. In this embodiment, the oxide semiconductor layer contains, for example, an In-Ga-Zn-O semiconductor (e.g., indium gallium zinc oxide). Here, the In-Ga-Zn-O semiconductor is a ternary oxide of In (indium), Ga (gallium), and Zn (zinc), and the ratio (composition ratio) of In, Ga, and Zn is not particularly limited, for example, In:Ga:Zn = 2:2:1, In:Ga:Zn = 1:1:1, In:Ga:Zn = 1:1:2, etc. This oxide semiconductor layer can be formed from an oxide semiconductor film containing an In-Ga-Zn-O semiconductor.

[0409] In-Ga-Zn-O semiconductors can be either amorphous or crystalline. As for crystalline In-Ga-Zn-O semiconductors, those with the c-axis oriented approximately perpendicular to the layer are preferred.

[0410] Furthermore, the crystal structure of crystalline In-Ga-Zn-O semiconductors is disclosed, for example, in Japanese Patent Application Publication Nos. 2014-007399, 2012-134475, and 2014-209727. For reference, the entire disclosures of Japanese Patent Application Publication Nos. 2012-134475 and 2014-209727 are incorporated herein by reference. TFTs having an In-Ga-Zn-O semiconductor layer have high mobility (more than 20 times that of a-Si TFTs) and low leakage current (less than one percent that of a-Si TFTs), and are therefore suitable for use as driving TFTs (e.g., TFTs included in driving circuits disposed around a display area containing multiple pixels on the same substrate as the display area) and pixel TFTs (TFTs disposed in pixels).

[0411] The oxide semiconductor layer can also contain other oxide semiconductors instead of the In-Ga-Zn-O semiconductor. For example, it can contain In-Sn-Zn-O semiconductors (e.g., In2O3-SnO2-ZnO; InSnZnO). The In-Sn-Zn-O semiconductor is a ternary oxide of In (indium), Sn (tin), and Zn (zinc). Alternatively, the oxide semiconductor layer may also include In-Al-Zn-O semiconductors, In-Al-Sn-Zn-O semiconductors, Zn-O semiconductors, In-Zn-O semiconductors, Zn-Ti-O semiconductors, Cd-Ge-O semiconductors, Cd-Pb-O semiconductors, CdO (cadmium oxide), Mg-Zn-O semiconductors, In-Ga-Sn-O semiconductors, In-Ga-O semiconductors, Zr-In-Zn-O semiconductors, Hf-In-Zn-O semiconductors, Al-Ga-Zn-O semiconductors, Ga-Zn-O semiconductors, In-Ga-Zn-Sn-O semiconductors, In-W-Zn-O semiconductors, etc.

[0412] Industrial availability

[0413] The embodiments of the present invention are applicable to active matrix substrates with peripheral circuits formed on a single ground plane. Such active matrix substrates are used in various electronic devices such as liquid crystal display devices, organic electroluminescent (EL) display devices, and inorganic electroluminescent display devices, as well as imaging devices such as image sensor devices, image input devices, fingerprint reading devices, and semiconductor memories.

Claims

1. An active matrix substrate, comprising a display area including multiple pixel areas and a non-display area disposed around the display area, characterized in that, have: Substrate; and Multiple oxide semiconductor TFTs are supported on the substrate and disposed in the display area or the non-display area. Each of the multiple oxide semiconductor TFTs has an oxide semiconductor layer and a gate electrode disposed on a portion of the oxide semiconductor layer through a gate insulating layer. The aforementioned oxide semiconductor layer includes a first region covered by the aforementioned gate electrode, separated from the aforementioned gate insulating layer. The aforementioned plurality of oxide semiconductor TFTs include a first TFT and a second TFT. In the first TFT described above, at least a portion of the first region of the oxide semiconductor layer has a stacked structure comprising a high-mobility oxide semiconductor film having a relatively high mobility, and a low-mobility oxide semiconductor film disposed on the high-mobility oxide semiconductor film and having a relatively low mobility compared to the high-mobility oxide semiconductor film. In the second TFT described above, the first region of the oxide semiconductor layer comprises one of the high-mobility oxide semiconductor film and the low-mobility oxide semiconductor film over its entire range, but does not contain the other oxide semiconductor film. Each of the aforementioned oxide semiconductor TFTs also has a source electrode and a drain electrode. Each of the aforementioned plurality of oxide semiconductor TFTs has an oxide semiconductor layer comprising a first contact region and a second contact region located on both sides of the first region, wherein the first contact region is electrically connected to the source electrode and the second contact region is electrically connected to the drain electrode. At least one of the source electrode and the drain electrode of the second TFT is disposed on the substrate side of the oxide semiconductor layer of the second TFT, separated by a lower insulating layer. The first region in the second TFT described above includes the low-mobility oxide semiconductor film, but does not include the high-mobility oxide semiconductor film. At least one of the first contact region and the second contact region in the second TFT has a stacked structure including the low-mobility oxide semiconductor film and a connection layer including the high-mobility oxide semiconductor film, and the connection layer is electrically connected to the at least one electrode in the opening of the lower insulating layer.

2. The active matrix substrate according to claim 1, wherein, The first region in the second TFT includes the low-mobility oxide semiconductor film but does not include the high-mobility oxide semiconductor film.

3. The active matrix substrate according to claim 1, wherein, The first region in the second TFT includes the high-mobility oxide semiconductor film, but does not include the low-mobility oxide semiconductor film.

4. The active matrix substrate according to any one of claims 1 to 3, wherein, In the first TFT, at least a portion of the first region has the stacked structure, and the first contact region and the second contact region contain the low-mobility oxide semiconductor film but do not contain the high-mobility oxide semiconductor film.

5. The active matrix substrate according to claim 4, wherein, In the first TFT described above, the entire range of the first region of the oxide semiconductor layer has the aforementioned stacked structure.

6. The active matrix substrate according to claim 4, wherein, In the first TFT, a portion of the first region of the oxide semiconductor layer has the stacked structure described above, and another portion contains the low-mobility oxide semiconductor film described above, but does not contain the high-mobility oxide semiconductor film described above.

7. The active matrix substrate according to any one of claims 1 to 3, It also includes an interlayer insulating layer that covers the gate electrode, the gate insulating layer, and the oxide semiconductor layer in the plurality of oxide semiconductor TFTs. The source electrode and the drain electrode of each of the first TFT and the second TFT are disposed on the interlayer insulating layer.

8. The active matrix substrate according to any one of claims 1 to 3, wherein, The aforementioned active matrix substrate also includes a pixel TFT disposed in each of the plurality of pixel regions. The aforementioned pixel TFT is the second TFT mentioned above. At least one of the aforementioned electrodes is the source electrode of the second TFT. The drain electrode of the second TFT is disposed above the oxide semiconductor layer of the second TFT.

9. The active matrix substrate according to any one of claims 1 to 3, wherein, The aforementioned plurality of oxide semiconductor TFTs also include a third TFT. In the first TFT described above, the first region, the first contact region, and the second contact region include the aforementioned stacked structure. In the third TFT, at least a portion of the first region has the stacked structure, and the first contact region and the second contact region contain the low-mobility oxide semiconductor film but do not contain the high-mobility oxide semiconductor film.

10. The active matrix substrate according to any one of claims 1 to 3, wherein, Both the aforementioned low-mobility oxide semiconductor film and the aforementioned high-mobility oxide semiconductor film contain In and / or Sn. The combined atomic ratio of In and Sn relative to all metal elements in the aforementioned high-mobility oxide semiconductor film is greater than the combined atomic ratio of In and Sn relative to all metal elements in the aforementioned low-mobility oxide semiconductor film.

11. The active matrix substrate according to any one of claims 1 to 3, wherein, The high-mobility oxide semiconductor film contains Sn, while the low-mobility oxide semiconductor film does not contain Sn, or contains Sn at a lower concentration than the high-mobility oxide semiconductor film.

12. The active matrix substrate according to claim 2, wherein, The first region of the oxide semiconductor layer of the first TFT further includes, between the high-mobility oxide semiconductor film and the substrate, another oxide semiconductor film having a lower mobility than the high-mobility oxide semiconductor film. The first region of the second TFT does not contain the other oxide semiconductor films mentioned above.

13. The active matrix substrate according to claim 3, wherein, The first region of the oxide semiconductor layer of the first TFT and the second TFT further includes another oxide semiconductor film having a lower mobility than the high mobility oxide semiconductor film between the high mobility oxide semiconductor film and the substrate.

14. The active matrix substrate according to claim 2, further comprising: Pixel TFTs, which are disposed in each of the plurality of pixel regions; and Peripheral circuitry is located in the aforementioned non-display area. The aforementioned peripheral circuitry includes the aforementioned first TFT. The aforementioned pixel TFT is the second TFT mentioned above.

15. The active matrix substrate according to claim 2, It also includes gate drive circuitry and SSD circuitry configured in the aforementioned non-display area. The aforementioned SSD circuit includes the aforementioned first TFT. The gate driving circuit described above includes the second TFT.

16. The active matrix substrate according to claim 2, wherein, Each of the aforementioned pixel regions has a pixel circuit that includes a selection TFT, a driving TFT, and a capacitor element. The TFT selected above is the first TFT mentioned above. The aforementioned driving TFT is the second TFT mentioned above.

17. The active matrix substrate according to claim 2, further comprising: A pixel circuit, disposed in each of the plurality of pixel regions, and including a selection TFT, a driving TFT, and a capacitor element; and The gate driving circuit is configured in the aforementioned non-display area. The aforementioned gate driving circuit includes the aforementioned first TFT. The aforementioned driving TFT is the second TFT mentioned above.

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