A verification method for a programmable signal processing module for aerospace fiber optic gyroscope

Abstract

A verification method for a programmable signal processing module for aerospace fiber optic gyroscopes includes step 1, designing a verification circuit; step 2, verifying the signal processing unit, that is, verifying the normal implementation of the FPGA and configuration refresh function or the functional implementation of the ASIC device; step 3, verifying the LAD and the signal processing unit; step 4, verifying the HAD and the signal processing unit; step 5, verifying the HDA and the signal processing unit; step 6, verifying the HAD, the signal processing unit and the HAD; step 7, verifying the HAD, the signal processing unit, the HAD, the peripheral circuit and the peripheral optical path. Aiming at the characteristics of the fiber optic gyroscope, this method adopts a multi-level combination verification method such as the device level, the local circuit level and the product level to reliably realize the verification of a micro-sized, highly integrated programmable signal processing module for aerospace, laying an important foundation for the one-time reliable development of a micro-sized, highly integrated programmable signal processing module for aerospace.

Description

Technical Field

[0001] The invention relates to a verification method for a programmable signal processing module for an aerospace fiber optic gyroscope, in particular to a method for verifying a closed-loop control of a full-digital closed-loop fiber optic gyroscope, and belongs to the technical field of fiber optic gyroscope angular velocity measurement. Background Art

[0002] At present, the detection circuit of fiber optic gyroscope is generally implemented by full digital closed-loop detection. The closed-loop detection circuit of fiber optic gyroscope generally includes preamplifier circuit, AD converter, signal processor, DA converter, post-amplifier and other parts, with relatively more components. The size of aerospace-grade components is generally relatively large, which becomes the bottleneck of miniaturization of fiber optic gyroscope, resulting in the high size and weight of fiber optic gyroscope, which is difficult to meet the needs of deep space exploration missions such as Mars exploration and micro-satellite missions.

[0003] In response to the above problems, a design scheme of aerospace programmable signal processing module based on SiP three-dimensional packaging technology has emerged. This scheme has the characteristics of high integration, small space occupation and low power consumption, and is very suitable for the miniaturization design of aerospace products.

[0004] Since SiP tape-out is costly and has a long iteration cycle, its early principle verification is of great significance. Currently, the verification of SiP devices generally adopts a general method, which lacks specificity for fiber optic gyroscope products, which is mainly manifested in the following aspects.

[0005] (1) In general SiP designs, core FPGA / ASIC devices are generally verified at the functional level, which makes it difficult to implement functional verification under complex logic and results in insufficient coverage.

[0006] (2) When there is no special requirement, the verification of the peripheral A / D converter is generally carried out by inputting analog quantity to traverse the A / D input, and then comparing the digital quantity after the conversion to determine its functional performance. This method lacks the verification of the fiber optic gyroscope product under the means of cumulative denoising;

[0007] (3) When there are no special requirements, the verification of the peripheral D / A converter is generally done by inputting digital quantities to traverse the D / A input and comparing them with the analog quantities after the conversion to determine its functional performance. This method is limited by the accuracy of analog quantity testing and the lack of targeted dynamic performance testing. Summary of the invention

[0008] The technical problem solved by the invention is: to overcome the deficiencies of the prior art and to propose a verification method for a programmable signal processing module for an aerospace fiber optic gyroscope.

[0009] The technical solution of the present invention is:

[0010] A verification method for a programmable signal processing module for an aerospace fiber optic gyroscope, the steps are as follows:

[0011] Step 1, design the verification circuit, and complete the design of the verification circuit according to the packaged device specifications of the same die as the programmable signal processing module, the same pin connection, the same device power network and ground network segmentation, the same relative position layout and the number of PCB layers, and set the adjustment column at the LAD analog input, HAD analog input, HDA analog output, FPGA or ASIC function configuration, and reserve more than 10 lead pins for FPGA / ASIC general IO for testing. For SRAM-type FPGA devices, reserve a JTAG program download interface, and each digital interface is designed to be anti-static;

[0012] Step 2: Verify the signal processing unit, that is, verify the normal implementation of the FPGA and configuration refresh functions or the functional implementation of the ASIC device;

[0013] Step 3: Verify the LAD and signal processing unit;

[0014] Step 4: Verify HAD and signal processing unit;

[0015] Step 5: Verify the HDA and signal processing unit;

[0016] Step 6: Verify the HAD, signal processing unit and HAD;

[0017] Step 7: Verify the HAD, signal processing unit, HAD, peripheral circuits, and peripheral optical paths.

[0018] Furthermore, LAD refers to low-speed analog-to-digital conversion, which is used for telemetry acquisition; HAD refers to high-speed analog-to-digital conversion, which is used for closed-loop detection; and HDA refers to high-speed digital-to-analog conversion, which is used for closed-loop detection.

[0019] Furthermore, the signal processing unit is verified, including verification for SRAM-type FPGA devices, anti-fuse-type FPGA and ASIC devices;

[0020] Verification for SRAM-type FPGA devices includes the following steps:

[0021] (2.1) JTAG configuration function verification

[0022] Connect the downloader via a computer, connect the downloader JTAG interface to the verification board JTAG interface, download the program from the JTAG interface to the FPGA and enable the FPGA to complete the preset function, thus completing the verification of the reserved JTAG interface configuration function;

[0023] (2.2) EEPROM power-on configuration verification

[0024] The program is downloaded to the EEPROM device by connecting the downloader to the computer, and the program is read from the EEPROM device and loaded into the FPGA after power-on, and the preset functions are completed to complete the verification of the reserved EEPROM functions;

[0025] (2.3) PROM power-on configuration verification

[0026] Solder the cured PROM device to the verification board, read the program from the PROM device and load it into the FPGA, complete the preset function, and complete the verification of the reserved PROM function. The PROM reading timing must be consistent with the actual application.

[0027] (2.4) Configuration refresh function verification

[0028] Generally, the configuration refresh chip reads the program stored in the PROM, then loads it into the FPGA, completes the preset functions, and completes the verification of the configuration refresh function;

[0029] The verification of the anti-fuse FPGA or ASIC device is specifically as follows: the anti-fuse FPGA or ASIC device function verification is completed by curing the anti-fuse FPGA program and powering on the ASIC device and completing the preset functions.

[0030] Furthermore, when verifying the LAD and the signal processing unit, specifically: set the LAD operating voltage, reference voltage and peripheral circuits, and after the basic functions of the FPGA are configured, input an adjustable analog voltage to the LAD through a low-speed A / D acquisition program. The analog voltage value covers the A / D input range, and the performance is judged by acquiring the digital quantity completed by the A / D conversion. The conversion frequency is designed to be a larger frequency that is close to the operating conditions and does not exceed 80% of the derating.

[0031] Furthermore, the HAD and signal processing unit are verified, specifically: the HAD operating voltage, reference voltage and peripheral circuits are set, and after the basic functions of the FPGA are configured, an adjustable analog voltage is input to the HAD through a high-speed A / D acquisition program. The analog voltage value covers the A / D input range, and the performance is judged by acquiring the digital quantity completed by the A / D conversion. The conversion frequency is designed to be a larger frequency that is close to the operating conditions and does not exceed 80% of the derating.

[0032] Furthermore, the HDA and signal processing unit are verified, specifically: the HDA operating voltage, reference voltage and peripheral circuits are set, and after the basic functions of the FPGA are configured, variable digital quantities are input to the HDA through a high-speed D / A conversion program, and the digital quantities cover the D / A input range. The performance is judged by testing the analog quantities converted by the D / A, and the conversion frequency is designed to be a larger frequency that is close to the operating conditions and does not exceed 80% of the derating.

[0033] Furthermore, the HAD, signal processing unit and HAD are verified, specifically:

[0034] (6.1) Set the HAD and HDA operating voltages and reference voltages, and set the input values ​​reasonably according to the input voltage range Vmin to Vmax, ensuring that the input value range covers the entire input voltage range, and the input voltage step value is better than (Vmax-Vmin) / 100;

[0035] (6.2) Design a test program in FPGA, which implements HAD control, basic filtering, digital quantity transmission, HDA control, and external serial port transmission; and the control frequency is designed to be a larger frequency close to the operating condition and not exceeding 80% derating;

[0036] (6.3) The voltage value after HDA conversion is measured through the output analog terminal, and compared with the input voltage value to determine the correctness and accuracy of the result and calculate the actual error.

[0037] Furthermore, the HAD, signal processing unit, HAD, peripheral circuits and peripheral optical paths are verified, specifically:

[0038] (7.1) Set HAD, HDA operating voltage, reference voltage and peripheral circuits;

[0039] (7.2) Design the gyro working program in FPGA to complete the closed-loop control and external output of the fiber optic gyro;

[0040] (7.3) Complete the function and performance level verification of the programmable signal processing module through fiber optic gyroscope product-level functional testing.

[0041] The advantages of the present invention compared with the prior art are:

[0042] (1) This method designs dedicated test cases for device-level verification to ensure the effectiveness of functional verification of complex logic;

[0043] (2) This method uses different combinations at the local circuit level to ensure comprehensive verification of each module combination;

[0044] (3) This method adopts optical path and circuit combination verification in product-level verification, which is mainly carried out under the actual working conditions of the product, with more comprehensive test coverage and more sufficient verification adequacy;

[0045] (4) This method takes into account the characteristics of fiber optic gyroscopes and adopts a multi-level combination verification method, such as device level, local circuit level, and product level, to reliably realize the verification of micro-sized, highly integrated programmable signal processing modules for aerospace use, laying an important foundation for the one-time reliable development of micro-sized, highly integrated programmable signal processing modules for aerospace use. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] Figure 1 It is a schematic diagram of the scheme of the present invention;

[0047] Figure 2 It is a schematic diagram of the SRAM type FPGA verification solution;

[0048] Figure 3 Schematic diagram of LAD+ signal processing circuit;

[0049] Figure 4 Schematic diagram of HAD+ signal processing circuit;

[0050] Figure 5 Schematic diagram of HDA+ signal processing circuit;

[0051] Figure 6 HAD+signal processing unit+HDA verification diagram;

[0052] Figure 7 Schematic diagram of HAD+signal processing unit+HDA+peripheral circuit+peripheral optical path verification. DETAILED DESCRIPTION

[0053] The present invention designs a verification method for a micro-miniature, highly integrated programmable signal processing module for aerospace. First, the verification circuit design is completed according to the same device specifications, same pin connections, same device power network and ground network segmentation, same relative position layout and PCB layer number as the SiP circuit. The SiP is verified in the order of signal processing part (FPGA+configuration refresh chip), LAD (generally used for remote measurement acquisition)+signal processing part, HAD (generally used for high-speed A / D conversion, used for closed-loop detection)+signal processing part, HDA (generally used for high-speed D / A conversion, used for closed-loop detection)+signal processing part, HAD+signal processing part+HDA, SiP+peripheral circuit+peripheral optical path to carry out layer-by-layer verification at the local level, integrated device level and whole machine level, that is, by maximizing and optimizing the board-level design of the integrated device, a combination of local software module verification+whole machine function verification is adopted, and on the basis of ensuring the simulation of all SiP internal connections, the SiP pre-tapeline verification work is completed with high quality and high efficiency.

[0054] like Figure 1 As shown, the present invention proposes a verification method for a programmable signal processing module for an aerospace fiber optic gyroscope, comprising the following steps:

[0055] Step 1: Design verification circuit;

[0056] Step 2: Verify the signal processing unit, that is, verify the normal implementation of the FPGA and configuration refresh functions or the functional implementation of the ASIC device;

[0057] Step 3: Verify the LAD and signal processing unit;

[0058] Step 4: Verify HAD and signal processing unit;

[0059] Step 5: Verify the HDA and signal processing unit;

[0060] Step 6: Verify the HAD, signal processing unit and HAD;

[0061] Step 7: Verify the HAD, signal processing unit, HAD, peripheral circuits, and peripheral optical paths.

[0062] 1. Verify circuit design

[0063] This part is mainly used to complete the circuit design for verification. According to the principle of minimization, this part designs the same device specifications, pin connections, power supply network and ground network segmentation, relative position layout and PCB layers as the SiP device. According to actual needs, the LAD analog input, HAD analog input, HDA analog output, FPGA / ASIC function configuration (refresh, JTAG and PROM switching, etc.) are used to set the adjustment column, and the FPGA / ASIC general IO reserves more than 10 lead pins for testing to ensure that the signal input and output can be effectively completed during the test.

[0064] 2. Signal processing unit verification

[0065] The signal processing unit is generally an FPGA and a configuration refresh chip or an ASIC device, and mainly verifies the normal implementation of the FPGA and configuration refresh functions or the functional implementation of the ASIC device. It mainly includes the following verification items.

[0066] 2.1 For SRAM-type FPGA devices

[0067] (1) JTAG configuration function verification

[0068] Connect the downloader via a computer, connect the downloader JTAG interface to the verification board JTAG interface, download the program from the JTAG interface to the FPGA and enable the FPGA to complete the preset function, thus completing the verification of the reserved JTAG interface configuration function;

[0069] (2) EEPROM power-on configuration verification

[0070] The program is downloaded to the EEPROM device by connecting the downloader to the computer, and the program is read from the EEPROM device and loaded into the FPGA after power-on, and the preset functions are completed to complete the verification of the reserved EEPROM functions;

[0071] (3) PROM power-on configuration verification

[0072] Solder the cured PROM device to the verification board, read the program from the PROM device and load it into the FPGA, complete the preset function, and complete the verification of the reserved PROM function. The PROM reading timing must be consistent with the actual application.

[0073] (4) Configuration refresh function verification

[0074] Generally, the configuration refresh chip reads the program stored in the PROM, then loads it into the FPGA, completes the preset functions, and completes the verification of the configuration refresh function;

[0075] The verification of the anti-fuse FPGA or ASIC device is specifically as follows: the anti-fuse FPGA or ASIC device function verification is completed by curing the anti-fuse FPGA program and powering on the ASIC device and completing the preset functions.

[0076] 2.2 For anti-fuse FPGA and ASIC devices

[0077] The anti-fuse FPGA and ASIC device function verification is completed by pre-burning the anti-fuse FPGA and powering up the ASIC device and completing the preset functions.

[0078] 3. LAD+ signal processing unit verification

[0079] Set the LAD working voltage, reference voltage and peripheral circuits. On the premise that the basic functions of the FPGA are configured, design a dedicated low-speed A / D acquisition program to input an adjustable analog voltage to the LAD. The analog voltage value covers the A / D input range. The performance is judged by collecting the digital quantity completed by the A / D conversion. The conversion frequency is generally designed to be close to the operating conditions and not exceed 80% of the derating.

[0080] 4. HAD+ signal processing unit verification

[0081] Set the HAD working voltage, reference voltage and peripheral circuits. On the premise that the basic functions of the FPGA are configured, design a dedicated high-speed A / D acquisition program to input an adjustable analog voltage to the HAD. The analog voltage value covers the A / D input range. The performance is judged by collecting the digital quantity completed by the A / D conversion. The conversion frequency is generally designed to be close to the operating conditions and not exceed 80% of the derating.

[0082] 5. HDA+ signal processing unit verification

[0083] Set the HDA working voltage, reference voltage and peripheral circuits. On the premise that the basic functions of the FPGA are configured, design a dedicated high-speed D / A conversion program, input variable digital quantities to the HDA, and the digital quantities cover the D / A input range. Perform performance judgment by testing the digital quantities completed by the D / A conversion. The conversion frequency is generally designed to be a larger frequency close to the operating conditions and not exceeding 80% derating;

[0084] 6.HAD+Signal Processing Unit+HDA Verification

[0085] (1) Set the HAD and HDA operating voltages and reference voltages, and set the input values ​​reasonably according to the input voltage range Vmin to Vmax to ensure that the input value range covers the entire input voltage range. The input voltage step value is guaranteed to be better than (Vmax-Vmin) / 100, and the step value can be further reduced according to the actual use range.

[0086] (2) Design a test program in FPGA. The test program has HAD control function, basic filtering processing function, digital quantity transmission function, HDA control function, and external serial port transmission function. The control frequency is generally designed to be a larger frequency close to the operating condition and not exceeding 80% derating;

[0087] (3) Measure the voltage / current value after HDA conversion through the output analog terminal, compare it with the input voltage value, compare the correctness and accuracy of the result, and calculate the actual error;

[0088] 7.HAD+signal processing unit+HDA+peripheral circuit+peripheral optical path verification

[0089] (1) Set HAD, HDA operating voltage, reference voltage and peripheral circuits (op amp, etc.);

[0090] (2) Design the gyro working program in FPGA to complete the closed-loop control function and external output function of the fiber optic gyro;

[0091] (3) Complete SiP function and performance level verification through fiber optic gyroscope product-level functional testing.

[0092] According to the characteristics of fiber optic gyroscope, this method adopts multi-level combined verification methods such as device level, local circuit level, and product level to reliably realize the verification of micro-small, highly integrated programmable signal processing modules for aerospace, laying an important foundation for the one-time reliable development of micro-small, highly integrated programmable signal processing modules for aerospace.

[0093] Example

[0094] This embodiment carries out layer-by-layer verification at the local level, integrated device level, and whole machine level in the order of signal processing part (FPGA+configuration refresh chip) verification, LAD+signal processing part, HAD+signal processing part, HDA+signal processing part, HAD+signal processing part+HDA, SiP+peripheral circuit+peripheral optical path.

[0095] 1. Verify circuit design

[0096] Design the same device specifications, pin connections, power network and ground network segmentation, relative position layout and PCB layer number as the SiP device, and set the adjustment columns at the LAD analog input, HAD analog input, HDA analog output, and FPGA / ASIC function configuration (refresh, JTAG and PROM switching, etc.) according to actual needs, and reserve more than 10 lead pins for FPGA / ASIC general IO for testing, to ensure that signal input and output can be effectively completed during testing.

[0097] 2. Signal processing unit verification

[0098] The signal processing unit is generally an FPGA and a configuration refresh chip or an ASIC device, and mainly verifies the normal implementation of the FPGA and configuration refresh functions or the functional implementation of the ASIC device. It mainly includes the following verification items.

[0099] In this embodiment, the SRAM-based FPGA device BQR2V3000 is used, so relevant verification methods are used based on this device, mainly involving JTAG configuration function, EEPROM power-on configuration verification, PROM power-on configuration verification, and configuration refresh function verification. Figure 2 Shown is a schematic diagram of the SRAM type FPGA verification solution.

[0100] (1) JTAG configuration function verification

[0101] By downloading the program from the JTAG interface to the FPGA and completing the preset functions, the verification of the reserved JTAG interface configuration function is completed. The FPGA test code frequency is 40MHz and the resource occupancy rate is not less than 20%.

[0102] (2) EEPROM completes power-on configuration verification

[0103] According to the SiP design, this verification circuit uses XCF32P as the peripheral configuration EEPROM. By reading the program from the XCF32P device and loading it into the FPGA, and completing the preset functions, the verification of the reserved EEPROM function is completed. The FPGA test code frequency is 40MHz, and the resource occupancy rate is not less than 20%.

[0104] (3) PROM completes power-on configuration verification

[0105] According to the SiP design, this verification circuit uses XQR17V16 as the peripheral configuration PROM. By reading the program from the XQR17V16 device and loading it into the FPGA, and completing the preset functions, the verification of the reserved PROM function is completed. The FPGA test code frequency is 40MHz, and the resource occupancy rate is not less than 20%.

[0106] (4) Configuration refresh function verification

[0107] According to the SiP design, this verification circuit uses the BSV2 device as the configuration refresh device. By reading the program from the BSV2 device and loading it into the FPGA and completing the preset functions, the configuration refresh function is verified. The FPGA test code frequency is 40MHz, and the resource occupancy rate is not less than 20%; the BSV2 clock is not less than 10MHz.

[0108] 3. LAD+ signal processing unit verification

[0109] like Figure 3 The figure shows the schematic diagram of the LAD+ signal processing circuit. According to the SiP design, this verification circuit uses the serial AD device B128S102 as the analog quantity acquisition device, powered by +5V. Set the LAD working voltage, reference voltage and peripheral circuit. On the premise that the basic function configuration of FPGA is completed, design a dedicated low-speed A / D acquisition program, input an adjustable analog voltage (0~5V) to LAD, and the analog voltage value covers the A / D input range. The performance is judged by collecting the digital quantity completed by A / D conversion. The device is an 8-channel serial AD device with a conversion frequency designed to be 100Ksps. Then, cumulative smoothing is performed to obtain the AD acquisition digital quantity and compare it.

[0110] 4. HAD+ signal processing unit verification

[0111] like Figure 4The figure shows the schematic diagram of the HAD+ signal processing circuit. The figure shows that according to the SiP design, this verification circuit uses the parallel AD device B9243 as a closed-loop analog-to-digital conversion device. Set the HAD operating voltage, reference voltage and peripheral circuits. On the premise that the basic functions of the FPGA are configured, design a dedicated high-speed A / D acquisition program, input an adjustable analog voltage (-2.5V~2.5V) to the HAD, and the analog voltage value covers the A / D input range. The performance is judged by collecting the digital quantity completed by the A / D conversion. The conversion frequency is designed to be 2.4Mbps (80% derating), and then cumulative smoothing is carried out to obtain the AD acquisition digital quantity and compare it.

[0112] 5. HDA+ signal processing unit verification

[0113] like Figure 5 The figure shows the schematic diagram of the HDA+ signal processing circuit. According to the SiP design, this verification circuit uses the 14-bit parallel AD device B9764 as a closed-loop digital-to-analog conversion device. Set the HDA operating voltage, reference voltage and peripheral circuits. On the premise that the basic functions of the FPGA are configured, design a dedicated high-speed D / A conversion program, input a variable digital quantity (0X0000~0X3FFF) to the HDA, and the digital quantity covers the D / A input range. The performance is judged by testing the digital quantity completed by the D / A conversion. The conversion frequency is designed to be 1Mbps, and then the analog quantity is collected for comparison.

[0114] 6.HAD+Signal Processing Unit+HDA Verification

[0115] like Figure 6 The figure shows the HAD+signal processing unit+HDA verification schematic diagram. According to the SiP design, this verification circuit uses the SRAM-based FPGA device BQR2V3000, the 14-bit parallel AD device B9764 as the analog-to-digital conversion device for closed-loop detection, and the 14-bit parallel DA device B9764 as the digital-to-analog conversion device for closed-loop detection.

[0116] (1) Set the HAD and HDA operating voltages and reference voltages, and set the input values ​​reasonably according to the input voltage range of -2.5V to 2.5V, ensuring that the input value range covers the entire input voltage range and the input voltage step value is better than 50mv;

[0117] (2) Design a test program in FPGA. The test program has HAD control function, basic filtering processing function, digital quantity transmission function, HDA control function, and external serial port transmission function. The FPGA design frequency is 40 MHz, the HAD conversion frequency is 2.4 MHz, and the HDA conversion frequency is 1 Mbps.

[0118] (3) Measure the voltage / current value after HDA conversion through the output analog terminal, compare it with the HDA input voltage value, compare the correctness and accuracy of the result, and calculate the actual error;

[0119] 7.HAD+signal processing unit+HDA+peripheral circuit+peripheral optical path verification

[0120] like Figure 7 The figure shows the HAD+signal processing unit+HDA+peripheral circuit+peripheral optical path verification schematic diagram. According to the SiP design, this verification circuit uses the SRAM-based FPGA device BQR2V3000, the 14-bit parallel AD device B9764 as the analog-to-digital conversion device for closed-loop detection, and the 14-bit parallel DA device B9764 as the digital-to-analog conversion device for closed-loop detection.

[0121] (1) Set HAD, HDA operating voltage, reference voltage and peripheral circuits (op amp, etc.);

[0122] (2) Design the gyro working program in the FPGA, connect the fiber optic gyro with a 1200m long fiber ring, set the corresponding frequency division parameters, and complete the closed-loop control function and external output function of the fiber optic gyro;

[0123] (3) Complete SiP function and performance level verification through fiber optic gyroscope product-level functional testing.

Claims

1. A verification method for a programmable signal processing module for an aerospace fiber optic gyroscope, characterized in that Here are the steps: Step 1, design the verification circuit, and complete the design of the verification circuit according to the packaged device specifications of the same die as the programmable signal processing module, the same pin connection, the same device power network and ground network segmentation, the same relative position layout and the number of PCB layers, and set the adjustment column at the LAD analog input, HAD analog input, HDA analog output, FPGA or ASIC function configuration, and reserve more than 10 lead pins for FPGA / ASIC general IO for testing. For SRAM-type FPGA devices, reserve a JTAG program download interface, and each digital interface is designed to be anti-static; Step 2: Verify the signal processing unit, that is, verify the normal implementation of the FPGA and configuration refresh functions or the functional implementation of the ASIC device, specifically including verification for SRAM-type FPGA devices, and verification for anti-fuse-type FPGA and ASIC devices; Verification for SRAM-type FPGA devices includes: JTAG configuration function verification, EEPROM power-on configuration verification, PROM power-on configuration verification, and configuration refresh function verification; The verification of the anti-fuse FPGA or ASIC device is as follows: the anti-fuse FPGA is cured and the ASIC device is powered on, and the preset functions are completed, so as to complete the functional verification of the anti-fuse FPGA or ASIC device; Step 3: Verify the LAD and signal processing unit; Step 4: Verify HAD and signal processing unit; Step 5: Verify the HDA and signal processing unit; Step 6: Verify the HAD, signal processing unit and HAD; Step 7: Verify the fiber optic gyroscope and closed loop of HAD, signal processing unit, HAD, peripheral circuit and peripheral optical path, specifically: (7.1) Set HAD, HDA operating voltage, reference voltage and peripheral circuits; (7.2) Design the gyro working program in FPGA to complete the digital closed-loop control of the fiber optic gyro and its external output; (7.3) Complete the function and performance level verification of the programmable signal processing module through the fiber optic gyro product-level functional test, including zero bias stability test, random walk coefficient test, scale factor test, range test, and bandwidth test.

2. The verification method of a programmable signal processing module for aerospace fiber optic gyroscope according to claim 1, characterized in that: LAD refers to low-speed analog-to-digital conversion, which is used for remote measurement acquisition; HAD refers to high-speed analog-to-digital conversion, which is used for closed-loop detection; HDA refers to high-speed digital-to-analog conversion, which is used for closed-loop detection.

3. The verification method of a programmable signal processing module for aerospace fiber optic gyroscope according to claim 1, characterized in that: The verification for SRAM-type FPGA devices is as follows: (2.1) JTAG configuration function verification Connect the downloader via a computer, connect the downloader JTAG interface to the verification circuit board JTAG interface, download the program from the JTAG interface to the FPGA and enable the FPGA to complete the preset function, thus completing the verification of the reserved JTAG interface configuration function; (2.2) EEPROM power-on configuration verification The program is downloaded to the EEPROM device by connecting the downloader to the computer, and the program is read from the EEPROM device and loaded into the FPGA after power-on, and the preset functions are completed to complete the verification of the reserved EEPROM functions; (2.3) PROM power-on configuration verification Solder the cured PROM device to the verification circuit board, read the program from the PROM device and load it into the FPGA, complete the preset function, and complete the verification of the reserved PROM function. The PROM reading timing is consistent with the actual application. (2.4) Configuration refresh function verification The program stored in the PROM is read from the configuration refresh chip, then loaded into the FPGA, and the preset functions are completed to complete the verification of the configuration refresh function.

4. The verification method of a programmable signal processing module for aerospace fiber optic gyroscope according to claim 1, characterized in that: When verifying the LAD and signal processing unit, specifically: set the LAD operating voltage, reference voltage and peripheral circuits. After the basic functions of the FPGA are configured, input an adjustable analog voltage to the LAD through a low-speed A / D acquisition program. The analog voltage value covers the A / D input range, and the performance is judged by acquiring the digital quantity completed by the A / D conversion.

5. The verification method of a programmable signal processing module for aerospace fiber optic gyroscope according to claim 1, characterized in that: Verify the HAD and signal processing unit, specifically: set the HAD operating voltage, reference voltage and peripheral circuits, and after the basic FPGA function configuration is completed, input an adjustable analog voltage to the HAD through a high-speed A / D acquisition program. The analog voltage value covers the A / D input range, and the performance is judged by acquiring the digital quantity completed by the A / D conversion.

6. The verification method of a programmable signal processing module for aerospace fiber optic gyroscope according to claim 1, characterized in that: Verify the HDA and signal processing unit, specifically: set the HDA operating voltage, reference voltage and peripheral circuits, and after the basic FPGA function configuration is completed, input variable digital quantities to the HDA through a high-speed D / A conversion program. The digital quantities cover the D / A input range, and perform performance judgment by testing the analog quantities completed by the D / A conversion.

7. The verification method of a programmable signal processing module for aerospace fiber optic gyroscope according to claim 1, characterized in that: Verify the HAD, signal processing unit and HAD, specifically: (6.1) Set the HAD and HDA operating voltages and reference voltages, and set the input values ​​reasonably according to their input voltage range Vmin~Vmax, ensuring that the input value range covers the entire input voltage range, and the input voltage step value is guaranteed to be better than (Vmax-Vmin) / 100; (6.2) Design a test program in FPGA to implement HAD control, basic filtering, digital quantity transmission, HDA control, and external serial port transmission; (6.3) The voltage value after HDA conversion is measured through the output analog terminal, and compared with the input voltage value to determine the correctness and accuracy of the result and calculate the actual error.

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