scan driver

Abstract

A scan driver includes a stage including an input circuit that controls a voltage of a first node in response to signals at a first input terminal and a second input terminal, a first signal processing circuit that controls a voltage of a second node in response to a signal at the first input terminal and supplies a voltage of a first power supply to the second node in response to a signal at the second input terminal, a second signal processing circuit that supplies a voltage of a second power supply to the first node in response to a signal at a third input terminal and the voltage of the second node, a first output circuit that outputs the signal at the third input terminal as a first scan signal, and a second output circuit that outputs a signal at a fourth input terminal as a second scan signal at a different timing from the first scan signal.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2020-0083646, filed on July 7, 2020, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] This invention relates to a display device. More specifically, this invention relates to a display device including a scan driver. Background Technology

[0004] For example, a display device is an output device used to represent information in a visual form. A display device, such as an organic light-emitting display device, includes a data driver for supplying data signals to data lines, a scan driver for supplying scan signals to scan lines, an emission driver for supplying emission control signals to emission control lines, and pixels connected to the data lines, scan lines, and emission control lines.

[0005] Reducing the size of non-display areas, such as the bezel of a display device, can result in a larger screen without increasing the device's overall size. Therefore, various studies have been conducted to minimize non-display areas, such as the bezel of a display device. Summary of the Invention

[0006] According to an exemplary embodiment of the present invention, a scan driver is provided, comprising: a stage configured to output a scan signal, wherein the stage includes: an input circuit that controls a voltage of a first node in response to a signal supplied to a first input terminal and a signal supplied to a second input terminal; a first signal processing circuit that controls a voltage of a second node in response to a signal supplied to the first input terminal and supplies a voltage of a first power supply to the second node in response to a signal supplied to the second input terminal; a second signal processing circuit that supplies a voltage of a second power supply to the first node in response to a signal supplied to a third input terminal and a voltage of the second node; a first output circuit that outputs a signal supplied to the third input terminal as a first scan signal based on the voltage of the first node and the voltage of the second node; and a second output circuit that outputs a signal supplied to a fourth input terminal as a second scan signal based on the voltage of the first node and the voltage of the second node, wherein the second scan signal and the first scan signal are output at different times.

[0007] The signal supplied to the second input terminal can be a first clock signal, the signal supplied to the third input terminal can be a second clock signal, and the signal supplied to the fourth input terminal can be a third clock signal, and the gate-on levels of the first clock signal, the gate-on level of the second clock signal, and the gate-on level of the third clock signal can not overlap with each other.

[0008] The first output circuit can include a sixth transistor connected between the first node and a third node, wherein the sixth transistor has a gate electrode connected to the first power supply; a seventh transistor connected between the third input terminal and the first output terminal, wherein the seventh transistor has a gate electrode connected to the third node; an eighth transistor connected between the first output terminal and the second power supply, wherein the eighth transistor has a gate electrode connected to the second node; and a second capacitor connected between the third node and the first output terminal.

[0009] The second output circuit can include a ninth transistor connected between the first node and a fourth node, wherein the ninth transistor has a gate electrode connected to the first power supply; a tenth transistor connected between the fourth input terminal and a second output terminal, wherein the tenth transistor has a gate electrode connected to the fourth node; an eleventh transistor connected between the second output terminal and the second power supply, wherein the eleventh transistor has a gate electrode connected to the second node; and a third capacitor connected between the fourth node and the second output terminal.

[0010] The input circuit can include a first transistor connected between the first input terminal and the first node, wherein the first transistor has a gate electrode connected to the second input terminal.

[0011] The first signal processing circuit can include a second transistor connected between the second input terminal and the second node, wherein the second transistor has a gate electrode connected to the first node; and a third transistor connected between the first power supply and the second node, wherein the third transistor has a gate electrode connected to the second input terminal.

[0012] The second signal processing circuit can include a fourth transistor and a fifth transistor connected in series with each other between the first node and the second power supply, a gate electrode of the fourth transistor being connected to the second node, and a gate electrode of the fifth transistor being connected to the third input terminal.

[0013] The second signal processing circuit can further include a first capacitor connected between the second node and the second power supply.

[0014] The first input terminal can be supplied with a start pulse or a second scan signal output from a previous stage.

[0015] The second scan signal can be offset with respect to the first scan signal.

[0016] According to an example embodiment of the present application, there is provided a display device including: a pixel; a scan driver including stages for supplying a scan signal to the pixel through a scan line; a data driver for supplying a data signal to the pixel through a data line; and a timing controller for controlling the scan driver and the data driver, wherein at least one of the stages includes: an input circuit that controls a voltage of a first node in response to a signal supplied to a first input terminal and a signal supplied to a second input terminal; a first signal processing circuit that controls a voltage of a second node in response to the signal supplied to the first input terminal and supplies a voltage of a first power supply to the second node in response to the signal supplied to the second input terminal; a second signal processing circuit that supplies a voltage of a second power supply to the first node in response to a signal supplied to a third input terminal and the voltage of the second node; a first output circuit that outputs the signal supplied to the third input terminal as a first scan signal based on the voltage of the first node and the voltage of the second node; and a second output circuit that outputs a signal supplied to a fourth input terminal as a second scan signal based on the voltage of the first node and the voltage of the second node, and wherein the second scan signal is output at a different timing from the first scan signal.

[0017] The second input terminal can be provided with a first clock signal, the third input terminal can be provided with a second clock signal, and the fourth input terminal can be provided with a third clock signal, and a gate-on voltage level of the first clock signal, a gate-on voltage level of the second clock signal, and a gate-on voltage level of the third clock signal can not overlap with each other.

[0018] The first output circuit can include: a sixth transistor connected between the first node and a third node, wherein the sixth transistor has a gate electrode connected to the first power supply; a seventh transistor connected between the third input terminal and the first output terminal, wherein the seventh transistor has a gate electrode connected to the third node; an eighth transistor connected between the first output terminal and the second power supply, wherein the eighth transistor has a gate electrode connected to the second node; and a second capacitor connected between the third node and the first output terminal.

[0019] The second output circuit can include: a ninth transistor connected between the first node and a fourth node, wherein the ninth transistor has a gate electrode connected to the first power supply; a tenth transistor connected between the fourth input terminal and a second output terminal, wherein the tenth transistor has a gate electrode connected to the fourth node; an eleventh transistor connected between the second output terminal and the second power supply, wherein the eleventh transistor has a gate electrode connected to the second node; and a third capacitor connected between the fourth node and the second output terminal.

[0020] The input circuit can include a first transistor connected between the first input terminal and the first node, wherein the first transistor has a gate electrode connected to the second input terminal, and wherein the first signal processing circuit includes a second transistor connected between the second input terminal and the second node, wherein the second transistor has a gate electrode connected to the first node, and a third transistor connected between the first power supply and the second node, wherein the third transistor has a gate electrode connected to the second input terminal.

[0021] The second signal processing circuit can include a fourth transistor and a fifth transistor connected in series with each other between the first node and the second power supply, and a first capacitor connected between the second node and the second power supply, a gate electrode of the fourth transistor being connected to the second node, and a gate electrode of the fifth transistor being connected to the third input terminal.

[0022] The first input terminal can be supplied with a start pulse or a second scan signal output from a previous stage.

[0023] The second scan signal can be offset with respect to the first scan signal.

[0024] According to an exemplary embodiment of the present application, there is provided a scan driver including a stage including a first output circuit and a second output circuit, wherein the first output circuit includes a first transistor connected between a first node and a third node, wherein the first transistor has a gate electrode connected to a first power supply, a second transistor connected between a first clock terminal and a first output terminal, wherein the second transistor has a gate electrode connected to the third node, and a third transistor connected between the first output terminal and a second power supply, wherein the third transistor has a gate electrode connected to a second node, wherein the second output circuit includes a fourth transistor connected between the first node and a fourth node, wherein the fourth transistor has a gate electrode connected to the first power supply, a fifth transistor connected between a second clock terminal and a second output terminal, wherein the fifth transistor has a gate electrode connected to the fourth node, and a sixth transistor connected between the second output terminal and the second power supply, wherein the sixth transistor has a gate electrode connected to the second node.

[0025] The first clock terminal can be supplied with a first clock signal and the second clock terminal can be supplied with a second clock signal, wherein a low level of the first clock signal and a low level of the second clock signal can not overlap.

[0026] The first output circuit can be configured to output a first scan signal to the first output terminal at a first time, and the second output circuit can be configured to output a second scan signal to the second output terminal at a second time different from the first time.

[0027] The first scan signal and the second scan signal can be based on a voltage of the second node, which can be generated in response to the third clock signal. BRIEF DESCRIPTION OF DRAWINGS

[0028] Figure 1 is a block diagram illustrating a display apparatus according to an exemplary embodiment of the present application.

[0029] Figure 2 is a block diagram illustrating a scan driver according to an exemplary embodiment of the present application.

[0030] Figure 3 is a circuit diagram of a stage included in the scan driver of Figure 2 according to an exemplary embodiment of the present application.

[0031] Figure 4 is a timing diagram of an operation of the stage of Figure 3 according to an exemplary embodiment of the present application.

[0032] Figure 5 is a circuit diagram of a stage included in the scan driver of Figure 2 according to an exemplary embodiment of the present application.

[0033] Figure 6 is a circuit diagram of a stage included in the scan driver of Figure 2 according to an exemplary embodiment of the present application. DETAILED DESCRIPTION

[0034] Hereinafter, exemplary embodiments of the present application will be described in further detail with reference to the accompanying drawings. The same reference numerals can refer to the same elements throughout the drawings and thus the redundant description can be omitted.

[0035] Figure 1 is a block diagram illustrating a display apparatus according to an exemplary embodiment of the present application.

[0036] Referring to Figure 1 , the display apparatus 1000 can include a pixel unit 100, a scan driver 200, an emission driver 300, a data driver 400, and a timing controller 500.

[0037] The display device 1000 can display an image at various driving frequencies (or image refresh rates and screen refresh rates) depending on certain driving conditions. The driving frequency is the frequency at which a data signal is written to the driving transistor of the pixel PX. For example, the driving frequency can be referred to as a screen refresh rate or a screen play frequency, and indicates the frequency at which a display screen plays for one second. In other words, the driving frequency can be the frequency at which an image is displayed on a display screen for one second. The display device 1000 can display an image in response to various driving frequencies of 1 Hz to 120 Hz.

[0038] The pixel unit 100 can include scan lines SL1 to SLn, emission control lines EL1 to ELn, and data lines DL1 to DLm. The pixel unit 100 can include pixels PX connected to the scan lines SL1 to SLn, the emission control lines EL1 to ELn, and the data lines DL1 to DLm (here, m and n are integers greater than 1). Each of the pixels PX can include a driving transistor, a plurality of switching transistors, and at least one light emitting element. The pixels PX can receive voltages of a first driving power source VDD and a second driving power source VSS from the outside.

[0039] In an exemplary embodiment of the present application, the light emitting element can be an organic light emitting diode including an organic light emitting layer. In another exemplary embodiment of the present application, the light emitting element can be an inorganic light emitting element formed of an inorganic material.

[0040] In another exemplary embodiment of the present application, the light emitting element can be a light emitting element composed of an inorganic material and an organic material.

[0041] Further, the pixel PX can be connected to one or more scan lines SLi (i is a natural number of n or less) and emission control lines ELi corresponding to the circuit structure of the pixel. For example, Figure 1 The example pixel PX shown in FIG. 1 is connected to the i-th scan line SLi, the j-th data line DLj (j is a natural number of m or less), and the i-th emission control line ELi.

[0042] The timing controller 500 can receive an input control signal and an input image signal from an image source such as an external graphic device. The timing controller 500 generates image data RGB suitable for an operation condition of the pixel unit 100 based on the input image signal, and provides the image data RGB to the data driver 400. The timing controller 500 can generate a first control signal SCS for controlling a driving timing of the scan driver 200, a second control signal ECS for controlling a driving timing of the emission driver 300, and a third control signal DCS for controlling a driving timing of the data driver 400 based on the input control signal. The timing controller 500 can provide the first control signal SCS, the second control signal ECS, and the third control signal DCS to the scan driver 200, the emission driver 300, and the data driver 400, respectively.

[0043] The scan driver 200 can receive the first control signal SCS from the timing controller 500. The scan driver 200 can supply a scan signal to the scan lines SL1 to SLn in response to the first control signal SCS. The first control signal SCS can include a plurality of clock signals and a start pulse for the scan signal.

[0044] The scan signal can be set to a gate-on voltage (e.g., a logic low level) corresponding to a type of a transistor to which the corresponding scan signal is supplied. The transistor receiving the scan signal can be set to an on state when the scan signal is supplied. For example, the gate-on voltage of the scan signal supplied to a P-channel metal-oxide-semiconductor (PMOS) transistor can be a logic low level, and the gate-on voltage of the scan signal supplied to an N-channel metal-oxide-semiconductor (NMOS) transistor can be a logic high level. Hereinafter, the phrase "a scan signal is supplied" can mean that the scan signal is supplied at a logic level capable of turning on a transistor controlled by the scan signal.

[0045] In an exemplary embodiment of the present application, a stage included in the scan driver 200 can be connected to a plurality of scan lines. The stage can supply a scan signal to the scan lines connected thereto at different times. For example, a stage of the scan driver 200 can supply a first scan signal to a first scan line at a different time from when it supplies a second scan signal to a second scan line.

[0046] The emission driver 300 can receive the second control signal ECS from the timing controller 500. The emission driver 300 can supply an emission control signal to the emission control lines EL1 to ELn in response to the second control signal ECS. The second control signal ECS can include a plurality of clock signals and a start pulse for the emission control signal.

[0047] The emission control signal can be set to a gate-on voltage (e.g., a low voltage). The transistor receiving the emission control signal can be turned on when the emission control signal is supplied, and can be turned off otherwise. Hereinafter, the phrase "the emission control signal is supplied" can mean that the emission control signal is supplied at a logic level capable of turning on the transistor controlled by the emission control signal.

[0048] In an exemplary embodiment of the present application, the stages included in the emission driver 300 can be connected to a plurality of emission control lines. The stages can supply emission control signals to the emission control lines connected thereto at different times. For example, the stages of the emission driver 300 can supply a first emission control signal to a first emission control line at a different time from when it supplies a second emission control signal to a second emission control line.

[0049] In Figure 1 For convenience of description, each of the scan driver 200 and the emission driver 300 is shown as a single unit, but the present application is not limited thereto. According to an exemplary embodiment of the present application, the scan driver 200 can include a plurality of scan drivers that supply at least one of the scan signals of different waveforms, respectively. Further, at least a part of the scan driver 200 and the emission driver 300 can be integrated into one driving circuit or module, etc.

[0050] The data driver 400 can receive a third control signal DCS from the timing controller 500. The data driver 400 can convert the image data RGB into an analog data signal (e.g., a data voltage) in response to the third control signal DCS, and can supply the data signal to the data lines DL1 to DLm.

[0051] In an exemplary embodiment of the present application, the display apparatus 1000 can further include a power supply. The power supply can supply a voltage of a first driving power source VDD and a voltage of a second driving power source VSS for driving the pixels PX to the pixel unit 100.

[0052] Figure 2 is a block diagram showing a scan driver according to an exemplary embodiment of the present application.

[0053] In Figure 2 For convenience of description, four stages and scan signals output therefrom will be shown.

[0054] Referring to Figure 1 and Figure 2The scan driver 200 can include a plurality of stages including a first stage ST1, a second stage ST2, a third stage ST3, and a fourth stage ST4. For example, the first stage ST1 to the fourth stage ST4 can be connected to a first scan line SL1, a second scan line SL2, a third scan line SL3, a fourth scan line SL4, a fifth scan line SL5, a sixth scan line SL6, a seventh scan line SL7, and an eighth scan line SL8, respectively, and can output scan signals in response to a first clock signal CLK1, a second clock signal CLK2, and a third clock signal CLK3. The first stage ST1 to the fourth stage ST4 can be implemented with substantially the same circuit as each other.

[0055] Although the first stage ST1 to the fourth stage ST4 of the scan driver 200 are illustrated in FIG. 1A, this is merely exemplary. For example, the emission driver 300 can also have a substantially the same or similar configuration as the first stage ST1 to the fourth stage ST4 of the scan driver 200. In this case, the first stage ST1 to the fourth stage ST4 can output emission control signals. Figure 2 Figure 2 Although the first stage ST1 to the fourth stage ST4 of the scan driver 200 are illustrated in FIG. 1A, this is merely exemplary. For example, the emission driver 300 can also have a substantially the same or similar configuration as the first stage ST1 to the fourth stage ST4 of the scan driver 200. In this case, the first stage ST1 to the fourth stage ST4 can output emission control signals.

[0056] In one exemplary embodiment of the present application, each of the first stage ST1 to the fourth stage ST4 can be connected to two scan lines. For example, the first stage ST1 can be connected to a first scan line SL1 and a second scan line SL2. The first stage ST1 can supply a first scan signal S(1) to the first scan line SL1 and a second scan signal S(2) to the second scan line SL2. The first scan line SL1 can be connected to a first pixel row (e.g., a first horizontal line) of the pixel unit 100, and the second scan line SL2 can be connected to a second pixel row (e.g., a second horizontal line) of the pixel unit 100. The first scan signal S(1) and the second scan signal S(2) can have substantially the same pulse and can be output at different time points. For example, the second scan signal S(2) can be a signal in which the first scan signal S(1) is offset by a predetermined period. In other words, the second scan signal S(2) can be offset with respect to the first scan signal S(1).

[0057] Similarly, the second stage ST2 can be connected to a third scan line SL3 and a fourth scan line SL4. The second stage ST2 can supply a third scan signal S(3) to the third scan line SL3 and can supply a fourth scan signal S(4) to the fourth scan line SL4. The third stage ST3 can supply a fifth scan signal S(5) to a fifth scan line SL5 and can supply a sixth scan signal S(6) to a sixth scan line SL6. The fourth stage ST4 can supply a seventh scan signal S(7) to a seventh scan line SL7 and can supply an eighth scan signal S(8) to an eighth scan line SL8.

[0058] ​For convenience of description, the first to eighth scan signals S(1) to S(8) are arbitrarily defined, and the first to eighth scan signals S(1) to S(8) can have substantially the same pulse and can be output at different times.

[0059] Further, a connection relationship between the first to eighth scan lines SL1 to SL8 and horizontal lines (e.g., pixel rows) can be differently set according to a pixel structure and a driving method of the display device 1000. For example, the first scan line SL1 connected to the first stage ST1 can be commonly connected to a plurality of horizontal lines (or pixel rows).

[0060] Each of the first to fourth stages ST1 to ST4 can include a first input terminal 101, a second input terminal 102, a third input terminal 103, a fourth input terminal 104, a first output terminal 105, and a second output terminal 106.

[0061] The first input terminal 101 can receive a start pulse SSP or an output signal (e.g., a second scan signal S(2)) output from a previous stage of the second output terminal 106. For example, the first input terminal 101 of the first stage ST1 can receive the start pulse SSP, and the first input terminal 101 of the second stage ST2 can receive the second scan signal S(2) output from the first stage ST1.

[0062] In an exemplary embodiment of the present application, the second input terminal 102 of the k-th stage (here, k is a natural number) can receive a first clock signal CLK1, the third input terminal 103 of the k-th stage can receive a second clock signal CLK2, and the fourth input terminal 104 of the k-th stage can receive a third clock signal CLK3. On the other hand, the second input terminal 102 of the k+1-th stage can receive the third clock signal CLK3, the third input terminal 103 of the k+1-th stage can receive the first clock signal CLK1, and the fourth input terminal 104 of the k+1-th stage can receive the second clock signal CLK2. The second input terminal 102 of the k+2-th stage can receive the second clock signal CLK2, the third input terminal 103 of the k+2-th stage can receive the third clock signal CLK3, and the fourth input terminal 104 of the k+2-th stage can receive the first clock signal CLK1.

[0063] The first clock signal CLK1, the second clock signal CLK2, and the third clock signal CLK3 have the same period, and the phase of the first clock signal CLK1, the phase of the second clock signal CLK2, and the phase of the third clock signal CLK3 do not overlap with each other. In other words, the gate-on level (e.g., logic low level) of the first clock signal CLK1, the gate-on level (e.g., logic low level) of the second clock signal CLK2, and the gate-on level (e.g., logic low level) of the third clock signal CLK3 do not overlap with each other. For example, each of the second clock signal CLK2 and the third clock signal CLK3 can be set as a signal with a different time offset from the first clock signal CLK1.

[0064] Further, the first to fourth stages ST1 to ST4 receive a voltage of a first power supply VGL and a voltage of a second power supply VGH. The voltage of the first power supply VGL and the voltage of the second power supply VGH can have a direct current (DC) voltage level. The voltage of the second power supply VGH can be set to be greater than the voltage of the first power supply VGL.

[0065] The voltage of the first power supply VGL can be set to a gate-on level, and the voltage of the second power supply VGH can be set to a gate-off level. For example, when the pixel PX is constituted by a PMOS transistor, the voltage (e.g., gate-on level) of the first power supply VGL can correspond to a low level, and the voltage (e.g., gate-off level) of the second power supply VGH can correspond to a high level. However, this is merely exemplary, and the first power supply VGL and the second power supply VGH are not limited thereto. For example, the voltage of the first power supply VGL and the voltage of the second power supply VGH can be set depending on the type of transistor and the use environment of the display device 1000, and the like.

[0066] Figure 3 is a circuit diagram of a stage included in a scan driver according to an exemplary embodiment of the present application, Figure 2

[0067] Referring to Figure 2 and Figure 3 The kth stage STk (here, k is a natural number) can include an input circuit 210, a first signal processing circuit 220, a second signal processing circuit 230, and a first output circuit 240 and a second output circuit 250.

[0068] As Figure 3 ​As shown in FIG. 1, the first clock signal CLK1 is supplied to the first input terminal 101, the second clock signal CLK2 is supplied to the third input terminal 103, and the third clock signal CLK3 is supplied to the fourth input terminal 104 in the first stage ST1. However, this is exemplary only, and in the kth stage STk, the third clock signal CLK3 can be supplied to the second input terminal 102, the first clock signal CLK1 can be supplied to the third input terminal 103, and the second clock signal CLK2 can be supplied to the fourth input terminal 104. In the k+1th stage, the second clock signal CLK2 can be supplied to the second input terminal 102, the first clock signal CLK1 can be supplied to the third input terminal 103, and the third clock signal CLK3 can be supplied to the fourth input terminal 104.

[0069] In an exemplary embodiment of the present application, the start pulse SSP can be supplied to the first input terminal 101 of the first stage ST1, and the scan signal output from the second output terminal 106 of the previous stage can be supplied to the first input terminal 101 of the other stages.

[0070] Hereinafter, the kth stage STk will be referred to as the stage STk.

[0071] The input circuit 210 can control the voltage of the first node N1 in response to signals supplied to the first input terminal 101 and the second input terminal 102. In an exemplary embodiment of the present application, the input circuit 210 can include a first transistor T1.

[0072] The first transistor T1 can be connected between the first input terminal 101 and the first node N1. The first transistor T1 can include a gate electrode connected to the second input terminal 102. The first transistor T1 can be turned on when the first clock signal CLK1 has a gate-on level (e.g., a low level) to electrically connect the first input terminal 101 and the first node N1.

[0073] The first signal processing circuit 220 can control the voltage of the second node N2 in response to a signal supplied to the first input terminal 101, and can supply the voltage of the first power supply VGL to the second node N2 in response to a signal supplied to the second input terminal 102. In an exemplary embodiment of the present application, the first signal processing circuit 220 can include a second transistor T2 and a third transistor T3.

[0074] The second transistor T2 can be connected between the second input terminal 102 and the second node N2. The gate electrode of the second transistor T2 can be connected to the first node N1. The second transistor T2 can be turned on or turned off in response to the voltage of the first node N1.

[0075] In an exemplary embodiment of the present application, the second transistor T2 can include a plurality of sub-transistors connected in series to each other. Each of the sub-transistors can include a gate electrode commonly connected to the first node N1 (e.g., a dual gate structure). Accordingly, leakage of current caused by the second transistor T2 can be minimized. However, this is merely exemplary, and at least one of the other transistors and the second transistor T2 can have a dual gate structure.

[0076] The third transistor T3 can be connected between the first power terminal 107 to which a voltage of the first power supply VGL is input and the second node N2. A gate electrode of the third transistor T3 can be connected to the second input terminal 102. The third transistor T3 can be turned on when the first clock signal CLK1 is supplied to the second input terminal 102 to supply the voltage of the first power supply VGL to the second node N2.

[0077] The second signal processing circuit 230 can supply a voltage of the second power supply VGH to the first node N1 in response to a signal supplied to the third input terminal 103 and a voltage of the second node N2. In an exemplary embodiment of the present application, the second signal processing circuit 230 can include a fourth transistor T4, a fifth transistor T5, and a first capacitor C1.

[0078] The fourth transistor T4 and the fifth transistor T5 can be connected in series between the first node N1 and the second power terminal 108 to which a voltage of the second power supply VGH is supplied. A gate electrode of the fourth transistor T4 can be connected to the second node N2. A gate electrode of the fifth transistor T5 can be connected to the third input terminal 103.

[0079] The fourth transistor T4 can be turned on or turned off in response to a voltage of the second node N2.

[0080] The fifth transistor T5 can be turned on in response to a gate-on level of the second clock signal CLK2 supplied to the third input terminal 103.

[0081] The first capacitor C1 can be connected between the second node N2 and the second power terminal 108. A voltage difference between the voltage of the second node N2 and the voltage of the second power supply VGH can be charged into the first capacitor C1. The first capacitor C1 can be used to stably maintain (or hold) a low level of the second node N2 by the voltage of the second power supply VGH as a DC voltage.

[0082] The first output circuit 240 can output a signal supplied to the third input terminal 103 as an i-th scan signal S(i) (i is an integer of k or more) to the first output terminal 105 based on a voltage of the first node N1 and a voltage of the second node N2. In an exemplary embodiment of the present application, the first output circuit 240 can include a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, and a second capacitor C2.

[0083] The sixth transistor T6 can be connected between the first node N1 and a third node N3. A gate electrode of the sixth transistor T6 can be connected to the first power terminal 107 to which a voltage of the first power source VGL is supplied. Accordingly, the sixth transistor T6 can have an on state. When the voltage of the third node N3 is lowered to a value lower than the voltage of the first power source VGL through coupling (or boosting) of the second capacitor C2, the voltage of the first node N1 can be maintained relatively stable by the sixth transistor T6. For example, the voltage of the first node N1 is not lower than the voltage of the first power source VGL. Accordingly, even if a change in the voltage of the third node N3 is large, an amplitude of a drain-source voltage of the first transistor T1 can not abruptly increase, and a bias stress that can be applied to the first transistor T1 can be mitigated. Accordingly, the first transistor T1 can be protected from voltage fluctuation of the third node N3.

[0084] The seventh transistor T7 can be connected between the third input terminal 103 and the first output terminal 105. A gate electrode of the seventh transistor T7 can be connected to the third node N3. For example, the gate electrode of the seventh transistor T7 can be connected between the sixth transistor T6 and the second capacitor C2. The seventh transistor T7 can be turned on or turned off in response to the voltage of the third node N3. Here, the i-th scan signal S(i) supplied to the first output terminal 105 can be at a low level (e.g., a gate on voltage of a P-type transistor) while the seventh transistor T7 is turned on.

[0085] The eighth transistor T8 can be connected between the first output terminal 105 and the second power source VGH (e.g., the second power terminal 108). A gate electrode of the eighth transistor T8 can be connected to the second node N2. The eighth transistor T8 can be turned on or turned off based on the voltage of the second node N2. When the eighth transistor T8 is turned on, the i-th scan signal S(i) supplied to the first output terminal 105 can have a high level (e.g., a gate off voltage of a P-type transistor).

[0086] The second capacitor C2 can be connected between the third node N3 and the first output terminal 105. The second capacitor C2 can couple the voltage of the first output terminal 105 and the voltage of the third node N3. For example, the second capacitor C2 can boost the voltage of the third node N3 based on the voltage of the first output terminal 105.

[0087] The second output circuit 250 can output a signal supplied to the fourth input terminal 104 as an i+1th scan signal S(i+1) to the second output terminal 106 based on a voltage of the first node N1 and a voltage of the second node N2. In an exemplary embodiment of the present application, the second output circuit 250 can include a ninth transistor T9, a tenth transistor T10, an eleventh transistor T11, and a third capacitor C3.

[0088] The configuration and operation of the second output circuit 250 can be similar to those of the first output circuit 240.

[0089] The ninth transistor T9 can be connected between the first node N1 and a fourth node N4. For example, the ninth transistor T9 can be connected to the sixth transistor T6 (the first node N1) and the third capacitor C3. A gate electrode of the ninth transistor T9 can be connected to the first power supply VGL (e.g., the first power terminal 107). Accordingly, the ninth transistor T9 can have an on state. When a voltage of the fourth node N4 is lowered to a value lower than that of the first power supply VGL through coupling (e.g., boosting) of the third capacitor C3, a voltage of the first node N1 can be maintained relatively stable by the ninth transistor T9. Accordingly, the first transistor T1 can be protected from voltage fluctuation of the fourth node N4.

[0090] The tenth transistor T10 can be connected between the fourth input terminal 104 and the second output terminal 106. A gate electrode of the tenth transistor T10 can be connected to the fourth node N4. The tenth transistor T10 can be turned on or turned off in response to a voltage of the fourth node N4. Here, the i+1th scan signal S(i+1) supplied to the second output terminal 106 can be at a low level (e.g., a gate on voltage of a P-type transistor) while the tenth transistor T10 is turned on.

[0091] The eleventh transistor T11 can be connected between the second output terminal 106 and a second power supply VGH (e.g., the second power terminal 108). A gate electrode of the eleventh transistor T11 can be connected to the second node N2. The gate electrode of the eleventh transistor T11 can also be connected to the first capacitor C1. The eleventh transistor T11 can be turned on or turned off based on a voltage of the second node N2.

[0092] The third capacitor C3 can be connected between the fourth node N4 and the second output terminal 106. The third capacitor C3 can couple a voltage of the second output terminal 106 and a voltage of the fourth node N4.

[0093] As described above, the first output circuit 240 and the second output circuit 250 can share the first node N1 and the second node N2, and can output the i-th scan signal S(i) and the (i+1)-th scan signal S(i+1), respectively, by using a time difference of the clock signals CLK2 and CLK3 having a gate-on level supplied to the third input terminal 103 and the fourth input terminal 104. Accordingly, the stage STk can stably output the i-th scan signal S(i) and the (i+1)-th scan signal S(i+1) at different timings with the same waveform using only three clock signals CLK1, CLK2, and CLK3, and although the first output circuit 240 and the second output circuit 250 share similar configurations, the first output circuit 240 receives the second clock signal CLK2 via the third input terminal 103 and the second output circuit 250 receives the third clock signal CLK3 via the fourth input terminal 104.

[0094] Accordingly, an area occupied by the scan driver 200 in the display device 1000 can be reduced. Further, a plurality of different scan signals can be output from one stage STk with a minimum number of the first clock signal CLK1, the second clock signal CLK2, and the third clock signal CLK3 and line structures, so that manufacturing costs and power consumption of the display device 1000 can be reduced.

[0095] Figure 4 is a timing diagram illustrating an operation of a stage of Figure 3 .

[0096] Referring to Figure 1 , Figure 3 and Figure 4 , the first clock signal CLK1, the second clock signal CLK2, and the third clock signal CLK3 can be supplied at different timings. A gate-on level (e.g., a logic low level) of the first clock signal CLK1, a gate-on level (e.g., a logic low level) of the second clock signal CLK2, and a gate-on level (e.g., a logic low level) of the third clock signal CLK3 do not overlap each other.

[0097] For example, the second clock signal CLK2 can be set as a signal offset by one horizontal period from the first clock signal CLK1, and the third clock signal CLK3 can be set as a signal offset by one horizontal period from the second clock signal CLK2. The first clock signal CLK1, the second clock signal CLK2, and the third clock signal CLK3 can be sequentially activated.

[0098] The high level (or high voltage) of the start pulse SSP can correspond to the voltage of the second power source VGH, and the low level (or low voltage) of the start pulse SSP can correspond to the voltage of the first power source VGL. For example, the voltage of the first power source VGL can be about -8V, and the voltage of the second power source VGH can be about 10V. However, this is merely exemplary, and the level of the voltage of the start pulse is not limited thereto.

[0099] Further, the low level of the third node N3 can be similar to a value obtained by adding the absolute value of the threshold voltage of the sixth transistor T6 to the voltage of the first power source VGL. However, because the threshold voltage of the sixth transistor T6 is very small compared to the voltage of the first power source VGL, the low level of the third node N3, the low level of the fourth node N4, the voltage of the first power source VGL, the low level of the start pulse SSP, and the low level of the scan signal can be substantially the same as or similar to each other and will be described below.

[0100] Further, the 2-low level (for example, the voltage of the third node N3 from the third time point t3 to the fourth time point t4) can be a voltage level similar to 2*VGL-VGH.

[0101] Hereinafter, it will be described that when the first clock signal CLK1, the second clock signal CLK2, and the third clock signal CLK3 are supplied, the voltage (or the voltage of the low level, the gate-on voltage) of the first power source VGL is supplied to each of the second input terminal 102, the third input terminal 103, and the fourth input terminal 104. Further, when the first clock signal CLK1, the second clock signal CLK2, and the third clock signal CLK3 are not supplied, the voltage (or the high level voltage, the gate-off voltage) of the second power source VGH is supplied to each of the second input terminal 102, the third input terminal 103, and the fourth input terminal 104.

[0102] The i-1th scan signal S(i-1) has a high level after the second time point t2.

[0103] The i-1th scan signal S(i-1) can be supplied to the first input terminal 101 at the first time point t1, and the first clock signal CLK1 can be supplied to the second input terminal 102. In other words, between the first time point t1 and the second time point t2, the i-1th scan signal S(i-1) and the first clock signal CLK1 can be low levels.

[0104] The first transistor T1 can be turned on by the first clock signal CLK1, and the voltage of the first node N1 can be at a low level. The voltage of the third node N3 and the voltage of the fourth node N4 can be changed to low levels through the sixth transistor T6 and the ninth transistor T9 in the on state.

[0105] In addition, the second transistor T2 can be turned on in response to the voltage of the first node N1 being at a low level, and the third transistor T3 can be turned on in response to the first clock signal CLK1 being at a low level. Accordingly, the second node N2 can have a voltage at a low level.

[0106] The supply of the i-1th scan signal S(i-1) and the first clock signal CLK1 can be stopped at a second time point t2. In other words, both the i-1th scan signal S(i-1) and the first clock signal CLK1 can be transitioned to a high level at the second time point t2. Because the voltage of the first node N1 is maintained at a low level, the second transistor T2 can be in an on state at the second time point t2. Accordingly, the high level of the first clock signal CLK1 can be supplied to the second node N2, and the voltage of the second node N2 can be transitioned to a high level at the second time point t2.

[0107] The second clock signal CLK2 can be supplied to the third input terminal 103 at a third time point t3. Because the voltage of the first output terminal 105 is transitioned to a low level by the second clock signal CLK2, the voltage of the third node N3 can be transitioned to a 2-low level by the coupling of the second capacitor C2. In other words, the voltage of the third node N3 can drop even lower between the third time point t3 and a fourth time point t4. Accordingly, the seventh transistor T7 can be fully turned on so that the i-th scan signal S(i) at a low level can be output to the first output terminal 105.

[0108] The supply of the second clock signal CLK2 can be stopped at the fourth time point t4, and the voltage of the first output terminal 105 can change to a high level. Accordingly, the voltage of the third node N3 can be transitioned to a low level. The output of the i-th scan signal S(i) can be stopped at the fourth time point t4. In other words, the high level of the i-th scan signal S(i) is output at the fourth time point t4.

[0109] The third clock signal CLK3 can be supplied to the fourth input terminal 104 at a fifth time point t5. Because the voltage of the second output terminal 106 is transitioned to a low level by the third clock signal CLK3, the voltage of the fourth node N4 can be transitioned to a 2-low level by the coupling of the third capacitor C3. In other words, the voltage of the fourth node N4 can drop even lower between the fifth time point t5 and a sixth time point t6. Accordingly, the tenth transistor T10 can be fully turned on so that the i+1th scan signal S(i+1) at a low level can be output to the second output terminal 106.

[0110] The supply of the third clock signal CLK3 can be stopped at a sixth time point t6, and the voltage of the second output terminal 106 can change to a high level. Accordingly, the voltage of the fourth node N4 can transition to a low level. The output of the i+1th scan signal S(i+1) can be stopped at the sixth time point t6. In other words, the high level of the i+1th scan signal S(i+1) is output at the sixth time point t6.

[0111] As described above, the i-th scan signal S(i) can be output in synchronization with the second clock signal CLK2, and the i+1th scan signal S(i+1) can be output in synchronization with the third clock signal CLK3. For example, the low level of the i-th scan signal S(i) and the second clock signal CLK2 can overlap, and the low level of the i+1th scan signal S(i+1) and the third clock signal CLK3 can overlap.

[0112] The first clock signal CLK1 can be supplied to the second input terminal 102 again at a seventh time point t7. The first transistor T1 can be turned on in response to the first clock signal CLK1, and the voltage of the first node N1 can transition to a high level. Accordingly, the voltage of the third node N3 and the voltage of the fourth node N4 can also transition to a high level through the turned-on sixth transistor T6 and the ninth transistor T9.

[0113] Further, the third transistor T3 can be turned on in response to the first clock signal CLK1 at the seventh time point t7, and the voltage of the first power supply VGL can be supplied to the second node N2. Accordingly, the voltage of the second node N2 can transition to a low level.

[0114] The fourth transistor T4 can be turned on in response to the voltage of the second node N2 being at a low level. Because the voltage of the second power supply VGH as a DC voltage is supplied to one terminal of the first capacitor C1, the voltage of the second node N2 can be stably maintained at a low level after the seventh time point t7.

[0115] Thereafter, the second clock signal CLK2 can be supplied to the third input terminal 103 at an eighth time point t8. The fifth transistor T5 can be turned on in response to the second clock signal CLK2, and the voltage of the second power supply VGH can be supplied to the first node N1 through the fifth transistor T5 and the fourth transistor T4. In other words, after the seventh time point t7, the voltage of the second power supply VGH is periodically supplied to the first node N1 through the second clock signal CLK2, so that the voltages of the third node N3 and the fourth node N4 can be stably maintained at a high level.

[0116] As described above, stage STk can use a simple structure that shares all configurations except for the first output circuit 240 and the second output circuit 250, and only three clock signals CLK1, CLK2 and CLK3 to stably output the i-th scan signal S(i) and the i+1-th scan signal S(i+1) with the same waveform at different times.

[0117] Therefore, the area occupied by the scan driver 200 in the display device 1000, the manufacturing cost of the display device 1000, and the power consumption can be reduced.

[0118] according to Figures 1 to 4 In the exemplary embodiment of the invention shown, the scan driver 200 includes a stage STk configured to output a scan signal, wherein the stage STk includes: an input circuit 210 that controls the voltage of a first node N1 in response to a signal supplied to a first input terminal 101 and a signal supplied to a second input terminal 102; a first signal processing circuit 220 that controls the voltage of a second node N2 in response to a signal supplied to the first input terminal 101 and supplies the voltage of a first power supply VGL to the second node N2 in response to a signal supplied to the second input terminal 102; and a second signal processing circuit... Path 230, the second signal processing circuit 230 supplies the voltage of the second power supply VGH to the first node N1 in response to the signal supplied to the third input terminal 103 and the voltage of the second node N2; the first output circuit 240 outputs the signal supplied to the third input terminal 103 as the i-th scan signal S(i) based on the voltage of the first node N1 and the voltage of the second node N2; and the second output circuit 250 outputs the signal supplied to the fourth input terminal 104 as the (i+1)-th scan signal S(i+1) based on the voltage of the first node N1 and the voltage of the second node N2. The (i+1)-th scan signal S(i+1) and the i-th scan signal S(i) are output at different times.

[0119] Figure 5 It is used to illustrate exemplary embodiments of the present invention. Figure 2 The circuit diagram of the stages included in the scan driver.

[0120] exist Figure 5 In this context, the same reference numerals may be used for reference. Figure 3 The aforementioned constituent elements, and therefore, can be omitted from repeated descriptions of these constituent elements. Furthermore, Figure 5 The level STk_A can have the same Figure 3 The configuration of the STk stage is basically the same or similar, except for the configuration of the input terminal connected to the gate electrode of the fifth transistor T5.

[0121] ReferenceFigure 4 and Figure 5 The stage STk_A can include the input circuit 210, the first signal processing circuit 220, the second signal processing circuit 230, the first output circuit 240, and the second output circuit 250.

[0122] In the exemplary embodiment of the present application, the gate electrode of the fifth transistor T5 can be connected to the fourth input terminal 104. The fifth transistor T5 can be turned on in response to the third clock signal CLK3.

[0123] Because the second signal processing circuit 230 periodically supplies the voltage of the second power source VGH to the first node N1 during a period after the seventh time point t7, the gate electrode of the fifth transistor T5 can be connected to the third input terminal 103 or the fourth input terminal 104. Accordingly, after the seventh time point t7, the voltage of the second power source VGH is periodically supplied to the first node N1 by the third clock signal CLK3, so that the voltages of the third node N3 and the fourth node N4 can be stably maintained at high levels.

[0124] Figure 6 is a circuit diagram of a stage included in a scan driver of Figure 2 according to an exemplary embodiment of the present application.

[0125] In Figure 6 , the same reference numerals can be used to refer to the constituent elements described in Figure 3 , and thus, repetitive descriptions of the constituent elements can be omitted. Also, Figure 6 The stage STk_B of Figure 3 may have substantially the same or similar configuration as the stage STk of , except for the types of transistors and the voltage levels of input signals and output signals.

[0126] Figure 6 Referring to , the stage STk_B can include the input circuit 210, the first signal processing circuit 220, the second signal processing circuit 230, the first output circuit 240, and the second output circuit 250.

[0127] Figure 4 The first to eleventh transistors T1 to T11 can be n-type transistors. Accordingly, the first, second, and third clock signals CLK1, CLK2, and CLK3 can have waveforms opposite to those of

[0128] Accordingly, the i-th scan signal S(i) and the (i+1)-th scan signal S(i+1) can be supplied to the first and second nodes N1 and N2, respectively, in the same manner as Figure 4waveform output opposite to the waveform of the first output signal. Figure 6 The stage STk_B can be applied to a pixel driven by an n-type transistor, a scan driver, and a display device.

[0129] As described above, the scan driver and the display device according to the exemplary embodiments of the present application can include a stage sharing a configuration except for first and second output circuits, and have a simple structure for implementing multiple outputs of a scan signal. In addition, one stage can stably output the same waveform of a scan signal at different time instants using three clock signals.

[0130] Accordingly, it is possible to reduce an area occupied by a scan driver in a display device, manufacturing costs of a display device, and power consumption.

[0131] While the present application has been shown and described with reference to exemplary embodiments thereof, it will be understood by those skilled in the art that various changes in form and details can be made therein without departing from the spirit and scope of the present application as set forth in the appended claims.

Claims

1. A scan driver comprising: a stage configured to output a scan signal, wherein the stage comprises: an input circuit that controls a voltage of a first node in response to a signal supplied to a first input terminal and a signal supplied to a second input terminal, wherein the input circuit includes a first transistor connected between the first input terminal and the first node; a first signal processing circuit that controls a voltage of a second node in response to the signal supplied to the first input terminal and supplies a voltage of a first power supply to the second node in response to the signal supplied to the second input terminal, wherein the first signal processing circuit includes a second transistor connected between the second input terminal and the second node and a third transistor connected between the first power supply and the second node; a second signal processing circuit that supplies a voltage of a second power supply to the first node in response to a signal supplied to a third input terminal and the voltage of the second node, wherein the second signal processing circuit includes a fourth transistor and a fifth transistor connected in series to each other between the first node and the second power supply; a first output circuit that outputs the signal supplied to the third input terminal as a first scan signal based on the voltage of the first node and the voltage of the second node; and a second output circuit that outputs a signal supplied to a fourth input terminal as a second scan signal based on the voltage of the first node and the voltage of the second node, wherein the first transistor has a gate electrode connected to the second input terminal, and the first input terminal is supplied with a start pulse or the second scan signal output from a previous stage, wherein the second transistor has a gate electrode connected to the first node, wherein the third transistor has a gate electrode connected to the second input terminal, wherein the gate electrode of the fourth transistor is connected to the second node, wherein the gate electrode of the fifth transistor is connected to the third input terminal, and wherein the second scan signal and the first scan signal are output at different timings.

2. The scan driver of claim 1, wherein, The signal supplied to the second input terminal is a first clock signal, the signal supplied to the third input terminal is a second clock signal, and the signal supplied to the fourth input terminal is a third clock signal, and a gate-on voltage level of the first clock signal, a gate-on voltage level of the second clock signal, and a gate-on voltage level of the third clock signal do not overlap with each other.

3. The scan driver of claim 2, wherein, The first output circuit includes: a sixth transistor connected between the first node and a third node, wherein the sixth transistor has a gate electrode connected to the first power supply; a seventh transistor connected between the third input terminal and a first output terminal, wherein the seventh transistor has a gate electrode connected to the third node; a sixth transistor connected between the first node and a third node, wherein the sixth transistor has a gate electrode connected to the first power supply; a seventh transistor connected between the third input terminal and a first output terminal, wherein the seventh transistor has a gate electrode connected to the third node; an eighth transistor connected between the first output terminal and the second power supply, wherein the eighth transistor has a gate electrode connected to the second node; and a second capacitor connected between the third node and the first output terminal.

4. The scan driver of claim 3, wherein, The second output circuit includes: a ninth transistor connected between the first node and a fourth node, wherein the ninth transistor has a gate electrode connected to the first power supply; a tenth transistor connected between the fourth input terminal and a second output terminal, wherein the tenth transistor has a gate electrode connected to the fourth node; an eleventh transistor connected between the second output terminal and the second power supply, wherein the eleventh transistor has a gate electrode connected to the second node; and a third capacitor connected between the fourth node and the second output terminal.

5. The scan driver of claim 2, wherein, The second signal processing circuit further includes: a first capacitor connected between the second node and the second power supply.

6. The scan driver of claim 2, wherein, The second scan signal is offset with respect to the first scan signal.

7. A scan driver, comprising: a stage including an input circuit, a first signal processing circuit, a second signal processing circuit, a first output circuit, and a second output circuit, wherein the input circuit includes a first transistor connected between a first input terminal and a first node, wherein the first signal processing circuit includes a second transistor connected between a second input terminal and a second node and a third transistor connected between a first power supply and the second node, wherein the second signal processing circuit includes a fourth transistor and a fifth transistor connected in series with each other between the first node and a second power supply, wherein the first output circuit includes: a sixth transistor connected between the first node and a third node, wherein the sixth transistor has a gate electrode connected to the first power supply; a seventh transistor connected between a first clock terminal and a first output terminal, wherein the seventh transistor has a gate electrode connected to the third node; and an eighth transistor connected between the first output terminal and the second power supply, wherein the eighth transistor has a gate electrode connected to the second node, wherein the second output circuit includes: a ninth transistor connected between the first node and a fourth node, wherein the ninth transistor has a gate electrode connected to the first power supply; a tenth transistor connected between a second clock terminal and a second output terminal, wherein the tenth transistor has a gate electrode connected to the fourth node; and an eleventh transistor connected between the second output terminal and the second power supply, wherein the eleventh transistor has a gate electrode connected to the second node, wherein the first output circuit is configured to output a first scan signal to the first output terminal at a first time, and the second output circuit is configured to output a second scan signal to the second output terminal at a second time different from the first time, wherein the first transistor has a gate electrode connected to the second input terminal, and the first input terminal is supplied with a start pulse or the second scan signal output from a preceding stage, wherein the second transistor has a gate electrode connected to the first node, wherein the third transistor has a gate electrode connected to the second input terminal, wherein the gate electrode of the fourth transistor is connected to the second node, and wherein the gate electrode of the fifth transistor is connected to a third input terminal.

8. The scan driver of claim 7, wherein, the first clock terminal is supplied with a first clock signal and the second clock terminal is supplied with a second clock signal, wherein a low level of the first clock signal and a low level of the second clock signal do not overlap.

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