A display panel, manufacturing method and display device

Abstract

Embodiments of the present application disclose a display panel, a manufacturing method, and a display device. The display panel includes a gate layer including a gate, a gate insulating layer covering the gate layer, an active layer, a source-drain layer including a source and a drain, an auxiliary insulating layer covering the source-drain layer, a light-shielding metal layer including a light-shielding metal, a passivation layer covering the light-shielding metal layer, and an auxiliary connection layer including an auxiliary connection portion, where the auxiliary connection portion is used to transfer a power signal transmitted to the source or the drain; wherein the fan-out region includes a gate signal line for transmitting a gate signal disposed on the same layer as the gate, a gate insulating layer covering the gate signal line, an auxiliary insulating layer covering the gate insulating layer, a first power signal line for transmitting a power signal disposed on the same layer as the light-shielding metal, a passivation layer covering the first power signal line, and the auxiliary connection portion is electrically connected to the first power signal line through a via hole penetrating the passivation layer.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel, a manufacturing method and a display device. Background Art

[0002] In the prior art, in order to effectively reduce the left and right frames and thus achieve a narrow frame, the gate signal line and the power signal line for transmitting the power signal to the source or drain are wired in the display area and the fan-out area. Figure 1 The integrated IC3 shown or Figure 2 When the separation IC3 is placed on one side as shown, the fan-out area of the display panel will form an overlapping capacitor due to the overlap of the gate signal line and the power signal line, resulting in the display panel having problems of high power consumption and signal crosstalk. Summary of the invention

[0003] In order to solve at least one of the above problems, the first embodiment of the present application provides a display panel, including a display area, a fan-out area and a binding area. The display panel includes a plurality of layers stacked on a substrate.

[0004] A gate layer including a gate,

[0005] a gate insulating layer covering the gate layer,

[0006] Active layer,

[0007] A source-drain layer including a source electrode and a drain electrode,

[0008] an auxiliary insulating layer covering the source and drain layers,

[0009] A light-shielding metal layer including a light-shielding metal,

[0010] a passivation layer covering the light-shielding metal layer, and

[0011] An auxiliary connection layer including an auxiliary connection portion, wherein the auxiliary connection portion is used to transfer a power signal transmitted to the source or drain;

[0012] The fan-out area includes a gate signal line for transmitting a gate signal and arranged in the same layer as the gate, a gate insulating layer covering the gate signal line, an auxiliary insulating layer covering the gate insulating layer, a first power signal line for transmitting a power signal and arranged in the same layer as the light shielding layer, and a passivation layer covering the first power signal line, and the auxiliary connection portion is electrically connected to the first power signal line through a via hole penetrating the passivation layer.

[0013] In a specific embodiment, the first power supply signal line extends to the display area. One end of the auxiliary connection part is electrically connected to the source electrode or the drain electrode through a first via hole penetrating through the source-drain layer, and the other end is electrically connected to the first power supply signal line through a second via hole penetrating through the light-shielding metal layer.

[0014] In a specific embodiment, the display panel further includes a second power supply signal line and a transfer metal disposed in the display area. The second data line is disposed on the same layer as the gate electrode, and the transfer metal is disposed on the same layer as the source electrode and the drain electrode. Among them,

[0015] One end of the second data line is electrically connected to the source electrode or the drain electrode through a third via hole penetrating through the gate insulating layer, and the other end of the second data line is electrically connected to the transfer metal through a fourth via hole penetrating through the gate insulating layer;

[0016] One end of the auxiliary connection part is electrically connected to the transfer metal through a fifth via hole penetrating through the source-drain layer, and the other end is electrically connected to the first power supply signal line through a sixth via hole penetrating through the light-shielding metal layer.

[0017] In a specific embodiment, the display panel further includes a protection part disposed in the fan-out area and on the same layer as the auxiliary connection part. The orthographic projection of the protection part on the substrate covers the orthographic projection of the first data line in the fan-out area on the substrate.

[0018] In a specific embodiment, the auxiliary insulating layer is composed of an inorganic layer;

[0019] Or

[0020] The auxiliary layer includes a buffer layer, a resin layer, and an inorganic layer disposed on the source-drain layer.

[0021] In a specific embodiment, the thickness of the inorganic layer is greater than or equal to And less than or equal to

[0022] The second embodiment of the present application provides a display device, including the display panel of the first embodiment.

[0023] The third embodiment of the present application provides a manufacturing method of a display panel. The display panel includes a display area, a fan-out area, and a bonding area. The manufacturing method includes:

[0024] Forming a gate layer on the substrate. The gate layer includes a gate electrode and a gate signal line for transmitting a gate signal to the gate electrode;

[0025] Forming a gate insulating layer covering the gate layer;

[0026] forming an active layer on the gate insulating layer;

[0027] Forming source and drain electrodes on the active layer, wherein the source and drain electrodes include a source electrode and a drain electrode;

[0028] forming an auxiliary insulating layer covering the source and drain layers;

[0029] forming a light-shielding metal layer on the auxiliary insulating layer, wherein the light-shielding metal layer comprises a light-shielding metal portion and a first power signal line located in the fan-out region, wherein the first power signal line is used to transmit a power signal;

[0030] forming a passivation layer covering the light-shielding metal layer;

[0031] An auxiliary connection layer is formed on the passivation layer, the auxiliary connection layer includes an auxiliary connection part, the auxiliary connection part is used to transfer the power signal transmitted to the source or drain, and the auxiliary connection part is electrically connected to the first power signal line through a via hole penetrating the passivation layer.

[0032] In a specific embodiment, the forming of the light-shielding metal layer on the auxiliary insulating layer further comprises: the light-shielding metal layer comprises a light-shielding metal portion and a first power signal line located in the display area and the fan-out area;

[0033] The forming of the passivation layer covering the light-shielding metal layer further comprises: patterning to form a first via hole penetrating the passivation layer and the auxiliary insulating layer, and a second via hole penetrating the passivation layer;

[0034] An auxiliary connection layer is formed on the passivation layer, the auxiliary connection layer includes an auxiliary connection part, the auxiliary connection part is used to transfer the power signal transmitted to the source or drain, the auxiliary connection part is electrically connected to the first power signal line through a via hole penetrating the passivation layer, and further includes: one end of the auxiliary connection part is electrically connected to the source or drain through a first via hole penetrating to the source and drain layer, and the other end is electrically connected to the first power signal line through a second via hole penetrating to the shading metal layer.

[0035] In a specific embodiment, the forming of the gate layer on the substrate further comprises: the gate layer comprises a gate, a gate signal line transmitting a gate signal to the gate, and a second power signal line located in the display area;

[0036] The forming of source and drain electrodes on the active layer further comprises: the source and drain electrodes comprise a source electrode, a drain electrode, and a transfer metal located in the display area, one end of the second power signal line is electrically connected to the source or drain electrode through a third via hole penetrating the gate insulating layer, and the other end of the second power signal line is electrically connected to the transfer metal through a fourth via hole penetrating the gate insulating layer;

[0037] The forming of the passivation layer covering the light-shielding metal layer further comprises: patterning to form a fifth via hole penetrating the passivation layer and the auxiliary insulating layer, and a sixth via hole penetrating the passivation layer;

[0038] An auxiliary connection layer is formed on the passivation layer, the auxiliary connection layer includes an auxiliary connection part, the auxiliary connection part is used to transfer the power signal transmitted to the source or drain, the auxiliary connection part is electrically connected to the first power signal line through a via hole penetrating the passivation layer, and further includes: one end of the auxiliary connection part is electrically connected to the transfer metal through the fifth via hole, and the other end is electrically connected to the first power signal line through the sixth via hole.

[0039] In a specific embodiment, the auxiliary connection layer formed on the passivation layer further includes: the auxiliary connection layer includes an auxiliary connection part, and a protection part located in the fan-out area, and the orthographic projection of the protection part on the substrate covers the orthographic projection of the first power signal line of the fan-out area on the substrate.

[0040] The beneficial effects of this application are as follows:

[0041] In view of the existing problems, the present application develops a display panel, a manufacturing method and a display device, wherein the gate signal line of the fan-out area is arranged at the gate layer, and the power signal line is arranged from the source and drain layer to the shading metal layer and the power signal is transferred by the auxiliary connection part. While realizing the normal display function, the overlapping capacitance can be effectively reduced to achieve the purpose of reducing crosstalk and reducing power. Furthermore, a passivation layer is arranged on the shading metal layer to avoid scratches, thereby reducing the overlapping capacitance of the fan-out area without increasing the number of mask plates, and protecting the shading metal layer, which makes up for the problems existing in the prior art and has broad application prospects. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0043] Figure 1 A schematic diagram showing the existence of overlapping capacitance in the fan-out region of a display panel in the prior art;

[0044] Figure 2 A schematic diagram showing the existence of overlapping capacitance in the fan-out region of a display panel in the prior art;

[0045] Figure 3The cross-sectional film layer schematic diagram of the process flow and the fan-out area in the prior art is shown;

[0046] Figure 4a The structural schematic diagram of the display panel according to an embodiment of the present application is shown;

[0047] Figure 4b The interface schematic diagram of the auxiliary connection part connecting the power signal according to an embodiment of the present application is shown;

[0048] Figure 4c The structural schematic diagram of the display panel in the prior art is shown;

[0049] Figure 5 The wiring schematic diagram of the gate signal line, data signal line and power supply signal line according to an embodiment of the present application is shown;

[0050] Figure 6 The structural schematic diagram of the display panel when the auxiliary insulating layer is an inorganic layer according to an embodiment of the present application is shown;

[0051] Figure 7 The structural schematic diagram of the display panel when the auxiliary insulating layer is a buffer layer, a resin layer and an inorganic layer according to an embodiment of the present application is shown;

[0052] Figure 8 The flow schematic diagram of the manufacturing method of the display panel according to an embodiment of the present application is shown. Detailed implementation manners

[0053] To illustrate the present application more clearly, the present application will be further described below in conjunction with the preferred embodiments and the drawings. Similar components in the drawings are denoted by the same reference numerals. Those skilled in the art should understand that the content specifically described below is illustrative rather than restrictive, and should not be used to limit the protection scope of the present application.

[0054] In the prior art, in order to effectively reduce the left and right borders to achieve a narrow border, the gate signal line and the power supply signal line for transmitting the power signal to the source or drain are routed in the display area and the fan-out area. However, as Figure 3 shown, the power supply signal line in the fan-out area ( Figure 3 the bent line in Figure 3 ) is arranged in the source-drain layer 50, and forms an overlapping capacitance with the gate signal line ( the straight line in Figure 3 ) arranged in the gate layer 20. The dielectric material between the two plates of the overlapping capacitance is only the gate insulating layer 30, and the overlapping capacitance is relatively large, resulting in problems of high power consumption and signal crosstalk in the display panel.

[0055] To this end, an embodiment of the present application provides a display panel, including a display area, a fan-out area, and a bonding area, comprising a gate layer including a gate sequentially stacked on a substrate, a gate insulating layer covering the gate layer, an active layer, a source-drain layer including a source and a drain, an auxiliary insulating layer covering the source-drain layer, a light-shielding metal layer including a light-shielding metal, a passivation layer covering the light-shielding metal layer, and an auxiliary connection layer including an auxiliary connection portion for transferring a power signal transmitted to the source or the drain; wherein

[0056] The fan-out area includes a gate signal line for transmitting a gate signal provided on the same layer as the gate, a gate insulating layer covering the gate signal line, an auxiliary insulating layer covering the gate insulating layer, a first power signal line for transmitting a power signal provided on the same layer as the light-shielding metal, and a passivation layer covering the first power signal line. The auxiliary connection portion is electrically connected to the first power signal line through a via penetrating the passivation layer. In this embodiment, by arranging the power signal line from the source-drain layer to the light-shielding metal layer and using the auxiliary connection portion to transfer the power signal, while realizing the normal display function, the overlapping capacitance is effectively reduced to achieve the purpose of reducing crosstalk and power consumption. Further, a passivation layer is provided on the light-shielding metal layer to avoid scratching, thereby reducing the overlapping capacitance of the fan-out area without increasing the number of mask plates and protecting the light-shielding metal layer, making up for the problems existing in the prior art and having a wide application prospect.

[0057] In a specific embodiment, as Figure 1 and Figure 2 shown, the display panel includes a display area 1 provided with pixel units arranged in an array, a bonding area 3 including discrete ICs and integrated ICs, and a fan-out area 2 located between the display area and the bonding area.

[0058] Specifically, as Figure 4a shown, it includes a gate layer 20 including a gate sequentially stacked on a substrate 10, a gate insulating layer 30 covering the gate layer, an active layer 40, a source-drain layer 50 including a source and a drain, an auxiliary insulating layer 60 covering the source-drain layer 50, a light-shielding metal layer 70 including a light-shielding metal, a passivation layer 80 covering the light-shielding metal layer 70, and an auxiliary connection layer 90 including an auxiliary connection portion for transferring a power signal transmitted to the source or the drain.

[0059] In this embodiment, the first power signal line extends to the display area, as Figure 4bThe figure shows a cross-sectional view of the auxiliary connection portion 90 transferring a power signal. One end of the auxiliary connection portion 90 is electrically connected to the source or drain 50 through a first via 900 penetrating through to the source-drain layer, and the other end is electrically connected to the first power signal line 70 through a second via 902 penetrating through to the light-shielding metal layer. The first power signal line 70 is disposed on the same layer as the light-shielding metal.

[0060] It should be noted that during the manufacturing process, the auxiliary insulating layer and the passivation layer are deposited in different steps, and then exposed and etched using a single mask. Specifically, an auxiliary insulating layer is deposited on the source or drain 50, a light-shielding metal material layer is formed on the auxiliary insulating layer, the light-shielding metal material layer is patterned to form a light-shielding metal layer, a passivation layer covering the light-shielding metal layer and the exposed auxiliary insulating layer is formed, and the passivation layer and the auxiliary insulating layer are exposed and etched using a single mask, as Figure 4b The first via 900 is formed by etching the passivation layer 80 and the auxiliary insulating layer 60 to expose the source-drain layer 50, as Figure 4b The second via 902 is formed by etching the passivation layer 80 to expose the first power signal line 70.

[0061] As Figure 4c The figure shows a display panel of the prior art. During the manufacturing process, a gate layer 120, a gate insulating layer 130, an active layer 140, a source-drain layer 150 including a source and a drain, an auxiliary insulating layer 160 covering the source-drain layer 150, a light-shielding metal layer 170 including a light-shielding metal, and a protective layer 190 covering the light-shielding metal layer 170 need to be fabricated on a substrate 110, and a total of 7 masks are required. In this embodiment, as Figure 4a shown, compared with the manufacturing process of the prior art, a passivation layer 80 is added. However, since the auxiliary insulating layer and the passivation layer are exposed and etched using the same mask, no additional mask is added, that is, no additional mask is added on the basis of the original manufacturing process of the display panel; at the same time, while setting the power signal line on the light-shielding metal layer to reduce the overlap capacitance, the overlap capacitance is further reduced by adding a passivation layer.

[0062] It should be noted that the light-shielding metal is used to prevent leakage current from being generated in the TFTs within the pixels in the display area under light, thereby affecting the display characteristics. Among them, the light-shielding metal is a metal film layer made of materials such as aluminum or molybdenum.

[0063] In other words, the first power signal line is disposed on the light-shielding metal layer in both the display area and the fan-out area. For the fan-out area, an overlap capacitance is formed between the first power signal line disposed on the light-shielding metal layer and the gate signal line disposed on the gate layer.

[0064] According to the capacitance calculation formula:

[0065]

[0066] Wherein, ε is the dielectric constant of the medium (relative dielectric constant), k is the electrostatic constant, with the unit of Nm / C, for example, k = 8.9880×10, S is the facing area of the two plates, and d is the perpendicular distance between the two plates. Therefore, by setting the gate signal line in the fan-out area on the gate layer and the power supply signal line on the light-shielding metal layer, the distance between the two plates of the overlapping capacitor and the dielectric material are effectively increased, thereby alleviating the crosstalk problem and power consumption problem caused by the overlapping capacitor.

[0067] In this embodiment, the first power supply signal line disposed on the light-shielding metal layer, the auxiliary connection portion for transferring the power supply signal, and the passivation layer disposed on the light-shielding metal can reduce the overlapping capacitor and prevent the power supply signal line from being scratched on the basis of realizing the normal display function, which has practical application value.

[0068] Considering that the first power supply signal line disposed on the light-shielding metal layer in the display area affects the area of the pixel electrode or the light-emitting aperture area, in an alternative embodiment, the display panel further includes a second power supply signal line and a transfer metal disposed in the display area, the second power supply signal line is disposed on the same layer as the gate, and the transfer metal is disposed on the same layer as the source and drain, wherein,

[0069] One end of the second power supply signal line is electrically connected to the source or drain through a third via hole penetrating the gate insulating layer, and the other end of the second power supply signal line is electrically connected to the transfer metal through a fourth via hole penetrating the gate insulating layer;

[0070] One end of the auxiliary connection portion is electrically connected to the transfer metal through a fifth via hole penetrating to the source-drain layer, and the other end is electrically connected to the first power supply signal line through a sixth via hole penetrating to the light-shielding metal layer.

[0071] In this embodiment, in the display area, the second power supply signal line for transmitting the power supply signal is disposed on the gate layer. At a position in the display area close to the fan-out area, the power supply signal is then transmitted to the transfer metal located in the source-drain layer, and then the power supply signal is transferred to the first power supply signal line disposed in the fan-out area by using the auxiliary connection portion, that is, one end of the auxiliary connection portion is electrically connected to the transfer metal, and the other end is electrically connected to the first power supply signal line disposed on the same layer as the light-shielding metal, thereby increasing the distance between the two plates of the capacitor and the dielectric material, and reducing the overlapping capacitor in the fan-out area. In other words, in this embodiment, the power supply signal line for transmitting the power supply signal to the source or drain is routed on the gate layer (i.e., the second power supply signal line) in the display area and on the light-shielding metal layer (i.e., the first power supply signal line) in the fan-out area. The second power supply signal line is transferred through the transfer metal disposed in the source-drain layer and is transferred to the first power supply signal line through the auxiliary connection portion.

[0072] Specifically, asFigure 5 As shown, the display area includes data signal lines 500 located in the source-drain layer and arranged horizontally, gate signal lines 502 located in the gate layer and arranged vertically, and second power signal lines 504 located in the gate layer and arranged vertically for transmitting power signals to the source or drain. Among them, the gate signal lines 502 are used to transmit gate signals to the gates of driving transistors, the data signal lines 500 are used to transmit data signals to one of the source or drain of the driving transistors, and the power signal lines are used to transmit power signals to the other of the source or drain of the driving transistors. The writing of data signals is achieved through vias 506 provided on the gate insulating layer.

[0073] Moreover, at the position where the display area is close to the fan-out area, vias are used to connect the second power signal lines provided on the gate layer to the transfer metal provided on the source-drain layer, as Figure 4b shown. Among them, the metal on the source-drain layer is the transfer metal rather than the source or drain, so that the power signal transmitted by the second power signal line is transferred to the first power signal line in the fan-out area through the auxiliary connection part. The specific implementation manner is the same as that of the foregoing embodiments and will not be elaborated herein.

[0074] In this embodiment, through the second power signal lines provided on the gate layer in the display area, the first power signal lines provided on the light-shielding metal layer, the transfer metal provided on the source-drain layer and the auxiliary connection part for transferring power signals, and the passivation layer provided on the light-shielding metal, the overlapping capacitance can be reduced and the power signal lines can be prevented from being scratched on the basis of realizing the normal display function, which has practical application value.

[0075] It should be noted that the scanning form of the gate signal lines in this embodiment is not limited, and it can be row scanning or column scanning.

[0076] In a specific embodiment, as Figure 6 shown, the auxiliary insulating layer 60 is only composed of an inorganic layer 600. Among them, the thickness of the inorganic layer 600 is inversely proportional to the capacitance value, and the thickness of the inorganic layer is greater than or equal to and less than or equal to

[0077] For example, when the area between the capacitor plates is 30000 μm 2 , the overlapping capacitance formed by the power signal lines in the fan-out area in the prior art and the gate signal lines in the gate layer is 4.85 Pf; in this embodiment, when the thickness of the inorganic layer 600 is , the overlapping capacitance is 2.44 Pf; by comparison, the overlapping capacitance in this embodiment is reduced by 50% compared with the overlapping capacitance in the prior art. Further, when the thickness of the inorganic layer 600 is When the overlapping capacitance is 1.81 pF, the overlapping capacitance of this embodiment is reduced by 63% compared with the overlapping capacitance of the prior art.

[0078] As Figure 6 shown, in the existing manufacturing process, including 7 mask plates for manufacturing the gate 20, gate insulating layer 30, active layer 40, source / drain layer 50, light-shielding metal layer 70, passivation layer 80 and auxiliary connection part 90, on the basis of not increasing the mask Mask, this embodiment further changes the dielectric material between the two plates of the overlapping capacitance from the gate insulating layer 30 to the gate insulating layer 30 and the inorganic layer 600, thereby further reducing the overlapping capacitance of the fan-out region.

[0079] Considering that when the display panel is large-sized, its bonding area is large. Therefore, in an alternative embodiment, as Figure 7 shown, the auxiliary insulating layer 60 includes a buffer layer 604, a resin layer 602 and an inorganic layer 600 provided on the source / drain layer 50, wherein the resin layer is a Resin resin material, the resin layer is thick and has a small dielectric constant. Using the auxiliary insulating layer including the resin layer can further reduce the overlapping capacitance of the fan-out region of the display panel in this embodiment. Similarly, when the area between the plates of the capacitor is 30000 μm 2 , the overlapping capacitance of this embodiment is 0.25 pF, which is reduced by 95% compared with the overlapping capacitance of the prior art.

[0080] It should be noted that since the adhesion between the source / drain metal and the resin layer resin is poor, the auxiliary insulating layer further includes a buffer layer 604.

[0081] Specifically, as Figure 7 shown, the gate signal line in the fan-out region is arranged on the gate layer 20, and the power signal line is arranged on the light-shielding metal layer 70. On the basis of not increasing the mask Mask, the dielectric material between the two plates of the formed overlapping capacitance changes from the gate insulating layer 30 to the gate insulating layer 30, the buffer layer 604, the resin layer 602 and the inorganic layer 600, and the overlapping capacitance of the fan-out region is further reduced.

[0082] It should be noted that considering that the protection of the first power signal line by the passivation layer 80 provided on the light-shielding metal layer is limited, in order to further improve the scratch resistance of the display panel, an ITO protection part is arranged on the power signal line in the fan-out region, that is, the display panel further includes a protection part arranged in the fan-out region and arranged on the same layer as the auxiliary connection part, and the orthographic projection of the protection part on the substrate covers the orthographic projection of the first power signal line in the fan-out region on the substrate.

[0083] In this embodiment, through the protection part covering the first power signal line, the protection effect is further enhanced. For example, it can prevent the scratch risk brought by hard metals such as knives.

[0084] Another embodiment of the present application provides a display device, including the display panel described in the foregoing embodiment. The display device can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, or a navigator.

[0085] Another embodiment of the present application provides a method for manufacturing the display panel described in the foregoing embodiment. The display panel includes a display area, a fan-out area, and a bonding area, as Figure 8 shown. The method includes:

[0086] S10. Form a gate layer on a substrate. The gate layer includes a gate and a gate signal line for transmitting a gate signal to the gate.

[0087] S20. Form a gate insulating layer covering the gate layer.

[0088] S30. Form an active layer on the gate insulating layer.

[0089] S40. Form source and drain electrodes on the active layer. The source and drain electrodes include a source electrode and a drain electrode.

[0090] S50. Form an auxiliary insulating layer covering the source-drain layer.

[0091] S60. Form a light-shielding metal layer on the auxiliary insulating layer. The light-shielding metal layer includes a light-shielding metal portion and a first power signal line located in the fan-out area. The first power signal line is used for transmitting a power signal.

[0092] S70. Form a passivation layer covering the light-shielding metal layer.

[0093] S80. Form an auxiliary connection layer on the passivation layer. The auxiliary connection layer includes an auxiliary connection portion. The auxiliary connection portion is used for relaying the power signal transmitted to the source electrode or the drain electrode. The auxiliary connection portion is electrically connected to the first power signal line through a via hole penetrating the passivation layer.

[0094] In this embodiment, by arranging the first power signal line from the source-drain layer to the light-shielding metal layer and using the auxiliary connection portion to connect the power signal, while realizing the normal display function, the effective overlapping capacitance can be reduced to achieve the purpose of reducing crosstalk and power consumption. Further, a passivation layer is provided on the light-shielding metal layer to avoid scratching, thereby reducing the overlapping capacitance of the fan-out area without increasing the number of mask plates and protecting the light-shielding metal layer, making up for the problems existing in the prior art and having a wide application prospect.

[0095] In a specific embodiment, forming the light-shielding metal layer on the auxiliary insulating layer further includes: the light-shielding metal layer includes a light-shielding metal portion and a first power supply signal line located in the display area and the fan-out area; forming the passivation layer covering the light-shielding metal layer further includes: patterning to form a first via hole penetrating through the passivation layer and the auxiliary insulating layer, and a second via hole penetrating through the passivation layer;

[0096] Forming the auxiliary connection layer on the passivation layer, the auxiliary connection layer includes an auxiliary connection portion, and the auxiliary connection portion is used for transferring the power supply signal transmitted to the source electrode or the drain electrode. The auxiliary connection portion is electrically connected to the first power supply signal line through a via hole penetrating through the passivation layer further includes: one end of the auxiliary connection portion is electrically connected to the source electrode or the drain electrode through a first via hole penetrating through to the source-drain layer, and the other end is electrically connected to the first power supply signal line through a second via hole penetrating through to the light-shielding metal layer.

[0097] That is to say, one end of the auxiliary connection portion is electrically connected to the source electrode or the drain electrode, and the other end is electrically connected to the first power supply signal line arranged on the same layer as the light-shielding metal. That is, the first power supply signal line is arranged on the light-shielding metal layer in both the display area and the fan-out area, so as to increase the distance between the two capacitor plates and the dielectric material, and the overlapping capacitance in the fan-out area can be reduced. For the specific implementation manners, please refer to the foregoing embodiments and will not be elaborated herein.

[0098] Considering that the first power supply signal line arranged on the light-shielding metal layer in the display area affects the area of the light-emitting aperture region, in an alternative example, forming the gate layer on the substrate further includes: the gate layer includes a gate, a gate signal line for transmitting a gate signal to the gate, and a second power supply signal line located in the display area;

[0099] Forming the source-drain electrodes on the active layer further includes: the source-drain electrodes include a source electrode, a drain electrode, and a transfer metal located in the display area;

[0100] One end of the second power supply signal line is electrically connected to the source electrode or the drain electrode through a third via hole penetrating through the gate insulating layer, and the other end of the second power supply signal line is electrically connected to the transfer metal through a fourth via hole penetrating through the gate insulating layer;

[0101] Forming the passivation layer covering the light-shielding metal layer further includes: patterning to form a fifth via hole penetrating through the passivation layer and the auxiliary insulating layer, and a sixth via hole penetrating through the passivation layer;

[0102] An auxiliary connection layer is formed on the passivation layer. The auxiliary connection layer includes an auxiliary connection portion which is used for relaying a power signal transmitted to the source electrode or the drain electrode. The further inclusion that the auxiliary connection portion is electrically connected to the first power signal line through a via hole penetrating the passivation layer is: one end of the auxiliary connection portion is electrically connected to the relay metal through the fifth via hole, and the other end is electrically connected to the first power signal line through the sixth via hole.

[0103] That is to say, the second power signal line in the display area is arranged in the gate layer. The power signal is transmitted to the relay metal of the source-drain layer at a position in the display area close to the fan-out area, and then the auxiliary connection portion is used to relay the power signal to the first power signal line arranged in the fan-out area. That is, one end of the auxiliary connection portion is electrically connected to the relay metal, and the other end is electrically connected to the first power signal line arranged in the same layer as the light-shielding metal, so as to increase the distance between the two capacitor plates and the dielectric material, and the overlapping capacitance in the fan-out area can be reduced. For the specific implementation manners, refer to the foregoing embodiments and will not be elaborated herein.

[0104] In order to further improve the scratch resistance of the display panel, the formation of the auxiliary connection layer on the passivation layer further includes: the auxiliary connection layer includes an auxiliary connection portion and a protection portion located in the fan-out area, and the orthographic projection of the protection portion on the substrate covers the orthographic projection of the first power signal line in the fan-out area on the substrate.

[0105] It should be noted that the foregoing embodiments and the accompanying beneficial effects are equally applicable to this embodiment. Therefore, the same parts will not be elaborated.

[0106] It should also be noted that the terms "on...", "formed on...", and "arranged on..." described herein may mean that one layer is directly formed or arranged on another layer, or may mean that one layer is indirectly formed or arranged on another layer, that is, there are other layers between the two layers. In this article, unless otherwise specified, the term "located in the same layer" means that two layers, components, members, elements, or parts can be formed by the same lithography process, and these two layers, components, members, elements, or parts are generally formed of the same material. In this article, unless otherwise specified, the expression "lithography process" generally includes steps such as coating of photoresist, exposure, development, etching, and stripping of photoresist. The expression "one lithography process" means a process of forming a patterned layer, component, member, etc. using a mask.

[0107] Obviously, the above embodiments of the present application are merely examples for clearly illustrating the present application, rather than limitations on the implementation manners of the present application. For those of ordinary skill in the art, other different forms of changes or modifications can be made based on the above description. It is impossible to enumerate all the implementation manners here. Any obvious changes or modifications derived from the technical solutions of the present application still fall within the protection scope of the present application.

Claims

1. A display panel, comprising a display area, a fan-out area, and a bonding area, characterized in that Comprising, sequentially stacked on a substrate, a gate layer including a gate, a gate insulating layer covering the gate layer, an active layer, a source-drain layer including a source and a drain, an auxiliary insulating layer covering the source-drain layer, a light-shielding metal layer including a light-shielding metal, a passivation layer covering the light-shielding metal layer, and an auxiliary connection layer including an auxiliary connection portion for relaying a power signal transmitted to the source or the drain; wherein the fan-out region includes a gate signal line for transmitting a gate signal disposed on the same layer as the gate, a gate insulating layer covering the gate signal line, an auxiliary insulating layer covering the gate insulating layer, a first power signal line for transmitting a power signal disposed on the same layer as the light-shielding metal, and a passivation layer covering the first power signal line, and the auxiliary connection portion is electrically connected to the first power signal line through a via hole penetrating the passivation layer.

2. The display panel according to claim 1, wherein The first power signal line extends to the display region, one end of the auxiliary connection portion is electrically connected to the source or the drain through a first via hole penetrating to the source-drain layer, and the other end is electrically connected to the first power signal line through a second via hole penetrating to the light-shielding metal layer.

3. The display panel according to claim 1, wherein The display panel further includes a second power signal line and a relay metal disposed in the display region, the second power signal line is disposed on the same layer as the gate, and the relay metal is disposed on the same layer as the source and the drain. Among them, one end of the second power signal line is electrically connected to the source or the drain through a third via hole penetrating the gate insulating layer, and the other end of the second power signal line is electrically connected to the relay metal through a fourth via hole penetrating the gate insulating layer; one end of the auxiliary connection portion is electrically connected to the relay metal through a fifth via hole penetrating to the source-drain layer, and the other end is electrically connected to the first power signal line through a sixth via hole penetrating to the light-shielding metal layer.

4. The display panel according to any one of claims 1 to 3, characterized in that The display panel further includes a protection portion disposed in the fan-out region and on the same layer as the auxiliary connection portion, and a positive projection of the protection portion on the substrate covers a positive projection of the first power signal line of the fan-out region on the substrate.

5. The display panel according to any one of claims 1 to 3, wherein the auxiliary insulating layer is composed of an inorganic layer; or the auxiliary insulating layer includes a buffer layer, a resin layer, and an inorganic layer disposed on the source-drain layer.

6. The display panel according to claim 5, wherein The thickness of the inorganic layer is greater than or equal to 3000 Å and less than or equal to 6500 Å.

7. A display device, characterized in that, Including the display panel according to any one of claims 1-6.

8. A manufacturing method of a display panel as described in any one of claims 1-6, the display panel including a display area, a fan-out area, and a bonding area, characterized in that, Including: forming a gate layer on a substrate, the gate layer including a gate and a gate signal line for transmitting a gate signal to the gate; forming a gate insulating layer covering the gate layer; forming an active layer on the gate insulating layer; forming a source-drain on the active layer, the source-drain including a source and a drain; forming an auxiliary insulating layer covering the source-drain layer; forming a light-shielding metal layer on the auxiliary insulating layer, the light-shielding metal layer including a light-shielding metal portion and a first power signal line located in the fan-out region, the first power signal line being used for transmitting a power signal; forming a passivation layer covering the light-shielding metal layer; An auxiliary connection layer is formed on the passivation layer. The auxiliary connection layer includes an auxiliary connection portion, and the auxiliary connection portion is used for relaying a power signal transmitted to the source electrode or the drain electrode. The auxiliary connection portion is electrically connected to the first power signal line through a via hole penetrating the passivation layer.

9. The manufacturing method according to claim 8, wherein forming the light-shielding metal layer on the auxiliary insulating layer further includes: the light-shielding metal layer includes a light-shielding metal portion and a first power signal line located in the display area and the fan-out area; forming the passivation layer covering the light-shielding metal layer further includes: patterning to form a first via hole penetrating the passivation layer and the auxiliary insulating layer, and a second via hole penetrating the passivation layer; forming the auxiliary connection layer on the passivation layer, the auxiliary connection layer includes an auxiliary connection portion, the auxiliary connection portion is used for relaying a power signal transmitted to the source electrode or the drain electrode, and the auxiliary connection portion is electrically connected to the first power signal line through a via hole penetrating the passivation layer further includes: one end of the auxiliary connection portion is electrically connected to the source electrode or the drain electrode through a first via hole penetrating to the source-drain layer, and the other end is electrically connected to the first power signal line through a second via hole penetrating to the light-shielding metal layer.

10. The manufacturing method according to claim 8, wherein forming the gate layer on the substrate further includes: the gate layer includes a gate, a gate signal line for transmitting a gate signal to the gate, and a second power signal line located in the display area; forming the source-drain electrode on the active layer further includes: the source-drain electrode includes a source electrode, a drain electrode, and a relay metal located in the display area. One end of the second power signal line is electrically connected to the source electrode or the drain electrode through a third via hole penetrating the gate insulating layer, and the other end of the second power signal line is electrically connected to the relay metal through a fourth via hole penetrating the gate insulating layer; forming the passivation layer covering the light-shielding metal layer further includes: patterning to form a fifth via hole penetrating the passivation layer and the auxiliary insulating layer, and a sixth via hole penetrating the passivation layer; forming the auxiliary connection layer on the passivation layer, the auxiliary connection layer includes an auxiliary connection portion, the auxiliary connection portion is used for relaying a power signal transmitted to the source electrode or the drain electrode, and the auxiliary connection portion is electrically connected to the first power signal line through a via hole penetrating the passivation layer further includes: one end of the auxiliary connection portion is electrically connected to the relay metal through the fifth via hole, and the other end is electrically connected to the first power signal line through the sixth via hole.

11. The manufacturing method according to any one of claims 8 to 10, characterized in that, forming the auxiliary connection layer on the passivation layer further includes: the auxiliary connection layer includes an auxiliary connection portion and a protection portion located in the fan-out area, and the orthographic projection of the protection portion on the substrate covers the orthographic projection of the first power signal line in the fan-out area on the substrate.

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