Interface circuit and interface device

Abstract

An interface circuit includes a first switching element connected to a first power supply node and an output node and controlled by a first input signal, a second switching element connected to a second power supply node and the output node and controlled by a second input signal, a first resistor connected between the first power supply node and the first switching element, a second resistor connected between the second power supply node and the second switching element, a first capacitor connected between the first resistor and the first switching element and charged and discharged by a first control signal, a second capacitor connected between the second resistor and the second switching element and charged and discharged by a second control signal, and a buffer circuit configured to output the first control signal and the second control signal and connected to a third power supply node through a first variable resistor and to a fourth power supply node through a second variable resistor.

Description

[0001] Cross-reference to related applications

[0002] This application claims the benefit of priority to Korean Patent Application No. 10-2020-0084787, filed with the Korean Intellectual Property Office on July 9, 2020, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] This disclosure relates to interface circuits and interface devices. Background Technology

[0004] Semiconductor devices within electronic devices can exchange data with each other via interface circuits. As the data capacity processed by electronic devices increases, interface circuits capable of providing high-speed communication between semiconductor devices have been developed. Furthermore, with the increasing number and types of semiconductor devices included in electronic devices, various methods have been provided to improve the operation of interface circuits. Summary of the Invention

[0005] Example embodiments provide an interface circuit and an interface device that can adjust the slewing rate of the input signal by taking into account the characteristics of the channel used for communication between semiconductor devices, in order to improve communication performance and signal eye margin.

[0006] According to an example embodiment, an interface circuit includes: a first switching element connected to a first power node and an output node and controlled by a first input signal, the first power node providing a first power supply voltage and the output node sending an output signal; a second switching element connected to a second power node and the output node and controlled by a second input signal different from the first input signal, the second power node providing a second power supply voltage lower than the first power supply voltage; a first resistor connected between the first power node and the first switching element; a second resistor connected between the second power node and the second switching element; a first capacitor connected between the first resistor and the first switching element and charged and discharged by a first control signal; a second capacitor connected between the second resistor and the second switching element and charged and discharged by a second control signal; and a buffer circuit configured to output the first control signal and the second control signal, and connected to a third power node via a first variable resistor and connected to a fourth power node via a second variable resistor, the third power node providing a third power supply voltage and the fourth power node providing a fourth power supply voltage lower than the third power supply voltage.

[0007] According to an example embodiment, an interface device includes: a plurality of interface circuits, each interface circuit including a first switching element and a second switching element connected in series with each other, a first capacitor connected between the first switching element and a first power node, a second capacitor connected between the second switching element and a second power node, and a buffer configured to charge and discharge the first capacitor and the second capacitor; and a controller configured to control the first switching element and the second switching element to determine an output signal of each of the plurality of interface circuits, and configured to adjust the slewing rate of the control signal output to the first capacitor and the second capacitor to determine the slewing rate of the output signal.

[0008] According to an example embodiment, an interface circuit includes: a first switching element configured to receive a first power supply voltage from a first power supply node and be turned on and off by a first input signal; a second switching element configured to receive a second power supply voltage lower than the first power supply voltage from a second power supply node and be turned on and off by a second input signal; a first capacitor having a first node and a second node, the first node of the first capacitor being connected to a first common node between the first switching element and the first power supply node, and the second node of the first capacitor receiving a control signal having the same phase as the first input signal; and a second capacitor having a first node and a second node, the first node of the second capacitor being connected to a second common node between the second switching element and the second power supply node, and the second node of the second capacitor receiving the control signal. The slew rate of the output signal output from the output node to which the first and second switching elements are connected is determined by the slew rate of the control signal. Attached Figure Description

[0009] The above and other aspects, features and advantages of this disclosure will be more clearly understood from the following detailed description in conjunction with the accompanying drawings.

[0010] Figures 1 to 3 This is a schematic diagram illustrating an electronic device including an interface device according to an example embodiment.

[0011] Figure 4 and Figure 5 This is a view illustrating the operation of an interface device according to an example embodiment.

[0012] Figure 6 This is a schematic circuit diagram of the interface circuit according to an example embodiment.

[0013] Figure 7 and Figure 8 This is a view illustrating the operation of the interface circuit according to an example embodiment.

[0014] Figure 9 and Figure 10This is a view illustrating the operation of the interface circuit according to an example embodiment.

[0015] Figure 11 This is a schematic circuit diagram showing an interface circuit according to an example embodiment.

[0016] Figure 12 and Figure 13 This is a view illustrating the operation of the interface circuit according to an example embodiment.

[0017] Figure 14 This is a schematic circuit diagram of the interface circuit according to an example embodiment.

[0018] Figure 15 and Figure 16 This is a view illustrating the operation of the interface circuit according to an example embodiment.

[0019] Figures 17 to 19 This is a schematic circuit diagram showing an interface circuit according to an example embodiment.

[0020] Figure 20 This is a schematic diagram of an interface device according to an example embodiment.

[0021] Figure 21 and Figure 22 This is a view illustrating the operation of an interface device according to an example embodiment.

[0022] Figure 23 This is a schematic diagram of an interface device according to an example embodiment.

[0023] Figures 24 to 27 This is a view illustrating the operation of an interface device according to an example embodiment.

[0024] Figure 28 This is a schematic block diagram of an electronic device including an interface device according to an example embodiment. Detailed Implementation

[0025] In the following description, exemplary embodiments will be illustrated with reference to the accompanying drawings.

[0026] Figures 1 to 3 This is a schematic diagram illustrating an electronic device including an interface device according to an example embodiment.

[0027] refer to Figure 1 The electronic device 10 may include an application processor 20 and a display driver 30. An interface device 21 of the application processor 20 may exchange data with an interface device 31 of the display driver 30. Each of the interface devices 21 and 31 may include multiple interface circuits.

[0028] Interface devices 21 and 31 can exchange data with each other according to a predetermined protocol or alternatively desired protocols. As an example, interface device 21 of application processor 20 and interface device 31 of display driver 30 can exchange data according to a protocol defined in the Mobile Industry Processor Interface (MIPI) standard. Each of interface devices 21 and 31 may include transmitting circuitry and receiving circuitry.

[0029] refer to Figure 2 In electronic device 40, application processor 50 can exchange data with image sensor 60. Interface device 51 of application processor 50 and interface device 61 of image sensor 60 can exchange data with each other. (Refer to reference...) Figure 1 The contents are similar, and each of the interface devices 51 and 61 may include multiple interface circuits for data exchange.

[0030] refer to Figure 3 In electronic device 70, application processor 80 can exchange data with storage device 90. Interface device 81 of application processor 80 and interface device 91 of storage device 90 can exchange data, commands, addresses, etc. with each other. (See reference...) Figure 1 and Figure 2 The contents described are similar, and interface devices 81 and 91 may include multiple interface circuits for data exchange.

[0031] The interface circuitry included in at least one of the interface devices 21, 31, 51, 61, 81, and 91 according to the example embodiments may have the function of adjusting the slewing rate of the output signal. A controller included in the application processors 20, 50, and 80, the display driver 30, the image sensor 60, and the storage device 90 may control the interface devices 21, 31, 51, 61, 81, and 91 to determine the slewing rate of the output signal. In some example embodiments, the controller may increase the slewing rate of the output signal when it is determined that a higher speed of data transmission is required. Additionally, the controller may adjust the slewing rate of the output signal based on the load of the channel through which data exchange between the interface devices 21, 31, 51, 61, 81, and 91 takes place.

[0032] Figure 4 and Figure 5 This is a view illustrating the operation of an interface device according to an example embodiment.

[0033] Figure 4 This can be a view illustrating the operation of interface device 100 transmitting data and clock signals using a differential signaling scheme. For example, refer to... Figure 4 The described example embodiments can be applied to D-PHY interfaces according to the MIPI standard. (See references) Figure 4Multiple transmitters TX0 to TX9 can output multiple data lines DN0 to DN3 and DP0 to DP3, as well as clock signals CLKN and CLKP, through multiple transmit pads TP0 to TP9.

[0034] Transmit pads TP0 to TP9 can be connected to multiple receive pads RP0 to RP9 via multiple data channels L0 to L9, and receive pads RP0 to RP9 can be connected to multiple receivers RX0 to RX4. For example, each of receivers RX0 to RX4 can be connected to a pair of receive pads RP0 to RP9, and receivers RX0 to RX4 can generate multiple data lines D0 to D3 and a clock signal CLK using a differential signaling scheme. Therefore, in Figure 4 In the example embodiment shown, ten transmit pads TP0 to TP9, ten data channels L0 to L9, and ten receive pads RP0 to RP9 may be required to transmit data using a differential signaling scheme. According to the example embodiment, dummy pads can be added to the transmit pads TP0 to TP9 and the receive pads RP0 to RP9 to achieve an electrical shielding effect. As an example, Figure 4 The interface device 100 shown can be applied to application processors, display drivers, image sensors, storage devices, etc.

[0035] Figure 5 This could be a view illustrating the operation of interface device 110 transmitting data using a single-ended signaling scheme. For example, refer to... Figure 5 The described example embodiments can be applied to C-PHY interfaces according to the MIPI standard. (See references) Figure 5 Multiple transmitters TX0 to TX8 can output multiple data lines A0 to C0, A1 to C1, and A2 to C2 through multiple transmit pads TP0 to TP8. Since image data is output using a single-ended signaling scheme, therefore... Figure 5 In the example embodiment shown, there may be no additional data channel in the interface for outputting clock signals.

[0036] Transmit pads TP0 to TP8 can be connected to multiple receive pads RP0 to RP8 via multiple data channels L0 to L8, and receive pads RP0 to RP8 can be connected to multiple receivers RX0 to RX8. Based on multiple data lines A0 to C0, A1 to C1, and A2 to C2, transmit pads TP0 to TP8 can be divided into multiple groups TP0 to TP2, TP3 to TP5, and TP6 to TP8, and receive pads RP0 to RP8 can also be divided into multiple groups RP0 to RP2, RP3 to RP5, and RP6 to RP8. Each of receivers RX0 to RX8 can receive signals from a pair of receive pads included in the corresponding group of groups RP0 to RP2, RP3 to RP5, and RP6 to RP8. As an example, the first receiver RX0 can output the difference between signal A0 and signal B0, and the second receiver RX1 can output the difference between signal B0 and signal C0. The third receiver RX2 can output the difference between signal C0 and signal A0.

[0037] exist Figure 5 In the example embodiment shown, nine transmit pads TP0 to TP8, nine data channels L0 to L8, and nine receive pads RP0 to RP8 may be required to transmit data using a single-ended signaling scheme. However, even in a single-ended signaling scheme, according to the example embodiment, dummy pads can be added to achieve an electrical shielding effect. Figure 5 The interface device 110 shown can also be used in application processors, display drivers, image sensors, storage devices, etc.

[0038] According to the reference Figure 4 and Figure 5 The interface devices 100 and 110 of the described example embodiments can also be used for communication between devices other than application processors, display drivers, image sensors, and storage devices. As an example, interface devices 100 and 110 can be used with interfaces such as PCI-Express, USB, and display ports.

[0039] As the capacity of data transmitted by interface devices 100 and 110 gradually increases and the data transmission rate required by the system increases, the noise characteristics of the signals output by interface devices 100 and 110 may deteriorate or the eye margin may decrease. In an example embodiment, the noise characteristics of interface devices 100 and 110 can be improved by connecting a capacitor between a resistor and a switching element in interface devices 100 and 110 and adjusting the slewing rate of the signals charging and discharging the capacitor. Additionally, the slewing rate of the signals charging and discharging the capacitor can be adjusted by considering the load of the channel through which interface devices 100 and 110 exchange data, in order to reduce or prevent overshoot and operate interface devices 100 and 110 with improved or optimal characteristics.

[0040] Figure 6 This is a schematic circuit diagram of the interface circuit according to an example embodiment.

[0041] refer to Figure 6 The interface circuit 200 according to the example embodiment may include a first switching element SW1 and a second switching element SW2, a first capacitor C1, a second capacitor C2, a first resistor R1, a second resistor R2, etc. The first switching element SW1 and the second switching element SW2 may be connected between a first power node VN1 and a second power node VN2. Each of the first switching element SW1 and the second switching element SW2 may be implemented as an N-channel metal-oxide-semiconductor (NMOS) transistor.

[0042] A first switching element SW1 can be connected to a first power node VN1 via a first resistor R1, and a second switching element SW2 can be connected to a second power node VN1 via a second resistor R2. A first power supply voltage VDD1 can be provided through the first power node VN1, and a second power supply voltage VDD2 can be provided through the second power node VN2. In some example embodiments, the first power supply voltage VDD1 may be higher than the second power supply voltage VDD2.

[0043] exist Figure 6 In the example embodiment shown, the node between the first resistor R1 and the first switching element SW1 can be defined as the first node N1, and the node between the second resistor R2 and the second switching element SW2 can be defined as the second node N2. An output node can be defined between the first switching element SW1 and the second switching element SW2. The output signal OUT output to the output node can be determined by the first input signal IN1 controlling the first switching element SW1 and the second input signal IN2 controlling the second switching element SW2.

[0044] The first capacitor C1 can be connected to the first node N1, and the second capacitor C2 can be connected to the second node N2. Figure 6 In the example embodiment shown, the charging and discharging of the first capacitor C1 and the second capacitor C2 can be controlled by the control signal CTR. The control signal CTR can be the output signal of the buffer BUF, and the buffer BUF can receive the buffer input signal INB to output the control signal CTR.

[0045] In some example embodiments, each of the first capacitor C1 and the second capacitor C2 can be implemented as a metal-oxide-semiconductor (MOS) capacitor, etc. When each of the first capacitor C1 and the second capacitor C2 is a MOS capacitor, a control signal CTR can be input to the gate terminal of each of the transistors providing the first capacitor C1 and the second capacitor C2.

[0046] The buffer BUF can receive the required third power supply voltage VDD3 and fourth power supply voltage VDD4 through the first variable resistor VR1 and the second variable resistor VR2. As an example, the third power supply voltage VDD3 can be higher than the fourth power supply voltage VDD4, and can be the same as the first power supply voltage VDD1, while the fourth power supply voltage VDD4 can be the same as the second power supply voltage VDD2. The third power supply voltage VDD3 can be supplied from the third power node VN3, and the fourth power supply voltage VDD4 can be supplied from the fourth power node VN4.

[0047] In some example embodiments, the slew rate of the control signal CTR can be determined by variable resistors VR1 and VR2 connected to the buffer BUF. As an example, the slew rate of the control signal CTR can increase when the resistance of variable resistors VR1 and VR2 decreases, and the slew rate of the control signal CTR can decrease when the resistance of variable resistors VR1 and VR2 increases.

[0048] The slew rate of the control signal CTR can affect the slew rate of the output signal OUT. For example, assuming other conditions are the same, when the slew rate of the control signal CTR increases to increase the charging and discharging rate of the first capacitor C1 and the second capacitor C2, the slew rate of the output signal OUT can increase. When the slew rate of the control signal CTR decreases to decrease the charging and discharging rate of the first capacitor C1 and the second capacitor C2, the slew rate of the output signal OUT can decrease.

[0049] Typically, when high-speed data communication is required, the slew rate of the output signal OUT in the interface circuit 200 can be increased. However, when the slew rate of the output signal OUT is increased without considering the load of the channel connected to the output node of the interface circuit 200, overshoot or other issues may occur in the output signal OUT, and the eye margin of the output signal OUT may decrease. In some example embodiments, the slew rate of the control signal CTR can be determined by considering the communication environment in which the interface circuit 200 is applied, and therefore the slew rate of the output signal OUT can be adjusted to improve the eye margin of the output signal OUT and the communication performance of the semiconductor device in which the interface circuit 200 is applied.

[0050] The capacitance of each of the first capacitor C1 and the second capacitor C2 can be selected differently. As an example, the first capacitor C1 and the second capacitor C2 can have the same capacitance. Alternatively, each of the first capacitor C1 and the second capacitor C2 can have a fixed capacitance. According to an example embodiment, each of the first capacitor C1 and the second capacitor C2 can have an adjustable variable capacitance.

[0051] When the interface circuit 200 transmits data using a differential signaling scheme, the phase of the first input signal IN1 may be opposite to the phase of the second input signal IN2. In some example embodiments, the output signal OUT may vary between a first level and a second level higher than the first level. As an example, when the first switching element SW1 is turned on via the first input signal IN1 and the second switching element SW2 is turned off via the second input signal IN2, the output signal OUT may have the second level. Conversely, when the first switching element SW1 is turned off via the first input signal IN1 and the second switching element SW2 is turned on via the second input signal IN2, the output signal OUT may have the first level.

[0052] When the output signal OUT decreases from the second level to the first level or increases from the first level to the second level, the slew rate of the output signal OUT may be affected by the following: the amplitudes of the first input signal IN1 and the second input signal IN2, the slew rate of the control signal CTR for charging and discharging the first capacitor C1 and the second capacitor C2, and parasitic elements present in the various components and nodes VN1, VN2, N1, and N2. In some example embodiments, as described above, the slew rate of the control signal CTR can be adjusted to control the charging and discharging of the first capacitor C1 and the second capacitor C2, and thus the slew rate of the output signal OUT can be controlled.

[0053] On the other hand, when the interface circuit 200 transmits data using a single-ended signaling scheme, the phase of the first input signal IN1 may not be opposite to the phase of the second input signal IN2. For at least a portion of the time, the first input signal IN1 and the second input signal IN2 may have the same value, and the output signal OUT may have a first level, a second level higher than the first level, and a third level higher than the second level.

[0054] Even when the interface circuit 200 transmits data using a single-ended signaling scheme, the switching rate of the control signal CTR for charging and discharging the first capacitor C1 and the second capacitor C2 can be adjusted to increase or decrease the switching rate of the output signal OUT. According to the example embodiment, when the interface circuit 200 operates using a single-ended signaling scheme, different control signals can be used to charge and discharge the first capacitor C1 and the second capacitor C2.

[0055] When according to Figure 6When the interface circuit 200 of the illustrated example embodiment is defined as a unit circuit, in a practically implemented interface device, multiple unit circuits can be connected to a single output pad to sense the output signal OUT. As an example, one or more first unit circuits and one or more second unit circuits can be connected to a single output pad. As an example, the values ​​of resistors R1 and R2 and capacitors C1 and C2 included in the first unit circuit can be the same as or different from the values ​​of resistors R1 and R2 and capacitors C1 and C2 included in the second unit circuit.

[0056] In some example embodiments, five first unit circuits and two second unit circuits can be connected to a single output pad. For example, the sum of the on-resistance of the first resistor R1 and the first switching element SW1 included in each first unit circuit can be half the sum of the on-resistance of the first resistor R1 and the first switching element SW1 included in each second unit circuit. Similarly, the sum of the on-resistance of the second resistor R2 and the second switching element SW2 included in each first unit circuit can be half the sum of the on-resistance of the second resistor R2 and the second switching element SW2 included in each second unit circuit. In practice, the first switching element SW1 and the second switching element SW2 included in each of the first and second unit circuits can be appropriately controlled to set the desired resistance values.

[0057] In some example embodiments, the dimensions of each of the first switching element SW1 and the second switching element SW2 can be determined based on the resistance conditions described above. As an example, assuming that the first and second switching elements included in each first unit circuit and each second unit circuit have the same gate length, the gate width of the first switching element included in each first unit circuit can be twice the gate width of the first switching element included in each second unit circuit. In the above example, the gate width can be defined in the direction intersecting the gate length. Similarly, the gate width of the second switching element included in each first unit circuit can be twice the gate width of the second switching element included in each second unit circuit.

[0058] Assuming the number of first and second unit circuits as described above, the capacitance of the first capacitor C1 included in the first unit circuit can be approximately twice the capacitance of the first capacitor C1 included in the second unit circuit. Furthermore, the capacitance of the second capacitor C2 included in the first unit circuit can be approximately twice the capacitance of the second capacitor C2 included in the second unit circuit.

[0059] When exchanging data using a single-ended signaling scheme, refer to the above. Figure 5As described above, at least three output pads may be required to transmit data. As mentioned, the output signals from the three output pads have different levels, and can have levels ranging from a first level to a third level. As an example, the number of actually operating unit circuits in the multiple unit circuits connected to the output pads can vary depending on the output signal OUT output through the output pads.

[0060] Figure 7 and Figure 8 This is a view illustrating the operation of the interface circuit according to an example embodiment.

[0061] Reference Figure 7 In the described example embodiment, the interface circuitry can operate using a differential signaling scheme. For example... Figure 7 As shown, when the first switching element SW1 is turned on via the first input signal IN1 and the second switching element SW2 is turned off via the second input signal IN2, the output signal OUT can increase from a low level to a high level. Conversely, when the first switching element SW1 is turned off via the first input signal IN1 and the second switching element SW2 is turned on via the second input signal IN2, the output signal OUT can decrease from a high level to a low level.

[0062] The first capacitor C1 and the second capacitor C2 can be charged and discharged using the control signal CTR. As an example, the buffer BUF can receive a buffer input signal INB with the same phase as the first input signal IN1 to output the control signal CTR. When the first switching element SW1 is on and the second switching element SW2 is off, the first capacitor C1 and the second capacitor C2 can be charged using the control signal CTR. When the first capacitor C1 and the second capacitor C2 are charged, the output signal OUT can rapidly increase from a low level to a high level. When the first switching element SW1 is off and the second switching element SW2 is on, the first capacitor C1 and the second capacitor C2 can be discharged, and the output signal OUT can rapidly decrease from a high level to a low level.

[0063] The slew rate of the control signal CTR can vary depending on the resistance values ​​of the first variable resistor VR1 and the second variable resistor VR2 connected to the buffer BUF. For example, when the resistance values ​​of the first variable resistor VR1 and the second variable resistor VR2 increase, the slew rate of the control signal CTR can decrease. When the resistance values ​​of the first variable resistor VR1 and the second variable resistor VR2 decrease, the slew rate of the control signal CTR can increase.

[0064] The slew rate of the output signal OUT can vary depending on the slew rate of the control signal CTR. For example, when the control signal CTR has a high slew rate, the slew rate of the output signal OUT can also increase in response to the high slew rate of the control signal CTR. Conversely, when the control signal CTR has a relatively low slew rate, the slew rate of the output signal OUT can also decrease. Therefore, as... Figure 7 As shown, the switching rate of the output signal OUT can be controlled simply by adjusting the resistance values ​​of the first variable resistor VR1 and the second variable resistor VR2 connected to the buffer BUF, without controlling the first input signal IN1, the second input signal IN2 and the buffer input signal INB.

[0065] Reference Figure 8 In the described example embodiment, the interface circuitry can operate with a single-ended signaling scheme. (See reference...) Figure 8 When the first switching element SW1 is turned on and the second switching element SW2 is turned off, the output signal OUT can increase from a low level to a high level. When the first switching element SW1 is turned off and the second switching element SW2 is turned on, the output signal OUT can decrease from a high level to a low level. Furthermore, as one of the first switching element SW1 or the second switching element SW2 is turned on or off, the output signal OUT can increase from a low level to a medium level, or decrease from a high level to a medium level.

[0066] Additionally, in reference Figure 8 In the described example embodiment, the first capacitor C1 of the interface circuit can be charged and discharged using a first control signal CTR1, and the second capacitor C2 of the interface circuit can be charged and discharged using a second control signal CTR2. The first control signal CTR1 and the second control signal CTR2 can be different from each other. As an example, the interface circuit may include a first buffer and a second buffer, wherein the first buffer receives a first buffer input signal INB1 and outputs the first control signal CTR1 to the first capacitor C1, and the second buffer receives a second buffer input signal INB2 and outputs the second control signal CTR2 to the second capacitor C2. As an example, the output signal OUT can be determined as shown in Table 1.

[0067] Table 1

[0068]

[0069]

[0070] refer to Figure 8According to Table 1, when the change in the output signal OUT is a first value, only one of the first capacitor C1 and the second capacitor C2 can be charged or discharged. On the other hand, when the change in the output signal OUT is a second value greater than the first value, both the first capacitor C1 and the second capacitor C2 can be charged or discharged simultaneously. The first value can be the difference between a high level and a medium level, and the second value can be the difference between a high level and a low level.

[0071] As an example, when the output signal OUT increases from a low level to a medium level, only the second capacitor C2 can be charged, and when the output signal OUT decreases from a medium level to a low level, only the second capacitor C2 can be discharged. When the output signal OUT increases from a medium level to a high level, only the first capacitor C1 can be charged, and when the output signal OUT decreases from a high level to a medium level, only the first capacitor C1 can be discharged. In the example embodiment shown in Table 1, the first control signal CTR1 can be the same as the first input signal IN1, and the second control signal CTR2 can be the complementary signal of the second input signal IN2.

[0072] like Figure 8 As shown, the switching rate of each of the first control signal CTR1 and the second control signal CTR2 can be adjusted to change the switching rate of the output signal OUT. For example, the switching rate of each of the first control signal CTR1 and the second control signal CTR2 can be increased to increase the switching rate of the output signal OUT. Alternatively, the switching rate of each of the first control signal CTR1 and the second control signal CTR2 can be decreased to decrease (e.g., slowly decrease) the switching rate of the output signal OUT.

[0073] Reference Figure 7 and Figure 8 In the described example embodiments, the switching rates of control signals CTR, CTR1, and CTR2 can be determined based on the operating conditions of the interface circuit. For example, when the interface circuit is required to support high-speed data communication, the switching rates of control signals CTR, CTR1, and CTR2 can be increased. In some example embodiments, the amount of increase in the switching rates of control signals CTR, CTR1, and CTR2 can vary depending on the load of the data communication channel through which the interface circuit transmits its output signal OUT.

[0074] As an example, when the load on the data communication channel is relatively low, the increase in the slewing rates of control signals CTR, CTR1, and CTR2 can be relatively small. Even when the load on the data communication channel is low, if the increase in the slewing rates of control signals CTR, CTR1, and CTR2 is set to be large, overshoot of the output signal OUT may occur, exceeding the upper limit. In the example embodiment, the slewing rates of control signals CTR, CTR1, and CTR2 can be determined by considering the load on the data communication channel and the data communication speed to reduce or prevent overshoot of the output signal OUT and improve the eye margin of the output signal OUT. When the load on the data communication channel is high, the increase in the slewing rates of control signals CTR, CTR1, and CTR2 can be set to be relatively large.

[0075] Figure 9 and Figure 10 This is a view illustrating the operation of an interface circuit according to an example embodiment (which may be a variable resistor circuit diagram).

[0076] Figure 9 and Figure 10 This could be a view showing in detail the buffers included in the interface circuitry. (Reference) Figure 9 and Figure 10 The buffer BUF can receive the power supply voltage through the first variable resistor VR1 and the second variable resistor VR2.

[0077] refer to Figure 9 The first variable resistor VR1 and the second variable resistor VR2 can have the same structure. As an example, each of the first variable resistor VR1 and the second variable resistor VR2 may include multiple transistors TR connected in parallel with each other. Each of the multiple transistors TR can have a predetermined on-resistance, or alternatively desired on-resistance, in the on-state. Based on this, variable resistors VR1 and VR2 can be implemented. As an example, the on-resistance of the multiple transistors TR can be the same.

[0078] The following description will use the first variable resistor VR1 as an example. Figure 9 In the diagram, the first variable resistor VR1 is shown as comprising seven transistors TR. However, the number of transistors TR is not limited to this. Some of the transistors TR can be simultaneously turned on and off by a single gate signal. (Reference) Figure 9 Two transistors TR can jointly receive a single gate signal G1, and four transistors TR can jointly receive a single gate signal G2.

[0079] Gate signals G0, G1, and G2 can be input to the interface circuit as a single digital signal. As an example, assuming gate signals G0, G1, and G2 are the least significant bit (LSB) to the most significant bit (MSB) in sequence, a three-bit digital signal can be used to determine the resistance value of the first variable resistor VR1. For example, when the digital signal is

[001] , only one transistor TR can be turned on, allowing the first variable resistor VR1 to have its maximum resistance value. When the digital signal is

[111] , all transistors TR can be turned on, allowing the first variable resistor VR1 to have its minimum resistance value. Similarly, the resistance value of the second variable resistor VR2 can be determined using a single digital signal corresponding to the gate signals G3, G4, and G5 input to the second variable resistor VR2.

[0080] refer to Figure 10 Each of the first variable resistor VR1 and the second variable resistor VR2 may include multiple transistors TR and multiple unit resistors UR connected in parallel with each other. For example, the multiple transistors TR may have the same on-resistance, and the multiple unit resistors UR may also have the same resistance value.

[0081] The following description will use the first variable resistor VR1 as an example. Figure 10 In the diagram, the first variable resistor VR1 is shown as comprising seven transistors TR. However, the number of transistors TR is not limited to this. (Refer to the reference...) Figure 9 The content is similar; some transistors in the TR can be turned on and off simultaneously by a single gate signal.

[0082] exist Figure 10 In the example embodiment shown, the resistance value of the first variable resistor VR1 can be determined by the resistance value of the unit resistor UR. For example, when the digital signal input to the first variable resistor VR1 is

[001] , the resistance value of the first variable resistor VR1 can be the same as the resistance value of a single unit resistor UR. When the digital signal is

[010] , the resistance value of the first variable resistor VR1 can be the same as the combined resistance value of the two unit resistors UR. Similarly, the resistance value of the second variable resistor VR2 can be determined using a single digital signal corresponding to the gate signals G3, G4, and G5 input to the second variable resistor VR2.

[0083] Figure 11 This is a schematic circuit diagram showing an interface circuit according to an example embodiment.

[0084] refer to Figure 11The interface circuit 300 according to the example embodiment may include a first switching element SW1 and a second switching element SW2, a first capacitor C1, a second capacitor C2, a first resistor R1, a second resistor R2, etc. Figure 11 In the example embodiment shown, the first switching element SW1 can be implemented as a P-channel metal-oxide-semiconductor (PMOS) transistor, and the second switching element SW2 can be implemented as an NMOS transistor. Therefore, the phase of the first input signal IN1 can be the same as the phase of the second input signal IN2.

[0085] As an example, according to Figure 11 The interface circuit 300 of the example embodiment shown can be applied to interfaces that require a large voltage swing. As an example, the interface circuit 300 can be applied to interfaces such as PCI-Express, USB, etc.

[0086] exist Figure 11 In the illustrated example embodiment, the interface circuit 300 may include a first buffer BUF1 and a second buffer BUF2. The first buffer BUF1 and the second buffer BUF2 may receive a third power supply voltage VDD3 and a fourth power supply voltage VDD4, respectively, via variable resistors VR1 to VR4. The first buffer BUF1 may output a first control signal CTR1 in response to the first buffer input signal INB1, and the first capacitor C1 may be charged and discharged via the first control signal CTR1. Similarly, the second capacitor C2 may be charged and discharged via the second control signal CTR2 output from the second buffer BUF2.

[0087] Except for the first switching element SW1 being implemented as a PMOS transistor, reference Figure 6 The content described can be similarly applied to Figure 11 The example embodiment is shown. As an example, the slewing rates of control signals CTR1 and CTR2 can be adjusted to change the slewing rate of the output signal OUT. The slewing rates of control signals CTR1 and CTR2 can be determined by the resistance values ​​of variable resistors VR1 to VR4. Additionally, when referring to... Figure 6 When the interface circuit 200 described operates in a single-ended signaling scheme, the first capacitor C1 and the second capacitor C2 can be connected to the first buffer BUF1 and the second buffer BUF2 respectively, so that they can be charged and discharged independently of each other.

[0088] refer to Figure 11When the second input signal IN2 is increased to turn on the second switching element SW2, the output signal OUT can decrease from a high level to a low level. When the first input signal IN1 and the second input signal IN2 are the same, the first switching element SW1 can be turned off. In some example embodiments, the voltage 307 on the second node N2 can increase instantaneously due to charge sharing, such as... Figure 11 As shown. Since the voltage 307 on the second node N2 increases when the output signal OUT decreases from high level to low level, the slewing rate of the output signal OUT can be relatively low.

[0089] In some example embodiments, a second capacitor C2 connected to the second node N2 can be used to significantly reduce the decrease in the slewing rate of the output signal OUT. (See reference...) Figure 11 The second control signal CTR2, output from the second buffer BUF2 to the second capacitor C2, can decrease from a high level to a low level. When the second control signal CTR2 decreases from a high level to a low level, the increase in voltage 307 on the second node N2 caused by charge sharing can be canceled out, and the decrease in the slewing rate of the output signal OUT can be significantly reduced.

[0090] Voltage fluctuations occurring in the first node N1 and / or the second node N2 due to charge sharing during the operation of the interface circuit 300 can vary depending on factors such as the load of the channel through which the output signal OUT is transmitted. For example, when the channel load is high, the voltage fluctuations occurring in the first node N1 and / or the second node N2 may be larger. In some example embodiments, the slewing rate of the second control signal CTR2 can be selected differently, taking into account the channel load, to appropriately eliminate voltage fluctuations occurring in the first node N1 and / or the second node N2.

[0091] refer to Figure 11 The second control signal CTR2 can have one of the waveforms from the first waveform 301 to the third waveform 303. It will be understood that the first waveform 301 has the highest slew rate, and the third waveform 303 has the lowest slew rate. When the second control signal CTR2 is output with one of the first waveforms 301 to the third waveform 303, a charge-sharing effect occurs in the second node N2 due to the second capacitor C2, which can take the form of one of the waveforms from the fourth waveform 304 to the sixth waveform 306. As an example, the fourth waveform 304 can correspond to the charge-sharing effect caused by the second control signal CTR2 with the first waveform 301, and the sixth waveform 306 can correspond to the charge-sharing effect caused by the control signal CTR2 with the third waveform 303.

[0092] The voltage fluctuation in the second node N2 can be determined by the charge-sharing effect caused by the switching operation of the second switching element SW2 and the charge-sharing effect caused by the second capacitor C2. As an example, in Figure 11 In the example embodiment shown, the second control signal CTR2 can be controlled to have a second waveform 302, thus eliminating the charge sharing effect caused by the switching of the second switching element SW2 through the charge sharing effect caused by the second capacitor C2. As a result, the eye margin of the output signal OUT can be significantly and / or reliably ensured, and the slewing rate of the output signal OUT can be improved.

[0093] Figure 12 and Figure 13 This is a view illustrating the operation of the interface circuit according to an example embodiment.

[0094] Figure 12 This may be a view illustrating an example embodiment of the interface circuit 300 operating with a differential signaling scheme. Since the first switching element SW1 is implemented as a PMOS transistor and the second switching element SW2 is implemented as an NMOS transistor, the phase of the first input signal IN1 can be the same as the phase of the second input signal IN2. As an example, a single input signal can be input to both the first switching element SW1 and the second switching element SW2. When the first switching element SW1 is on and the second switching element SW2 is off, the output signal OUT increases from a low level to a high level. When the first switching element SW1 is off and the second switching element SW2 is on, the output signal OUT decreases from a high level to a low level.

[0095] When the first switching element SW1 is turned on and the second switching element SW2 is turned off, the first capacitor C1 and the second capacitor C2 can be charged, and when the first switching element SW1 is turned off and the second switching element SW2 is turned on, the first capacitor C1 and the second capacitor C2 can be discharged. Therefore, the first buffer input signal INB1 and the second buffer input signal INB2 can have phases opposite to the first input signal IN1 and the second input signal IN2. When the first switching element SW1 is turned on and the second switching element SW2 is turned off, the control signals CTR1 and CTR2 can increase, and when the first switching element SW1 is turned off and the second switching element SW2 is turned off, the control signals CTR1 and CTR2 can decrease.

[0096] refer to Figure 12The slew rate of the output signal OUT can be determined by controlling the slew rates of signals CTR1 and CTR2. When the slew rates of control signals CTR1 and CTR2 decrease, the slew rate of the output signal OUT can decrease. When the slew rates of control signals CTR1 and CTR2 increase, the slew rate of the output signal OUT can increase. As mentioned above, the slew rates of control signals CTR1 and CTR2 can be varied according to the resistance values ​​of variable resistors VR1 to VR4 connected to buffers BUF1 and BUF2. Therefore, by adjusting the resistance values ​​of variable resistors VR1 to VR4, the slew rate of the output signal OUT can be determined to the desired value.

[0097] Figure 13 This may be a view illustrating an example embodiment of the interface circuitry 300 operating in a single-ended signaling scheme. When the interface circuitry operates in a single-ended signaling scheme, it is compared with the reference... Figure 12 The example embodiments described may differ, and the first buffer input signal INB1 and the second buffer input signal INB2 may be different from each other. Therefore, the charging and discharging of each of the first capacitor C1 and the second capacitor C2 can be controlled independently.

[0098] As described with reference to Table 1, the first input signal IN1, the second input signal IN2, the first control signal CTR1, the second control signal CTR2, and the output signal OUT can be determined. As an example, when the first input signal IN1 increases and the second input signal IN2 decreases, the output signal OUT can increase from a low level to a high level. In some example embodiments, the first capacitor C1 and the second capacitor C2 can be charged, and the slewing rate of the output signal OUT can be determined based on the slewing rates of the first control signal CTR1 and the second control signal CTR2 during the charging of the first capacitor C1 and the second capacitor C2.

[0099] refer to Figure 13 When the switching rates of the first control signal CTR1 and the second control signal CTR2 increase, the switching rate of the output signal OUT can also increase. When the switching rates of the first control signal CTR1 and the second control signal CTR2 decrease, the switching rate of the output signal OUT can also decrease. The resistance values ​​of the variable resistors VR1 to VR4 that supply power voltage to each of the first buffer BUF1 and the second buffer BUF2 can be changed to adjust the switching rates of the first control signal CTR1 and the second control signal CTR2, as well as the switching rate of the output signal OUT.

[0100] Figure 14 This is a schematic circuit diagram of the interface circuit according to an example embodiment.

[0101] refer to Figure 14The interface circuit 400 according to the example embodiment may include a first switching element SW1 and a second switching element SW2, a first capacitor C1, a second capacitor C2, a first resistor R1, a second resistor R2, etc. Except that each of the first capacitor C1 and the second capacitor C2 is a variable capacitor, the other components and features may be similar to those in the referenced document. Figure 6 The components and features in the described example embodiment are shown. As an example, the charging and discharging of the first capacitor C1 and the second capacitor C2 can be controlled by a control signal CTR. The control signal CTR can be the output signal of a buffer BUF, and the buffer BUF can receive a buffer input signal INB to output the control signal CTR.

[0102] exist Figure 14 In the example embodiment shown, the first capacitor C1 and the second capacitor C2 may have variable capacitance. As an example, in a communication environment where a significant increase in the slew rate of the output signal OUT is required, the capacitance of the first capacitor C1 and the second capacitor C2 can be set to a larger value, and in a communication environment where a significant increase in the slew rate of the output signal OUT is not required, the capacitance of the first capacitor C1 and the second capacitor C2 can be set to a smaller value.

[0103] In some example embodiments, the first capacitor C1 and the second capacitor C2 may include a plurality of unit capacitors connected in parallel with each other, such that each of the first capacitor C1 and the second capacitor C2 is implemented as a variable capacitor. Additionally, the plurality of unit capacitors may be connected to different buffers, enabling efficient charging and discharging of each of the plurality of unit capacitors. Reference will be made below to... Figure 15 and Figure 16 To describe this in more detail.

[0104] Figure 15 and Figure 16 This is a view illustrating the operation of the interface circuit according to an example embodiment.

[0105] Figure 15 and Figure 16 This could be a view illustrating an example of implementing a first capacitor C1 and a buffer BUF included in interface circuit 400. (Reference) Figure 15 and Figure 16 The interface circuit may include multiple buffers BUF1 to BUF4 for receiving the buffer input signal INB, and multiple unit capacitors VC1 to VC4. One end of the multiple unit capacitors VC1 to VC4 may be connected to the first node N1 between the first resistor R1 and the first switching element SW1.

[0106] As an example, the number of buffers BUF1 to BUF4 that charge and discharge unit capacitors VC1 to VC4 can be selected to change the capacitance of the first capacitor C1 included in the interface circuit 400. As an example, when only the first buffer BUF1 operates, the capacitance of the first capacitor C1 can be determined as the capacitance of the first unit capacitor VC1. On the other hand, when all buffers BUF1 to BUF4 operate, the capacitance of the first capacitor C1 can be determined as the sum of the capacitances of the first unit capacitor VC1 to the fourth unit capacitor VC4. Taking into account the load of the channel through which the output signal OUT of the output interface circuit 400 passes, it can be determined whether each of the buffers BUF1 to BUF4 operates, and the capacitance of the first capacitor C1 can be changed, allowing the interface circuit 400 to be controlled to generate an output signal OUT with an improved or optimized slew rate.

[0107] refer to Figure 16 The resistors connected to each of the buffers BUF1 to BUF4 can be implemented as variable resistors VR1 and VR2. Therefore, the capacitance of the first capacitor C1 can be determined based on whether each of the buffers BUF1 to BUF4 is operational. By changing the resistance values ​​of the variable resistors VR1 and VR2 connected to the buffers BUF1 to BUF4 according to the determined capacitance of the first capacitor C1, the slew rate of the output signal OUT can be adjusted more precisely. In some example embodiments, the slew rate of the output signal OUT can be set to a desired value by controlling only the operation of the first buffer BUF1 and adjusting the resistance values ​​of the variable resistors VR1 and VR2 connected to the first buffer BUF1.

[0108] Additionally, as an example, two or more buffers BUF1 to BUF4 can be controlled to operate, and some of the variable resistors VR1 and VR2 in the two or more buffers BUF1 to BUF4 may have different resistance values. For example, when the first buffer BUF1 and the second buffer BUF2 are operating, the variable resistors VR1 and VR2 connected to the first buffer BUF1 may have different resistance values ​​than the variable resistors VR1 and VR2 connected to the second buffer BUF2.

[0109] Figures 17 to 19 This is a schematic circuit diagram showing an interface circuit according to an example embodiment.

[0110] exist Figures 17 to 19In the example embodiments shown, interface circuits 500 to 520 may be provided. In addition to the first capacitor C1 and the second capacitor C2, each of the interface circuits 500 to 520 may also include a third capacitor C3 and a fourth capacitor C4 connected to the output node. The capacitance of each of the third capacitor C3 and the fourth capacitor C4 may be the same as or different from the capacitance of each of the first capacitor C1 and the second capacitor C2. Even Figures 17 to 19 In the example embodiment shown, the slew rate of the output signal OUT from each of the interface circuits 500 to 520 can also vary according to the slew rate of the control signals CTR, CTR1, and CTR2 for charging and discharging capacitors C1 to C4.

[0111] refer to Figure 17 The first capacitor C1 through the fourth capacitor C4 can be charged and discharged via the control signal CTR output from the buffer BUF. Referring to the example embodiment described above, it will be understood whether the first capacitor C1 through the fourth capacitor C4 is charged and discharged. For example, when the interface circuit 500 operates with a differential signaling scheme, when the first switching element SW1 is turned on and the second switching element SW2 is turned off, the first capacitor C1 through the fourth capacitor C4 can be charged via the control signal CTR. On the other hand, when the interface circuit 500 operates with a single-ended signaling scheme, the first capacitor C1 and the third capacitor C3 can be connected to one buffer, and the second capacitor C2 and the fourth capacitor C4 can be connected to another buffer.

[0112] Alternatively, at least some of the first capacitors C1 through the fourth capacitor C4 can be connected to different buffers to reduce the load on the buffers, regardless of the operating scheme. (Reference) Figure 18 The first capacitor C1 and the second capacitor C2 can be connected to the first buffer BUF1, and the third capacitor C3 and the fourth capacitor C4 can be connected to the second buffer BUF2. (Reference) Figure 19 The first capacitor C1 and the second capacitor C2 can receive the first constant voltage V1 and the second constant voltage V2 respectively, and only the third capacitor C3 and the fourth capacitor C4 can be charged and discharged through the buffer BUF.

[0113] Figure 20 This is a schematic diagram of an interface device according to an example embodiment. Figure 21 and Figure 22 This is a view illustrating the operation of an interface device according to an example embodiment.

[0114] refer to Figure 20The interface device 600 according to the example embodiment can operate using a differential signaling scheme. The interface device 600 may include: a first interface circuit 610 that outputs a first output signal DN0; and a second interface circuit 620 that outputs a second output signal DP0. The phase of the first output signal DN0 may be opposite to the phase of the second output signal DP0, and can be transmitted from output pads TP0 and TP1 to receive pads RP0 and RP1 via a first data channel L0 and a second data channel L1. Termination circuitry, including a terminating resistor RT and a terminating capacitor CT, may be connected to each of the first receive pad RP0 and the second receive pad RP1. Receiver RX0 can use the first output signal DN0 and the second output signal DP0 to generate received data D0.

[0115] The first interface circuit 610 and the second interface circuit 620 can have the same structure. The first interface circuit 610 will now be described as an example. The first interface circuit 610 may include a first switching element SW1 and a second switching element SW2, a first resistor R1 and a second resistor R2, a first capacitor C1, a second capacitor C2, etc. The operation of each of the first switching element SW1 and the second switching element SW2 can be controlled by a first input signal IN1 and a second input signal IN2, and a first output signal DN0 can be output through an output node ON1 and an output pad TP0. Each of the first capacitor C1 and the second capacitor C2 can be charged and discharged by a first control signal CTR1. According to an example embodiment, the first capacitor C1 and the second capacitor C2 can be charged and discharged by an additional control signal.

[0116] In some example embodiments, the slewing rates of the first control signal CTR1 and the second control signal CTR2 input to capacitors C1 to C4 can be adjusted to change the slewing rates of the first output signal DN0 and the second output signal DP0. These will be referred to together below. Figure 24 and Figure 25 This describes the operation of interface device 600.

[0117] Figure 21 The waveform diagram may illustrate an example embodiment where the slew rate of the first output signal DN0 and the second output signal DP0 is significantly increased. As an example, when the loads of data channels L0 and L1 transmitting the first output signal DN0 and the second output signal DP0 are relatively high, a reference can be applied. Figure 21 The example implementation described.

[0118] refer to Figure 21The phase of the first input signal IN1 can be opposite to the phase of the second input signal IN2, and the phase of the third input signal IN3 can be opposite to the phase of the fourth input signal IN4. The phase of the first input signal IN1 can be the same as the phase of the fourth input signal IN4. Therefore, the phase of the first output signal DN0 can be opposite to the phase of the second output signal DP0.

[0119] As an example, the first control signal CTR1 may have the same phase as the first input signal IN1, and the second control signal CTR2 may have the same phase as the third input signal IN3. Therefore, in the first interface circuit 610, when the first switching element SW1 is turned on, the first capacitor C1 can be charged and the first output signal DN0 can increase rapidly. Additionally, when the second switching element SW2 is turned on, the second capacitor C2 can be discharged and the first output signal DN0 can decrease rapidly. Similarly, in the second interface circuit 620, when the third switching element SW3 is turned on, the third capacitor C3 can be charged and the second output signal DP0 can increase rapidly. Additionally, when the fourth switching element SW4 is turned on, the fourth capacitor C4 can be discharged and the second output signal DP0 can decrease rapidly.

[0120] As mentioned above, such as Figure 24 As shown, capacitors C1 to C4 can be controlled to increase eye margin. Furthermore, it can be sufficiently ensured that the received data D0 output by receiver RX0 has a high or low level duration, and the received data D0 can be accurately detected on the receiving side.

[0121] Figure 22 The waveform diagram may be an example embodiment showing a relatively small increase in the slew rate of the first output signal DN0 and the second output signal DP0. (Refer to...) Figure 22 Input signals IN1 to IN4 can be used with reference signals. Figure 21 The input signals IN1 to IN4 are described as identical. Additionally, the first control signal CTR1 may have the same phase as the first input signal IN1, and the second control signal CTR2 may have the same phase as the third input signal IN3.

[0122] However, in Figure 22 In the example embodiment shown, the switching rates of the first control signal CTR1 and the second control signal CTR2 can be relatively lower than the reference rate. Figure 21The slew rate in the described example embodiment. For example, the first control signal CTR1 and the second control signal CTR2 can increase slowly and decrease slowly. The slew rate of the first control signal CTR1 and the second control signal CTR2 can be controlled such that the resistance value of a variable resistor connected to a buffer that inputs the first control signal CTR1 and the second control signal CTR2 to capacitors C1 to C4 is adjusted. When the slew rate of the first control signal CTR1 and the second control signal CTR2 decreases, the slew rate of the first output signal DN0 and the second output signal DP0 can also be relatively lower than the reference slew rate. Figure 21 The conversion rate in the example embodiments described.

[0123] As a result, the interface device 600 according to the example embodiment can control the slewing rates of the output signals DN0 and DP0. As an example, the slewing rates of the output signals DN0 and DP0 can be controlled by adjusting the slewing rate of the control signal for the buffer that charges and discharges the capacitors C1 to C4 included in the interface circuits 610 and 620, rather than adjusting the capacitance of the capacitors C1 to C4. Therefore, unlike adjusting the capacitance of the capacitors C1 to C4, the slewing rates of the output signals DN0 and DP0 can be effectively adjusted without increasing the capacitance reflected in the output nodes ON1 and ON2 of the interface circuits 610 and 620. Furthermore, the interface circuits 610 and 620 can adjust the slewing rates of the output signals DN0 and DP0 by considering the load along the data paths L0 and L1 through which they transmit the output signals DN0 and DP0 to solve problems such as overshoot occurring in the output signals DN0 and DP0 due to excessively high slewing rates.

[0124] Figure 23 This is a schematic diagram of an interface device according to an example embodiment. Figures 24 to 27 This is a view illustrating the operation of an interface device according to an example embodiment.

[0125] refer to Figure 23 The interface device 700 according to an example embodiment may include: a first interface circuit 710 that outputs a first output signal A0; a second interface circuit 720 that outputs a second output signal B0; and a third interface circuit 730 that outputs a third output signal C0. As an example, the interface device 700 may support communication in the C_PHY interface according to the Mobile Industrial Processor Interface (MIPI) standard. The first output signal A0 to the third output signal C0 may have high, low, and medium levels, and the first output signal A0 to the third output signal C0 may not have different levels from each other. As an example, when the first output signal A0 is at a high level, one of the second output signal B0 and the third output signal C0 may be at a medium level, while the other may be at a low level.

[0126] A first output signal A0 can be input to the first receiving pad RP0 along the first data channel L0, a second output signal B0 can be input to the second receiving pad RP1 along the second data channel L1, and a third output signal C0 can be input to the third receiving pad RP2 along the third data channel L2. A termination circuit is connected to each of the receiving pads RP0, RP1, and RP2. The termination circuit may include a termination resistor RT and a termination capacitor CT.

[0127] The first receiver RX0, the second receiver RX1, and the third receiver RX2 can generate first received data AB0, second received data BC0, and third received data CA0 using the first output signal A0, the second output signal B0, and the third output signal C0, respectively. The first receiver RX0 can generate the first received data AB0 using the difference between the first output signal A0 and the second output signal B0, and the second receiver RX1 can generate the second received data BC0 using the difference between the second output signal B0 and the third output signal C0. The third receiver RX2 can generate the third received data CA0 using the difference between the third output signal C0 and the first output signal A0. In some example embodiments, the first received data AB0, the second received data BC0, and the third received data CA0 can be converted into three-bit state information at the receiving side, and changes in the state information can be used to generate symbol information.

[0128] The first interface circuit 710, the second interface circuit 720, and the third interface circuit 730 can have the same structure. Now, the first interface circuit 710 will be described as an example. The first interface circuit 710 may include a first switching element SW1 and a second switching element SW2, a first resistor R1 and a second resistor R2, a first capacitor C1, a second capacitor C2, etc. The first capacitor C1 can be charged and discharged via a first control signal CTR1, and the second capacitor C2 can be charged and discharged via a second control signal CTR2. Figure 23 In the example embodiment shown, capacitors C1 to C6 included in each of the first interface circuit 710, the second interface circuit 720, and the third interface circuit 730 can be charged and discharged by different control signals CTR1 to CTR6.

[0129] In the following text, we will refer to them together. Figures 24 to 27 To describe the operation of interface device 700.

[0130] Figure 24 and Figure 25 This can correspond to some operational embodiments where the conversion rate from the first output signal A0 to the third output signal C0 can be significantly increased. (See reference...) Figure 24The amplitude of each of the first output signal A0 to the third output signal C0 can be determined as high level, low level and medium level, and the first output signal A0 to the third output signal C0 can not have the same level at the same time.

[0131] Figure 25 It shows the relationship with Figure 24 The diagram shows a view of the input signals IN1 to IN6 and control signals CTR1 to CTR6 corresponding to the first output signal A0 to the third output signal C0. Now, the first interface circuit 710 will be described as an example. The first control signal CTR1 can be the same signal as the first input signal IN1, and the second control signal CTR2 can be the complementary signal of the second input signal IN2. As described above, the first control signal CTR1 and the second control signal CTR2 can be selected to increase the slewing rate of the first output signal A0. Similarly, in the second interface circuit 720, the third control signal CTR3 can be the same signal as the third input signal IN3, and the fourth control signal CTR4 can be the complementary signal of the fourth input signal IN4. Figure 24 and Figure 25 In the example embodiment shown, the resistance value of the variable resistor connected to each of the buffers that transmit control signals CTR1 to CTR6 can be reduced to increase the switching rate of control signals CTR1 to CTR6. Therefore, the switching rate of the first output signal A0 to the third output signal C0 can be significantly increased.

[0132] Figure 26 and Figure 27 This can correspond to an operational embodiment where the conversion rate from the first output signal A0 to the third output signal C0 can be reduced. (See reference...) Figure 26 Each of the first output signal A0 to the third output signal C0 can have a high level, a low level, and a medium level, and the first output signal A0 to the third output signal C0 can not have the same level at the same time.

[0133] Figure 27 It shows the relationship with Figure 26 The diagram shows a view of the input signals TN1 to IN6 and the control signals CTR1 to CTR6 corresponding to the first output signal A0 to the third output signal C0. The first interface circuit 710 will now be described as an example. The first control signal CTR1 may be the same signal as the first input signal IN1, and the second control signal CTR2 may be a complementary signal to the second input signal IN2.

[0134] Reference Figure 24 and Figure 25 The content described is different, in Figure 27In the example embodiment shown, the resistance value of the variable resistor connected to each of the buffers that transmit control signals CTR1 to CTR6 can be increased. Therefore, the slew rate of control signals CTR1 to CTR6 can be reduced, and the slew rate of the first output signal A0 to the third output signal C0 can be set to be relatively lower than... Figure 24 and Figure 25 The conversion rate in the example embodiment shown. For example, when the load on data channels L0 to L2 is not high, the conversion rate from the first output signal A0 to the third output signal C0 can be set to a relatively low value, as shown in the reference. Figure 26 and 27 The purpose is to reduce or prevent overshoot from the first output signal A0 to the third output signal C0.

[0135] Figure 28 This is a schematic block diagram of an electronic device including an interface device according to an example embodiment.

[0136] refer to Figure 28 The mobile system 1000 may include a camera 1100, a display 1200, an audio processing unit 1300, a modem 1400, DRAM 1500a and 1500b, flash memory devices 1600a and 1600b, input / output (I / O) devices 1700a and 1700b, and / or an application processor (hereinafter referred to as "AP") 1800.

[0137] The mobile system 1000 can be implemented as a laptop computer, mobile terminal, smartphone, tablet PC, wearable device, healthcare device, or Internet of Things (IoT) device. Furthermore, the mobile system 1000 can be implemented as a server or PC.

[0138] Camera 1100 can capture still images or videos under user control. Mobile system 1000 can use the still images / videos captured by camera 1100 to obtain specific information, or it can convert the still images / videos into other types of data such as text and store that data. Alternatively, mobile system 1000 can recognize strings included in the still images / videos captured by camera 1100 and can provide text or audio translations corresponding to those strings. As described above, camera 1100 in mobile system 1000 is often used in various application areas. In some example embodiments, camera 1100 can send data such as still images / videos to AP 1800 according to the D-PHY or C-PHY interface in the MIPI standard.

[0139] Display 1200 can be implemented in various forms, such as liquid crystal display (LCD), organic light-emitting diode (OLED) display, active-matrix organic light-emitting diode (AMOLED) display, plasma display panel (PDP), field emission display (FED), electronic paper, etc. In some example embodiments, display 1200 can provide touch screen functionality to also serve as an input device for mobile system 1000. Additionally, display 1200 can be integrated with a fingerprint sensor, etc., to provide security features for mobile system 1000. In some example embodiments, AP 1800 can send image data to display 1200 via a D-PHY or C-PHY interface according to the MIPI standard.

[0140] The interface device described with reference to the example embodiment can be used for communication between AP 1800 and display 1200, and between AP 1800 and camera 1100. At least one of AP 1800, display 1200 and camera 1100 can appropriately select control signals for charging and discharging capacitors included in the interface device as needed, so as to increase or decrease the conversion rate of the output signal output by the interface device.

[0141] As an example, the slewing rate of the output signal from the interface device can be increased to increase the data transmission rate between AP 1800 and display 1200 and / or between AP 1800 and camera 1100 and improve noise characteristics. Additionally, increasing the slewing rate of the output signal from the interface device can significantly reduce the impact of communication between AP 1800 and display 1200 and / or between AP 1800 and camera 1100 on other components and reduce power consumption.

[0142] The audio processing unit 1300 can process audio data stored in flash memory devices 1600a and 1600b, or audio data included in content received from external sources via modem 1400 or I / O devices 1700a and 1700b. For example, the audio processing unit 1300 can perform various processes on the audio data, such as encoding / decoding, amplification, and noise filtering.

[0143] The modem 1400 can modulate and transmit signals to send and receive wired / wireless data, and can demodulate signals received from external sources to recover the original signals. I / O devices 1700a and 1700b can provide digital inputs and outputs, and may include input devices such as ports for connecting to external recording media, touchscreens, or mechanical button keys, as well as output devices capable of outputting haptic vibrations. In some examples, I / O devices 1700a and 1700b can connect to external recording media via ports such as USB, Lightning cable, SD card, microSD card, DVD, network adapter, etc.

[0144] AP 1800 can control the overall operation of mobile system 1000. For example, AP 1800 can control display 1200 to display a portion of the content stored in flash memory devices 1600a and 1600b on the screen. When user input is received through I / O devices 1700a and 1700b, AP 1800 can perform control operations corresponding to the user input.

[0145] The AP 1800 can be provided as a system-on-a-chip (SoC) driving applications, an operating system (OS), etc. Alternatively, the AP 1800 can be included in a single semiconductor package along with other devices included in the mobile system 1000 (e.g., DRAM 1500a, flash memory 1620, and / or memory controller 1610). For example, the AP 1800 and at least one device can be provided in a package form such as a stacked package (PoP), ball grid array (BGA), chip-scale package (CSP), system-in-package (SIP), multi-chip package (MCP), wafer-level assembly package (WFP), or a wafer in a package form such as a layered processing stack (WSP). The kernel of the operating system driving the AP 1800 may include an input / output scheduler and device drivers for controlling flash memory devices 1600a and 1600b. Device drivers can control the access performance of flash devices 1600a and 1600b by referring to the number of synchronization queues managed by the I / O scheduler, or they can control CPU modes, dynamic voltage and frequency scaling (DVFS) levels, etc. within the SoC.

[0146] In some example embodiments, the AP 1800 may include: a processor block that performs operations or drives applications and / or an operating system; and various other peripheral components connected via a system block and a system bus. Peripheral components may include a memory controller, internal memory, a power management block, an error detection block, a monitoring block, etc. The processor block may include one or more cores. When multiple cores are included in a processor block, each core includes a cache memory, and a common cache shared by the cores may be included in the processor block.

[0147] In some example embodiments, AP 1800 may include an accelerator block 1820, i.e., dedicated circuitry for AI data manipulation. Alternatively, according to example embodiments, a separate accelerator chip may be provided to be separate from AP 1800, and DRAM 1500b may be additionally connected to accelerator block 1820 or the accelerator chip. Accelerator block 1820 may be a function block dedicated to performing specific functions of AP 1800, and may include a graphics processing unit (GPU) used as a function block dedicated to processing graphics data, a neural processing unit (NPU) used as a function block dedicated to performing AI computation and inference, a data processing unit (DPU) used as a function block dedicated to transmitting data, etc.

[0148] According to an example embodiment, the mobile system 1000 may include multiple DRAMs 1500a and 1500b. In some example embodiments, the AP 1800 may include a controller 1810 for controlling the DRAMs 1500a and 1500b, and the DRAM 1500a may be directly connected to the AP 1800.

[0149] The AP 1800 can be configured with command and mode register setting (MRS) commands according to JEDEC standards to control the DRAM, or it can configure the specifications and functions required by the mobile system 1000 (e.g., low voltage, high speed, and reliability), as well as the DRAM interface protocol for enabling CRC / ECC communication. For example, the AP 1800 can communicate with the DRAM 1500a through an interface compliant with JEDEC standards (e.g., LPDDR4, LPDDR5, etc.). Alternatively, the AP 1800 can configure a new DRAM interface protocol to control the DRAM 1500b used in the accelerator, where the accelerator block 1820 or accelerator chip provided by the AP 1800 has a higher bandwidth than the DRAM 1500a for communication.

[0150] exist Figure 28Only DRAMs 1500a and 1500b are shown, but the configuration of the mobile system 1000 is not limited to these. Depending on the bandwidth and response speed of the AP 1800 and accelerator block 1820, as well as voltage conditions, the mobile system 1000 may include memories other than DRAMs 1500a and 1500b. As an example, the controller 1810 and / or the accelerator block 1820 can control various types of memories, such as PRAM, SRAM, MRAM, RRAM, FRAM, hybrid RAM, etc. Compared to input / output devices 1700a and 1700b or flash memory devices 1600a and 1600b, DRAMs 1500a and 1500b have relatively lower latency and higher bandwidth. DRAMs 1500a and 1500b can be initialized at the power-on time of the mobile system 1000. When loading operating system and application data, DRAM 1500a and 1500b can be used as a location for temporary storage of operating system and application data, or as space for executing various software code.

[0151] Four basic arithmetic operations (e.g., addition, subtraction, multiplication, and division), as well as vector operations, address operations, or FFT operations, can be stored in DRAMs 1500a and 1500b. In other example embodiments, DRAMs 1500a and 1500b can be provided as processing-in-memory (PIM) with operational functions. For example, functions for performing inference in DRAMs 1500a and 1500b can be executed. In some example embodiments, inference can be performed in deep learning algorithms using artificial neural networks. Deep learning algorithms can include training operations and inference operations, in which a model is learned from various data, and in inference operations, the trained model is used to identify data. For example, functions used in inference can include hyperbolic tangent functions, sigmoid functions, rectified linear unit (ReLU) functions, etc.

[0152] As an example embodiment, an image captured by a user through camera 1100 can be signal-processed, and then the signal-processed image can be stored in DRAM 1500b. Accelerator block 1820 or accelerator chip can use the data stored in DRAM 1500b and the functions used in inference to perform AI data operations to identify the data.

[0153] According to an example embodiment, the mobile system 1000 may include multiple storage devices or multiple flash memory devices 1600a and 1600b, the capacity of which is higher than that of DRAM 1500a and 1500b. Flash memory devices 1600a and 1600b may include a controller 1610 and flash memory 1620. The controller 1610 may receive control commands and data from the AP 1800, and may write data to the flash memory 1620 in response to control commands, or may read data stored in the flash memory 1620 and send the read data to the AP 1800.

[0154] According to an example embodiment, accelerator block 1820 or accelerator chip can use flash memory devices 1600a and 1600b to perform training operations and AI data operations. As an example embodiment, operational logic devices capable of performing predetermined or alternatively desired operations in flash memory devices 1600a and 1600b can be implemented in controller 1610. Instead of AP 1800 and / or accelerator block 1820, the operational logic devices can use data stored in flash memory 1620 to perform at least a portion of the training and inference operations performed by AP 1800 and / or accelerator block 1820.

[0155] In some example embodiments, AP 1800 may include interface 1830. Therefore, flash memory devices 1600a and 1600b can be directly connected to AP 1800. For example, AP 1800 can be implemented as a SoC, flash memory device 1600a can be implemented as a chip independent of AP 1800, and AP 1800 and flash memory device 1600a can be mounted in a single package. However, the example embodiments are not limited to this, and multiple flash memory devices 1600a and 1600b can be electrically connected to mobile system 1000 via interconnection.

[0156] Flash memory devices 1600a and 1600b can store data captured by camera 1100 (such as still images / videos) or data received via a communication network and / or ports included in input / output devices 1700a and 1700b. For example, flash memory devices 1600a and 1600b can store augmented reality / virtual reality, high-definition (HD), or ultra-high-definition (UHD) content.

[0157] Any element disclosed above may include or be implemented in the following: processing circuitry (e.g., hardware including logic circuitry); hardware / software combination (e.g., a processor executing software); or a combination thereof. For example, processing circuitry may more specifically include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field-programmable gate array (FPGA), a system-on-a-chip (SoC), a programmable logic unit, a microprocessor, an application-specific integrated circuit (ASIC), etc.

[0158] As described above, according to the example embodiment, the conversion rate of the output signal output by the interface circuit can be adjusted by connecting capacitors to each switching element of the interface circuit and adjusting the conversion rate of the control signal for charging and discharging the capacitors.

[0159] While exemplary embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and alterations may be made without departing from the scope of the inventive concept as defined by the appended claims.

Claims

1. An interface circuit, comprising: A first switching element is connected to a first power node and an output node and controlled by a first input signal, wherein the first power node provides a first power supply voltage and the output node sends an output signal; A second switching element is connected to a second power node and the output node and is controlled by a second input signal different from the first input signal. The second power node provides a second power voltage lower than the first power voltage. A first resistor is connected between the first power node and the first switching element; A second resistor is connected between the second power node and the second switching element; A first capacitor is connected to a first node between the first resistor and the first switching element, and is charged and discharged by a first control signal; The second capacitor is connected to the second node between the second resistor and the second switching element, and is charged and discharged by the second control signal; as well as A buffer circuit is configured to output the first control signal and the second control signal, and is connected to a third power node via a first variable resistor and to a fourth power node via a second variable resistor. The third power node provides a third power supply voltage, and the fourth power node provides a fourth power supply voltage lower than the third power supply voltage.

2. The interface circuit according to claim 1, wherein, The phase of the first input signal is opposite to the phase of the second input signal.

3. The interface circuit according to claim 2, wherein, The first input signal and the first control signal have the same phase.

4. The interface circuit according to claim 3, wherein, The first control signal and the second control signal are the same signal.

5. The interface circuit according to claim 2, wherein, Each of the first switching element and the second switching element is an N-channel metal-oxide-semiconductor (NMOS) transistor.

6. The interface circuit according to claim 1, wherein, Each of the first and second variable resistors includes a plurality of transistors connected in parallel with each other.

7. The interface circuit according to claim 6, wherein, At least some of the plurality of transistors are simultaneously turned off by a single gate signal.

8. The interface circuit according to claim 1, wherein, The first input signal and the second input signal are the same signal, and The first switching element is a P-channel metal-oxide-semiconductor (PMOS) transistor, and the second switching element is an NMOS transistor.

9. The interface circuit according to claim 8, wherein, The buffer circuit includes a first buffer and a second buffer, the first buffer being configured to output the first control signal, and the second buffer being configured to output the second control signal.

10. The interface circuit according to claim 9, wherein, The phase of the first control signal is the same as the phase of the first input signal, and the phase of the second control signal is opposite to the phase of the first input signal.

11. The interface circuit according to claim 1, wherein, The amplitude of the output signal has a first level, a second level higher than the first level, and a third level higher than the second level.

12. The interface circuit according to claim 11, wherein, When the amplitude of the output signal increases from the first level to the second level, the first capacitor is charged; when the amplitude of the output signal increases from the second level to the third level, the second capacitor is charged; and when the amplitude of the output signal increases from the first level to the third level, both the first capacitor and the second capacitor are charged simultaneously.

13. The interface circuit according to claim 11, wherein, When the amplitude of the output signal decreases from the second level to the first level, the first capacitor is discharged; when the amplitude of the output signal decreases from the third level to the second level, the second capacitor is discharged; and when the amplitude of the output signal decreases from the third level to the first level, both the first capacitor and the second capacitor are discharged simultaneously.

14. The interface circuit according to claim 1, wherein, The output signal has a first level and a second level that is higher than the first level.

15. The interface circuit according to claim 14, wherein, When the amplitude of the output signal increases from the first level to the second level, the first capacitor and the second capacitor are charged, and when the amplitude of the output signal decreases from the second level to the first level, the first capacitor and the second capacitor are discharged.

16. An interface device, comprising: Multiple interface circuits, each interface circuit including a first switching element and a second switching element connected in series with each other, a first capacitor connected to a first node between the first switching element and a first power node, a second capacitor connected to a second node between the second switching element and a second power node, and a buffer configured to output a first control signal for charging and discharging the first capacitor and a second control signal for charging and discharging the second capacitor, the buffer being connected to a third power node via a first variable resistor and to a fourth power node via a second variable resistor; as well as The controller is configured to control the first switching element and the second switching element to determine the output signal of each of the plurality of interface circuits, and is configured to adjust the switching rate of the first control signal output to the first capacitor and the second control signal output to the second capacitor to determine the switching rate of the output signal.

17. The interface device according to claim 16, wherein, The controller adjusts the resistance of the first variable resistor and the second variable resistor to adjust the switching rate of the first control signal and the second control signal.

18. The interface device according to claim 17, wherein, The controller adjusts the switching rate of the first control signal and the second control signal based on the load of the channel connected to the output node between the first switching element and the second switching element.

19. An interface circuit, comprising: A first switching element is configured to receive a first power supply voltage from a first power supply node and be turned on and off by a first input signal; The second switching element is configured to receive a second power supply voltage lower than the first power supply voltage from the second power supply node and be turned on and off by a second input signal. A first capacitor has a first node and a second node, the first node of the first capacitor is connected to a first common node between the first switching element and the first power supply node, and the second node of the first capacitor receives a control signal having the same phase as the first input signal. The second capacitor has a first node and a second node. The first node of the second capacitor is connected to a second common node between the second switching element and the second power supply node. The second node of the second capacitor receives the control signal. as well as A buffer circuit is configured to output the control signal and is connected to a third power node via a first variable resistor and to a fourth power node via a second variable resistor. The conversion rate of the output signal from the output node to which the first and second switching elements are connected is determined by the conversion rate of the control signal.

20. The interface circuit according to claim 19, wherein, When the switching rate of the control signal increases, the switching rate of the output signal increases; and when the switching rate of the control signal decreases, the switching rate of the output signal decreases.

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